Light-emitting display device and driving method thereof

Abstract

The present disclosure relates to a light-emitting display device and a driving method thereof. The light-emitting display device includes: a display panel configured to display an image; a data driver configured to provide a data voltage to the display panel; and a timing controller configured to control the data driver. The data driver pauses a data latch operation.

Description

Technical Field

[0001] The present invention relates to a light-emitting display device and a driving method thereof. Background Art

[0002] With the progress of information technology, the market for display devices as a connection medium between users and information is expanding. Accordingly, the use of display devices such as light-emitting display devices (LEDs), quantum dot display devices (QDDs), liquid crystal display devices (LCDs), etc. is increasing.

[0003] The above display device includes: a display panel including sub-pixels; a driver configured to output a driving signal for driving the display panel; a power supply configured to generate power to be supplied to the display panel or the driver; etc.

[0004] In such a display device, when driving signals (e.g., a scan signal and a data signal) are provided to sub-pixels formed in the display panel, the selected sub-pixels in the sub-pixels transmit light or directly emit light, and thus an image can be displayed. Summary of the Invention

[0005] Accordingly, the present disclosure relates to a light-emitting display device and a driving method thereof that substantially eliminate one or more problems caused by limitations and disadvantages of the related art.

[0006] An object of the present invention is to provide a light-emitting display device and a driving method thereof that can eliminate problems (such as latch failures and screen flickering) caused by power noise, thereby enhancing display quality and enhancing driving reliability and driving stability.

[0007] Additional advantages, objects, and features of the present invention will be partly set forth in the description that follows and, in part, will be obvious to those of ordinary skill in the art upon examination of the following or may be learned from practice of the present invention. The objects and other advantages of the present invention may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

[0008] To achieve these objects and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described herein, a light-emitting display device includes: a display panel configured to display an image; a data driver configured to provide a data voltage to the display panel; and a timing controller configured to control the data driver, wherein the data driver pauses a data latch operation.

[0009] The data driver may pause the data latch operation corresponding to a falling edge or a rising edge of a source output enable signal.

[0010] The suspension of the data latching operation can be performed by a latch hold signal generated from a data driver or a timing controller.

[0011] The data driver may include a shift register configured to suspend the output of a clock signal so as to suspend the data latching operation corresponding to the latch hold signal.

[0012] The shift register may include: an AND gate configured to perform an AND operation on the latch hold signal and a shift clock signal to output the resulting signal; and a flip-flop configured to output a clock signal based on the signal output from the AND gate and a pulse externally applied to the flip-flop.

[0013] When the latch hold signal is generated at a logic low level, the latch connected to the shift register may have a latch hold period during which the latch suspends the data latching operation.

[0014] The shift register may include: an inverter configured to invert the latch hold signal and output the inverted latch hold signal; an AND gate configured to perform an AND operation on the inverted latch hold signal output from the inverter and the shift clock signal and output the resulting signal; and a flip-flop configured to output a clock signal based on the signal output from the AND gate and a pulse externally applied to the flip-flop.

[0015] When the latch hold signal is generated at a logic high level, the latch connected to the shift register may have a latch hold period during which the latch suspends the data latching operation.

[0016] In another aspect of the present invention, a method for driving a light-emitting display device includes: a display panel configured to display an image; a data driver configured to provide a data voltage to the display panel; and a timing controller configured to control the data driver. The method includes the steps of: transmitting data including a control packet and a data packet to the data driver via an interface coupled between the timing controller and the data driver; and generating a latch hold period during which the data latching operation of the data driver is suspended during a transmission period of the data packet.

[0017] In the step of generating the latch hold period, the latch hold period may be generated corresponding to a falling time or a rising time of a source output enable signal that activates the output of the data driver.

[0018] According to the present invention, there is an effect of being able to eliminate problems (such as latch failures and screen flickering) caused by power supply noise, thereby enhancing the display quality. According to the present invention, there is an effect of being able to prevent abnormal outputs of amplifiers, increases in blank periods, increases in transmission frequencies (or increases in transmission bandwidths), etc., thereby enhancing drive reliability and drive stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The accompanying drawings are included to provide a further understanding of the present invention and are incorporated into and constitute a part of this application. The accompanying drawings illustrate embodiments of the present invention and, together with the description, are used to explain the principles of the present invention. In the accompanying drawings:

[0020] Figure 1 is a block diagram schematically showing a light-emitting display device;

[0021] Figure 2 schematically shows Figure 1 a configuration diagram of the sub-pixels shown;

[0022] Figure 3A and Figure 3B is a diagram showing an arrangement example of a gate-in-panel type gate driver within a panel;

[0023] Figure 4 and Figure 5 is a block diagram illustrating a configuration of a device associated with a gate-in-panel type gate driver;

[0024] Figure 6 is a diagram schematically showing internal blocks of a data driver connected to a timing controller;

[0025] Figure 7 is a diagram briefly explaining a data transfer mode between a timing controller and a data driver;

[0026] Figure 8 is a diagram explaining problems caused by power supply noise;

[0027] Figure 9 and Figure 10 is a diagram explaining experimental examples for solving problems caused by power supply noise;

[0028] Figure 11 is a diagram briefly explaining a latch holding method according to a first embodiment of the present invention;

[0029] Figure 12 is a diagram more specifically explaining a latch holding method according to a first embodiment of the present invention;

[0030] Figure 13 is a diagram briefly explaining a latch holding method according to a second embodiment of the present invention;

[0031] Figure 14 is a diagram briefly illustrating a latch holding method according to a first variation of a second embodiment of the present invention;

[0032] Figure 15 is a diagram briefly illustrating a latch holding method according to a second variation of a second embodiment of the present invention;

[0033] Figure 16 is a diagram showing internal blocks of a data driver according to a third embodiment of the present invention;

[0034] Figure 17 is a diagram illustrating a method for controlling a latch holding signal according to a third embodiment of the present invention;

[0035] Figure 18 and Figure 19 is a diagram illustrating a configuration of a part of internal blocks of a data driver according to a third embodiment of the present invention and changes according to latch holding;

[0036] Figure 20 and Figure 21 is a diagram briefly comparing an experimental example with a third embodiment of the present invention and briefly illustrating differences therebetween;

[0037] Figure 22 is a diagram illustrating a method for controlling a latch holding signal according to a fourth embodiment of the present invention; and

[0038] Figure 23 is a diagram illustrating a part of a configuration of internal blocks of a data driver according to a fourth embodiment of the present invention. DETAILED DESCRIPTION

[0039] The display device according to the present invention can be implemented as a television, an image player, a personal computer (PC), a home theater, an automotive electronic device, a smart phone, etc., but is not limited thereto. The display device according to the present invention can be implemented as a light-emitting display device (LED), a quantum dot display device (QDD), a liquid crystal display device (LCD), etc. However, for ease of description, the following description will be given by taking as an example a light-emitting display device in which the display device according to the present invention is configured to emit light directly based on an inorganic light-emitting diode or an organic light-emitting diode.

[0040] Figure 1 is a block diagram schematically showing a light-emitting display device. Figure 2 is schematically shown Figure 1 a configuration diagram of a sub-pixel shown.

[0041] As Figure 1 and Figure 2As shown, the light-emitting display device may include an image provider 110, a timing controller 120, a gate driver 130, a data driver 140, a display panel 150, and a power supply 180.

[0042] The image provider (set system or host system) 110 may output various driving signals together with an image data signal provided from the outside thereof or an image data signal stored in an internal memory. The image provider 110 may provide a data signal and various driving signals to the timing controller 120.

[0043] The timing controller 120 may output a gate timing control signal GDC for controlling the operation timing of the gate driver 130, a data timing control signal DDC for controlling the operation timing of the data driver 140, various synchronization signals (vertical synchronization signal Vsync and horizontal synchronization signal Hsync), etc. The timing controller 120 may provide the data signal DATA provided from the image provider 110 to the data driver 140 together with the data timing control signal DDC. The timing controller 120 may be formed in the form of an integrated circuit (IC) and thus may be mounted on a printed circuit board, but is not limited thereto.

[0044] The gate driver 130 may output a gate signal (or scan signal) in response to a gate timing control signal GDC, etc. provided from the timing controller 120. The gate driver 130 may provide the gate signal to sub-pixels included in the display panel 150 via gate lines GL1 to GLm. The gate driver 130 may be formed in the form of an IC or may be directly formed on the display panel 150 in the form of an in-panel gate structure, but is not limited thereto.

[0045] The data driver 140 may sample and latch the data signal DATA in response to the data timing control signal DDC provided from the timing controller 120, may convert the data signal in digital form into a data voltage in analog form, and then may output the resulting data voltage. The data driver 140 may provide the data voltage to sub-pixels included in the display panel 150 via data lines DL1 to DLn. The data driver 140 may be formed in the form of an IC and thus may be mounted on the display panel 150 or a printed circuit board, but is not limited thereto.

[0046] The power supply 180 can generate a first power at a high level and a second power at a low level based on an external input voltage supplied from outside thereof, and can output the first power and the second power through a first power line EVDD and a second power line EVSS. The power supply 180 can not only generate and output the first power and the second power, but also generate and output a voltage required to drive the gate driver 130 (e.g., a gate voltage including a gate high voltage and a gate low voltage) or a voltage required to drive the data driver 140 (e.g., a drain voltage and a drain voltage including a half-drain voltage).

[0047] The display panel 150 can display an image corresponding to a gate signal, a driving signal including a data voltage, a first power, a second power, and the like. Sub-pixels of the display panel 150 emit light directly. The display panel 150 can be manufactured based on a substrate having rigidity or extensibility such as glass, silicon, polyimide, or the like. The light-emitting sub-pixels can be composed of pixels including red, green, and blue or pixels including red, green, blue, and white.

[0048] For example, one sub-pixel SP can be connected to a first data line DL1, a first gate line GL1, a first power line EVDD, and a second power line EVSS, and can include a pixel circuit composed of a switching transistor, a driving transistor, a capacitor, an organic light-emitting diode, or the like. The sub-pixel SP used in the light-emitting display device emits light directly, and thus its circuit configuration is complex. In addition, compensation circuits configured to not only compensate for the degradation of the organic light-emitting diode but also compensate for the degradation of the driving transistor configured to supply a driving current to the organic light-emitting diode or the like are also diverse. However, in Figure 2 the sub-pixel SP is simply shown in the form of a square.

[0049] In addition, in the above description, the timing controller 120, the gate driver 130, the data driver 140, etc. have been described as separate configurations. However, depending on the implementation type of the light-emitting display device, one or more of the timing controller 120, the gate driver 130, and the data driver 140 can be integrated into one IC.

[0050] Figure 3A and Figure 3B are diagrams showing an example of the arrangement of the in-panel gate type gate driver. Figure 4 and Figure 5 are block diagrams illustrating the configuration of a device associated with the in-panel gate type gate driver.

[0051] As Figure 3A and Figure 3B shown, the in-panel gate type gate drivers 130a and 130b are disposed in the non-display area NA of the display panel 150. AsFigure 3A As shown, the gate drivers 130a and 130b can be respectively disposed in the non-display regions NA on the left and right sides of the display panel 150. Alternatively, as Figure 3B shown, the gate drivers 130a and 130b can be respectively disposed in the non-display regions NA on the upper and lower sides of the display panel 150.

[0052] Although the gate drivers 130a and 130b have been illustrated and described in connection with examples in which the gate drivers 130a and 130b are disposed in the non-display regions NA on the left and right sides or the upper and lower sides of the display area AA, only one gate driver can be disposed in the non-display region NA on the left, right, upper, or lower side.

[0053] As Figure 4 shown, the in-panel gate type gate driver can include a shift register 131 and a level shifter 135. The level shifter 135 can generate a clock signal Clk and a start signal Vst based on signals and voltages output from the timing controller 120 and the power supply 180. The clock signal Clk can be generated in the form of a K-phase (such as, 2-phase, 4-phase, 8-phase, etc.) having K different phases (K is an integer of 2 or greater).

[0054] The shift register 131 can operate based on signals Clk and Vst output from the level shifter 135, etc., and can output gate signals Gate[1] to Gate[m] for turning on or off transistors formed at the display panel. The shift register 131 can be formed on the display panel in the form of a thin film according to the in-panel gate method. Therefore, Figure 3A and Figure 3B the "130a" and "130b" in

[0055] As Figure 4 and Figure 5 shown, different from the shift register 131, the level shifter 135 can be independently formed in the form of an IC or can be included in the power supply 180. Of course, these configurations are merely illustrative, and the present invention is not limited thereto. Figure 6 is a diagram schematically showing internal blocks of a data driver connected to a timing controller. Figure 7 is a diagram briefly explaining a data transfer mode between a timing controller and a data driver.

[0056] As Figure 6 and Figure 7As shown, the timing controller 120 and the data driver 140 can receive and transmit various signals through an embedded clock point-to-point interface (EPI) (simply referred to as the "EPI interface EPI") based on an embedded clock scheme.

[0057] The various signals transmitted through the EPI interface EPI can include: a control packet CTR including control signals for controlling the data driver 140, a data packet including data signals to be applied to the display panel, a data enable signal DE defining the input period of the data signals of a line, etc. In addition, the data driver 140 can generate a data enable signal DE based on the control signals included in the control packet CTR by itself.

[0058] The data driver 140 can include a shift register SR, a latch LAT, a DA converter DAC, a multi-channel output circuit, etc. The shift register SR, the latch LAT, the DA converter DAC, and the multi-channel output circuit can perform functions such as converting the data signals to be applied to the display panel into data voltages and other functions based on the data packet transmitted via the EPI interface EPI and the various signals included in the control packet CTR. In addition, Figure 6 The internal blocks of the data driver 140 briefly shown herein are merely illustrative, and thus the present invention is not limited thereto.

[0059] In addition, the data driver 140 may generate power supply noise during the output operation of its internal devices (for example, when the data voltage is output by the amplifier AMP included in the multi-channel output circuit). Hereinafter, a solution for eliminating problems caused by power supply noise according to an embodiment of the present invention will be described.

[0060] Figure 8 is a diagram illustrating problems caused by power supply noise. Figure 9 and Figure 10 is a diagram illustrating experimental examples for solving problems caused by power supply noise.

[0061] As Figure 6 and Figure 8 shown, when the source output enable signal SOE switches from a logic high level to a logic low level, the output operation of the amplifier AMP included in the multi-channel output circuit can be performed to output a data voltage. That is, the source output enable signal SOE is a signal for activating the output of the data driver 140 (the output operation of the amplifier AMP) (a signal allowing the output of a data voltage).

[0062] A plurality of amplifiers AMP, which are respectively configured to output data voltages via a plurality of data lines DL1 to DLn, are included in a multi-channel output circuit. However, when the plurality of amplifiers AMP perform an output operation for outputting data voltages, power supply noise may be generated within the data driver 140.

[0063] During an output period in which the output of the amplifier AMP is performed, there is a higher possibility of power supply noise generation than in a high-impedance period (Hi-Z period) in which the output of the amplifier AMP is not performed.

[0064] Therefore, when the latch LAT operates in a state where power supply noise is generated within the data driver 140, data latching for receiving a data packet (or data signal) may not be performed normally but may be performed abnormally. That is, when the latch LAT operates in a state where power supply noise is generated, there is a high possibility of occurrence of a data latching failure (a failure that causes screen flickering during high-frequency transmission).

[0065] In Figure 9 a first experimental example of, the width of the source output enable signal SOE (SOE width) is minimized to prevent the occurrence of data latching failure. In Figure 10 a second experimental example of, the horizontal blanking (H-blanking) period is increased corresponding to the time when power supply noise is generated, so as to prevent the occurrence of data latching failure.

[0066] It has been found that, as in Figure 9 a first experimental example of, when the width of the source output enable signal SOE (SOE width) is minimized, noise may be generated at the DA converter, and thus abnormal output of the amplifier AMP may occur.

[0067] On the other hand, as in Figure 10 a second experimental example of, it has been found that when the horizontal blanking (H-blanking) period is increased, power supply noise may be generated during a period in which clock training is performed, and thus data latching failure can be prevented.

[0068] However, due to the increase in the horizontal blanking (H-blanking) period, the method of the second experimental example may have another problem such as an increase in transmission frequency (or an increase in transmission bandwidth). For this reason, the following embodiments are proposed.

[0069] Figure 11 is a diagram briefly illustrating a latch holding method according to a first embodiment of the present invention. Figure 12 is a diagram more specifically illustrating a latch holding method according to a first embodiment of the present invention.

[0070] As Figure 11As shown, according to the first embodiment of the present invention, the latch can have a latch hold (LH) period during which the data latch operation is paused corresponding to the power supply noise generation time.

[0071] Preferably, the latch hold LH occurs during the period when the data packet including the data signal is transmitted, rather than during the period when the control packet CTR including the control signal is transmitted, so as to maintain the stable operation of the device.

[0072] As Figure 12 shown, there is a higher possibility of power supply noise generation during the output period in which the output of the amplifier AMP is performed than during the high-impedance period (hi-Z period) in which the output of the amplifier AMP is not performed.

[0073] Therefore, the latch hold LH can occur corresponding to the period when the source output enable signal SOE switches from logic high to logic low. Additionally, in order to achieve a stable latch hold (LH) operation, the latch hold LH can occur immediately before the source output enable signal SOE drops from logic high to logic low, and can end after a predetermined time has elapsed since the power supply noise disappeared.

[0074] According to the first embodiment of the present invention, not only can the problems caused by power supply noise (latch failure) be eliminated, but also the occurrence of other problems such as abnormal output of the amplifier AMP or an increase in the transmission frequency (or an increase in the transmission bandwidth) caused by an increased blank period that may occur in the experimental example can be prevented.

[0075] Figure 13 is a diagram briefly illustrating the latch hold method according to the second embodiment of the present invention. Figure 14 is a diagram briefly illustrating the latch hold method according to the first variation of the second embodiment of the present invention. Figure 15 is a diagram briefly illustrating the latch hold method according to the second variation of the second embodiment of the present invention.

[0076] As Figure 13 shown, according to the second embodiment of the present invention, the latch hold (LH) operation can be performed corresponding to the time of generating power supply noise. The latch hold (LH) operation can be performed based on an artificially generated latch hold signal LHS.

[0077] The timing controller or the data driver can each identify the time when the data voltage that causes power supply noise is output based on the operation timing of the device and the devices related thereto. Therefore, the latch hold signal LHS can be applied to the data driver after being generated from the timing controller, or can be generated within the data driver itself.

[0078] The latch LAT included in the data driver may receive the data signal included in the data packet based on the channel according to the data latch operation. However, when the latch hold signal LHS is generated at a logic high level, the latch LAT included in the data driver may pause the data latch operation during the logic high period of the latch hold signal LHS. When the latch hold signal LHS is subsequently generated at a logic low level, the data latch operation may resume.

[0079] Therefore, the data signal included in the data packet may be transmitted in such a manner that the first channel data Ch1 to the seventh channel data Ch7 are input, and then the eighth channel data Ch8 and the ninth channel data Ch9 are input after pausing the data input through the latch hold (LH) operation.

[0080] As Figure 14 shown, according to the first variant of the second embodiment of the present invention, the latch hold (HL) operation may occur when the source output enable signal SOE switches from a logic high level to a logic low level. That is, the latch hold (LH) operation may occur near the time when the source output enable signal SOE drops to a logic low level (the falling time of the signal SOE).

[0081] As Figure 15 shown, according to the second variant of the second embodiment of the present invention, the latch hold (LH) operation may occur when the source output enable signal SOE rises from a logic low level to a logic high level. That is, the latch hold LH may occur near the time when the source output enable signal SOE rises to a logic high level (the rising time of the source output enable signal SOE) (or may occur synchronously with the rising time of the signal SOE).

[0082] From Figure 14 and Figure 15 it can be seen that the amplifier AMP may be implemented to generate an output when the source output enable signal SOE drops to a logic low level, or may be implemented to generate an output when the source output enable signal SOE rises to a logic high level. Therefore, the latch hold (LH) operation may be controlled to occur at the power supply noise generation time, the output time of the amplifier AMP, or at a time determined in consideration of these two times.

[0083] Figure 16 is a diagram showing the internal blocks of the data driver according to the third embodiment of the present invention. Figure 17 is a diagram illustrating a method for controlling the latch hold signal according to the third embodiment of the present invention. Figure 18 and Figure 19 are diagrams illustrating the configuration of a part of the internal blocks of the data driver in the third embodiment of the present invention and the change according to the latch hold.

[0084] As Figure 16 shown, according to the third embodiment of the present invention, the data driver 140 may include an interface unit EPIRX&CDR, a logic circuit unit S2P&LOGIC, a shift register SR, a first latch LAT1, a second latch LAT2, a DA converter DAC, a multi-channel output circuit, and the like.

[0085] The interface unit EPI RX&CDR may include communication terminals EPI0A&B, EPI1A&B, etc. for data communication with the timing controller. The logic circuit unit S2P&LOGIC may include a selection terminal LbR for selecting a latch direction.

[0086] The interface unit EPI RX&CDR may receive data via the EPI interface connected to the timing controller, and may separate the data into a control signal and a data signal in a form that can be used in the internal device.

[0087] The logic circuit unit S2P&LOGIC may output a data signal and control signals for controlling the shift register SR, the first latch LAT1, the second latch LAT2, the DA converter DAC, the multi-channel output circuit, etc. based on the control signal transmitted via the interface unit EPI RX&CDR. In addition, the logic circuit unit S2P&LOGIC may transmit a latch hold signal LHS provided based on the signal transmitted to it via the EPI interface to the shift register SR.

[0088] In addition, the data driver 140 may include gamma voltage terminals GMA<1:10> for receiving gamma voltages to be provided to the DA converter DAC, test terminals LITEST and TEST for testing the operation of the internal device, voltage terminals VCCA / R, VSSA / R, VDDH, and VSSH for receiving the operating voltage of the internal device, and output terminals OUT1 to OUTn.

[0089] As Figure 17 shown, according to the third embodiment of the present invention, the latch hold signal LHS may be generated near the time when the source output enable signal drops to a logic low level (fall time of the source output enable signal SOE). In addition, when the latch hold signal LHS is generated at a logic high level, a latch hold (LH) operation may be performed.

[0090] The latch hold signal LHS can be generated before or after the time when the source output enable signal falls from a logic high level to a logic low level (the falling edge of the signal) over its entire width (SOE width). The generation time of the latch hold signal LHS (i.e., LHS_S[3:0]) can be earlier or later according to the data bit values. Additionally, the width of the latch hold signal LHS (i.e., LHS_W[5:0]) can be wider or narrower according to the data bit values. Furthermore, a clock training pattern CT Pattern can be generated during a latch hold (LH) period in which the latch hold signal LHS is generated at a logic high level instead of a data packet.

[0091] As Figure 18 and Figure 19 shown, the shift register SR according to the third embodiment of the present invention may include an inverter INV, first flip-flops FF1 to nth flip-flops FFn, first AND gates AND1 to nth AND gates ANDn, etc. The first flip-flops FF1 to nth flip-flops FFn may each be implemented as D flip-flops capable of shifting a signal in correspondence with a clock signal applied to their clock terminals and outputting the shifted signal.

[0092] The first flip-flops FF1 to nth flip-flops FFn may be independently interconnected such that the output from the data output terminal Q of one stage is applied to the data input terminal D of the next stage. Of course, the first flip-flop FF1 provided at the uppermost stage may receive a signal such as a source start pulse SSP from the outside. The first flip-flops FF1 to nth flip-flops FFn may be respectively connected to the first AND gates AND1 to nth AND gates ANDn such that the outputs from the output terminals of the AND gates AND1 to ANDn are respectively applied to the clock terminals of the flip-flops FF1 to FFn.

[0093] The first latch LAT1 according to the third embodiment of the present invention may include first data registers DR1 to nth data registers DRn, etc. The first data registers DR1 to nth data registers DRn may each be connected to a data bus S2P[Data Bus] at their input terminals. The first data registers DR1 to nth data registers DRn may also be respectively connected to the output terminals Q of the first flip-flops FF1 to nth flip-flops FFn at their clock terminals.

[0094] The first data register DR1 to the nth data register DRn can respectively store data signals transmitted to them via the data bus S2P [Data Bus] based on pixels (based on one-line) corresponding to the first clock signal CLK1 to the nth clock signal CLKn output from the output terminals Q of the first flip-flop FF1 to the nth flip-flop FFn. According to the operations of the first data register DR1 to the nth data register DRn, the data signals transmitted in serial form can be converted into data signals in parallel form.

[0095] Hereinafter, a part of the configurations included in the shift register SR and the first latch LAT1 will be described in conjunction with the connection and operation relationships of, for example, the shift register SR and the first latch LAT1. Of course, descriptions of the remaining configurations included in the shift register SR and the first latch LAT1 will not be given because the remaining configurations have the same connection and operation relationships as the configuration part to be described hereinafter.

[0096] The first flip-flop FF1 can be connected to the source start pulse line transmitting the source start pulse SSP at its data input terminal D, and at the same time, can be connected to the data input terminal D of the second flip-flop FF2 at its data output terminal Q. The first AND gate AND1 can be connected to the shift clock signal line transmitting the shift clock signal LCLK at its first input terminal, and can be connected to the output terminal of the inverter INV that outputs the latch hold signal LHS in an inverted state at its second input terminal, and at the same time, can be connected to the clock terminal of the first flip-flop FF1 at its output terminal.

[0097] The first flip-flop FF1 can output a logic high first clock signal CLK1 corresponding to the logic high shift clock signal LCLK (the rising time of the shift clock signal LCLK) generated during the period when the source start pulse SSP is held at logic high. The first data register DR1 can store the data signals D0 to D5 of the first pixel Pixel1 transmitted via the data bus S2P [Data Bus] based on the first clock signal CLK1 output from the first flip-flop FF1.

[0098] The second flip-flop FF2 can be connected to the data output terminal Q of the first flip-flop FF1 at its data input terminal D, and at the same time, can be connected to the data input terminal D of the third flip-flop FF3 at its data output terminal Q. The second AND gate AND2 can be connected to the shift clock signal line transmitting the shift clock signal LCLK at its first input terminal, and can be connected to the output terminal of the inverter INV that outputs the latch hold signal LHS in an inverted state at its second input terminal, and at the same time, can be connected to the clock terminal of the second flip-flop FF2 at its output terminal.

[0099] The second flip-flop FF2 can output a second clock signal CLK2 of logic high level corresponding to a first clock signal CLK1 of logic high level (fall time of the first clock signal CLK1) applied during a period in which the source start pulse SSP remains at logic high level. The second data register DR2 can store data signals D0 to D5 of a second pixel Pixel2 transmitted thereto via the data bus S2P [Data Bus] based on the second clock signal CLK2 output from the second flip-flop FF2.

[0100] When the latch hold signal LHS passes through the inverter INV, Figure 17 the latch hold signal LHS of shown logic low level is converted into a latch hold signal iLHS of logic high level (as Figure 19 shown), and thus outputs a latch hold signal iLHS of logic high level. On the other hand, when the latch hold signal LHS passes through the inverter INV, Figure 17 the latch hold signal LHS of shown logic high level is converted into a latch hold signal iLHS of logic low level (as Figure 19 shown), and thus outputs a latch hold signal iLHS of logic low level.

[0101] Therefore, the above operation is implemented until the latch hold signal LHS applied to the input terminal of the inverter INV is applied with logic low level. On the other hand, when the inverter INV generates a latch hold signal iLHS of logic low level, the first AND gate AND1 to the nth AND gate ANDn do not output 1, but output 0. This is because the AND gate multiplies the inputs of its two input terminals, thereby generating an output (logical product), and thus when a logical low value or 0 is input to one of the input terminals, 0 is output. As a result, during the latch hold (LH) period in which a latch hold signal iLHS of low logic level is output, the first flip-flop FF1 to the nth flip-flop FFn output a clock signal of low logic level instead of a clock signal of logic high level.

[0102] As an example, Figure 19 it is shown that the third clock signal CLK3 is output after a predetermined time delay by a latch hold (LH) operation after the second clock signal CLK2 is output. In addition, as can be seen from Figure 19 it, although a certain data signal (Certain Data) can be generated during the latch hold (LH) period, since a clock signal of logic high level is not generated, the data signal is not stored in the data register.

[0103] Figure 20 and Figure 21 are diagrams for briefly comparing an experimental example and a third embodiment of the present invention with each other and briefly explaining the differences therebetween.

[0104] As Figure 20 and Figure 21 shown, the shift register SR according to the experimental example may include a first flip-flop FF1 to an nth flip-flop FFn, etc. Additionally, the first latch LAT1 according to the experimental example may include a first data register DR1 to an nth data register DRn, etc.

[0105] The latch hold signal is not applied to the structure according to the experimental example. For this reason, since the latch hold signal LHS is not applied and the latch hold (LH) operation based on the latch hold signal LHS is not performed, it is difficult to eliminate problems caused by power supply noise. Therefore, when power supply noise is generated, there is a high possibility of occurrence of data latch failures with reference to Figure 8 the data described.

[0106] Hereinafter, a fourth embodiment of the present invention will be described. The following description is mainly given in combination with configurations different from those of the third embodiment.

[0107] Figure 22 is a diagram illustrating a method of controlling a latch hold signal according to a fourth embodiment of the present invention. Figure 23 is a diagram illustrating a part of the configuration of an internal block of a data driver according to a fourth embodiment of the present invention.

[0108] As Figure 22 shown, according to a fourth embodiment of the present invention, the latch hold signal LHS may be generated near the time when the source output enable signal SOE falls to a logic low level (the falling time of the signal SOE). Additionally, when the latch hold signal LHS is generated at a low logic level, a latch hold (LH) operation may be performed. That is, the latch hold (LH) operation may be performed by a latch hold signal LHS generated in a form inverted from the latch hold signal LHS of the third embodiment.

[0109] As Figure 23 shown, the shift register SR according to a fourth embodiment of the present invention may include a first flip-flop FF1 to an nth flip-flop FFn, a first AND gate AND1 to an nth AND gate ANDn, etc. In the fourth embodiment of the present invention, different from the third embodiment, an inverter is not included in the clock terminals of the shift register SR.

[0110] The first flip-flop FF1 to the nth flip-flop FFn can be independently interconnected such that the output from the data output terminal Q of one stage is applied to the data input terminal D of the next stage. Of course, the first flip-flop FF1 provided at the topmost stage can receive a signal such as a source start pulse SSP from the outside. The first flip-flop FF1 to the nth flip-flop FFn can be respectively connected to the first AND gate AND1 to the nth AND gate ANDn such that the outputs from the output terminals of the AND gates AND1 to ANDn are respectively applied to the clock terminals of the flip-flops FF1 to FFn.

[0111] The first latch LAT1 according to the fourth embodiment of the present invention can include the first data register DR1 to the nth data register DRn and the like. The first data register DR1 to the nth data register DRn can each be connected to the data bus S2P [Data Bus] at their input terminals. The first data register DR1 to the nth data register DRn can also be respectively connected to the output terminals of the first flip-flop FF1 to the nth flip-flop FFn at their clock terminals.

[0112] The first data register DR1 to the nth data register DRn can respectively store the data signals transmitted to them via the data bus S2P [Data Bus] based on pixels (based on a single line) corresponding to the first clock signal CLK1 to the nth clock signal CLKn output from the output terminals Q of the first flip-flop FF1 to the nth flip-flop FFn. According to the operations of the first data register DR1 to the nth data register DRn, the data signals transmitted in serial form can be converted into data signals in parallel form.

[0113] Hereinafter, a part of the configurations included in the shift register SR and the first latch LAT1 will be described in conjunction with the connection and operation relationships of, for example, the shift register SR and the first latch LAT1. Of course, descriptions of the remaining configurations included in the shift register SR and the first latch LAT1 will not be given because the remaining configurations have the same connection and operation relationships as the configuration part to be described hereinafter.

[0114] The first flip-flop FF1 can be connected to the source start pulse line that transmits the source start pulse SSP at its data input terminal D, and can be connected to the data input terminal D of the second flip-flop FF2 at its data output terminal Q. The first AND gate AND1 can be connected to the shift clock signal line that transmits the shift clock signal LCLK at its first input terminal, and can be connected to the latch hold signal line that transmits the latch hold signal LHS at its second input terminal, and can be connected to the clock terminal of the first flip-flop FF1 at its output terminal.

[0115] The first flip-flop FF1 can output a first clock signal CLK1 of logic high level corresponding to a logic high level shift clock signal LCLK (the rising time of the shift clock signal LCLK) generated during a period in which the source start pulse SSP remains at logic high level. The first data register DR1 can store the data signal of the first pixel Pixel1 transmitted via the data bus S2P[Data Bus] based on the first clock signal CLK1 output from the first flip-flop FF1.

[0116] The second flip-flop FF2 can be connected to the data output terminal Q of the first flip-flop FF1 at its data input terminal D, and at the same time be connected to the data input terminal D of the third flip-flop FF3 at its data output terminal Q. The second AND gate AND2 can be connected to the shift clock signal line transmitting the shift clock signal LCLK at its first input terminal, and can be connected to the latch hold signal line transmitting the latch hold signal LHS at its second input terminal, and at the same time be connected to the clock terminal of the second flip-flop FF2 at its output terminal.

[0117] The second flip-flop FF2 can output a second clock signal CLK2 of logic high level corresponding to a logic high level first clock signal CLK1 (the falling time of the first clock signal CLK1) applied during a period in which the source start pulse SSP remains at logic high level. The second data register DR2 can store the data signal of the second pixel Pixel2 transmitted to it via the data bus S2P[Data Bus] based on the second clock signal CLK2 output from the second flip-flop FF2.

[0118] As can be seen from Figure 22 and Figure 23 When the logic low level latch hold signal LHS is applied to the first AND gate AND1 to the nth AND gate ANDn, the first AND gate AND1 to the nth AND gate ANDn do not output 1, but output 0. As a result, during the latch hold (LH) period in which the low logic level latch hold signal LHS is output, the first flip-flop FF1 to the nth flip-flop FFn output clock signals of low logic level instead of clock signals of logic high level.

[0119] As is obvious from the above description, according to the present invention, there is an effect of being able to eliminate problems (such as latch failure, screen flicker, etc.) caused by power supply noise, thereby enhancing the display quality. According to the present invention, there are effects of being able to prevent output abnormalities of the amplifier, increase in blanking period, increase in transmission frequency (or increase in transmission bandwidth), etc., thereby enhancing the driving reliability and driving stability.

[0120] The foregoing description and drawings have been presented to illustrate the technical idea of the present invention by way of example. Those skilled in the art to which the present invention pertains will understand that various modifications and variations are possible by combining, dividing, substituting, or changing the constituent elements without changing the basic features of the present invention. Therefore, the foregoing embodiments disclosed herein should be construed as merely illustrative and not as limiting the principles and scope of the present invention. It should be understood that the scope of the present invention should be defined by the appended claims and that all equivalents thereof fall within the scope of the present invention.

[0121] This application claims the benefit of Korean Patent Application No. 10-2021-0068322, filed on May 27, 2021, the entire contents of which are incorporated herein by reference.

Claims

1. A light-emitting display device, the light-emitting display device comprising: A display panel configured to display an image; A data driver configured to provide a data voltage to the display panel; And A timing controller configured to control the data driver, Wherein the data driver or the timing controller is configured to generate a latch hold signal during a transmission period of a data packet and at each falling time or rising time of a source output enable signal SOE that activates an output of the data driver, and Wherein the data driver pauses a data latching operation through the latch hold signal.

2. The light-emitting display device according to claim 1, wherein, The data driver includes a shift register configured to pause an output of a clock signal so as to pause the data latching operation corresponding to the latch hold signal.

3. The light-emitting display device according to claim 2, wherein, The shift register includes: An AND gate configured to perform an AND operation on the latch hold signal and a shift clock signal and output a resulting signal; and A flip-flop configured to output the clock signal based on the signal output from the AND gate and a pulse externally applied to the flip-flop.

4. The light-emitting display device according to claim 3, wherein, When the latch hold signal is generated at a logic low level, a latch connected to the shift register has a latch hold period during which the latch pauses the data latching operation.

5. The light-emitting display device according to claim 2, wherein, The shift register includes: An inverter configured to invert the latch hold signal and output an inverted latch hold signal; An AND gate configured to perform an AND operation on the inverted latch hold signal output from the inverter and a shift clock signal, and output a resulting signal; and A flip-flop configured to output the clock signal based on the signal output from the AND gate and a pulse externally applied to the flip-flop.

6. The light-emitting display device according to claim 5, wherein, When the latch hold signal is generated at a logic high level, a latch connected to the shift register has a latch hold period during which the latch pauses the data latching operation.

7. A method for driving a light-emitting display device, the light-emitting display device comprising: A display panel configured to display an image; A data driver configured to provide a data voltage to the display panel; And a timing controller configured to control the data driver, the method comprising the steps of: Transmitting data including a control packet and a data packet to the data driver via an interface connected between the timing controller and the data driver; and Generating a latch hold period during which the data latching operation of the data driver is paused during a transmission period of the data packet, Wherein, in the step of generating the latch hold period, the latch hold period is generated corresponding to each falling time or rising time of a source output enable signal that activates an output of the data driver.

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