Gallium oxide device preparation method based on high-temperature annealing technology and gallium oxide device

Abstract

The application discloses a gallium oxide device preparation method based on high-temperature annealing technology and a gallium oxide device, and relates to the technical field of semiconductor preparation. The method comprises the following steps: a first barrier layer is prepared on the surface of a gallium oxide wafer, and the barrier layer plays a role in blocking a high-temperature oxygen atmosphere environment in a high-temperature oxygen annealing process; a patterning process is performed on the barrier layer for the purpose of impurity regulation of the gallium oxide wafer, and the process depth of the patterning process does not exceed the thickness of the barrier layer; the gallium oxide wafer after the above treatment is subjected to oxygen atmosphere annealing treatment; the barrier layer of the gallium oxide wafer after the annealing treatment is removed; and the surface layer of the gallium oxide wafer after the barrier layer is removed is removed. Through the annealing technology and the design of the patterning process, the problems that the oxygen atmosphere high-temperature annealing technology cannot be used for processing only the local region of the gallium oxide material and cannot be used for selectively regulating the net carrier concentration of the gallium oxide material are solved.

Description

Technical Field

[0001] This invention relates to semiconductor material processing technology, and more particularly to a method for fabricating gallium oxide devices based on high-temperature annealing technology and a gallium oxide device. Background Technology

[0002] Currently, selective control of net carrier concentration in gallium oxide (GaO) materials is primarily achieved through ion implantation. This involves doping with donor impurities such as Si, Sn, and Ge to increase net carrier concentration, and doping with acceptor impurities such as Fe, Mg, and N to compensate for free electrons and thus reduce net carrier concentration. However, ion implantation technology for GaO materials faces numerous challenges, both economically and technically. Firstly, economically, ion implantation is very expensive. Besides requiring high-power equipment to emit high-energy ions, further high-temperature annealing is necessary to activate the implanted ions and repair damage caused by the high-energy ions, both of which consume significant energy. Secondly, regarding the technical characteristics of GaO ion implantation, the activation efficiency of the implanted ions is currently unclear; implantation at deeper locations within the material is difficult to achieve; implanted ions diffuse, making precise dosage control challenging, and the distribution pattern of implanted ions remains uncertain; the types and distribution patterns of defects caused by implantation are unclear; and defect repair techniques are still immature. These technical barriers significantly hinder the application of ion implantation technology.

[0003] Besides ion implantation, another way to change the conductivity of gallium oxide is through high-temperature oxygen annealing. However, high-temperature oxygen annealing affects the overall conductivity of the material and cannot selectively treat a specific area, which limits the application of this technique.

[0004] Therefore, for selective region net carrier concentration control technology of gallium oxide materials, both ion implantation technology and high-temperature oxygen annealing technology still have significant technical barriers to overcome in order to better meet the future development needs of gallium oxide-based semiconductor devices. Summary of the Invention

[0005] The present invention mainly solves the problem that the existing high-temperature annealing technology cannot treat only a local area of ​​gallium oxide material and cannot control the net carrier concentration of selective regions of gallium oxide material.

[0006] To solve the above-mentioned technical problems, the present invention provides the following technical solution:

[0007] A method for fabricating gallium oxide devices based on high-temperature annealing technology includes the following steps:

[0008] A barrier layer is prepared on the surface of a gallium oxide wafer, which serves to block the oxygen atmosphere during high-temperature oxygen annealing.

[0009] A patterning process is performed on the barrier layer for the purpose of controlling gallium oxide wafer impurities, wherein the process depth of the patterning process does not exceed the thickness of the barrier layer.

[0010] The gallium oxide wafers treated as described above were then annealed in an oxygen atmosphere.

[0011] Remove the barrier layer from the annealed gallium oxide wafer;

[0012] Remove the surface layer of the gallium oxide wafer from which the barrier layer has been stripped.

[0013] As a preferred embodiment, a method for fabricating a barrier layer on the surface of a gallium oxide wafer includes the following steps:

[0014] A first barrier layer and a second barrier layer are prepared on the surface of a gallium oxide wafer. The first barrier layer is grown on the surface of the second barrier layer. The second barrier layer isolates the gallium oxide wafer surface from the first barrier layer. The second barrier layer is a release layer.

[0015] As a preferred embodiment, a method for fabricating a barrier layer on the surface of a gallium oxide wafer includes the following steps:

[0016] A first barrier layer and a second barrier layer are prepared on the surface of a gallium oxide wafer; the second barrier layer is located between the surface of the gallium oxide wafer and the first barrier layer, and the patterning rate of the second barrier layer is lower than that of the first barrier layer. The materials of the first barrier layer and the second barrier layer are selected according to the temperature of the high-temperature oxygen annealing process.

[0017] As a preferred option, the barrier layer is patterned using photolithography or etching.

[0018] As a preferred option, the net carrier concentration can be controlled by adjusting the individual thickness or the total thickness of the first and second barrier layers.

[0019] Alternatively, by adjusting the thickness of the second barrier layer, the net carrier concentration in the region not covered by the first barrier layer after patterning can be controlled.

[0020] As a preferred embodiment, the barrier layer is fabricated on all surfaces of the gallium oxide wafer.

[0021] As a preferred approach, the net carrier concentration is controlled by one or more parameters among annealing temperature, oxygen concentration, and annealing equipment chamber pressure.

[0022] As a preferred embodiment, a dry etching method is used to pattern the barrier layer, wherein the etching rate of the second barrier layer is less than that of the second barrier layer.

[0023] As a preferred embodiment, the material of the barrier layer is selected according to the following requirements:

[0024] The melting point is higher than the annealing temperature;

[0025] It can be removed by solutions with slow reaction rates on the surface of gallium oxide materials.

[0026] Furthermore, based on the above method, a gallium oxide device is provided, comprising a gallium oxide epitaxial layer and / or a gallium oxide substrate that have undergone regional regulation by a gallium oxide device fabrication method such as high-temperature annealing technology.

[0027] A method for fabricating a gallium oxide device, employing the above-described gallium oxide device fabrication method based on high-temperature annealing technology, further includes the following step after the step of removing the surface layer of the gallium oxide wafer with the barrier layer already stripped:

[0028] Ohmic contact electrodes are grown on the back side of the gallium oxide wafer, i.e., the gallium oxide substrate layer;

[0029] Photoresist is spin-coated on the front side of the gallium oxide wafer, i.e., the surface of the gallium oxide epitaxial layer;

[0030] The photoresist is exposed and developed to pattern it for use in electrode growth. The patterned region in this step is designed in the region of low net carrier concentration.

[0031] Long Schottky electrodes are generated using physical vapor deposition (PVD) technology.

[0032] Remove excess metal from the Schottky electrode and clean the photoresist.

[0033] Further, another method for fabricating gallium oxide devices is provided, which employs a gallium oxide device fabrication method based on high-temperature annealing technology, and further includes the following steps:

[0034] The regions on the front and back sides of the wafer where the net carrier concentration needs to be changed are patterned, specifically the areas on the wafer used for device fabrication.

[0035] Further, another method for fabricating gallium oxide devices is provided, employing a gallium oxide device fabrication method based on high-temperature annealing technology. After removing the blocking layer of the patterned portion, the method includes the following steps:

[0036] Ion implantation technology is used to implant the required ions into the gallium oxide epitaxial layer to form an ion implantation region. The implanted ions are acceptor impurities or donor impurities.

[0037] After the above treatment, the gallium oxide wafer is annealed in an oxygen atmosphere. Under high temperature annealing, the ion implantation region is formed after the implanted impurities are activated, and the gallium oxide substrate and gallium oxide epitaxial layer are formed due to the influence of oxygen annealing.

[0038] Remove the barrier layer from the annealed gallium oxide wafer;

[0039] Remove the surface layer of the gallium oxide wafer from which the barrier layer has been stripped.

[0040] The beneficial effects of this invention are:

[0041] 1) First, the effect of oxygen annealing on the net carrier concentration of gallium oxide can penetrate into the material to a depth of more than 1 mm. Therefore, combining oxygen atmosphere annealing with patterning process can solve the difficulty of deep implantation in gallium oxide by ion implantation technology.

[0042] Secondly, compared to ion implantation, high-temperature oxygen annealing significantly reduces lattice damage, ensuring material quality and facilitating subsequent device fabrication. Furthermore, high-temperature oxygen annealing avoids issues related to ion activation, diffusion, and distribution patterns, resulting in fewer technological barriers compared to ion implantation. Finally, the process flow of high-temperature oxygen annealing is simpler, reducing costs compared to ion implantation.

[0043] 2) The technical barrier of high-temperature oxygen annealing technology is the lack of a suitable barrier layer, which makes it impossible to control the net carrier concentration of the material in a specific area. This greatly limits the application scenarios of this special treatment method. This invention solves this problem.

[0044] 3) For applications that do not require highly precise net carrier concentration control, such as high-resistivity terminations, current blocking layers, and device isolation, this method offers a significant cost advantage over ion implantation. Firstly, the equipment used in this invention is less expensive than ion implanters. Secondly, ion implantation can only be performed on a single wafer, and its efficiency is limited by the maximum number of wafers the equipment can process; wafers must be placed horizontally, resulting in low space utilization. In contrast, the annealing technology proposed in this invention theoretically has a directly proportional relationship between the number of wafers processed per cycle and the size of the cavity, and wafers can be placed vertically during processing. This greatly improves space utilization and significantly enhances device processing efficiency. Attached Figure Description

[0045] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0046] Figure 1 This is a flowchart of the method for controlling net carrier concentration disclosed in Example 2;

[0047] Figure 2 This is a flowchart of another method for controlling net carrier concentration disclosed in Example 4;

[0048] Figure 3 This is a flowchart of the anode edge terminal preparation method disclosed in Example 6;

[0049] Figure 4 This is a flowchart of the device isolation fabrication method disclosed in Example 7.

[0050] Figure 5 This is a flowchart of the method for controlling the net carrier concentration in a region based on ion implantation technology disclosed in Example 8;

[0051] 10 - First barrier layer, 20 - Second barrier layer, 30 - Gallium oxide epitaxial layer, 40 - Gallium oxide, 50 - Photoresist layer, 30 - 1 - Net carrier concentration control layer after annealing, 60 - Ohmic contact electrode, 70 - Schottky contact electrode. Detailed Implementation

[0052] Unless otherwise defined, the technical or scientific terms used in this application shall be understood by those skilled in the art.

[0053] In its ordinary sense, the terms "first," "second," "third," "fourth," and similar words used in this application specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components.

[0054] Therefore, the features defined by "first," "second," "third," and "fourth" may explicitly or implicitly include one or more of those features. In the description of the embodiments of this application, unless otherwise stated, "multiple" means two or more. The directional terms such as "left," "right," "up," and "down" are defined relative to the indicated orientation in the accompanying drawings. It should be understood that these directional terms are relative concepts used for relative description and clarification, and they may change accordingly depending on the orientation. The embodiments of this application are described below with reference to the accompanying drawings. In the following description, reference is made to the drawings that form part of this application and illustrate specific aspects of the embodiments of this application or that may be used in relation to specific aspects of the embodiments of this application. It should be understood that the embodiments of this application may be used in other aspects and may include structural or logical variations not depicted in the drawings. Therefore, the following detailed description should not be construed in a limiting sense, and the scope of this application is defined by the appended claims. Furthermore, it should be understood that, unless explicitly stated otherwise, the features of the various exemplary embodiments and / or aspects described herein may be combined with each other.

[0055] Example 1:

[0056] A method for fabricating gallium oxide devices based on high-temperature annealing technology is a method for selectively controlling the net carrier concentration in gallium oxide materials, including the following process steps:

[0057] Step 1: Prepare a first barrier layer on the surface of a gallium oxide wafer. The first barrier layer serves to block the high-temperature oxygen atmosphere during the high-temperature oxygen annealing process.

[0058] Step 2: Perform a patterning process on the first barrier layer for the purpose of controlling gallium oxide wafer impurities, wherein the process depth of the patterning process does not exceed the thickness of the first barrier layer.

[0059] Step 3: Anneal the gallium oxide wafer after the above treatment in an oxygen atmosphere;

[0060] Step 4: Remove the first barrier layer from the annealed gallium oxide wafer;

[0061] Step 5: Remove the surface layer of the gallium oxide wafer that has been stripped of the first barrier layer.

[0062] In step 1, during actual operation, the annealing atmosphere affects the material from all 360 degrees, therefore the first barrier layer needs to cover the entire surface of the gallium oxide wafer. Besides multiple growth processes, a preferred method is LPCVD, where a single growth process covers the entire gallium oxide wafer surface, which helps reduce costs. The material selection for the first barrier layer includes all high-temperature resistant materials (the reference temperature can be a melting point not lower than 900℃), and elements or compounds that react with oxygen to form new compounds, with a coefficient of thermal expansion not exceeding 1×10⁻⁶. -4 / K.

[0063] Step 2 involves patterning the barrier layer using photolithography or etching. For the area requiring control, a corresponding region is designed. Within this designed region, the first barrier layer on the gallium oxide wafer surface is patterned using photolithography or etching to control impurities in the gallium oxide wafer. The thickness of the first barrier layer is adjusted to regulate the net carrier concentration, ensuring that the patterning depth does not exceed the thickness of the first barrier layer.

[0064] Step 3: The gallium oxide wafer after the above treatment is annealed in an oxygen atmosphere. The first barrier layer is made of a high-temperature resistant material with a melting point not lower than the annealing temperature. In this embodiment, a material with a melting point not lower than the annealing temperature is used. The selection of the melting point of the high-temperature resistant material is adapted according to the actual requirements of the annealing process. Based on this scheme, the net carrier concentration of the gallium oxide selective region can be controlled through patterning process + annealing.

[0065] Specifically, the prepared gallium oxide wafer samples are annealed in an oxygen atmosphere within a high-temperature apparatus. A reference temperature is 600-1700 °C. Theoretically, even a very short annealing time will affect the net carrier concentration of the sample, but the degree of influence varies with time and temperature. During annealing, oxygen is continuously supplied, and the oxygen content within the chamber should not be lower than the oxygen content in air (21%).

[0066] Other optional additional methods include adjusting the net carrier concentration by adjusting the oxygen atmosphere, for example 1) the oxygen concentration of general annealing treatment is not lower than the oxygen content in the air, but the net carrier concentration can also be adjusted by controlling the oxygen concentration.

[0067] For example, 2) the pressure inside the high-temperature equipment cavity in the above-mentioned annealing process is usually one standard atmosphere, but the net carrier concentration can also be controlled by adjusting the gas pressure parameter. 3) On the other hand, it is also important to note that the annealing time includes the heating and cooling time. During the cooling process, selecting a suitable point to stop oxygen supply within the range of 400 ℃ (reference temperature) to the actual annealing temperature can effectively control the net carrier concentration. 4) Intermittently stopping oxygen supply during the annealing process and introducing other gases to assist in the adjustment process can also be considered. These will not be listed here.

[0068] Step 4: The sample that has undergone the annealing process is placed in a solution capable of corroding the first barrier layer and ultrasonically removed to remove the first barrier layer. Since the first barrier layer will have an oxidized portion after oxygen atmosphere annealing, the first barrier layer after step 3 is an element or compound that has reacted with oxygen to form new compounds. Therefore, preferably, a solution capable of dissolving the raw materials and oxidized substances is selected.

[0069] Step 5: Depending on the application scenario, the gallium oxide material after removing the first barrier layer is sequentially subjected to surface removal and repair treatment on both the front and back surfaces. The etching depth for the surface with epitaxial material or the surface that has undergone barrier layer patterning is 0-1 μm, while the etching depth for the surface without epitaxial material is 0-10 μm. The surface removal thickness range can be adjusted according to different application scenarios. In addition to etching, the surface layer can also be removed by uniformly thinning the material through chemical mechanical polishing, with a thickness similar to that of etching. Finally, the treated material surface is repaired using wet etching technology, with the reaction rate between the repair solution and the gallium oxide material not exceeding 100 nm / min.

[0070] In this embodiment, the thickness of the first barrier layer does not exceed 100 micrometers to prevent the barrier layer from detaching due to large vertical deformation caused by thermal expansion during subsequent high-temperature annealing. This thickness requirement for the first barrier layer is a current experimental requirement for gallium oxide samples, and other parameters are not excluded.

[0071] Example 2:

[0072] The material of the first barrier layer selected in Example 1 generally needs to be removable by a certain solution, and the reaction rate between this solution and the gallium oxide material should not exceed 10 nm / min. When there are difficulties in peeling off the first barrier layer, such as impurities generated during the annealing process making solution peeling difficult, resulting in impurity residue, or the solution used for peeling off the first barrier layer reacting with the gallium oxide material, or the solution being too expensive, a new implementation method is provided. This method effectively removes the first barrier layer while maintaining the surface quality of the gallium oxide material by adding a peeling layer.

[0073] For the reasons mentioned above, this embodiment discloses a method for fabricating a gallium oxide device, referring to... Figure 1 This includes the following process steps:

[0074] Step 1', as Figure 1 -a, A first barrier layer 10 and a second barrier layer 20 are prepared on the surface of a gallium oxide wafer. The first barrier layer 10 serves to block the high-temperature oxygen atmosphere during the high-temperature oxygen annealing process. The second barrier layer 20 is a release layer, which serves to remove the first barrier layer 10 after the annealing process. The gallium oxide wafer includes a gallium oxide substrate layer 40 and a gallium oxide epitaxial layer 30.

[0075] Step 2', as Figure 1 -b, A patterning process for controlling gallium oxide impurities is performed on the first barrier layer 10 and the second barrier layer 20. The process depth of the patterning process does not exceed the thickness of the first barrier layer 10 plus the thickness of the second barrier layer 20. Specifically, it cannot exceed the depth of the second barrier layer 20, that is, the process depth is greater than or equal to the thickness of the first barrier layer 10 and less than the total thickness of the first barrier layer 10 and the second barrier layer 20.

[0076] Another option is that the first barrier layer of the patterned process region 10-1 may not be completely removed in order to adjust the net carrier concentration in that region.

[0077] Step 3', as Figure 1 -c, the gallium oxide treated as described above is annealed in an oxygen atmosphere to form a net carrier concentration control layer 30-1 after annealing; as... Figure 1 After the -c patterning process, a portion of the first barrier layer is etched. After annealing, the gallium oxide epitaxial layer with the first barrier layer and the gallium oxide epitaxial layer without the first barrier layer are affected by the annealing process to different depths. The gallium oxide epitaxial layer with the first barrier layer is affected to a shallower depth.

[0078] Step 4', as Figure 1 -d, peel off the first barrier layer 10 and the second barrier layer 20 of gallium oxide after annealing; then remove the surface layer of the gallium oxide wafer after peeling off the first barrier layer 10 and the second barrier layer 20.

[0079] The first barrier layer 10 is made of a high-temperature resistant material with a melting point not lower than the annealing temperature. In this embodiment, a material with a melting point not lower than the annealing temperature is used. The melting point of the high-temperature resistant material is adjusted according to the actual requirements of the annealing process. The second barrier layer 20 has a melting point higher than the annealing temperature and is easily removed by solutions such as hydrofluoric acid, concentrated sulfuric acid, hydrochloric acid, and nitric acid, which have minimal impact on the surface quality of gallium oxide. In addition, the second barrier layer 20 (stripping layer) also has a low coefficient of thermal expansion to prevent it from falling off during annealing. Here, "minimal impact on the surface of gallium oxide" can be considered as a corrosion rate of less than 10 nm / min, and "low coefficient of thermal expansion" can be considered as not exceeding 1 × 10⁻⁶. -4 / K. The parameters in this solution are for implementation reference only and are not specific limitations.

[0080] To further optimize this implementation scheme, in order to prevent the barrier layer from undergoing large vertical deformation due to thermal expansion during the high-temperature annealing process, which would cause the barrier layer to fall off, the total thickness of the first barrier layer 10 and the second barrier layer 20 shall not exceed 100 micrometers, preferably not exceeding 10 micrometers.

[0081] Step 5', as follows Figure 1 -e, depending on the application scenario, the gallium oxide material after removing the first barrier layer 10 is subjected to removal and repair treatment on the front and back surfaces of the material in sequence. The etching depth of the side with epitaxial material or the side that has undergone barrier layer patterning process is in the range of 0-1 μm, and the etching depth of the side without epitaxial material is in the range of 0-10 μm. The part of the gallium oxide epitaxial part that retains the first barrier layer before the previous annealing process is removed from the part affected by the annealing process.

[0082] Based on the above steps, a gallium oxide wafer with regionally regulated net carrier concentration can be obtained.

[0083] Example 3:

[0084] This embodiment provides a method for fabricating gallium oxide devices based on high-temperature annealing technology. Regarding the barrier layer, it differs from Embodiments 1 and 2 in that a first barrier layer and a second barrier layer are fabricated on the surface of a gallium oxide wafer. The second barrier layer is located between the surface of the gallium oxide wafer and the first barrier layer. The patterning rate of the second barrier layer is lower than that of the first barrier layer. The materials of the first barrier layer and the second barrier layer are selected according to the temperature of the high-temperature oxygen annealing treatment.

[0085] Based on Example 1, this example adds a second barrier layer as an etching termination layer;

[0086] Based on Example 2, this example adds a second barrier layer. When selecting the material of the second barrier layer, it must simultaneously satisfy the functions of a stripping layer and an etching termination layer.

[0087] Therefore, this embodiment discloses a method for fabricating a gallium oxide device, specifically including a net carrier concentration control method, comprising the following process steps:

[0088] Step 1”: A first barrier layer and a second barrier layer are prepared on the surface of a gallium oxide wafer. The first barrier layer serves to block the high-temperature oxygen atmosphere during the high-temperature oxygen annealing process. The second barrier layer is a release layer and an etching stop layer. For the technical solution of the release layer, please refer to Example 2. This example mainly discloses the technical solution of the etching stop layer.

[0089] Step 2”, a patterning process for controlling gallium oxide impurities is performed on the first barrier layer and the second barrier layer. The process depth of the patterning process does not exceed the thickness of the first barrier layer plus the thickness of the second barrier layer; specifically, it cannot exceed the depth of the second barrier layer, that is, the process depth is greater than or equal to the thickness of the first barrier layer and less than the total thickness of the first barrier layer and the second barrier layer.

[0090] Specifically, using dry etching as a patterning process, a first barrier layer is formed on the surface of a second barrier layer. The first barrier layer is etched using dry etching. When the second barrier layer is etched, the etching rate decreases depending on the material. Therefore, the etching process can be configured with a large etching time redundancy to ensure that this etching step does not affect the surface of the gallium oxide material.

[0091] As can be seen from the above, the technology for etching termination layer disclosed in Example 3 can be combined with Example 1 and Example 2 to form two technical solutions.

[0092] Example 4:

[0093] This embodiment provides a material example for the first and second barrier layers, using SiO2 as the second barrier layer and a Si layer as the first barrier layer. During material selection, Si was found to have superior high-temperature resistance, which can be used to block the oxygen atmosphere during high-temperature annealing. SiO2 is a substance that is easily removed by solutions such as hydrofluoric acid, concentrated sulfuric acid, hydrochloric acid, and nitric acid, which have minimal impact on the surface quality of gallium oxide. It can be used to strip the Si layer after oxidation, and its low coefficient of thermal expansion prevents it from falling off during annealing. The Si layer is grown on the SiO2 film and etched using a dry etching process. However, the etching rate for SiO2 is slower than that for the Si layer, thus achieving a large etching time redundancy to ensure that this etching step does not affect the surface of the gallium oxide material.

[0094] Regarding the etching termination layer, it should be noted that when using a dry etching process to remove the barrier layer, the SiO2 layer thickness should not be less than 5 nm.

[0095] A method for fabricating gallium oxide devices based on high-temperature annealing technology, such as Figure 2 This includes the following steps:

[0096] Step 100, as follows Figure 2 -a:

[0097] The first barrier layer 10 is preferably made of Si, and the second barrier layer 20 is preferably made of SiO2. The SiO2 layer and the Si layer are grown sequentially on the surface of the gallium oxide wafer using PECVD and LPCVD processes, respectively. The Si layer acts as a barrier against the oxygen atmosphere, while the SiO2 layer acts as a stripper layer for the Si layer. The total thickness of the SiO2 and Si layers does not exceed 100 micrometers, preferably not more than 10 micrometers, to prevent the barrier layer from detaching due to large vertical deformation caused by thermal expansion during subsequent high-temperature annealing.

[0098] Considering that the Si layer needs to cover all surfaces of the gallium oxide wafer, the preferred growth method is a growth method such as LPCVD, which can cover the entire surface of the gallium oxide wafer sample in one growth.

[0099] Step 200, as follows Figure 2 -b:

[0100] The Si layer and SiO2 layer are patterned using photolithography or etching techniques. The depth of the patterning process is greater than the thickness of the Si layer but less than the total thickness of the two materials. In other words, for a preset patterned area 10-1, the Si layer in the patterned area is removed while some or all of the SiO2 is retained.

[0101] The Si layer in the patterned process region may not be completely removed in order to adjust the net carrier concentration in that region.

[0102] The SiO2 layer can also be used to adjust the net carrier concentration of the material. Furthermore, the net carrier concentration of the material in the region without the Si barrier layer can be controlled within a certain range by adjusting the thickness of the SiO2 layer.

[0103] Etching techniques include dry etching and wet etching, which involve using etching plasma or etching solution to perform patterning operations on gallium oxide wafers. Dry etching offers higher patterning precision than wet etching, and dry etching is preferred to ensure patterning precision.

[0104] Step 300, as follows Figure 2 -c:

[0105] Gallium oxide wafer samples prepared according to steps 100-200 are placed in a high-temperature device (such as an annealing furnace) for oxygen atmosphere annealing at 600-1700 °C. During annealing, oxygen is continuously supplied, and the oxygen content in the chamber should not be lower than the oxygen content in the air (21%). In addition to the above parameters, the pressure in the high-temperature device chamber is one standard atmosphere. The annealing time includes heating and cooling times. During cooling, the net carrier concentration can be effectively controlled by selecting an appropriate point to stop oxygen supply within the range of 400 °C to the actual annealing temperature. A low net carrier concentration region with localized control appears 30-1;

[0106] Furthermore, in practice, the net carrier concentration can be controlled using the following methods:

[0107] The net carrier concentration is controlled by intermittently stopping the oxygen supply during annealing and by introducing other gases for auxiliary regulation.

[0108] By changing the oxygen concentration, the net carrier concentration of gallium oxide wafer samples can be controlled.

[0109] The net carrier concentration of gallium oxide wafer samples can be controlled by adjusting the gas pressure parameters;

[0110] Generally, even a very short annealing time will affect the net carrier concentration of gallium oxide wafer samples. However, the degree of influence changes with time and temperature. Therefore, the net carrier concentration of gallium oxide wafer samples can be further controlled by adjusting the relationship between time and temperature.

[0111] Step 400, such as Figure 2 -d:

[0112] The gallium oxide wafer sample, after annealing, is placed in a solution capable of etching SiO2 and ultrasonically removed to remove the barrier layer. The second barrier layer serves as a release layer. Since the alkaline solution used to remove Si reacts with gallium oxide, causing damage to the surface quality of the gallium oxide material, a non-alkaline solution is required. However, non-alkaline solutions are not ideal for removing the Si / SiO2 mixed layer after annealing. Therefore, as a preferred embodiment of Example 1, a second barrier layer is added, functioning as a release layer. This ensures that the second barrier layer can react and dissolve rapidly in the non-alkaline solution, solving the problems of the first barrier layer being difficult to remove or the release solution easily damaging the gallium oxide material.

[0113] Step 500 Figure 2 -e:,

[0114] Depending on the application scenario, the gallium oxide material after removing the Si / SiO2 barrier layer is subjected to removal and repair treatment on both the front and back surfaces in sequence. The etching depth of the surface with epitaxial material or the surface with the barrier layer patterned is in the range of 0-1 μm, and the etching depth of the surface without epitaxial material is in the range of 0-10 μm.

[0115] Besides etching, the surface layer can also be removed by uniformly thinning the material through chemical mechanical polishing, achieving a thickness similar to that of etching. Finally, the treated material surface is repaired using wet etching technology, with the reaction rate between the repair solution and the gallium oxide material not exceeding 100 nm / min.

[0116] Example 5:

[0117] Based on the Si / SiO2 barrier layer example of Example 4. (Refer to...) Figure 2 The specific implementation steps are as follows:

[0118] The wafer used in this case is a single-crystal (001) oriented wafer. β Gallium oxide phase, wherein the wafer includes a (001) crystal orientation with a high doping concentration (~10). 18 cm -3 The image shows a gallium oxide substrate and a 9 μm low-doped (~10⁻⁶) layer grown on it using halide vapor phase epitaxy (HVPE). 16 cm -3 single crystal β Gallium oxide epitaxial thin film.

[0119] Figure 2 -a. A 150 nm layer of SiO2 is grown on a gallium oxide thin film using PECVD. This SiO2 simultaneously functions as an etching stop layer, a lift-off layer, and a net carrier concentration control layer. Subsequently, a 400 nm layer of polycrystalline Si is grown using LPCVD as an oxygen atmosphere barrier layer. Due to the characteristics of LPCVD growth, the polycrystalline Si will cover the entire surface of the gallium oxide wafer.

[0120] Figure 2 -b, The barrier layer with epitaxial gallium oxide surface is patterned using photolithography and reactive ion etching (RIE) techniques. The patterning process involves selecting the region where the net carrier concentration needs to be changed, removing the Si barrier layer in this region, or removing part of the SiO2 group as an error range, or as a requirement for adjusting the impurity concentration.

[0121] Figure 2-c, the patterned gallium oxide wafer is placed in an annealing furnace for annealing. The oxygen flow rate is 3000 sccm, the chamber pressure is one standard atmosphere, the chamber temperature is controlled at 1100 ℃, the heating time is 2 hours, and the cooling time is 2.5 hours to 500 ℃. Oxygen is continuously supplied during the annealing process, and the oxygen supply is stopped when the temperature drops to 500 ℃.

[0122] Figure 2 -d, After annealing, the gallium oxide wafer is ultrasonically cleaned in HF acid for 20 min to remove the SiO2 / Si barrier layer material. It is then washed sequentially with acetone, isopropanol, and deionized water.

[0123] Figure 2 -e, Inductively Coupled Plasma Etching (ICP-E) is used to sequentially etch the back and front sides (with epitaxial layers) of the wafer. The front side is etched at 600 nm, and the back side at 1 μm. Chemical Mechanical Polishing (CMP) can be used as an alternative. After etching, the wafer is immersed in a piranha solution (H₂SO₄:H₂O₂ = 3:1) for 15 min to repair etching defects. The etching process should be selectively implemented based on the actual application scenario and is not restricted; this description is for reference only.

[0124] Example 6:

[0125] Based on the descriptions in Examples 1-5 above, the core idea of ​​this solution and the specific implementation methods based on this core idea are clearly understood. This example further illustrates a method for fabricating gallium oxide devices, specifically a method for fabricating anode edge terminals, as described above. Figure 3 The photoresist is used as the etching capping layer in the patterning process. The specific steps are as follows:

[0126] Step 3-a: Prepare a gallium oxide wafer, which includes a gallium oxide substrate 40 and a gallium oxide epitaxial layer 30;

[0127] Step 3-b: A SiO2 layer 20 is grown on the surface of the gallium oxide epitaxial layer for the purpose of removing the Si layer and / or for the purpose of etching a stop layer.

[0128] Step 3-c: Growing Si layer 10 (polycrystalline silicon layer) on the surface of SiO2 layer and all surfaces of gallium oxide wafer to block high-temperature oxygen atmosphere, which can be done using LPCVD process;

[0129] Step 3-d: Spin-coat photoresist 50 onto the Si layer surface at one end of the gallium oxide epitaxial layer for patterning process;

[0130] Step 3-e: Expose and develop the area where the net carrier concentration needs to be changed to pattern the photoresist;

[0131] Step 3-f: Use an etching process to remove the barrier layer Si layer of the patterned part and wash away the photoresist 50.

[0132] Step 3-g: Annealing treatment for 8 hours, annealing atmosphere: 1100℃, one standard atmosphere, oxygen flow rate 3000 sccm, annealing equipment cavity space 0.04 m. 3 At this point, the original Si layer is annealed in an oxygen atmosphere and becomes a Si / SiO2 mixture layer; in which the gallium oxide epitaxial region shows different regions with low net carrier concentration 30-1;

[0133] Step 3-h: Use BOE solution to wet remove the barrier layer. Here, the barrier layer refers to the Si / SiO2 mixture layer after the return process, as well as the SiO2 layer.

[0134] Step 3-i: ICP etching is used to etch 1 μm on the back side of the gallium oxide wafer;

[0135] Step 3-j: ICP etching is used to etch 600 nm on the back side of the gallium oxide wafer, followed by immersion in a piranha solution for 10-20 min.

[0136] Step 3-k: On the back side of the gallium oxide wafer, i.e. the gallium oxide substrate, an ohmic contact electrode Ti / Au 60 is grown using physical vapor deposition.

[0137] Step 3-1: Spin-coat photoresist on the front side of the gallium oxide wafer, i.e., the surface of the gallium oxide epitaxial layer;

[0138] Step 3-m involves exposing and developing the photoresist to pattern it. Unlike the patterning in step 3-e, this step is used to grow electrodes. The patterning region in this step is designed based on the low net carrier concentration region 30-1 formed in step 3-g.

[0139] Step 3-n: A long Schottky electrode 70 is generated using physical vapor deposition (PVD).

[0140] Step 3-o: Remove excess metal from the Schottky electrode and clean the photoresist.

[0141] Simultaneously, gallium oxide wafers with epitaxial thin films can be replaced with gallium oxide substrates without epitaxial thin films, or with amorphous, polycrystalline, or single-crystal gallium oxide materials grown on other substrates (such as sapphire, Si, GaN, SiC, etc., or substrates with epitaxial layers such as GaN substrates with AlGaN grown), while the rest of the process remains unchanged. Examples of physical vapor deposition techniques mentioned above include electron beam evaporation.

[0142] Example 7:

[0143] Based on Examples 1-5 above, this embodiment provides a new method for fabricating gallium oxide devices, specifically a method for isolating semiconductor devices, as described above. Figure 4 The photoresist is used as the etching capping layer in the patterning process (other materials can also be used). The specific steps are as follows:

[0144] Step 4-a: Prepare a gallium oxide wafer, which includes a gallium oxide substrate 40 and a gallium oxide epitaxial layer 30;

[0145] Step 4-b: A SiO2 layer 20 is grown on the surface of the gallium oxide epitaxial layer for the purpose of removing the Si layer and / or for the purpose of etching a stop layer.

[0146] Step 4-c: Growing Si layer 10 (polycrystalline silicon layer) on the surface of SiO2 layer and all surfaces of gallium oxide wafer to block high-temperature oxygen atmosphere, which can be done using LPCVD process;

[0147] Step 4-d: Spin-coat photoresist onto the Si layer surface at one end of the gallium oxide epitaxial layer for patterning process;

[0148] Step 4-e: Expose and develop the area on the front side of the wafer where the net carrier concentration needs to be changed to pattern the photoresist.

[0149] Step 4-f involves using an etching process to remove the barrier layer Si layer from the patterned area, specifically the area on the wafer used for device fabrication, as shown in the figure, which is the middle part of a gallium oxide wafer, and then washing away the photoresist.

[0150] Step 4-g: Spin-coat photoresist onto the Si layer surface at one end of the gallium oxide substrate for patterning process;

[0151] Step 4-h, similar to step 4-e, exposes and develops the area on the back of the wafer where the net carrier concentration needs to be changed to pattern the photoresist, and the area on the wafer used for device fabrication.

[0152] Step 4-i: Use etching technology to remove the back barrier Si layer and wash away the photoresist; at this point, the Si layer on both the front and back sides of the gallium oxide wafer has been patterned, that is, the middle area is used as the selective control position.

[0153] Step 4-j: Annealing treatment for 8 hours, annealing atmosphere: 1150 ℃, one standard atmosphere, oxygen flow rate 3000 sccm, annealing equipment cavity space 0.04 m. 3 At this point, the original Si layer is annealed in an oxygen atmosphere and becomes a Si / SiO2 mixture layer; low net carrier concentration regions 30-1 appear in different regions in both the gallium oxide epitaxial region and the substrate region.

[0154] Step 4-k: Use BOE solution to wet remove the barrier layer. Here, the barrier layer refers to the Si / SiO2 mixture layer after the return process, as well as the SiO2 layer.

[0155] Step 4-i: ICP etching is used to etch the back side of the gallium oxide wafer to 1 μm; ICP etching is used to etch the back side of the gallium oxide wafer to 600 nm, and then the wafer is immersed in piranha solution for 10-20 min to repair the etching damage on the wafer surface.

[0156] The single annealing process has its limitations. To obtain a large-scale range of net carrier concentration control, the wafer obtained in Example 6 needs to be repeated, with the annealing area being the same location. Before the second annealing, the final surface layer removal process in Example 6 is a necessary step.

[0157] Other techniques, such as localized passivation of semiconductor surfaces and conductivity modulation, as well as the design of current blocking layers within vertical MOSFET devices, can be derived from the above embodiments. It is important to note that the annealing time for each application needs to be adjusted according to specific requirements. Other techniques include, as mentioned earlier, changing the thickness of the SiO2 layer, the thickness of the polycrystalline Si layer, the annealing temperature, oxygen concentration, and cavity pressure to align with the design method. For example, to obtain a lower net carrier concentration and a deeper low net carrier concentration region, one or more methods can be used, such as increasing the annealing time, increasing the oxygen concentration, increasing the pressure, and reducing the SiO2 thickness. Conversely, the trend in using these control methods is the opposite.

[0158] Example 8:

[0159] This embodiment provides a process for a barrier layer structure to function during high-temperature impurity activation in ion implantation technology. A net carrier concentration control process based on ion implantation technology is disclosed, such as... Figure 5 ,

[0160] Step 5-a: Prepare a gallium oxide wafer, which includes a gallium oxide substrate 40 and a gallium oxide epitaxial layer 30;

[0161] Step 5-b, complete the following processes: 1) Grow a SiO2 layer 20 on the surface of the gallium oxide epitaxial layer for the purpose of stripping the Si layer and / or for the purpose of etching stop layer; 2) Grow a Si layer 10 (polycrystalline silicon layer) on the surface of the SiO2 layer and on all surfaces of the gallium oxide wafer to block the high-temperature oxygen atmosphere, which can be done using LPCVD process; 3) Spin-coat a photoresist 50 on the Si layer surface at one end of the gallium oxide epitaxial layer for the purpose of patterning process;

[0162] Step 5-c: Expose and develop the area where the net carrier concentration needs to be changed to pattern the photoresist.

[0163] Step 5-d: The barrier layer Si layer and SiO2 layer 20 of the patterned part are removed by etching process;

[0164] Step 5-e: Ions are implanted into the gallium oxide epitaxial layer 30 using ion implantation technology to form an ion implantation region 60. The implanted ions are acceptor impurities (Mg or N); they can also be donor impurities.

[0165] Step 5-f: Remove the photoresist;

[0166] Step 5-g: Annealing treatment for 8 hours, annealing atmosphere: 1100℃, one standard atmosphere, oxygen flow rate 3000 sccm, annealing equipment cavity space 0.04 m. 3 Under high-temperature annealing conditions, the ion implantation region 60 forms the impurity-activated implantation region 70, and the gallium oxide substrate 40 and the gallium oxide epitaxial layer 30 form a high-resistivity region 80 due to the influence of oxygen annealing.

[0167] Step 5-h: Remove the barrier layer, which refers to the annealed Si / SiO2 mixture layer and the SiO2 layer.

[0168] Step 5-i: ICP etching is used to remove the affected gallium oxide wafer surface layer.

[0169] In this embodiment, currently, after ion implantation of gallium oxide materials, impurity activation and lattice repair typically use annealing in a nitrogen or argon atmosphere. Oxygen atmosphere annealing itself affects the net carrier concentration of the material, so it has not been suitable as an annealing atmosphere for impurity implantation activation. The oxygen atmosphere barrier layer structure proposed in this invention can effectively isolate the influence of oxygen on the net carrier concentration of gallium oxide materials, making it possible to use oxygen atmosphere annealing to activate implanted impurities. By implanting acceptor or donor impurities into local areas of a gallium oxide wafer and covering the non-implanted areas on the wafer with a barrier layer, it is expected that while repairing defects caused by high-energy particles, the net carrier concentration of the gallium oxide wafer can be more precisely controlled, giving full play to the advantages of both technologies.

[0170] In the above embodiments, the descriptions of each embodiment have different focuses. Parts not described in detail in a certain embodiment can be referred to in the relevant descriptions of other embodiments. The process steps discussed in the above embodiments are merely preferred implementation methods used to illustrate the feasibility of the structure described in this application and do not limit the scope of the invention. Other process methods or sequences used to implement the concentration control method of this invention are also within the scope of protection of this invention. The above descriptions are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for fabricating gallium oxide devices based on high-temperature annealing technology, characterized in that, Includes the following steps: A barrier layer is prepared on the surface of a gallium oxide wafer, which serves to block the oxygen atmosphere during high-temperature oxygen annealing. A patterning process is performed on the barrier layer for the purpose of controlling gallium oxide wafer impurities, wherein the process depth of the patterning process is less than the thickness of the barrier layer. The gallium oxide wafers treated as described above were then annealed in an oxygen atmosphere. Remove the barrier layer from the annealed gallium oxide wafer; Remove the surface layer of the gallium oxide wafer from which the barrier layer has been stripped; The method for preparing a barrier layer on the surface of a gallium oxide wafer includes the following steps: A first barrier layer and a second barrier layer are prepared on the surface of a gallium oxide wafer. The second barrier layer is located between the gallium oxide wafer surface and the first barrier layer. The second barrier layer isolates the gallium oxide wafer surface and the first barrier layer. The second barrier layer is a release layer. The patterning rate of the second barrier layer is lower than that of the first barrier layer. The net carrier concentration can be controlled by adjusting the individual thickness or the total thickness of the first and second barrier layers. Alternatively, by adjusting the thickness of the second barrier layer, the net carrier concentration in the region not covered by the first barrier layer after patterning can be controlled.

2. The method for fabricating gallium oxide devices based on high-temperature annealing technology according to claim 1, characterized in that, The materials for the first and second barrier layers are selected based on the temperature of the high-temperature oxygen annealing treatment.

3. The method for fabricating gallium oxide devices based on high-temperature annealing technology according to claim 1, characterized in that, The barrier layer is patterned using photolithography or etching.

4. The method for fabricating gallium oxide devices based on high-temperature annealing technology according to claim 1, characterized in that, The barrier layer is fabricated on all surfaces of the gallium oxide wafer.

5. The method for fabricating gallium oxide devices based on high-temperature annealing technology according to claim 1 or 2, characterized in that, The net carrier concentration can be controlled by one or more parameters, including annealing temperature, oxygen concentration, and annealing equipment chamber pressure.

6. The method for fabricating gallium oxide devices based on high-temperature annealing technology according to claim 1, characterized in that, The barrier layer is patterned using a dry etching method, wherein the etching rate of the second barrier layer is less than that of the second barrier layer.

7. The method for fabricating gallium oxide devices based on high-temperature annealing technology according to claim 1, characterized in that, The material of the barrier layer is selected according to the following requirements: The melting point is higher than the annealing temperature; It can be removed by solutions with slow reaction rates on the surface of gallium oxide materials.

8. A gallium oxide device, characterized in that, This includes gallium oxide epitaxial layers and / or gallium oxide substrates that have undergone regional regulation using the gallium oxide device fabrication method based on high-temperature annealing technology as described in any one of claims 1-7.

9. A method for fabricating a gallium oxide device, characterized in that, The gallium oxide device fabrication method based on high-temperature annealing technology according to any one of claims 1-7, after the step of removing the surface layer of the gallium oxide wafer with the barrier layer stripped, further includes the step of: Ohmic contact electrodes are grown on the back side of the gallium oxide wafer, i.e., the gallium oxide substrate layer; Photoresist is spin-coated on the front side of the gallium oxide wafer, i.e., the surface of the gallium oxide epitaxial layer; The photoresist is exposed and developed to pattern it for use in electrode growth. The patterned region in this step is designed in the region of low net carrier concentration. Long Schottky electrodes are generated using physical vapor deposition (PVD) technology. Remove excess metal from the Schottky electrode and clean the photoresist.

10. A method for fabricating a gallium oxide device, characterized in that, The method for fabricating gallium oxide devices based on high-temperature annealing technology according to any one of claims 1-7 further includes the following steps: The regions on the front and back sides of the wafer where the net carrier concentration needs to be changed are patterned, specifically the areas on the wafer used for device fabrication.

11. A method for fabricating a gallium oxide device, characterized in that, The gallium oxide device fabrication method based on high-temperature annealing technology according to any one of claims 1-7 includes the following steps after removing the barrier layer of the patterned portion: Ion implantation technology is used to implant the required ions into the gallium oxide epitaxial layer to form an ion implantation region. The implanted ions are acceptor impurities or donor impurities. After the above treatment, the gallium oxide wafer is annealed in an oxygen atmosphere. Under high temperature annealing, the ion implantation region is formed after the implanted impurities are activated, and the gallium oxide substrate and gallium oxide epitaxial layer are formed due to the influence of oxygen annealing. Remove the barrier layer from the annealed gallium oxide wafer; Remove the surface layer of the gallium oxide wafer from which the barrier layer has been stripped.

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