Back contact photovoltaic cell and preparation method thereof
By forming arc-shaped grooves on the back of TBC cells and preparing N+ and P+ polycrystalline silicon, the process steps are simplified, solving the problems of high equipment cost, low capacity and low bifaciality of TBC cell production, and improving photoelectric conversion efficiency and capacity.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- JOLYWOOD (TAIZHOU) SOLAR TECHNOLOGY CO LTD
- Filing Date
- 2026-01-28
- Publication Date
- 2026-05-15
Smart Images
Figure CN122054734A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of photovoltaic technology, specifically to a back-contact photovoltaic cell and its preparation method. Background Technology
[0002] With the continuous development of photovoltaic cell technology, crystalline silicon cells have entered the production and application stage; however, further exploration is needed to improve efficiency. As shown in publication number CN118888627A, the TBC cell is a novel crystalline silicon cell structure developed based on TOPCon (tunneling oxide passivated contact) crystalline silicon cell technology. It places the emitter, surface field, and metal electrodes on the back of the cell in an interdigitated arrangement. The N+ emitter (e.g., N+ polycrystalline silicon with a phosphorus-doped layer) and P+ emitter (e.g., P+ polycrystalline silicon with a phosphorus-doped layer) of the TBC cell are both located on the back of the crystalline silicon cell, and the N+ and P+ emitters are interdigitated. The front surface of the TBC cell has no electrode grid lines obstructing the light, thus maximizing the utilization of incident light, reducing optical losses, and providing a larger effective power generation area, resulting in higher photoelectric conversion efficiency. Furthermore, the solid-color front appearance of the TBC cell is more aesthetically pleasing and conforms to popular tastes, giving it greater competitiveness in the market.
[0003] Currently, laser processing is a relatively mature technology for TBC (Temperature-Based Cells). However, this process is not only costly in terms of equipment, but it also involves selectively removing either the N+ or P+ emitter based on a pre-defined pattern. Therefore, the actual area of the N+ emitter (located in the N-region), P+ emitter (located in the P-region), and GAP (gap region) on the back of the silicon wafer is limited by the wafer size, and the area ratio between different regions is also affected by equipment precision. In crystalline silicon solar cells, the emitter area directly affects the cell's series resistance, short-circuit current, and open-circuit voltage, ultimately impacting the photoelectric conversion efficiency.
[0004] To address these issues, many manufacturers and researchers have opted for small-spot lasers in their laser processing to improve machining accuracy and reduce the width of the gap region, thereby increasing the emitter area ratio. However, small-spot lasers not only significantly reduce the production capacity of TBC cells, but the excessively small gap region width also leads to a decrease in the parallel resistance of the TBC cells, resulting in increased leakage current and ultimately hindering the improvement of the TBC cell's photoelectric conversion efficiency. Furthermore, during the TBC cell development phase, adjusting the width ratio (or area ratio) of the N-region of the N+ emitter, the P-region of the P+ emitter, and the gap region often requires replacing the metallization screen, further increasing the development cost of TBC cells.
[0005] In addition, TBC batteries generally suffer from low bifaciality. This is because all electrodes of a BC battery (back contact battery) are concentrated on the back of the battery, which significantly increases the back-side light-blocking area. This limits the light absorption and power generation capacity of the back side, resulting in low bifaciality and hindering the improvement of the battery's photoelectric conversion efficiency. Summary of the Invention
[0006] The purpose of this invention is to overcome the shortcomings of existing technologies and provide a back-contact photovoltaic cell and its fabrication method. This simplifies the current production process of back-contact photovoltaic cells (such as TBC cells), increases production capacity, reduces the production and development costs of TBC cells, and further optimizes the area ratio of the N+ emitter (e.g., N+ polycrystalline silicon, located in the N-region), P+ emitter (e.g., P+ polycrystalline silicon, located in the P-region) and GAP region of the TBC cell (increasing the actual area of the N+ and P+ emitters), and improves the bifaciality of the TBC cell. It solves the problems of high equipment cost, low bifaciality (the area ratio of the N+ emitter, P+ emitter, and GAP region of the TBC cell is limited by the silicon wafer size and the precision of the laser equipment), complex fabrication processes for the N+ and P+ emitters, and low production capacity of current TBC cell laser process routes.
[0007] Based on this, the present invention discloses a method for preparing a back-contact photovoltaic cell, comprising the following preparation steps: S1. Use an infrared laser to perform laser grooving on the N-region and P-region on the back of the silicon wafer, so as to form a first arc-shaped groove and a second arc-shaped groove in the N-region and P-region respectively. S2. After removing the laser-damaged layer, deposit an amorphous silicon layer on the back side of the silicon wafer; S3. Print N-type doped paste and P-type doped paste in the first and second arc grooves on the back of the amorphous silicon layer, respectively. S4. Perform oxygen annealing treatment to dope and diffuse the amorphous silicon layer at the first arc groove and the second arc groove with N-type doped paste and P-type doped paste respectively, so that the amorphous silicon layer at the first arc groove and the second arc groove is crystallized into N+ polycrystalline silicon and P+ polycrystalline silicon respectively, and a protective layer is formed by annealing on the back of N-type doped paste and P-type doped paste. S5. After removing the protective layer, N-type doped paste and P-type doped paste, a passivation film is deposited on the surface of the silicon wafer, and the back side of the silicon wafer is metallized to prepare N-type electrodes and P-type electrodes that respectively contact N+ polycrystalline silicon and P+ polycrystalline silicon.
[0008] Preferably, the back side of the silicon wafer includes a plurality of N regions for the preparation of N+ polycrystalline silicon, a plurality of P regions for the preparation of P+ polycrystalline silicon, and a plurality of GAP regions that separate the N regions from the P regions. In step S1, the number of first arc grooves opened in a single N region on the back side of the silicon wafer is an integer greater than or equal to 1, and the total width of the first arc grooves opened in a single N region is less than or equal to the width of the N+ polysilicon in a single N region; the number of second arc grooves opened in a single P region on the back side of the silicon wafer is an integer greater than or equal to 1, and the total width of the second arc grooves opened in a single P region is less than or equal to the width of the P+ polysilicon in a single P region.
[0009] More preferably, in step S1, the radius of the slotted spot of the infrared laser is 50~1000μm, and the energy density is 0.1~2J / cm². 2 The first and second arc-shaped grooves have a groove depth of less than or equal to 50 μm, a groove spacing of 100~1000 μm, and a groove curvature of less than or equal to 20.00*10. -3 .
[0010] Preferably, in step S2, the laser-damaged layer on the silicon wafer surface is removed by wet cleaning; The amorphous silicon layer is an intrinsic amorphous silicon layer with a thickness of 100~400 nm. The amorphous silicon layer is deposited using a low-pressure chemical vapor deposition equipment at a deposition temperature of 500~700℃. Step S2 further includes: before depositing the amorphous silicon layer, preparing a tunneling oxide layer on the back surface of the silicon wafer.
[0011] Preferably, in step S3, screen printing is used to print the N-type doped paste and the P-type doped paste, wherein the N-type doped paste is a phosphorus-containing doped paste and the P-type doped paste is a boron-containing doped paste.
[0012] Preferably, in step S4, the temperature of the aerobic annealing is 800~950℃, and the annealing time is 0.5~4h.
[0013] Preferably, in step S5, the protective layer, N-type doped paste and P-type doped paste are removed by wet cleaning so as to expose the back surface of the silicon wafer in the GAP area, the N+ polysilicon back surface at the first arc groove and the P+ polysilicon back surface at the second arc groove. The sintering temperature for metallization is 700~860℃, and the sintering belt speed is 7000~15000 mm / min.
[0014] More preferably, in step S5, passivation films are deposited on both the front and back sides of the silicon wafer; the front passivation film includes a front aluminum oxide layer located on the front surface of the silicon wafer, and a front silicon nitride layer located on the front surface of the front aluminum oxide layer; the back passivation film includes a back aluminum oxide layer located on the back surface of the silicon wafer in the GAP area, the back surface of N+ polysilicon, and the back surface of P+ polysilicon, and a back silicon nitride layer located on the back surface of the back aluminum oxide layer.
[0015] Preferably, before step S1, the process further includes: double-sided cleaning and texturing of the silicon wafer.
[0016] The present invention also discloses a back-contact photovoltaic cell, which is prepared by the back-contact photovoltaic cell preparation method described above in the present invention.
[0017] Compared with the prior art, the present invention has at least the following beneficial effects: 1. The present invention discloses a method for fabricating a back-contact photovoltaic cell, which replaces the existing planar N+ polycrystalline silicon and P+ polycrystalline silicon with curved N+ polycrystalline silicon. Under the same width, the curved surface has a larger exposed area. This can effectively increase the area ratio of N+ polycrystalline silicon and P+ polycrystalline silicon while ensuring the predetermined width of the GAP area (to avoid the risk of reduced parallel resistance and leakage). This is beneficial to improving the carrier collection efficiency and the back-side light-receiving area, reducing the series resistance, and further improving the photoelectric conversion efficiency and bifaciality of the back-contact photovoltaic cell.
[0018] 2. Compared to rectangular grooves like those in CN118888627A, the continuous arc-shaped grooves of the first and second arc-shaped grooves have no corners, which is more conducive to improving the density and uniformity of the coating (such as N+ polysilicon, P+ polysilicon, Al2O3 layer, SiN). x The use of multiple layers (such as film layers) can effectively reduce film defects, improve the passivation effect of the battery, reduce carrier recombination, lower series resistance, and further improve the photoelectric conversion efficiency of back-contact photovoltaic cells such as TBC cells. Furthermore, the use of continuous laser processing in the laser grooving process for preparing the first and second arc-shaped grooves also helps reduce internal stress and decrease the fragmentation rate.
[0019] 3. After laser grooving and wet cleaning, N+ polycrystalline silicon and P+ polycrystalline silicon can be prepared by sequentially performing one amorphous silicon layer deposition, printing doping paste, and one oxygen annealing. This greatly simplifies the process steps and reduces production costs. It eliminates the need for small-spot lasers and is beneficial for increasing the production capacity of back-contact photovoltaic cells.
[0020] 4. Furthermore, it eliminates the need for costly green-skin laser equipment, reducing overall costs. The graphic pattern of the red laser can be adjusted based on existing metallization drawings. The effective area of N+ and P+ polycrystalline silicon can also be adjusted by modifying the grooving spot radius, arc depth, and grooving curvature, reducing the cost of replacing metallization screens and offering high compatibility. Red lasers have higher energy, larger spot size, and grooving speeds far exceeding those of green-skin lasers, which is beneficial for increasing the production capacity of back-contact photovoltaic cells and demonstrates good versatility. Attached Figure Description
[0021] Figure 1 This is a process flow diagram of a method for preparing a back-contact photovoltaic cell according to the present invention.
[0022] Figure 2 This is a schematic diagram of the cross-sectional structure of the original silicon wafer used in step 1 of the preparation method of the present invention.
[0023] Figure 3 This is a schematic diagram of the cross-sectional structure of the silicon wafer after cleaning and texturing in step 1 in the preparation method of the present invention.
[0024] Figure 4 This is a schematic diagram of the cross-sectional structure of the silicon wafer after laser grooving in step 2 of the preparation method of the present invention (the number of arc grooves in a single N-region and P-region is 1).
[0025] Figure 5 This is a schematic diagram of the cross-sectional structure of the silicon wafer after laser grooving in step 2 of the preparation method of the present invention (the number of arc grooves in a single N-region and P-region is multiple).
[0026] Figure 6 This is a schematic diagram of the cross-sectional structure of the silicon wafer after wet cleaning in step 3 of the preparation method of the present invention.
[0027] Figure 7 This is a schematic diagram of the cross-sectional structure of the silicon wafer after the deposition of the ia-Si layer in step 4 of the preparation method of the present invention.
[0028] Figure 8 This is a schematic diagram of the cross-sectional structure of the silicon wafer after the doping paste is printed in step 5 in the preparation method of the present invention.
[0029] Figure 9 This is a schematic diagram of the cross-sectional structure of the silicon wafer after oxygen annealing in step 6 of the preparation method of the present invention.
[0030] Figure 10 This is a schematic diagram of the cross-sectional structure of the silicon wafer after the removal of the doping paste and protective layer in step 7 of the preparation method of the present invention.
[0031] Figure 11 This is a schematic diagram of the cross-sectional structure of the silicon wafer after double-sided growth of Al2O3 layers in step 8 of the preparation method of the present invention.
[0032] Figure 12 In the preparation method of this invention, the silicon wafer undergoes double-sided SiN growth in step 9. x A schematic diagram of the cross-sectional structure behind the layer.
[0033] Figure 13 This is a schematic diagram of the cross-sectional structure of a back-contact photovoltaic cell prepared according to the present invention.
[0034] Figure 14This is a schematic diagram showing the calculation of the curved surface dimensions after slotting with different spot radii in Embodiments 1 and 2 of the present invention.
[0035] Reference numerals: 1. Original silicon wafer; 2. Laser-damaged layer; 31. First arc groove; 32. Second arc groove; 4. Al2O3 layer; 5. Doping paste; 51. N-type doped paste; 52. P-type doped paste; 61. N+ polysilicon; 62. P+ polysilicon; 63. Protective layer; 7. Al2O3 layer; 8. SiN x Layer 8; N-type electrode 91; P-type electrode 92. Detailed Implementation
[0036] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.
[0037] A method for preparing a back-contact photovoltaic cell according to the present invention, see [link to relevant documentation]. Figure 1 It includes the following preparation steps: Step 1, Cleaning and texturing: For the original silicon wafer 1 (e.g. Figure 2 (As shown) Double-sided cleaning and texturing are performed to form a textured surface on both the front and back surfaces of the original silicon wafer 1 (as shown). Figure 3 (As shown).
[0038] In step 1, the solution used for cleaning the silicon wafer is a mixed solution consisting of a NaOH solution with a mass fraction of 0.5~2.5 wt.% and an H2O2 solution with a mass fraction of 0.05~1.5 wt.%. The cleaning temperature is 60~70℃ and the cleaning time is 100~300s.
[0039] In step 1, the solution used for texturing silicon wafers is a mixed solution of NaOH solution with a mass fraction of 1.5~5.0 wt.% and alkaline texturing additive with a mass fraction of 0.02~3.0 wt.%, the texturing temperature is 70~85℃, and the texturing time is 100~400s.
[0040] Step 2, Laser Grooving: The back side of the silicon wafer includes several pre-defined N+ emitters (e.g., N+ polysilicon 61) N-regions, several pre-defined P+ emitters (e.g., P+ polysilicon 62) P-regions, and several GAP regions (spacers) separating the N-regions from the P-regions. An infrared laser device is used to perform laser grooving at the pre-defined N-region and P-region positions on the back side of the silicon wafer, forming a first arc-shaped groove 31 at the N-region position and a second arc-shaped groove 32 at the P-region position (e.g., P+ polysilicon 62). Figure 4-5 (As shown).
[0041] In step 2, the number of first arc-shaped grooves 31 formed in a single N-region on the back side of the silicon wafer is an integer greater than or equal to 1; the number of second arc-shaped grooves 32 formed in a single P-region on the back side of the silicon wafer is also an integer greater than or equal to 1. The total width of the first arc-shaped grooves 31 formed in a single N-region on the back side of the silicon wafer is less than or equal to the width of the N+ emitter corresponding to a single N-region; the total width of the second arc-shaped grooves 32 formed in a single P-region on the back side of the silicon wafer is less than or equal to the width of the P+ emitter corresponding to a single P-region.
[0042] In step 2, the radius of the slotted spot of the infrared laser device is not less than 50 μm (e.g., the radius of the slotted spot is 50~1000 μm), and the energy density is 0.1~2 J / cm². 2 The groove depth should not exceed 50μm (i.e., the groove depth is greater than 0μm and less than or equal to 50μm), the groove spacing (referring to the center distance between two adjacent arc-shaped grooves in a single N-region or a single P-region, i.e., the center distance between two adjacent grooved light spots in a single N-region or a single P-region) should not be less than 100μm (e.g., the groove spacing is 100~1000μm), and the groove curvature should be less than or equal to 20.00*10 -3 (That is, the groove curvature is greater than 0 and less than or equal to 20.00*10) -3 ).
[0043] In practice, the infrared laser equipment used for laser grooving is commercially available equipment that meets the following requirements: it is a red laser device capable of emitting lasers that cause physical damage such as grooving, cutting, and film opening, and the infrared laser device has, but is not limited to, marking and positioning functions such as marking. In step 2, the laser grooving process conditions of the infrared laser equipment include: laser power of 1~340W, laser speed of 30000~80000mm / s, and laser frequency of 500~800KHz.
[0044] Step 3, Wet Cleaning: Perform wet cleaning on the silicon wafer to remove the laser-damaged layer 2 (e.g., ...) on the silicon wafer surface. Figure 6 (As shown).
[0045] In step 3, the etching solution used for wet cleaning is a mixture of 0.5~2.0 wt.% NaOH solution and 0.5~1.5 wt.% of a specific alkaline etching additive for etching silicon oxide / poly Si. The additive in the etching solution used for wet cleaning has a good removal effect on silicon oxide, poly Si (polycrystalline silicon), and amorphous silicon.
[0046] Step 4, ia-Si layer 4 (intrinsic amorphous silicon layer) deposition: An ia-Si layer 4 is deposited on the entire back surface of the silicon wafer after the process in step 3. Therefore, an ia-Si layer 4 is deposited on the back surface of both the first arc groove 31 and the second arc groove 32 of the silicon wafer (e.g., Figure 7(As shown).
[0047] In step 4, the thickness of the ia-Si layer 4 is 100~400nm, and it is deposited using an LPCVD (low-pressure chemical vapor deposition) device at a deposition temperature of 500~700℃.
[0048] Preferably, before depositing the ia-Si layer 4, a tunneling oxide layer can be grown on the back surface of the silicon wafer after step 3, and then the ia-Si layer 4 can be deposited.
[0049] Step 5, Doping Paste 5 Printing: N-type doping paste 51 (e.g., phosphorus doping paste) and P-type doping paste 52 (e.g., boron doping paste) are printed in the first arc groove 31 and the second arc groove 32 on the back side of the ia-Si layer 4, respectively. Figure 8 (As shown).
[0050] In step 5, the P-type doped paste 52 contains the following components: boron oxide (10-20 wt.%), borosilicate glass powder (10-20 wt.%, 400 mesh), ammonium bifluoride (2-10 wt.%), calcium hydroxide (20-45 wt.%), aluminum fluoride (5-15 wt.%), alumina (10-20 wt.%, 100 mesh), ethyl cellulose (5-10 wt.%), and sodium chloride (5-10 wt.%). The N-type doped paste 51 contains the following components: phosphorus pentoxide (25-50 wt.%), phosphosilicate glass powder (15-40 wt.%, 400 mesh), ammonium bifluoride (2-10 wt.%), sodium chloride (5-10 wt.%), sodium fluoride (5-10 wt.%), alumina (10-20 wt.%, 100 mesh), and ethyl cellulose (5-10 wt.%).
[0051] Step 6, Oxygen Annealing: The silicon wafer processed in Step 5 is subjected to oxygen annealing, which causes the N-type doped paste 51 to dope and diffuse into the ia-Si layer 4 at the first arc groove 31, and the ia-Si layer 4 at the first arc groove 31 crystallizes into N+ poly Si (N+ polysilicon 61). Similarly, the P-type doped paste 52 is used to dope and diffuse into the ia-Si layer 4 at the second arc groove 32, and the ia-Si layer 4 at the second arc groove 32 crystallizes into P+ poly Si (P+ polysilicon 62). The back surfaces of the ia-Si layer 4 in the GAP area (corresponding to the area without printed doped paste), as well as the N-type doped paste 51 and P-type doped paste 52, are annealed to form a protective layer 63 (e.g., ...). Figure 9 (As shown).
[0052] In step 6, the temperature for aerobic annealing is 800~950℃, and the annealing time is 0.5~4h.
[0053] Step 7: Remove doping paste 5 and protective layer 63: Perform wet cleaning on the silicon wafer processed in Step 6 to etch and remove the protective layer 63 on the back of the silicon wafer, and clean and remove the P-type doping paste 52 and N-type doping paste 51 on the back of the silicon wafer. After Step 7, the back surface of the silicon wafer in the GAP area, the back surface of the N+ polysilicon 61 at the first arc groove 31 (corresponding to the N area), and the back surface of the P+ polysilicon 62 at the second arc groove 32 (corresponding to the P area) will all be exposed (e.g., Figure 10 (As shown).
[0054] In step 7, the etching solution used is a 1.5~3.5 wt.% NaOH solution, the cleaning temperature is 70~85℃, and the cleaning time is 200~400s.
[0055] Step 8, Double-sided growth of Al2O3 layer 7: An Al2O3 layer 7 is grown on both the front and back sides of the silicon wafer after step 7 (e.g., Figure 11 (As shown). Specifically, the back Al2O3 layer 7 is grown on the back surface of the silicon wafer in the GAP region, the back surface of N+ polysilicon 61, and the back surface of P+ polysilicon 62.
[0056] In step 8, the double-sided Al2O3 layer 7 is grown using the ALD (atomic layer deposition) process, and the thickness of the Al2O3 layer 7 is 3~9nm.
[0057] Step 9: Double-sided SiN growth x Layer 8 (Silicon Nitride Layer): A SiN layer is grown on both the front surface of the front Al2O3 layer 7 and the back surface of the back Al2O3 layer 7. x Layer 8 (e.g.) Figure 12 (As shown).
[0058] In step 9, SiN x Layer 8 has a thickness of 65~75nm and a refractive index of 2~2.2%.
[0059] Step 10, Electrode Printing and Sintering: Metal paste is printed at localized locations in the corresponding N-regions and P-regions of the back silicon nitride layer; then sintering is performed to make ohmic contact between the metal paste in the N-region and the N+ polycrystalline silicon 61 to form an N-type electrode 91, while the metal paste in the P-region makes ohmic contact between the metal paste in the P-region and the P+ polycrystalline silicon 62 to form a P-type electrode 92 (e.g., ...). Figure 13 (As shown).
[0060] In step 10, the metal paste is preferably silver paste, the sintering temperature is 700~860℃, and the belt speed is 7000~15000mm / min.
[0061] After completing step 10, a back-contact photovoltaic cell of the present invention can be obtained (its structure is as follows). Figure 13 (As shown).
[0062] Example 1 This embodiment describes a method for preparing a back-contact photovoltaic cell, see [link to relevant documentation]. Figure 1-13 Taking TBC batteries as an example, their preparation steps include the following: Step 1, Cleaning and texturing: For the original silicon wafer 1 (e.g. Figure 2 (As shown) Double-sided cleaning and texturing are performed to form a textured surface on both the front and back surfaces of the original silicon wafer 1 (as shown). Figure 3 (As shown).
[0063] In step 1, the solution used for cleaning the silicon wafer is a mixed solution of 2.5 wt.% NaOH solution and 1.0 wt.% H2O2 solution, the cleaning temperature is 67℃, and the cleaning time is 180s; the solution used for texturing the silicon wafer is a mixed solution of 3.0 wt.% NaOH solution and 0.6 wt.% existing alkaline texturing additive, the texturing temperature is 82℃, and the texturing time is 280s.
[0064] Step 2, Laser Grooving: Using an infrared laser device, laser grooving is performed on the pre-defined N-region and P-region locations on the back of the silicon wafer to form a first arc-shaped groove 31 at the N-region location and a second arc-shaped groove 32 at the P-region location (e.g., ...). Figure 4-5 (As shown). In step 2, the process conditions for laser grooving using the infrared laser equipment include: laser power of 17W, laser speed of 30000mm / s, and laser frequency of 500KHz.
[0065] In step 2, the infrared laser device creates a 150 μm radius spot in the N-region corresponding to the N+ emitter, with an energy density of 1.4 J / cm². 2 The first arc-shaped groove 31 formed at location N has a groove depth of 50 μm and a groove curvature of 4.00*10. -3 The radius of the light spot corresponding to the P-region slot at the P+ emitter is 250 μm, and the energy density is 1.5 J / cm². 2 The second arc-shaped groove 32 formed at the P region has a groove depth of 50 μm and a groove curvature of 1.53*10. -3 .
[0066] In Example 1, the width of the N+ emitter (e.g., N+ polysilicon 61) corresponding to a single N-region is 300 μm, and the width of the P+ emitter (e.g., P+ polysilicon 62) corresponding to a single P-region is 500 μm. The number of first arc-shaped grooves 31 opened in a single N-region is 1, and the number of second arc-shaped grooves 32 opened in a single P-region is 1.
[0067] Step 3, Wet Cleaning: Perform wet cleaning on the silicon wafer to remove the laser-damaged layer 2 (e.g., ...) on the silicon wafer surface. Figure 6 (As shown).
[0068] In step 3, the etching solution used for wet cleaning is a mixture of 2.0 wt.% NaOH solution and 1.5 wt.% of existing alkaline etching additives for etching silicon oxide / poly Si.
[0069] Step 4, ia-Si layer 4 deposition: A tunneling oxide layer and an ia-Si layer 4 (e.g., ...) are sequentially deposited on the entire back side of the silicon wafer after step 3. Figure 7 (As shown).
[0070] In step 4, the thickness of the ia-Si layer 4 is 350 nm, and it is deposited using an LPCVD device at a deposition temperature of 620 °C.
[0071] Step 5, Doping paste 5 printing: N-type doping paste 51 and P-type doping paste 52 are printed in the first arc groove 31 and the second arc groove 32 on the back of the ia-Si layer 4, respectively (e.g., Figure 8 (As shown).
[0072] In step 5, the P-type doped paste 52 is a boron doped paste containing the following components: boron oxide (20 wt.%), borosilicate glass powder (10 wt.%, 400 mesh), ammonium bifluoride (5 wt.%), calcium hydroxide (25 wt.%), aluminum fluoride (5 wt.%), alumina (20 wt.%, 100 mesh), ethyl cellulose (10 wt.%), and sodium chloride (5 wt.%).
[0073] N-type doped paste 51 is a phosphorus doped paste containing the following components: phosphorus pentoxide (40 wt.%), phosphosilicate glass powder (15 wt.%, 400 mesh), ammonium bifluoride (5 wt.%), sodium chloride (5 wt.%), sodium fluoride (5 wt.%), alumina (20 wt.%, 100 mesh) and ethyl cellulose (10 wt.%).
[0074] Step 6, Oxygen Annealing: The silicon wafer processed in Step 5 is subjected to oxygen annealing, which causes the N-type doped paste 51 to dope and diffuse into the ia-Si layer 4 at the first arc groove 31, and the ia-Si layer 4 at the first arc groove 31 crystallizes into N+ poly Si (N+ polysilicon 61). Similarly, the P-type doped paste 52 is used to dope and diffuse into the ia-Si layer 4 at the second arc groove 32, and the ia-Si layer 4 at the second arc groove 32 crystallizes into P+ poly Si (P+ polysilicon 62). The back surfaces of the ia-Si layer 4 in the GAP area (corresponding to the area without printed doped paste), as well as the N+ polysilicon 61 and P+ polysilicon 62, are annealed to form a protective layer 63 (such as borosilicate glass, phosphosilicate glass). Figure 9 (As shown).
[0075] In step 6, the aerobic annealing temperature is 860℃, and the annealing time is 3 hours. Step 7: Remove doping paste 5 and protective layer 63: Perform wet cleaning on the silicon wafer processed in Step 6 to etch and remove the protective layer 63 on the back of the silicon wafer, and clean and remove the P-type doping paste 52 and N-type doping paste 51 on the back of the silicon wafer. After Step 7, the back surface of the silicon wafer in the GAP area, the back surface of the N+ polysilicon 61 at the first arc groove 31 (corresponding to the N area), and the back surface of the P+ polysilicon 62 at the second arc groove 32 (corresponding to the P area) will all be exposed (e.g., Figure 10 (As shown).
[0076] In step 7, the etching solution used is a 3.5 wt.% NaOH solution, the cleaning temperature is 82℃, and the cleaning time is 350 s.
[0077] Step 8, Double-sided growth of Al2O3 layer 7: An Al2O3 layer 7 is grown on both the front and back sides of the silicon wafer after step 7 (e.g., Figure 11 (As shown). Specifically, the back Al2O3 layer 7 is grown on the back surface of the silicon wafer in the GAP region, the back surface of N+ polysilicon 61, and the back surface of P+ polysilicon 62.
[0078] In step 8, the double-sided Al2O3 layer 7 is grown using the ALD process, and the thickness of the Al2O3 layer 7 is 5~7nm.
[0079] Step 9: Double-sided SiN growth x Layer 8: A SiN layer is grown on both the front surface of the front Al2O3 layer 7 and the back surface of the back Al2O3 layer 7. x Layer 8 (e.g.) Figure 12 (As shown).
[0080] In step 9, SiN x Layer 8 has a thickness of 65~75nm and a refractive index of 2~2.2%.
[0081] Step 10, Electrode Printing and Sintering: Silver paste is printed at localized locations in the corresponding N-regions and P-regions of the back silicon nitride layer; then sintering is performed to make ohmic contact between the silver paste in the N-region and the N+ polycrystalline silicon 61 to form an N-type electrode 91, while the silver paste in the P-region makes ohmic contact between the silver paste in the P-region and the P+ polycrystalline silicon 62 to form a P-type electrode 92 (e.g., ...). Figure 13 (As shown).
[0082] In step 10, the sintering temperature is 860℃ and the belt speed is 11000mm / min.
[0083] After completing step 10, a TBC battery of the present invention can be obtained (its structure is as follows). Figure 13 (As shown).
[0084] Example 2 This embodiment describes a TBC battery and its preparation method. Referring to Embodiment 1, the difference between this embodiment and Embodiment 1 is as follows: In step 2 of this embodiment, multiple laser grooves exist on the surfaces of both the same N-region and the same P-region, and the edges of the multiple laser grooves on the surface of the same N-region (or P-region) are sequentially connected (that is, there are multiple first arc-shaped grooves 31 in a single N-region, and the edges of adjacent first arc-shaped grooves 31 in a single N-region are sequentially connected; there are also multiple second arc-shaped grooves 32 in a single P-region, and the edges of adjacent second arc-shaped grooves 32 in a single P-region are sequentially connected). The grooving spot radius of the infrared laser device is 50 μm, and the energy density is 1.15 J / cm². 2 The groove curvature is 20.00*10. -3 The groove spacing is 100μm. The groove depth of the first arc groove 31 formed at the N region position is still 50μm, and the groove depth of the second arc groove 32 formed at the P region position is still 50μm.
[0085] In this embodiment, the width of the P+ emitter (e.g., P+ polysilicon 62) corresponding to a single P region remains 500 μm, and the width of the N+ emitter (e.g., N+ polysilicon 61) corresponding to a single N region remains 300 μm. The number of second arc-shaped grooves 32 opened in a single P region is 5, and the number of first arc-shaped grooves 31 opened in a single N region is 3.
[0086] Comparative Example 1 This comparative example describes a TBC battery and its preparation method. Referring to Example 1, the difference between this comparative example and Example 1 is: This comparative example omits the laser grooving process in the N and P regions of step 2. In Comparative Example 1, the width of the N+ emitter (such as N+ polysilicon) corresponding to a single N region is 300 μm, and the width of the P+ emitter (such as P+ polysilicon) corresponding to a single P region is 500 μm.
[0087] In summary, during the laser grooving process in step 2 of Examples 1-2 and Comparative Example 1, the proportions of the N-region, P-region, and GAP region can be optimized by adjusting the grooving depth and the grooving spot radius, thereby increasing the actual area of the subsequently fabricated N+ emitters (such as N+ polycrystalline silicon) and P+ emitters (such as P+ polycrystalline silicon). Specifically: The grooving spot radius is adjusted by controlling the spot radius of the infrared laser equipment; the grooving depth is adjusted by adjusting the laser energy density and the number of processing cycles; and the grooving spacing is adjusted by using a pre-set graphic pattern on the back of the battery. Taking an example where the width of an N+ emitter (e.g., N+ polysilicon 61) corresponding to a single N-region is 300 μm, the width of a P+ emitter (e.g., P+ polysilicon 62) corresponding to a single P-region is 500 μm, the GAP area width is 100 μm, the grid line width of the electrode is 30 μm, the grooving depth is no higher than 50 μm, and the grooving radius is no less than 50 μm: Referring to Table 1, if both the N+ emitter in the N region and the P+ emitter in the P region are planar designs (as shown in Comparative Example 1), then the area ratio of the N region to the P region is 0.6 (300μm / 500μm=0.6), the fixed area ratio of the GAP region on the back of the BC battery is 20%, and the area ratio of the grid lines in the electrodes is 3.75%. If the technical solution of this invention is adopted, the area ratio of the N region to the P region can be controlled within the range of 0.38~0.94, the area ratio of the GAP region can be controlled within 13.73~20.00%, the area ratio of the grid lines can be controlled within 2.38~3.75%, the maximum area gain of the emitter can be increased by 57.08%, the maximum area gain on the back of the battery can be increased by 45.66%, and the maximum occupancy of the grid lines on the emitter can be reduced from 3.75% to 2.38%. Increasing the emitter area directly increases the light-receiving area on the back of the BC battery. At the same time, the curved structure helps to increase the multi-level reflection of visible light on the back surface of the battery, thereby increasing the back efficiency of the battery and improving the bifaciality of the battery.
[0088] Table 1
[0089] Table 1 shows the calculations for the edge length of the N+ emitter in a single N-region, the edge length of the P+ emitter in a single P-region, the slot depth of the emitter region, and the laser spot diameter of the slot in the N / P region in Examples 1 and 2, as follows: Figure 14 As shown.
[0090] Furthermore, as shown in publication CN118888627A, a plurality of alternating first grooves and a plurality of second grooves are formed on the back side of a silicon substrate. A first dielectric layer (such as a tunneling oxide layer) and a first doped layer (such as a phosphorus-doped layer, N+ emitter) are stacked in the first grooves, and a second dielectric layer (such as a tunneling oxide layer) and a second doped layer (such as a boron-doped layer, P+ emitter) are stacked in the second grooves. While this also helps to increase the area ratio of the N-region of the N+ emitter and the P-region of the P+ emitter on the back side of the battery, publication CN118888627A uses grooves (the bottom and two sides of the groove are flat, and the entire groove forms a shape similar to a rectangle). Therefore, the arc-shaped grooves (the bottom and two sides of the arc-shaped groove are continuous arc surfaces) of the first and second arc-shaped grooves of this invention have the following advantages compared to the rectangular grooves of publication CN118888627A: (1) Compared to rectangular grooves, continuous arc grooves have no corners or sides perpendicular to the silicon wafer, which is more conducive to improving the density and uniformity of the coating (such as N+ polycrystalline silicon, P+ polycrystalline silicon, Al2O3 layer, SiN). x (e.g., film layers). However, the coating uniformity and density of the rectangular grooves on the sides perpendicular to the silicon wafer (or substrate) have many defects. This is detrimental to improving the passivation effect of the battery. Furthermore, these defects act as carrier recombination sites, leading to increased parasitic absorption, which is counterproductive to reducing series resistance. Moreover, compared to porous structures (as shown in CN102779866A), continuous arc-shaped grooves are more conducive to the diffusion of cleaning reagents during chemical cleaning, resulting in superior cleaning performance.
[0091] (2) Continuous arc-shaped grooves have a greater area improvement effect on N+ emitters and P+ emitters compared to rectangular grooves or hole structures. If we calculate based on the common width of 300 / 500μm for N+ emitters (N region) / P+ emitters (P region) in current BC batteries (back contact batteries), and if the rectangular grooves in the N region / P region both adopt the maximum groove depth (10 / 9.95μm) shown in CN118888627A, the emitter area gain compared to BC batteries without grooves in the N region / P region is equal to the area of the grooved side surface; according to calculation, the total area improvement of N+ emitters and P+ emitters is 5% ({[(10+9.95+300+500) / (300+500)]-1}*2*100%≈5%). In this invention, if the laser grooving spot diameter of the N+ emitter and P+ emitter is 100 μm, and the grooving depth of the arc-shaped groove is calculated as 50 μm (as in Example 2), then the number of arc-shaped grooves of the N+ emitter / P+ emitter is 3 / 5 (meaning that the number of grooves in a single N region is 3, and the number of grooves in a single P region is 5). The total area of the N+ emitter and P+ emitter is increased by 57.1% ({[(471.24+785.4) / (300+500)]-1}*100%=57.08%). Furthermore, the total area increase of the N+ emitter / P+ emitter can be further improved by adjusting the grooving diameter and controlling the grooving depth. Therefore, this invention has advantages in improving carrier collection efficiency and back-side light-receiving area.
[0092] (3) Compared to rectangular grooves, the inner surface of arc grooves is smoother and more continuous, and the stress on the inner surface is more uniform when subjected to external force deformation. Rectangular grooves are more prone to breakage at the bottom and corners, leading to an increase in the fragmentation rate during battery production. Due to its discontinuous nature, the hole structure requires multiple laser impacts on the silicon wafer surface to melt and cool the silicon. The repeated rapid heating and cooling can cause stress inside the silicon wafer, resulting in microcracks and other damage. Furthermore, the laser impact on the silicon wafer surface causes microdeformation due to the impact force. As the laser continuously impacts the silicon wafer during processing, internal microcracks and other damage can grow, leading to hidden cracks or fragmentation of the sample and increasing the fragmentation rate. In contrast, the present invention uses continuous laser processing during laser grooving, ensuring a stable output of laser energy, stable silicon wafer deformation, and continuous movement of the laser spot slows down the heating and cooling rate of the molten area, which helps reduce internal stress and further reduces the fragmentation rate.
[0093] Although preferred embodiments of the present invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the embodiments of the present invention.
[0094] The technical solution provided by the present invention has been described in detail above. Specific examples have been used to illustrate the principle and implementation of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core idea of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation and application scope based on the idea of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.
Claims
1. A method for preparing a back-contact photovoltaic cell, characterized in that, The preparation steps include the following: S1. Use an infrared laser to perform laser grooving on the N-region and P-region on the back of the silicon wafer, so as to form a first arc-shaped groove and a second arc-shaped groove in the N-region and P-region respectively. S2. After removing the laser-damaged layer, deposit an amorphous silicon layer on the back side of the silicon wafer; S3. Print N-type doped paste and P-type doped paste in the first and second arc grooves on the back of the amorphous silicon layer, respectively. S4. Perform oxygen annealing treatment to dope and diffuse the amorphous silicon layer at the first arc groove and the second arc groove with N-type doped paste and P-type doped paste respectively, so that the amorphous silicon layer at the first arc groove and the second arc groove is crystallized into N+ polycrystalline silicon and P+ polycrystalline silicon respectively, and a protective layer is formed by annealing on the back of N-type doped paste and P-type doped paste. S5. After removing the protective layer, N-type doped paste and P-type doped paste, a passivation film is deposited on the surface of the silicon wafer, and the back side of the silicon wafer is metallized to prepare N-type electrodes and P-type electrodes that respectively contact N+ polycrystalline silicon and P+ polycrystalline silicon.
2. The method for preparing a back-contact photovoltaic cell according to claim 1, characterized in that, The back side of the silicon wafer includes several N regions for N+ polysilicon fabrication, several P regions for P+ polysilicon fabrication, and several GAP regions that separate the N regions from the P regions. In step S1, the number of first arc grooves opened in a single N region on the back side of the silicon wafer is an integer greater than or equal to 1, and the total width of the first arc grooves opened in a single N region is less than or equal to the width of the N+ polysilicon in a single N region; the number of second arc grooves opened in a single P region on the back side of the silicon wafer is an integer greater than or equal to 1, and the total width of the second arc grooves opened in a single P region is less than or equal to the width of the P+ polysilicon in a single P region.
3. A method for preparing a T-back contact photovoltaic cell according to claim 1 or 2, characterized in that, In step S1, the radius of the slotted spot of the infrared laser is 50~1000μm, and the energy density is 0.1~2J / cm². 2 The first and second arc-shaped grooves have a groove depth of less than or equal to 50 μm, a groove spacing of 100~1000 μm, and a groove curvature of less than or equal to 20.00*10. -3 .
4. The method for preparing a back-contact photovoltaic cell according to claim 1, characterized in that, In step S2, the laser damage layer on the surface of the silicon wafer is removed by wet cleaning; The amorphous silicon layer is an intrinsic amorphous silicon layer with a thickness of 100~400 nm. The amorphous silicon layer is deposited using a low-pressure chemical vapor deposition equipment at a deposition temperature of 500~700℃. Step S2 further includes: before depositing the amorphous silicon layer, preparing a tunneling oxide layer on the back surface of the silicon wafer.
5. The method for preparing a back-contact photovoltaic cell according to claim 1, characterized in that, In step S3, screen printing is used to print the N-type doped paste and the P-type doped paste. The N-type doped paste is a phosphorus-containing doped paste, and the P-type doped paste is a boron-containing doped paste.
6. The method for preparing a back-contact photovoltaic cell according to claim 1, characterized in that, In step S4, the temperature of the aerobic annealing is 800~950℃, and the annealing time is 0.5~4h.
7. The method for preparing a back-contact photovoltaic cell according to claim 1, characterized in that, In step S5, the protective layer, N-type doped paste and P-type doped paste are removed by wet cleaning so as to expose the back surface of the silicon wafer in the GAP area, the N+ polysilicon back surface at the first arc groove and the P+ polysilicon back surface at the second arc groove. The sintering temperature for metallization is 700~860℃, and the sintering belt speed is 7000~15000 mm / min.
8. The method for preparing a back-contact photovoltaic cell according to claim 7, characterized in that, In step S5, passivation films are deposited on both the front and back sides of the silicon wafer. The front passivation film includes a front aluminum oxide layer on the front surface of the silicon wafer and a front silicon nitride layer on the front surface of the front aluminum oxide layer. The back passivation film includes a back aluminum oxide layer on the back surface of the silicon wafer in the GAP area, the back surface of N+ polysilicon and the back surface of P+ polysilicon, and a back silicon nitride layer on the back surface of the back aluminum oxide layer.
9. The method for preparing a back-contact photovoltaic cell according to claim 1, characterized in that, Before step S1, the process also includes: double-sided cleaning and texturing of the silicon wafer.
10. A back-contact photovoltaic cell, characterized in that, It is prepared by the method for preparing a back-contact photovoltaic cell as described in any one of claims 1-9.