Silicon-based microchannel fluid and thermoelectric cooler for electronic chips

Abstract

A cold plate for cooling a microchip. Fluid channels are formed in a semiconductor plate, each channel being defined by a sidewall. The sidewall is doped with a series of alternating n-type and p-type regions, creating a plurality of p-n junctions in each sidewall. Electrical contacts are disposed across the p-n junctions, establishing a plurality of thermoelectric cooling (TEC) devices within the sidewall. When current is applied to the contacts, the TEC devices transport and draw away heat flux from the microchip. The heat is then collected, in whole or in part, by a cooling fluid flowing within the channels.

Description

Technical Field

[0001] Embodiments of the present invention generally relate to enhanced and reliable cooling of advanced microchips, such as the cooling of microchips used in servers within data centers. Background Technology

[0002] Cooling is a critical factor in computer system and data center design. The number of high-performance electronic components (such as high-performance processors packaged within servers) is steadily increasing, leading to a rise in the heat generated and dissipated during normal server operation. The proper functioning of these processors largely depends on the reliable dissipation of the heat they generate. Therefore, proper cooling of the processors can provide high overall system reliability.

[0003] Cooling electronic components is critical for computing hardware and other electronic devices, such as CPU servers, GPU servers, storage servers, network equipment, edge and mobile systems, and automotive computing enclosures. All these devices and computers are used in mission-critical environments and are fundamental to a company's day-to-day operations. The design of hardware components and electronic packages requires continuous improvement to support performance requirements. Cooling these electronic devices is becoming increasingly challenging, ensuring their proper functioning by consistently providing a properly designed and reliable thermal environment.

[0004] Many advanced chips, especially high-power-density chips, require liquid cooling. These chips are extremely expensive, so every effort must be made to ensure proper heat dissipation. Furthermore, the liquid cooling system must be highly reliable, as any irregular heat dissipation can lead to chip failure, resulting in a loss of available computing power during replacement operations, and even potentially impacting the service level agreements processed by the failed chip.

[0005] While liquid cooling solutions must deliver the required thermal performance and reliability, the cost of liquid cooling systems must remain at an acceptable level, given that data centers may have thousands of chips requiring liquid cooling. The cost of a liquid cooling system may include the expense of introducing redundancy to improve reliability. Furthermore, since different chips have different cooling requirements, cooling designs tailored to these diverse needs are necessary.

[0006] Thermoelectric cooling (TEC) has been used in a variety of industrial applications and consumer products. A key advantage of TEC systems is that they have no moving parts or circulating fluid, thus providing high reliability. TEC utilizes the Peltier effect to generate heat flux at the junction of two different types of materials, such as p-type and n-type semiconductors. The amount of heat flow from one side of the TEC to the other is directly proportional to the applied DC current, allowing for precise control of the cooling rate. Summary of the Invention

[0007] A cooling plate for cooling a microchip includes: a semiconductor plate comprising a plurality of fluid channels, each fluid channel being defined by a sidewall, and each sidewall comprising an n-type doped region and a p-type doped region, wherein each pair of n-type and p-type doped regions forms a pn junction; a fluid inlet port fluidly connected to the fluid channels; a fluid outlet port fluidly connected to the fluid channels; and a plurality of electrical contacts, wherein each pair of contacts is disposed across one of the pn junctions, thereby forming a thermoelectric cooling device.

[0008] In some embodiments, the cooling plate further includes an inlet manifold connected to an inlet port leading to a plurality of fluid channels, and an outlet manifold connected to an outlet port leading to a fluid channel.

[0009] In some embodiments, the cooling plate further includes: a base plate; a top plate; and a core plate made of semiconductor material and sandwiched between the base plate and the top plate, wherein fluid channels are contained in the core plate.

[0010] In some embodiments, at least one of the base plate and the top plate is made of a semiconductor material.

[0011] In some embodiments, a plurality of electrical contacts are formed on at least one of the base plate and the top plate.

[0012] In some embodiments, the top plate includes a secondary cooling device.

[0013] In some embodiments, the secondary cooling device includes fins formed on the top plate.

[0014] In some embodiments, at least one of the fluid inlet port and the fluid outlet port is formed in the bottom plate or the top plate.

[0015] In some embodiments, at least one of the inlet manifold and the outlet manifold is formed in the bottom plate or the top plate.

[0016] In some embodiments, at least one of the inlet manifold and the outlet manifold is formed in the core plate.

[0017] A method for manufacturing a cooling plate for a microchip includes: providing a semiconductor plate made of a semiconductor material; forming a plurality of channels in the semiconductor plate, each channel being defined by a sidewall; doping the sidewalls to form a series of n-type and p-type regions along each sidewall, thereby forming a plurality of pn junctions in each sidewall; and forming a plurality of electrical contacts, wherein one of the junctions in each pair of the plurality of electrical contacts is disposed across the pn junction.

[0018] In some embodiments, forming multiple channels includes etching a semiconductor substrate.

[0019] In some embodiments, forming a plurality of electrical contacts includes forming contacts on at least one of a base plate and a top plate, and attaching the base plate and the top plate to a semiconductor plate.

[0020] In some embodiments, the method further includes forming an inlet port and an outlet port in at least one of the base plate and the top plate.

[0021] In some embodiments, the base plate and top plate comprise semiconductor materials.

[0022] In some embodiments, the method further includes forming a semiconductor device in a substrate.

[0023] In some embodiments, the method further includes connecting a plurality of contacts to a power source for the semiconductor device.

[0024] In some embodiments, the method further includes forming a fluid manifold in at least one of the base plate and the top plate.

[0025] In some embodiments, doped sidewalls include diffusing or implanting dopants into the sidewalls.

[0026] A cooling plate integrated in a microchip package includes: a semiconductor plate comprising a plurality of fluid channels, each fluid channel being defined by a sidewall, and each sidewall comprising an n-type doped region and a p-type doped region, wherein each pair of n-type and p-type doped regions forms a pn junction; a fluid inlet port fluidly coupled to a fluid channel; a fluid outlet port fluidly coupled to a fluid channel; a plurality of electrical contacts, wherein each pair of contacts is disposed across a junction in the pn junction to form a thermoelectric cooling device; a microchip in physical contact with the semiconductor plate; and power lines connected in parallel to the microchip and the plurality of electrical contacts. Attached Figure Description

[0027] Embodiments of the present invention are illustrated in the accompanying drawings by way of example rather than limitation, and the same reference numerals in the drawings denote the same elements.

[0028] Figure 1 This is a block diagram illustrating an example of a cold plate construction according to one embodiment.

[0029] Figure 2 This is a conceptual schematic diagram showing a cross-section of a cooling plate according to one embodiment.

[0030] Figure 3 An embodiment of a cooling device comprising multiple fluid channels within a plurality of TEC structures is shown.

[0031] Figure 4 An embodiment of a cooling plate that can be integrated into a 3D package is shown.

[0032] Figure 5 A cross-sectional side view of another embodiment of the cooling plate is shown.

[0033] Figure 6 A cooling plate integrated with the power supply of a microchip is shown according to one embodiment.

[0034] Figure 7 This is a flowchart of a general process for manufacturing a cooling device according to one embodiment.

[0035] Figure 8A-8G A process for manufacturing a cooling plate according to one embodiment is shown. Detailed Implementation

[0036] Various embodiments and aspects of the invention will be described with reference to the details discussed below, and the accompanying drawings will illustrate various embodiments. The following description and drawings are illustrative of the invention and should not be construed as limiting the invention. Numerous specific details are described to provide a thorough understanding of various embodiments of the invention. However, in some cases, well-known or conventional details are not described in order to provide a concise discussion of embodiments of the invention.

[0037] References to "one embodiment" or "an embodiment" in the specification mean that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the invention. The phrase "in one embodiment" appearing in different places in the specification does not necessarily refer to the same embodiment.

[0038] The disclosed embodiments provide silicon-based microchannel fluid cooling for electronic devices, which utilizes TEC to enhance heat flux. The cooling device can be implemented for cooling a variety of electronic devices, such as single-chip modules (SCMs), system-on-a-chip (SoCs), multi-chip modules (MCMs), systems-in-package (SIPs), etc. For brevity, these are referred to herein as microchips or simply chips, but any such reference should be understood to include any such and similar differences between wafers and packages.

[0039] In this regard, it should be noted that in this invention, the term "silicon-based" is broadly used as an abbreviation for any type of semiconductor material used in the semiconductor industry and that can be used to manufacture pn junctions. However, since silicon is used in most of the semiconductor industry to manufacture chips, the term silicon is used extensively herein. However, just as other semiconductor materials (e.g., silicon carbide (SiC), gallium nitride (GaN), gallium arsenide (GaAs), etc.) can be used to manufacture chips, these materials can be replaced for use in the cooling devices disclosed herein.

[0040] A cooling solution incorporating advanced chip-level design is disclosed. The disclosed embodiments integrate a microchannel fluid system with a semiconductor-based thermoelectric cooler. The resulting structure efficiently cools high-power chips. Furthermore, the cooling structure can be integrated with and manufactured alongside the chip itself or its package. The disclosed design is well-suited for advanced chip packaging and electronics used in next-generation high-power-density devices. Additionally, the disclosed embodiments include a semiconductor-based thermoelectric cooler (TEC) co-packaged with the chip, enabling automatic adjustment of the heat dissipation rate based on the chip's power consumption. In fact, the TEC can be powered by the same power supply as the chip. Therefore, the disclosed embodiments provide a fully fluid-based cooling module that includes a built-in TEC module for improved and precisely controlled heat dissipation.

[0041] Figure 1 This is a schematic diagram illustrating a chip cold plate structure that can be implemented or modified according to the embodiments disclosed herein. The chip / cold plate assembly 100 can represent any processor / cold plate structure of a server or other computing platform that incorporates fluid cooling. Reference Figure 1 Chip 101 is inserted into a slot mounted on a printed circuit board (PCB) or motherboard 102, which is connected to other electrical components or circuits of a data processing system or server. For fluid cooling, chip 101 also includes a cold plate 103 attached thereto, which is connected to a rack manifold, for example, via a blind-mating connector, to a liquid supply line 132 and / or a liquid return line 131. A portion of the heat generated by chip 101 is removed by the cold plate 103. The remaining heat enters the air space below or above, and can be removed by airflow generated by a cooling fan 104.

[0042] Figure 2 This is a 3D conceptual illustration of a cooling assembly 200, which combines fluid channel heat dissipation with a semiconductor-based thermal conductivity (TEC). Assembly 200 includes a base plate 205, a semiconductor core section 210, and a top plate 215. The base plate 205 and top plate 215 can also be made of semiconductor materials, such as silicon, gallium nitride, etc. The core section 210 includes a fluid channel 212 defined by two sidewalls 213, each sidewall containing multiple pn pairs 214. Multiple conductive contacts 216, such as copper sheets, are formed on the base plate 205, and corresponding contacts 218 are formed on the top plate 215. Each pn pair, together with its corresponding contact, forms a TEC that transports heat, which is then carried away by the fluid in the channel 212.

[0043] In this embodiment, the TEC is used to transfer heat from the base plate 205 to the top plate 215. Since the base plate 205 is in physical contact with the chip (obscured in this view), the TEC generates a heat flow from the chip and transfers the heat to the top plate 215. The removed heat is at least partially carried away from the cooling assembly 200 by a fluid flowing in channel 212. Optionally, additional cooling mechanisms may be included in or in contact with the top plate 215, as will be shown in other embodiments below.

[0044] Incidentally, in the following embodiments, similar elements are labeled with similar reference numerals in the form of x##, wherein the first digit x is replaced by the same digit as the figure number, and the following two digits ## remain consistent in the embodiments. Therefore, the explanation of previously disclosed elements will not be repeated in later embodiments.

[0045] Figure 3 An embodiment of a cooling device 300 is shown, comprising multiple fluid channels 312 in multiple TEC structures formed on sidewalls 313. The cooling device 300 may be made entirely of a semiconductor material (e.g., silicon) and includes a base plate 305, a core section 310, and a top plate 315. Multiple fluid channels 312 are formed in the core section, for example, by etching the silicon mass. The fluid channels are surrounded by multiple sidewalls 313, each sidewall 313 including multiple TEC devices. Cooling fluid enters the cooling channel 312 from an inlet (not visible in this view), as indicated by the dashed arrow, and flows out from an outlet 320, as indicated by the dashed dotted arrow, after collecting heat from the multiple TECs formed in the sidewalls 313. An outlet manifold 322 may be formed in the top plate 315 to collect fluid from all fluid channels 312.

[0046] As in Figure 2 In this embodiment, each of the plurality of TECs 314 consists of a pair of p-type and n-type doped blocks with corresponding contacts 316, 318. The doped blocks can be formed, for example, by diffusing or embedding dopants into the silicon sidewalls. The channels can be etched into the silicon using wet or dry plasma etching. Therefore, the cooling plate can be fabricated using standard semiconductor manufacturing techniques.

[0047] Cooling plates can also be integrated as part of standard semiconductor device packages. For example, three-dimensional integrated circuits, or 3D packaging, refer to integrated circuits (ICs) manufactured by stacking semiconductor wafers and vertically interconnecting them, allowing them to function as a single device to achieve performance improvements—lower power consumption and a smaller footprint compared to multiple separate two-dimensional devices required to achieve the same function. 3D packaging is one of several 3D integration schemes that utilize vertical integration to achieve electrical performance advantages. Figure 4 An embodiment of a cooling plate that can be integrated into a 3D package is shown.

[0048] Figure 4 A side cross-section of a cooling plate or cooling device 400, which can be included as one of multiple layers in a vertically stacked package, is shown. The cooling device 400 includes a base plate 405 and a top plate 415, which may be made of a semiconductor material compatible with the remaining semiconductor wafers in the stack. The base plate includes contacts 416, and the top plate includes contacts 418. A core 410 includes fluid channels 412 and doped sidewalls 413 forming multiple TEC devices. The cooling plate 400 is included in the package such that the base plate 405 is in physical contact with a microchip 435. When the microchip 435 operates and generates heat, the TEC operates to transfer heat away from the microchip 435 by causing a heat flux from the base plate 405 to the top plate 415. The transferred heat diffuses across the body of the plate 415 and is then collected and removed by the fluid flowing in the channels 412.

[0049] Figure 5 A side cross-sectional view of another embodiment of the cooling plate is shown. This embodiment is similar to... Figure 4 The illustrated embodiment is similar, except that the top plate 515 includes a secondary cooling device. The secondary cooling device enhances heat removal as heat is transported by the TEC and cooling fluid. In one example, the secondary cooling device may include fins 530, where air can be forced through the fins. Thus, the TEC pumps heat from the bottom plate 505 to the top plate 515, where this heat is partially removed by the fluid flowing in the channel 512 and also partially removed by the air flowing at the fins 530.

[0050] Figure 6 An embodiment that elevates integration to a higher level is illustrated. Typically, an IC chip receives DC voltage from a DC / DC voltage regulator (VR). In the disclosed embodiment, the voltage to multiple TECs in a cooling device can be supplied by accessing the same VR voltage, such as... Figure 6 The arrow between VR 640 and contact 616 indicates this (of course, all contacts are actually connected to the VR power supply, for example, through electrical interconnections formed in the base and top plates). This feature enables automatic regulation of the amount of heat transferred through the TEC. That is, when the chip consumes more current for increased processing demands, the increased current is automatically applied to the TEC because the TEC is connected to the same current source. Naturally, as the current to the TEC increases, their heat transfer rate increases. Therefore, when the chip performs high-intensity processing and consumes higher current, the TEC also automatically increases its heat transfer rate.

[0051] Figure 6Another feature shown is integrating the chip into the substrate (and vice versa, integrating the cooling plate structure with the chip wafer). Specifically, as... Figure 6 As shown, chip 635 is integrated into the base plate 605 of the cooling device. Since the base plate 605 is made of semiconductor, chip 635 can be manufactured in a manner that integrates it into the base plate 635. This integration also enables improved power transfer from the VR power supply to chip 635 and the TEC. Furthermore, in some 3D packages, the DC / DC VR 640 is also integrated into the package. Therefore, in such 3D packages, the integration of the chip with the cooling device and the common connection from the chip and the TEC to the VR are fabricated very efficiently.

[0052] Incidentally, Figure 6 The embodiment also illustrates another optional secondary heat removal device. As shown by the dashed lines, a fluid plate 662 is provided in physical contact with a top plate 615. The fluid plate 662 includes a fluid channel 666 having a fluid port 664. In addition to circulating in the channel 612, the cooling fluid also circulates within the fluid channel 666 to enhance heat removal from the top plate 615.

[0053] Figure 7 This is a flowchart of a general process for manufacturing a cooling device according to one embodiment. At 770, a silicon plate or silicon block is formed to serve as the core layer of the device. At 771, channels are etched into the silicon plate. These etched channels form cooling fluid microchannels. At 772, a second etching process is performed to form inlets and outlets, as well as fluid distribution manifolds. In other embodiments, the two etching processes may be combined into a single etching process. In either case, at 773, the resulting core layer has channels with sidewalls, dividing the core layer into fluid channel recesses separated by silicon ridges. At 774, the silicon ridges are doped with impurities to form a plurality of pn junctions. According to 775, trivalent impurities are added to the regions forming p-type blocks, and pentavalent impurities are added to the regions forming n-type blocks. At 776, semiconductor plates, such as GaN plates, are fabricated as top and bottom layers by forming metal contacts on their surfaces. Furthermore, suitable circuitry can also be fabricated on the top and bottom plates at this time to interconnect the contacts. At 777, the base plate, core layer, and top plate are assembled (e.g., adhered) to form a cooling plate. At 778, the cooling plate is attached to the microchip, and by applying a voltage to the cooling device, the pn junction generates a heat flux away from the microchip, which is transferred to cold water, which dissipates the heat from the cooling device.

[0054] Figure 8A-8G A process for manufacturing a cooling plate according to one embodiment is shown, wherein Figure 8A , Figure 8B , Figure 8D , Figure 8F and Figure 8GThis is a cross-sectional view along line AA. Figure 8C and Figure 8E It's a top view. Figure 8A In this process, a board made of semiconductors (such as silicon or GaN) is used to fabricate the core layer 810 of the cooling device. Figure 8B In this process, channel 812 is etched into plate 810, while sidewall 813 is retained. For example... Figure 8C As shown, in one embodiment, the etching process forms: an island that serves as a sidewall 813 and defines a channel 812 therebetween; additionally, an etched region 823 that serves as an intake manifold; and a region 822 that serves as an outlet manifold. The intake manifold is fluidly connected to an inlet 821, and the outlet manifold 822 is fluidly connected to an outlet 820.

[0055] exist Figure 8D In this process, a doping process is used to dope the sidewalls 813 with impurities in order to form n-type and p-type regions, such as... Figure 8E As shown. Each pair of n-type and p-type regions forms the junction of the TEC device. Figure 8F In this process, base plate 805 and top plate 815 are manufactured by forming contacts 816 and 818. Furthermore, circuitry interconnecting the contacts can also be formed at this time, including contacts for power transmission. For example, through-holes 817 and 819 can be formed to connect contacts 816 and 818 to power transmission electrodes. Figure 8G In the middle, the bottom plate and top plate are attached to the core plate to form a complete cooling device.

[0056] Therefore, a cooling device comprising cooling channels and thermoelectric cooling units is provided through the disclosed embodiments. The cooling device has a semiconductor plate portion having multiple fluid channels etched therein. Each fluid channel is surrounded by sidewalls of a semiconductor material, which are doped to form multiple pn junctions. Multiple contacts are provided in contact with the doped sidewalls to enable the application of a voltage potential to the pn junctions, thereby functioning as multiple TECs. The cooling device is attached to a microchip or included in a microchip package such that by applying a voltage potential to the cooling device, the multiple TECs generate a heat flow from the microchip, which is then removed by the cooling fluid flowing in the fluid channels.

[0057] According to the disclosed embodiments, the cooling device comprises a core plate having fluid channels and PN junctions, and a bottom plate and a top plate having contacts aligned with the PN junctions. The bottom plate and top plate also include a fluid inlet port and a fluid outlet port. The cooling device may further include a fluid inlet manifold and a fluid outlet manifold, which may be formed in any one of the bottom plate, core plate, and top plate.

[0058] According to the disclosed embodiments, a method for manufacturing a microchip cooling device is provided, comprising forming a plurality of fluid channels in a semiconductor board. The sidewalls of the fluid channels are doped to form a plurality of pn junctions. Electrical contacts are provided to enable the application of a voltage potential to each pn junction, thereby forming a plurality of thermoelectric cooling devices between the fluid channels. Inlet and outlet ports for cooling fluid are formed to fluidly connect the cooling devices to a liquid cooling system.

[0059] Therefore, aspects of this disclosure include a cooling plate for cooling a microchip, comprising: a semiconductor plate containing a plurality of fluid channels, each fluid channel being defined by a sidewall, each sidewall including an n-type doped region and a p-type doped region, wherein each pair of n-type and p-type doped regions forms a pn junction; a fluid inlet port fluidly coupled to a fluid channel; a fluid outlet port fluidly coupled to a fluid channel; and a plurality of electrical contacts, wherein each pair of contacts is disposed across a junction in the pn junction, thereby forming a thermoelectric cooling device. An inlet manifold coupled to the inlet port leading to the plurality of fluid channels and an outlet manifold coupled to the outlet port leading to the fluid channels may be included. The cooling plate may consist of a base plate, a top plate, and a core plate, the core plate being made of a semiconductor material and sandwiched between the base plate and the top plate, wherein the fluid channels are contained within the core plate, and at least one of the base plate and the top plate is made of a semiconductor material. A plurality of electrical contacts may be formed on at least one of the base plate and the top plate. The top plate may also include a secondary cooling device, such as air-cooled fins. Furthermore, at least one of the fluid inlet port and the fluid outlet port may be formed in the bottom plate or the top plate, and similarly, at least one of the inlet manifold and the outlet manifold may be formed in the bottom plate or the top plate. Alternatively, at least one of the inlet manifold and the outlet manifold may be formed in the core plate.

[0060] According to a further disclosed aspect, a method for manufacturing a cooling plate for a microchip is provided, comprising: providing a semiconductor plate made of a semiconductor material; forming a plurality of channels in the plate, each channel being defined by a sidewall; doping the sidewalls by diffusion of a dopant or ion implantation into the sidewalls to form a series of n-type and p-type regions along each sidewall, thereby forming a plurality of pn junctions in each sidewall; and forming a plurality of electrical contacts, wherein each pair of the plurality of electrical contacts is disposed across one of the pn junctions. The plurality of channels can be formed by wet etching or dry etching of the semiconductor plate. The plurality of electrical contacts can be formed by forming contacts on at least one of a base plate and a top plate, and attaching the base plate and the top plate to the semiconductor plate. The method may include forming an inlet port and an outlet port in at least one of the base plate and the top plate, the base plate and the top plate being made of a semiconductor material. A semiconductor device can be arranged to contact or be integrated in the base plate, and the plurality of contacts can be coupled to a power supply for the semiconductor device.

[0061] Further disclosed aspects include a cooling plate integrated in a microchip package, comprising: a semiconductor plate containing multiple fluid channels, each fluid channel being defined by a sidewall, and each sidewall including an n-type doped region and a p-type doped region, wherein each pair of n-type and p-type doped regions forms a pn junction; a fluid inlet port fluidly coupled to a fluid channel; a fluid outlet port fluidly coupled to a fluid channel; multiple electrical contacts, wherein each pair of contacts is disposed across a junction in the pn junction to form a thermoelectric cooling device; a microchip in physical contact with the semiconductor plate; and power lines connected in parallel to the microchip and the multiple electrical contacts.

[0062] In the foregoing description, embodiments of the invention have been described with reference to specific exemplary embodiments. It is obvious that various modifications can be made without departing from the broader spirit and scope of the invention as set forth in the claims. Therefore, the description and drawings should be considered illustrative rather than restrictive.

Claims

1. A cooling plate for cooling a microchip, comprising: A semiconductor plate comprising a plurality of fluid channels, wherein each fluid channel is defined by a sidewall, and wherein each sidewall includes an n-type doped region and a p-type doped region, wherein each pair of n-type and p-type doped regions forms a pn junction; The fluid inlet port is fluidly connected to the fluid channel; The fluid outlet port is fluidly connected to the fluid channel; Multiple electrical contacts, wherein each pair of the multiple contacts is provided across one of the pn junctions, thereby forming a thermoelectric cooling device; The thermoelectric cooling device is configured to be connected to the same current source as the microchip; Base plate; roof; and The core plate, made of semiconductor material and sandwiched between the base plate and the top plate, The fluid channels are contained within the core board.

2. The cooling plate according to claim 1, further comprising: An inlet manifold connected to an inlet port leading to multiple fluid channels, and an outlet manifold connected to an outlet port leading to the fluid channels.

3. The cooling plate according to claim 1, wherein at least one of the bottom plate and the top plate is made of a semiconductor material.

4. The cooling plate according to claim 1, wherein a plurality of electrical contacts are formed on at least one of the bottom plate and the top plate.

5. The cooling plate according to claim 1, wherein the top plate includes a secondary cooling device.

6. The cooling plate of claim 5, wherein the secondary cooling device comprises fins formed on the top plate.

7. The cooling plate according to claim 2, wherein at least one of the fluid inlet port and the fluid outlet port is formed in the bottom plate or the top plate.

8. The cooling plate according to claim 7, wherein at least one of the inlet manifold and the outlet manifold is formed in the bottom plate or the top plate.

9. The cooling plate according to claim 7, wherein at least one of the inlet manifold and the outlet manifold is formed in the core plate.

10. A method for manufacturing a cooling plate for a microchip, comprising: Provide semiconductor boards made of semiconductor materials; Multiple channels are formed in the semiconductor board, each channel being defined by a sidewall; The sidewalls are doped to form a series of n-type and p-type regions along each sidewall, thereby forming multiple pn junctions in each sidewall; and Multiple electrical contacts are formed, wherein each pair of multiple electrical contacts is provided across one of the pn junctions; Contacts are formed on at least one of the base plate and the top plate, and the base plate and the top plate are attached to the semiconductor plate.

11. The method of claim 10, wherein forming a plurality of channels comprises etching a semiconductor plate.

12. The method of claim 10, further comprising forming an inlet port and an outlet port in at least one of the bottom plate and the top plate.

13. The method of claim 10, wherein the base plate and the top plate comprise semiconductor materials.

14. The method of claim 13, further comprising forming a semiconductor device in a substrate.

15. The method of claim 14, further comprising connecting a plurality of contacts to a power supply of the semiconductor device.

16. The method of claim 13, further comprising forming a fluid manifold in at least one of the bottom plate and the top plate.

17. The method of claim 10, wherein the doped sidewall comprises diffusing or ionizing a dopant into the sidewall.

18. A cooling plate integrated in a microchip package, comprising: A semiconductor plate comprising a plurality of fluid channels, wherein each fluid channel is defined by a sidewall, and wherein each sidewall includes an n-type doped region and a p-type doped region, wherein each pair of n-type and p-type doped regions forms a pn junction; The fluid inlet port is fluidly connected to the fluid channel; The fluid outlet port is fluidly connected to the fluid channel; Multiple electrical contacts, wherein each pair of the multiple contacts is arranged across one of the pn junctions, thereby forming a thermoelectric cooling device; Microchips are in physical contact with semiconductor boards; The power lines are connected in parallel to the microchip and multiple electrical contacts; Base plate; roof; and The core plate, made of semiconductor material and sandwiched between the base plate and the top plate, The fluid channels are contained within the core board.

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