Delay modulation circuit, method, chip and server
By adjusting the delay time using a delay modulation circuit, the problem of duty cycle distortion in pulse width modulation is solved, achieving accuracy and stability of the pulse signal, which is applicable to the field of integrated circuit technology.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- BEIJING BITMAIN TECHNOLOGIES
- Filing Date
- 2021-05-28
- Publication Date
- 2026-07-24
AI Technical Summary
In existing technologies, duty cycle distortion exists during pulse width modulation, making it difficult to finely adjust the pulse width, which affects chip performance and stability.
By using a delay modulation circuit, a comparison circuit, and a control module, a comparison signal is generated based on the clock signal and the data signal. The delay time of the delay circuit is adjusted to ensure the accuracy of the duty cycle of the pulse signal.
Effective calibration of pulse width modulation reduces duty cycle distortion and improves the accuracy and stability of chip signal processing.
Smart Images
Figure CN115412064B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit technology, and in particular to a delay modulation circuit, method, chip, and server. Background Technology
[0002] Clock pulses play an irreplaceable role in signal processing within chips, and clock quality is a crucial factor determining chip performance and stability. As chip system complexity and clock frequencies increase, pulse width modulation (PWM) becomes increasingly important. The proportion of a clock cycle occupied by a high-level signal relative to that cycle is called the duty cycle, and the product of the duty cycle and the pulse period is the delay time. However, in actual circuit design, various irrational factors can lead to duty cycle distortion, deviating from the ideal clock duty cycle. Pulse width modulation is a circuit that can recalibrate the distorted duty cycle to the ideal clock duty cycle.
[0003] Pulse width modulation (PWM) is a highly effective technique for controlling analog circuits using the digital output of a microprocessor, and it is widely used in many fields, from measurement and communication to power control and conversion. Fine-tuning the pulse width remains a major challenge in this field. Summary of the Invention
[0004] The main objective of this invention is to provide a delay modulation circuit, method, chip, and server.
[0005] In a first aspect, embodiments of the present invention provide a delay modulation circuit, comprising:
[0006] A delay circuit, connected to a clock source and a data source, is used to output a first pulse signal after delay processing based on the clock signal from the clock source and the data signal from the data source. A comparison circuit includes a delay reference unit and a comparison signal generation unit. The delay reference unit is connected to the clock source and is used to output a corresponding second pulse signal based on the clock signal. The comparison signal generation unit is connected to the delay reference unit and the delay circuit and is used to output a corresponding comparison signal based on the first pulse signal and the second pulse signal. A control module is connected to the comparison signal generation unit and the delay circuit and is used to generate a corresponding control signal based on the comparison signal, so as to adjust the delay time of the delay circuit according to the control signal.
[0007] Secondly, embodiments of the present invention provide a delay modulation method applied to the delay modulation circuit described in the above embodiments, the method comprising:
[0008] Obtain the delay modulation start command; obtain the first pulse signal of the delay circuit and the second pulse signal of the delay reference unit according to the delay modulation start command; generate a comparison signal according to the first pulse signal and the second pulse signal; generate a corresponding control signal according to the comparison signal, so as to adjust the delay time of the delay circuit according to the control signal.
[0009] Thirdly, embodiments of the present invention provide a chip that integrates the delay modulation circuit described in the above embodiments.
[0010] Fourthly, embodiments of the present invention provide a server including at least one chip as described in the above embodiments.
[0011] By acquiring the first pulse signal from the delay circuit and the second pulse signal from the delay reference unit, the comparison signal generation unit generates a corresponding comparison signal based on the first and second pulse signals. This comparison signal represents the deviation between the current delay time of the delay circuit and the preset delay time. The control module generates a corresponding control signal based on the comparison signal to adjust the current delay time of the delay circuit, reducing the deviation between the current delay time and the preset delay time. This avoids duty cycle distortion of the first pulse signal generated by the delay circuit and ensures the accuracy of the first pulse signal. Attached Figure Description
[0012] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0013] Figure 1 This is a schematic diagram of the structure of a delay modulation circuit provided in an embodiment of the present invention;
[0014] Figure 2 for Figure 1 A schematic diagram of the intermediate delay circuit and the comparison signal generation unit;
[0015] Figure 3 This is a schematic diagram of the structure of a delay unit provided in an embodiment of the present invention;
[0016] Figure 4 This is a schematic diagram of the delay modulation circuit provided in another embodiment of the present invention;
[0017] Figure 5 When the duty cycle of the first pulse signal is greater than 50% Figure 4 A schematic diagram of the waveforms of each signal;
[0018] Figure 6When the duty cycle of the first pulse signal is less than 50% Figure 4 A schematic diagram of the waveforms of each signal;
[0019] Figure 7 This is a schematic diagram of the delay modulation circuit provided in another embodiment of the present invention;
[0020] Figure 8 When the duty cycle of the first pulse signal is greater than 50% Figure 7 A schematic diagram of the waveforms of each signal;
[0021] Figure 9 When the duty cycle of the first pulse signal is less than 50% Figure 7 A schematic diagram of the waveforms of each signal;
[0022] Figure 10 This is a schematic diagram of the delay modulation circuit provided in another embodiment of the present invention. Detailed Implementation
[0023] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0024] The flowchart shown in the attached diagram is for illustrative purposes only and does not necessarily include all content and operations / steps, nor does it necessarily have to be performed in the order described. For example, some operations / steps can be broken down, combined, or partially merged, so the actual execution order may change depending on the actual situation.
[0025] It should be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention.
[0026] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.
[0027] Please see Figure 1 , Figure 1 This is a schematic diagram of a delay modulation circuit 1 provided in an embodiment of the present invention.
[0028] Specifically, the delay modulation circuit 1 includes a delay circuit 10, a comparator circuit 20, and a control module 30. The delay circuit 10 is connected to a clock source and a data source to generate corresponding pulse signals based on the clock signal Clk-in from the clock source and the data signal Data-in from the data source. It then delays these pulse signals to output a corresponding first pulse signal. The comparator circuit 20 specifically includes a delay reference unit 201 and a comparison signal generation unit 202. The delay reference unit 201 is connected to the clock source to receive the clock signal Clk-in and output a corresponding second pulse signal based on it. The input terminal of the comparison signal generation unit 202 is connected to the output terminal of the delay reference unit 201 and the output terminal of the delay circuit 10 to receive the first and second pulse signals and output a corresponding comparison signal based on the first and second pulse signals.
[0029] The first pulse signal is a pulse signal obtained by the delay circuit 10 after a preset delay process, and the second pulse signal is a pulse signal representing the standard delay. Therefore, the comparison signal is used to represent the relationship between the delay time of the preset delay process and the standard delay.
[0030] The input terminal of the control module 30 is connected to the output terminal of the comparison signal generation unit 202, and the output terminal of the control module 30 is connected to the delay circuit 10. After receiving the comparison signal output by the comparison signal generation unit 202, the control module 30 determines the relationship between the preset delay processing delay time and the standard delay based on the comparison signal, and outputs a corresponding control signal to the delay circuit 10. This causes the delay circuit 10 to adjust the delay time of the preset delay processing according to the control signal, thereby reducing the deviation between the preset delay processing delay time and the standard delay.
[0031] In some implementations, please refer to Figure 2 The comparison signal generation unit 202 includes a first D flip-flop 2021, which includes a first clock input terminal Clk-1, a first data input terminal D-1, and a first signal output terminal Q-1. The first clock input terminal Clk-1 is connected to one of the delay circuit 10 and the delay reference unit 201, the first data input terminal D-1 is connected to the other of the delay circuit 10 and the delay reference unit 201, and the first signal output terminal Q-1 is connected to the control module 30. The first D flip-flop processes the pulse signal input to the first data input terminal D-1 according to the pulse signal input to the first clock input terminal Clk-1 to generate a corresponding comparison signal.
[0032] In some embodiments, the delay circuit 10 includes a delay unit 11 and a second D flip-flop 12. The second D flip-flop 12 uses a clock signal Clk-in as a control signal and outputs a corresponding initial pulse signal according to the control signal. The delay unit 11 is used to delay the initial pulse signal output by the second D flip-flop 12 to obtain a first pulse signal.
[0033] Specifically, such as Figure 2 As shown, the second D flip-flop 12 includes a second data input terminal D-2, a second clock input terminal Clk-2, a second signal output terminal Q-2, and a clear signal terminal CDN. The second data input terminal D is connected to the data source, the second clock input terminal Clk is connected to the clock source, the second signal output terminal Q is connected to the input terminal of the delay unit 11, and the clear signal terminal CDN is connected to the output terminal of the delay unit 11.
[0034] When the clock signal Clk-in received at the second clock input terminal Clk is high, the second D flip-flop 12 reads the data from the second data input terminal D and transmits it to the second signal output terminal Q. When the clock signal Clk-in received at the second clock input terminal Clk is low, the data at the second data input terminal D is blocked. Only when the next high level arrives will the current data be output to the second signal output terminal Q. According to the clock signal Clk-in, the second D flip-flop 12 is controlled to sample the data from the data source and output the corresponding initial pulse signal.
[0035] The delay unit 11 contains a preset number of inverters, and multiple inverters are connected in series to form a delay chain to delay the input initial pulse signal.
[0036] An inverter consists of a PMOS transistor and an NMOS transistor. The source of the PMOS transistor is connected to the power supply VDD, the gate of the PMOS transistor is connected to the gate of the NMOS transistor and serves as the input terminal, the drain of the PMOS transistor is connected to the drain of the NMOS transistor and serves as the output terminal, and the source of the NMOS transistor is connected to the ground terminal.
[0037] Typically, a PMOS transistor is used as the load transistor, and an NMOS transistor as the input transistor. This configuration significantly reduces power consumption because one of the transistors is always off in both 0 and 1 logic states. The turn-on voltage of the PMOS transistor is VGS(th)P < 0, and the turn-on voltage of the NMOS transistor is VGS(th)N > 0. To ensure normal operation, VDD > |VGS(th)P| + VGS(th)N is required, where VDD is the power supply voltage. If the input is low (e.g., 0V), the PMOS transistor is turned on, the NMOS transistor is turned off, and the output voltage is close to VDD. If the input is high (e.g., VDD), the NMOS transistor is turned on, the PMOS transistor is turned off, and the output voltage is close to 0V.
[0038] It is understandable that the more inverters connected in series in the delay unit 11, the longer the delay time will be when the initial pulse signal is delayed. Therefore, the number of inverters in the delay unit 11 can be set according to the specific application scenario, and is not limited here.
[0039] In some embodiments, the number of inverters in the delay reference unit 201 and the number of inverters in the delay circuit 10 are either odd or even. The output of the unit corresponding to the odd number of inverters is connected to the first clock input Clk-1 of the first D flip-flop, and the output of the unit corresponding to the even number of inverters is connected to the first data input D-1 of the first D flip-flop. This allows the comparison signal generation unit 202 to acquire the input of the first data input D-1 based on the input of the first clock input Clk-1 and generate a comparison signal.
[0040] In some implementations, the control module 30 generates a corresponding control signal based on the comparison signal, wherein the control signal is specifically a control word signal. The control word signal is used to control the duty cycle of the first pulse signal generated by the delay circuit 10, such that the duty cycle of the generated first pulse signal is the desired duty cycle, that is, the delay time corresponding to the generated first pulse signal is the desired delay time.
[0041] For example, please see Figure 3 The delay unit 11 has multiple inverters A connected sequentially from the input terminal IN to the output terminal OUT. The output terminal of each inverter A is grounded through a variable load capacitor C. The control word DCTRL is used to adjust the capacitance value of each variable capacitor C. When the input signal passes through the inverter A between the input terminal IN and the output terminal OUT, there will be a delay. This delay can be adjusted by adjusting the value of the load capacitor C at the output terminal of each inverter A. The adjustment of the load capacitor C is controlled by the control word DCTRL to achieve adjustable delay.
[0042] It is understandable that the delay can also be adjusted by adjusting the current or voltage of the delay unit 11. The specific implementation method of delay adjustment can be selected according to the specific application, and no restrictions are imposed here.
[0043] One possibility is that the control module 30 has a delay chip, and control words are written directly to the delay chip. The adjustment resolution is the numerically controlled delay step of the chip itself (e.g., the delay step is 10ps).
[0044] The working principle of the delay modulation circuit 1 described above in the embodiments of the present invention will be explained in detail below.
[0045] After receiving the delay modulation start command, the delay modulation circuit 1 obtains the first pulse signal and the second pulse signal according to the delay modulation start command, so as to obtain the comparison signal based on the first pulse signal and the second pulse signal. The delay modulation start command can be generated by the user or by the delay modulation circuit 1 periodically and automatically to start the delay modulation of the delay circuit 10.
[0046] In some embodiments, the delay reference unit 201 includes an odd number of inverters, the delay circuit 10 includes an even number of inverters, and the delay of the delay circuit 10 increases when the control word is increased.
[0047] For example, please see Figure 4 The output of the delay circuit 10 is connected to the first data input D-1 of the first D flip-flop 2021. The delay reference unit 201 includes an inverter whose output is connected to the first clock input Clk-1 of the first D flip-flop 2021. The inverter is used to reverse the phase of the input clock signal Clk-in by 180° and output a second pulse signal so that the first D flip-flop 2021 samples the first pulse signal input to the first data input D-1 according to the second pulse signal to obtain a comparison signal.
[0048] The delay time is the product of the pulse duty cycle and the pulse period. Therefore, the current delay time T1 of the delay circuit 10 is obtained according to the first pulse signal, and the preset delay time TA corresponding to the clock signal Clk-in is obtained according to the second pulse signal.
[0049] For example, please refer to Figure 5 , Figure 5 This is a waveform diagram of each signal when the current delay time T1 of the delay circuit 10 is greater than the preset delay time TA. The clock signal Clk-in and the second pulse signal B have a duty cycle of 50%, and the first pulse signal A has a duty cycle greater than 50%. At this time, the first D flip-flop 2021 samples the first pulse signal A based on the rising edge of the second pulse signal B, which is also based on the falling edge of the clock signal Clk-in. Because the duty cycle of the first pulse signal A is greater than 50%, the comparison signal output by the first D flip-flop 2021 is a high-level signal.
[0050] After receiving a high-level signal, the control module 30 generates a control signal that decreases the control word. The delay unit 11 adjusts its parameters according to the corresponding control word to reduce the current delay time T1 of the delay circuit 10. The parameter adjustment of the delay unit 11 can be adjusting voltage parameters, capacitance parameters, current parameters, etc., and is not limited here. When the comparison signal output by the first D flip-flop 2021 is a low-level signal, that is, when the comparison signal changes, it indicates that the current delay time T1 is equal to the preset delay time TA, thus completing the delay adjustment of the delay circuit 10.
[0051] For example, please refer to Figure 6 , Figure 6 This diagram illustrates the waveforms of each signal when the current delay time T1 of the delay circuit 10 is less than the preset delay time TA. The clock signal Clk-in and the second pulse signal B have a duty cycle of 50%, while the first pulse signal A has a duty cycle less than 50%. At this time, the first D flip-flop 2021 samples the first pulse signal A based on the rising edge of the second pulse signal B, which is also the falling edge of the clock signal Clk-in. Because the duty cycle of the first pulse signal A is less than 50%, the comparison signal output by the first D flip-flop 2021 is a low-level signal.
[0052] After receiving a low-level signal, the control module 30 generates a control signal that increases the control word. The delay unit 11 adjusts its parameters according to the corresponding control word to increase the current delay time T1 of the delay circuit 10. The parameter adjustment of the delay unit 11 can be adjusting voltage parameters, capacitance parameters, current parameters, etc., and is not limited here. When the comparison signal output by the first D flip-flop 2021 is a high-level signal, that is, when the comparison signal changes, it indicates that the current delay time T1 is equal to the preset delay time TA, thus completing the delay adjustment of the delay circuit 10.
[0053] After the delay adjustment is completed, the parameter configuration of the delay unit 11 is saved so that the delay unit 11 can perform delay processing on subsequent pulse signals according to the current configuration.
[0054] The deviation between the current delay time T1 and the preset delay time TA of the delay circuit 10 is obtained through the first pulse signal and the second pulse signal, so that the control module 30 generates a corresponding control signal to adjust the current delay time T1 of the delay circuit 10, thereby reducing the deviation between the current delay time and the preset delay time, thus avoiding the distortion of the duty cycle of the first pulse signal generated by the delay circuit 10 and ensuring the accuracy of the first pulse signal.
[0055] In some embodiments, the delay reference unit 201 includes an even number of inverters, the delay circuit 10 includes an odd number of inverters, and the delay of the delay circuit 10 increases when the control word is increased.
[0056] For example, please see Figure 7 The delay reference unit 201 includes two inverters, the output of which is connected to the first data input D-1 of the first D flip-flop 2021 to output a second pulse signal. The output of the delay circuit 10 is connected to the first clock input Clk-1 of the first D flip-flop 2021, which is used to delay the initial pulse signal and invert its phase by 180° to output a first pulse signal, so that the first D flip-flop 2021 samples the input second pulse signal according to the first pulse signal to obtain a comparison signal.
[0057] The delay time is the product of the pulse duty cycle and the pulse period. Therefore, the current delay time T1 of the delay circuit 10 is obtained according to the first pulse signal, and the preset delay time TA corresponding to the clock signal Clk-in is obtained according to the second pulse signal.
[0058] It is understandable that an inverter is set at the signal output terminal Output of the delay circuit 10 to ensure the logical correctness of the pulse signal output by the delay circuit 10.
[0059] For example, please refer to Figure 8 , Figure 8 The diagram shows the waveforms of each signal when the current delay time T1 of the delay circuit 10 is greater than the preset delay time TA. The clock signal Clk-in and the second pulse signal B have a duty cycle of 50%, while the duty cycle of the first pulse signal A is less than 50%. At this time, the first D flip-flop 2021 samples the second pulse signal B based on the rising edge of the first pulse signal A. Therefore, the comparison signal output by the first D flip-flop 2021 is a low-level signal.
[0060] After receiving a low-level signal, the control module 30 generates a control signal that decreases the control word. The delay unit 11 adjusts its parameters according to the corresponding control word to reduce the current delay time T1 of the delay circuit 10. The parameter adjustment of the delay unit 11 can be adjusting voltage parameters, capacitance parameters, current parameters, etc., and is not limited here. When the comparison signal output by the first D flip-flop 2021 is a high-level signal, that is, when the comparison signal changes, it indicates that the current delay time T1 is equal to the preset delay time TA, thus completing the delay adjustment of the delay circuit 10.
[0061] For example, please refer to Figure 9 , Figure 9The diagram shows the waveforms of each signal when the current delay time T1 of the delay circuit 10 is less than the preset delay time TA. The clock signal Clk-in and the second pulse signal B have a duty cycle of 50%, while the first pulse signal A has a duty cycle greater than 50%. At this time, the first D flip-flop 2021 samples the second pulse signal B based on the rising edge of the first pulse signal A. Therefore, the comparison signal output by the first D flip-flop 2021 is a high-level signal.
[0062] After receiving a high-level signal, the control module 30 generates a control signal that increases the control word. The delay unit 11 adjusts its parameters according to the corresponding control word to increase the current delay time T1 of the delay circuit 10. The parameter adjustment of the delay unit 11 can be adjusting voltage parameters, capacitance parameters, current parameters, etc., and is not limited here. When the comparison signal output by the first D flip-flop 2021 is a low-level signal, that is, when the comparison signal changes, it indicates that the current delay time T1 is equal to the preset delay time TA, thus completing the delay adjustment of the delay circuit 10.
[0063] After the delay adjustment is completed, the parameter configuration of the delay unit 11 is saved so that the delay unit 11 can perform delay processing on subsequent pulse signals according to the current configuration.
[0064] The deviation between the current delay time T1 and the preset delay time TA of the delay circuit 10 is obtained through the first pulse signal and the second pulse signal, so that the control module 30 generates a corresponding control signal to adjust the current delay time T1 of the delay circuit 10, thereby reducing the deviation between the current delay time and the preset delay time, thus avoiding the distortion of the duty cycle of the first pulse signal generated by the delay circuit 10 and ensuring the accuracy of the first pulse signal.
[0065] In some implementations, please refer to Figure 10 The delay reference unit 201 includes a reference circuit 211, which includes a preset number of inverters for outputting a second pulse signal that has undergone a preset delay processing. A preset delay time TA corresponding to the preset delay processing is obtained based on the second pulse signal, and the current delay time T1 of the delay circuit 10 is obtained based on the first pulse signal. The comparison signal generation unit 202 obtains a corresponding comparison signal based on the second pulse signal and the first pulse signal. The control module 30 generates a corresponding control signal based on the comparison signal, so that the delay circuit 10 adjusts the parameter configuration of the delay unit 11 according to the control signal to adjust the delay time T1, thereby reducing the deviation between the delay time T1 and the preset delay time TA.
[0066] After the delay adjustment is completed, the parameter configuration of the delay unit 11 is saved so that the delay unit 11 can perform delay processing on subsequent pulse signals according to the current configuration.
[0067] Using the preset delay time TA of the reference circuit 211 as the target for delay adjustment, the deviation between the current delay time T1 of the delay circuit 10 and the preset delay time TA is obtained through the first pulse signal and the second pulse signal, so that the control module 30 generates a corresponding control signal to adjust the current delay time T1 of the delay circuit 10, thereby aligning the delay time of the delay circuit 10 with the delay time of the reference circuit 211, that is, realizing clock synchronization between the delay circuit 10 and the reference circuit 211.
[0068] The present invention also provides a chip comprising the delay modulation circuit described in any of the above embodiments of the present invention.
[0069] Therefore, the specific implementation of the chip in this embodiment of the invention is similar to the specific implementation of the delay modulation circuit in this embodiment of the invention. Please refer to the description of the delay modulation circuit section for details, which will not be repeated here.
[0070] The present invention also provides a server for data processing or computation. The server includes a connection board, a control board, a heat sink, a power supply board, and one or more computing boards, each computing board including one or more chips. The control board is connected to the computing boards via the connection board, and the heat sink is disposed around the computing boards. The power supply board provides power to the connection board, control board, heat sink, and computing boards.
[0071] It should be understood that the term "and / or" as used in this specification and the appended claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes such combinations. It should be noted that, herein, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or system. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or system that includes that element.
[0072] The sequence numbers of the above embodiments of the present invention are merely for descriptive purposes and do not represent the superiority or inferiority of the embodiments. The above descriptions are only specific embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and these modifications or substitutions should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.
Claims
1. A delay modulation circuit, characterized in that, include: A delay circuit, connected to a clock source and a data source, is used to output a first pulse signal that has undergone delay processing based on the clock signal from the clock source and the data signal from the data source. The comparison circuit includes a delay reference unit and a comparison signal generation unit; the delay reference unit is connected to the clock source and is used to output a corresponding second pulse signal according to the clock signal, wherein the second pulse signal is a pulse signal that has undergone standard delay processing. The comparison signal generation unit includes a first D flip-flop, which includes a first clock input, a first data input, and a first signal output. The first clock input is connected to one of the delay circuit and the delay reference unit; the first data input is connected to the other of the delay circuit and the delay reference unit; the first signal output is connected to a control module; the first D flip-flop is used to output a corresponding comparison signal based on the first pulse signal and the second pulse signal, wherein the comparison signal represents the magnitude relationship between the delay time corresponding to the delay processing and the standard delay time corresponding to the standard delay processing. and A control module, connected to the comparison signal generation unit and the delay circuit, is used to generate a corresponding control signal based on the comparison signal, so as to adjust the delay time of the delay circuit for delay processing according to the control signal.
2. The delay modulation circuit according to claim 1, characterized in that, Both the delay reference unit and the delay circuit include a preset number of inverters. The number of inverters in the delay reference unit and the number of inverters in the delay circuit are either odd or even.
3. The delay modulation circuit according to claim 1, characterized in that, The delay circuit includes a second D flip-flop and a delay unit; The second D flip-flop is connected to the clock source and the data source, and is used to generate a corresponding initial pulse signal according to the clock signal of the clock source and the data signal of the data source; The delay unit is connected to the second D flip-flop and is used to delay the initial pulse signal to output the first pulse signal after the delay.
4. The delay modulation circuit according to claim 3, characterized in that: The second D flip-flop includes a second data input terminal, a second clock input terminal, a second signal output terminal, and a clear signal terminal. The second data input terminal is connected to the data source, the second clock input terminal is connected to the clock source, the second signal output terminal is connected to the input terminal of the delay unit, and the clear signal terminal is connected to the output terminal of the delay unit. The delay unit includes multiple inverters connected in series. Each inverter includes a PMOS transistor and an NMOS transistor. The source of the PMOS transistor is connected to a power supply, the gate of the PMOS transistor is connected to the gate of the NMOS transistor and serves as the input terminal, the drain of the PMOS transistor is connected to the drain of the NMOS transistor and serves as the output terminal, and the source of the NMOS transistor is connected to ground.
5. A delay modulation method, characterized in that, The method, applied to the delay modulation circuit according to any one of claims 1-4, comprises: Obtain the delay modulation start command; According to the delay modulation start command, the first clock input terminal and the first data input terminal of the first D flip-flop of the comparison signal generation unit are controlled to obtain the first pulse signal of the delay circuit and the second pulse signal of the delay reference unit. The first pulse signal is a pulse signal after delay processing, and the second pulse signal is a pulse signal after standard delay processing. The first D flip-flop is controlled to generate a comparison signal based on the first pulse signal and the second pulse signal. The comparison signal is the magnitude relationship between the delay time corresponding to the delay processing and the standard delay time corresponding to the standard delay processing. Based on the comparison signal output from the first signal output terminal of the first D flip-flop, a control signal corresponding to the comparison signal is generated to adjust the delay time of the delay circuit according to the control signal.
6. The delay modulation method according to claim 5, characterized in that, The comparison signal includes a low-level signal and a high-level signal; the delay reference unit includes an odd number of inverters; the delay circuit includes an even number of inverters; and generating the comparison signal based on the first pulse signal and the second pulse signal includes: When the current delay time of the delay circuit is greater than the preset delay time, the output comparison signal is a high-level signal; When the current delay time of the delay circuit is less than the preset delay time, the output comparison signal is a low-level signal.
7. The delay modulation method according to claim 6, characterized in that, The control signal includes a control word signal. Generating a corresponding control signal based on the comparison signal to adjust the delay time of the delay circuit according to the control signal includes: Generate the corresponding control word signal based on the comparison signal; The delay time of the delay circuit is adjusted according to the control word signal; When the comparison signal changes abruptly, the delay adjustment is completed.
8. A chip, characterized in that, The chip integrates the delay modulation circuit as described in any one of claims 1-4.
9. A server, characterized in that, It includes at least one chip as described in claim 8.