Pixel Circuit, Driving Method Thereof, Display Substrate, and Display Device

Abstract

A pixel circuit, a driving method thereof, a display substrate, and a display device, wherein the pixel circuit includes: a first node control sub-circuit, a second node control sub-circuit, a light-emitting control sub-circuit, and a driving sub-circuit. The second node control sub-circuit is electrically connected to a scan signal line, a first node, and a fourth node respectively, and is configured to store signals of the first node and the fourth node, and drive the signal of the first node to change under the control of the signal of the scan signal line.

Description

Technical Field

[0001] The present disclosure relates to, but is not limited to, the field of display technologies, and particularly relates to a pixel circuit, a driving method thereof, a display substrate, and a display device. Background Art

[0002] Organic Light Emitting Diodes (OLEDs) and Quantum-dot Light Emitting Diodes (QLEDs) are active light-emitting display devices, which have the advantages of self-luminescence, wide viewing angles, high contrast ratios, low power consumption, extremely high response speeds, thinness, flexibility, and low cost. With the continuous development of display technologies, flexible display devices (Flexible Displays) using OLEDs or QLEDs as light-emitting devices and controlled by Thin Film Transistors (TFTs) have become the mainstream products in the current display field. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail in the present disclosure. This overview is not intended to limit the scope of protection of the claims.

[0004] In a first aspect, the present disclosure provides a pixel circuit, including: a first node control sub-circuit, a second node control sub-circuit, a light-emitting control sub-circuit, and a driving sub-circuit. The pixel circuit is configured to drive a light-emitting device to emit light;

[0005] The first node control sub-circuit is electrically connected to a scan signal line, a data signal line, a first reset signal line, a second reset signal line, an initial signal line, a first power supply line, a first node, a second node, a third node, and a fourth node respectively, and is configured to provide the signal of the first power supply line or the signal of the second node to the first node, provide the signal of the data signal line to the third node, and provide the signal of the initial signal line to the fourth node under the control of the signals of the scan signal line, the first reset signal line, and the second reset signal line;

[0006] The second node control sub-circuit is electrically connected to the scan signal line, the first node, and the fourth node respectively, and is configured to store the signals of the first node and the fourth node, and drive the signal of the first node to change under the control of the signal of the scan signal line;

[0007] The driving sub-circuit is electrically connected to the first node, the second node, and the third node respectively, and is configured to provide a driving current to the third node under the control of the signals of the first node and the second node;

[0008] The light-emitting control sub-circuit is electrically connected to the light-emitting signal line, the first power supply line, the second node, the third node, and the fourth node respectively, and is configured to provide the signal of the first power supply line to the second node and the signal of the third node to the fourth node under the control of the signal of the light-emitting signal line;

[0009] The light-emitting device is electrically connected to the fourth node and the second power supply line respectively.

[0010] In an exemplary embodiment, the first node control sub-circuit includes: a reset sub-circuit, a compensation sub-circuit, and a write sub-circuit;

[0011] The reset sub-circuit is electrically connected to the first reset signal line, the second reset signal line, the first power supply line, the initial signal line, the first node, and the fourth node respectively, and is configured to provide the signal of the first power supply line to the first node under the control of the signal of the first reset signal line and provide the signal of the initial signal line to the fourth node under the control of the signal of the second reset signal line;

[0012] The compensation sub-circuit is electrically connected to the scan signal line, the first node, and the second node respectively, and is configured to provide the signal of the second node to the first node under the control of the signal of the third scan signal line;

[0013] The write sub-circuit is electrically connected to the scan signal line, the data signal line, and the third node respectively, and is configured to provide the signal of the data signal line to the third node under the control of the signal of the scan signal line.

[0014] In an exemplary embodiment, the reset sub-circuit includes: a first transistor and a seventh transistor, the compensation sub-circuit includes: a second transistor, and the write transistor includes: a fourth transistor;

[0015] The control electrode of the first transistor is electrically connected to the first reset signal line, the first electrode of the first transistor is electrically connected to the first power supply line, and the second electrode of the first transistor is electrically connected to the first node;

[0016] The control electrode of the second transistor is electrically connected to the scan signal line, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the second node;

[0017] The control electrode of the fourth transistor is electrically connected to the scan signal line, the first electrode of the fourth transistor is electrically connected to the data signal line, and the second electrode of the fourth transistor is electrically connected to the third node;

[0018] The control electrode of the seventh transistor is electrically connected to the second reset signal line, the first electrode of the seventh transistor is electrically connected to the initial signal line, and the second electrode of the seventh transistor is electrically connected to the fourth node.

[0019] In an exemplary embodiment, the second node control sub - circuit includes: a first capacitor and a second capacitor, and both the first capacitor and the second capacitor include: a first electrode plate and a second electrode plate;

[0020] The first electrode plate of the first capacitor is electrically connected to the first node, and the second electrode plate of the first capacitor is electrically connected to the fourth node;

[0021] The first electrode plate of the second capacitor is electrically connected to the scan signal line, and the second electrode plate of the second capacitor is electrically connected to the first node.

[0022] In an exemplary embodiment, the first node control sub - circuit includes: a first transistor, a second transistor, a fourth transistor, and a seventh transistor; the second node control sub - circuit includes: a first capacitor and a second capacitor; the driving sub - circuit includes: a third transistor; the light - emitting control sub - circuit includes: a fifth transistor and a sixth transistor; and both the first capacitor and the second capacitor include: a first electrode plate and a second electrode plate;

[0023] The control electrode of the first transistor is electrically connected to the first reset signal line, the first pole of the first transistor is electrically connected to the first power supply line, and the second pole of the first transistor is electrically connected to the first node;

[0024] The control electrode of the second transistor is electrically connected to the scan signal line, the first pole of the second transistor is electrically connected to the first node, and the second pole of the second transistor is electrically connected to the second node;

[0025] The control electrode of the third transistor is electrically connected to the first node, the first pole of the third transistor is electrically connected to the second node, and the second pole of the third transistor is electrically connected to the third node;

[0026] The control electrode of the fourth transistor is electrically connected to the scan signal line, the first pole of the fourth transistor is electrically connected to the data signal line, and the second pole of the fourth transistor is electrically connected to the third node;

[0027] The control electrode of the fifth transistor is electrically connected to the light - emitting signal line, the first pole of the fifth transistor is electrically connected to the first power supply line, and the second pole of the fifth transistor is electrically connected to the second node;

[0028] The control electrode of the sixth transistor is electrically connected to the light - emitting signal line, the first pole of the sixth transistor is electrically connected to the third node, and the second pole of the sixth transistor is electrically connected to the fourth node;

[0029] The control electrode of the seventh transistor is electrically connected to the second reset signal line, the first pole of the seventh transistor is electrically connected to the initial signal line, and the second pole of the seventh transistor is electrically connected to the fourth node;

[0030] The first electrode plate of the first capacitor is electrically connected to the first node, and the second electrode plate of the first capacitor is electrically connected to the fourth node;

[0031] The first electrode plate of the second capacitor is electrically connected to the scan signal line, and the second electrode plate of the second capacitor is electrically connected to the first node.

[0032] In an exemplary embodiment, the transistor types of the first transistor to the seventh transistor are the same, and all are oxide transistors.

[0033] In an exemplary embodiment, the time when the signal of the second reset signal line is at an effective level signal includes: a first time period and a second time period that occur in sequence and are continuous;

[0034] The signal of the first reset signal line is at an effective level signal in the first time period and at an invalid level signal in the second time period, the signal of the scan signal line is at an invalid level signal in the first time period, and at an effective level signal in the second time period;

[0035] When the signal of the second reset signal line is at an effective level signal, the signal of the light emitting signal line is at an invalid level signal, and when the signal of the light emitting signal line is at an effective level signal, the signals of the first reset signal line, the second reset signal line, and the scan signal line are all at invalid level signals.

[0036] In an exemplary embodiment, the capacitance value C1 of the first capacitor and the capacitance value C2 of the second capacitor satisfy:

[0037] C2 = C1 / (ΔV1 + V OLED -V init )

[0038] Wherein, ΔV1 is the voltage value of the jump of the signal of the first node N1, V OLED is the anode voltage of the light emitting device, V init is the voltage value of the signal of the initial signal line;

[0039] The voltage value of the signal of the initial signal line is less than the voltage value of the signal of the second power supply line.

[0040] In a second aspect, the present disclosure also provides a display substrate, including: the above pixel circuit.

[0041] In an exemplary embodiment, it includes: a substrate and a driving circuit layer and a light emitting structure layer provided on the substrate. The driving circuit layer includes: a pixel circuit, a light emitting signal line, an initial signal line, a first scan signal line, a first reset signal line, a second reset signal line, a first power supply line, and a data signal line. The light emitting structure layer includes: a light emitting device.

[0042] In an exemplary embodiment, the driving circuit layer includes a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a fourth insulating layer, and a planarization layer that are sequentially disposed on a substrate; the pixel circuit includes: a plurality of transistors, a first capacitor, and a second capacitor, and the first capacitor and the second capacitor each include: a first electrode plate and a second electrode plate;

[0043] The semiconductor layer at least includes the active layers of a plurality of transistors;

[0044] The first conductive layer at least includes a first reset signal line, a scan signal line, a light-emitting signal line, a second reset signal line, the control electrodes of a plurality of transistors, the first electrode plate of the first capacitor, and the second electrode plate of the second capacitor;

[0045] The second conductive layer at least includes an initial signal line and the second electrode plate of the first capacitor;

[0046] The third conductive layer at least includes a data signal line, a first power supply line, the second electrode plate of the second capacitor, and the first and second poles of a plurality of transistors.

[0047] In an exemplary embodiment, the driving circuit layer includes a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a fourth insulating layer, and a planarization layer that are sequentially disposed on a substrate; the pixel circuit includes: a first transistor to a seventh transistor, a first capacitor, and a second capacitor, and the first capacitor and the second capacitor each include: a first electrode plate and a second electrode plate;

[0048] The semiconductor layer at least includes the active layers of a plurality of transistors;

[0049] The first conductive layer at least includes a first reset signal line, a scan signal line, a light-emitting signal line, and a second reset signal line, and the control electrodes of the first transistor to the seventh transistor, the first electrode plate of the first capacitor, and the second electrode plate of the second capacitor, and the first reset signal line, the scan signal line, the light-emitting signal line, and the second reset signal line extend along a first direction;

[0050] The second conductive layer at least includes an initial signal line and the second electrode plate of the first capacitor;

[0051] The third conductive layer at least includes a data signal line, a first power supply line, the second electrode plate of the second capacitor, and the first and second poles of the first transistor, the first pole of the second transistor, the first pole of the fourth transistor, the first pole of the fifth transistor, the second pole of the sixth transistor, the first and second poles of the seventh transistor, and the data signal line and the first power supply line extend along a second direction, and the first direction intersects with the second direction.

[0052] In an exemplary embodiment, the region where the scan signal line overlaps with the active layer of the second transistor serves as the control electrode of the second transistor, the region where the scan signal line overlaps with the active layer of the fourth transistor serves as the control electrode of the fourth transistor, and the region where the scan signal line overlaps with the second electrode of the first transistor serves as the first electrode plate of the second capacitor.

[0053] In an exemplary embodiment, the second electrode plate of the first capacitor includes: a capacitor main body portion and a capacitor connection portion. The capacitor connection portion is located on the side of the capacitor main body portion close to the initial signal line and is interconnected with the capacitor main body portion;

[0054] The orthographic projection of the capacitor main body portion on the substrate at least partially overlaps with the orthographic projection of the first electrode plate of the first capacitor on the substrate; an opening is provided on the capacitor main body portion, and the opening exposes the first electrode plate covering the first capacitor; the orthographic projection of the capacitor connection portion on the substrate partially overlaps with the orthographic projections of the light-emitting signal line and the active layer of the sixth transistor on the substrate.

[0055] In an exemplary embodiment, it further includes: first vias to sixth vias provided on the first insulating layer to the third insulating layer, a seventh via provided on the second insulating layer and the third insulating layer, an eighth via and a ninth via provided on the third insulating layer;

[0056] The orthographic projection of the first via on the substrate is within the range of the orthographic projection of the active layer of the first transistor on the substrate, the orthographic projection of the second via on the substrate is within the range of the orthographic projection of the active layer of the first transistor on the substrate, the orthographic projection of the third via on the substrate is within the range of the orthographic projection of the active layer of the fourth transistor on the substrate, the orthographic projection of the fourth via on the substrate is within the range of the orthographic projection of the active layer of the fifth transistor on the substrate, the orthographic projection of the fifth via on the substrate is within the range of the orthographic projection of the active layer of the sixth transistor on the substrate, the orthographic projection of the sixth via on the substrate is within the range of the orthographic projection of the active layer of the seventh transistor on the substrate, the orthographic projection of the seventh via on the substrate is within the range of the orthographic projection of the opening on the substrate, the orthographic projection of the eighth via on the substrate is within the range of the orthographic projection of the initial signal line on the substrate, and the orthographic projection of the ninth via on the substrate is within the range of the orthographic projection of the second electrode plate of the first capacitor on the substrate.

[0057] In an exemplary embodiment, a virtual straight line extending in the second direction passes through the first via and the fourth via, a virtual straight line extending in the first direction passes through the second via and the third via, a virtual straight line extending in the second direction passes through the fifth via and the ninth via, and a virtual straight line extending in the first direction passes through the sixth via and the eighth via.

[0058] In an exemplary embodiment, the positive projection of the first power supply line on the substrate at least partially overlaps with the positive projections of the first via hole and the fourth via hole on the substrate. The region where the first power supply line overlaps with the first via hole serves as the first pole of the first transistor, and the region where the first power supply line overlaps with the fourth via hole serves as the first pole of the fifth transistor.

[0059] In an exemplary embodiment, the data signal line includes: a first data connection portion, a second data connection portion, a third data connection portion, a fourth data connection portion, and a fifth data connection portion arranged in sequence along a second direction. The second data connection portion is respectively connected to the first data connection portion and the third data connection portion. The fourth data connection portion is respectively connected to the third data connection portion and the fifth data connection portion. A virtual straight line extending along the second direction passes through the first data connection portion and the fifth data connection portion. The third data connection portion is located on a side of the first data connection portion and the fifth data connection portion away from the first power supply line;

[0060] The first data connection portion extends along the second direction, and the angle between the first data connection portion and the second data connection portion is greater than 90 degrees and less than 180 degrees. The third data connection portion extends along the second direction, and the angles between the third data connection portion and the second data connection portion and the fourth data connection portion are both greater than 90 degrees and less than 180 degrees. The fifth data connection portion extends along the second direction, and the angle between the fifth data connection portion and the fourth data connection portion is greater than 90 degrees and less than 180 degrees.

[0061] In an exemplary embodiment, the positive projection of the second data connection portion on the substrate partially overlaps with the positive projection of the first reset signal line on the substrate. The positive projection of the third data connection portion on the substrate partially overlaps with the positive projections of the third via hole and the scan signal line on the substrate. The region where the third data connection portion overlaps with the third via hole serves as the first pole of the fourth transistor. The positive projection of the fourth data connection portion on the substrate partially overlaps with the positive projections of the light-emitting signal line and the second electrode plate of the first capacitor on the substrate. The positive projection of the fifth data connection portion on the substrate partially overlaps with the positive projections of the second reset signal line and the initial signal line on the substrate.

[0062] In an exemplary embodiment, the second pole of the first transistor and the first pole of the second transistor are the same electrode, and their positive projections on the substrate partially overlap with the positive projections of the second via hole, the seventh via hole, the second electrode plate of the first capacitor, and the scan signal line on the substrate. The region where the second pole of the first transistor overlaps with the scan signal line serves as the second electrode plate of the second capacitor;

[0063] The second pole of the sixth transistor and the second pole of the seventh transistor are the same electrode, and their positive projections on the substrate at least partially overlap with the positive projections of the fifth via hole and the ninth via hole on the substrate;

[0064] The positive projection of the first pole of the seventh transistor on the substrate overlaps at least partially with the positive projections of the sixth via and the eighth via on the substrate.

[0065] In a third aspect, the present disclosure also provides a display device, including: the above-mentioned display substrate.

[0066] In a fourth aspect, the present disclosure also provides a driving method for a pixel circuit, configured to drive the above-mentioned pixel circuit, and the method includes:

[0067] Under the control of the signals of the scanning signal line, the first reset signal line, and the second reset signal line, the first node control sub-circuit provides the signal of the first power supply line or the signal of the second node to the first node, provides the signal of the data signal line to the third node, and provides the signal of the initial signal line to the fourth node;

[0068] The second node control sub-circuit stores the signals of the first node and the fourth node, and drives the signal of the first node to change under the control of the signal of the scanning signal line;

[0069] The driving sub-circuit provides a driving current to the third node under the control of the signals of the first node and the second node, and the light-emitting control sub-circuit provides the signal of the first power supply line to the second node and provides the signal of the third node to the fourth node under the control of the signal of the light-emitting signal line.

[0070] Other aspects can be understood after reading and understanding the drawings and the detailed description. Description of the Drawings

[0071] The drawings are used to provide an understanding of the technical solutions of the present disclosure, and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solutions of the present disclosure, and do not constitute a limitation to the technical solutions of the present disclosure.

[0072] Figure 1 It is a schematic structural diagram of a pixel circuit provided by an embodiment of the present disclosure;

[0073] Figure 2 It is a schematic structural diagram of a first node control sub-circuit provided by an exemplary embodiment;

[0074] Figure 3 It is an equivalent circuit diagram of a first node control sub-circuit provided by an exemplary embodiment;

[0075] Figure 4 It is an equivalent circuit diagram of a second node control sub-circuit provided by an exemplary embodiment;

[0076] Figure 5 It is an equivalent circuit diagram of a pixel circuit;

[0077] Figure 6It is a timing diagram of the operation of a pixel driving circuit;

[0078] Figure 7 It is a schematic structural diagram of a display substrate provided by an embodiment of the present disclosure;

[0079] Figure 8 It is a schematic diagram after forming a semiconductor layer pattern;

[0080] Figure 9 It is a schematic diagram of a first conductive layer pattern;

[0081] Figure 10 It is a schematic diagram after forming a first conductive layer pattern;

[0082] Figure 11 It is a schematic diagram of a second conductive layer pattern;

[0083] Figure 12 It is a schematic diagram after forming a second conductive layer pattern;

[0084] Figure 13 It is a schematic diagram after forming a third insulating layer;

[0085] Figure 14 It is a schematic diagram of a third conductive layer pattern;

[0086] Figure 15 It is a schematic diagram after forming a third conductive layer pattern. Detailed implementation manners

[0087] To make the objectives, technical solutions and advantages of the present disclosure clearer and more understandable, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation manners can be implemented in multiple different forms. It is easy for those of ordinary skill in the art to understand the fact that the manners and contents can be transformed into various forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be construed as being limited only to the contents described in the following implementation manners. Without conflict, the embodiments and features in the embodiments of the present disclosure can be combined with each other arbitrarily. To keep the following description of the embodiments of the present disclosure clear and concise, the detailed descriptions of some known functions and known components are omitted. The accompanying drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures can refer to the general design

[0088] The scale of the drawings in the present disclosure can be used as a reference in the actual process, but is not limited thereto. For example, the width-to-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the drawings. The drawings described in the present disclosure are only schematic diagrams of the structure, and one embodiment of the present disclosure is not limited to the shapes or values shown in the drawings.

[0089] The ordinal numbers such as "first", "second", "third", etc. in this specification are set to avoid confusion of components, rather than to limit the quantity.

[0090] In this specification, for convenience, terms indicating orientation or positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are used to describe the positional relationship of components with reference to the drawings. This is only for the convenience of describing this specification and simplifying the description, rather than indicating or implying that the device or component referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation to the present disclosure. The positional relationship of the components is appropriately changed according to the direction of describing each component. Therefore, it is not limited to the terms described in the specification and can be appropriately replaced according to the situation.

[0091] In this specification, unless otherwise clearly defined and limited, the terms "mounted", "connected", and "connected" shall be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected, or indirectly connected through an intermediate member, or the internal communication of two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.

[0092] In this specification, a transistor refers to an element that includes at least three elements: a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (drain electrode element, drain region, or drain electrode) and the source electrode (source electrode element, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region where current mainly flows.

[0093] In this specification, the first pole can be the drain electrode and the second pole can be the source electrode, or the first pole can be the source electrode and the second pole can be the drain electrode. In the case of using transistors with opposite polarities or when the current direction changes during circuit operation, etc., the functions of the "source electrode" and "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged with each other.

[0094] In this specification, "electrically connected" includes cases where components are connected together through elements having some electrical effect. The "elements having some electrical effect" are not particularly limited as long as they can transfer electrical signals between the components to be connected. Examples of the "elements having some electrical effect" include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0095] In this specification, "parallel" means a state where the angle formed by two straight lines is -10° or more and 10° or less. Therefore, it also includes a state where the angle is -5° or more and 5° or less. In addition, "perpendicular" means a state where the angle formed by two straight lines is 80° or more and 100° or less. Therefore, it also includes a state where the angle is 85° or more and 95° or less.

[0096] In this specification, "film" and "layer" can be interchanged. For example, sometimes "conductive layer" can be changed to "conductive film". Similarly, sometimes "insulating film" can be changed to "insulating layer".

[0097] In this specification, the "formed on the same layer" means a structure formed by patterning two (or more) structures through the same patterning process, and their materials can be the same or different. For example, the materials of the precursors for forming multiple structures formed on the same layer are the same, and the finally formed materials can be the same or different.

[0098] Triangles, rectangles, trapezoids, pentagons, hexagons, etc. in this specification are not strictly defined and can be approximate triangles, rectangles, trapezoids, pentagons, hexagons, etc. There can be some small deformations due to tolerances, chamfers, arc edges, and deformations.

[0099] "About" in this disclosure means not strictly defining the boundary and allowing values within the process and measurement errors.

[0100] The low temperature poly-silicon (LTPS) technology is used in the display substrate. The LTPS technology has advantages such as high resolution, high response speed, high brightness, and high aperture ratio. Although it is welcomed by the market, the LTPS technology also has some defects, such as high production cost and large power consumption. At this time, the low temperature polycrystalline oxide (LTPO) technology solution emerged. Compared with the LTPS technology, the LTPO technology has smaller leakage current, faster pixel response, and an additional oxide layer on the display substrate, reducing the energy consumption required to activate the pixel points, thereby reducing the power consumption during screen display. However, compared with the manufacturing process of display products using the LTP0 technology, it is more complex and costly. With the emergence of high-mobility oxide materials, it becomes possible to drive OLED devices with oxides. At this time, it becomes possible to produce display products using oxide technology. Compared with the LTPO technology, the oxide technology has a simpler process, lower cost, and smaller leakage current, and has become the new mainstream trend. However, in the display products using oxide technology, the jump of the gate electrode of the driving transistor in the pixel circuit is relatively large, resulting in an increase in brightness when the display product is in low gray-scale display, reducing the contrast of the display product and affecting the display effect of the display product.

[0101] Figure 1 The following is a schematic structural diagram of the pixel circuit provided by the embodiment of the present disclosure. As Figure 1 shown, the pixel circuit provided by the embodiment of the present disclosure is configured to drive a light-emitting device to emit light, and includes: a first node control sub-circuit, a second node control sub-circuit, a light-emitting control sub-circuit, and a driving sub-circuit.

[0102] As Figure 1As shown, the first node control sub-circuit is electrically connected to the scan signal line Gate, the data signal line Data, the first reset signal line Reset1, the second reset signal line Reset2, the initial signal line INIT, the first power supply line VDD, the first node N1, the second node N2, the third node N3, and the fourth node N4 respectively, and is configured to provide the signal of the first power supply line VDD or the signal of the second node N2 to the first node N1 under the control of the signals of the scan signal line Gate, the first reset signal line Reset1, and the second reset signal line Reset2, provide the signal of the data signal line Data to the third node N3, and provide the signal of the initial signal line INIT to the fourth node N4; the second node control sub-circuit is electrically connected to the scan signal line Gate, the first node N1, and the fourth node N4 respectively, and is configured to store the signals of the first node N1 and the fourth node N4 and control the signal of the first node N1 under the control of the signal of the scan signal line Gate; the driving sub-circuit is electrically connected to the first node N1, the second node N2, and the third node N3 respectively, and is configured to provide a driving current to the third node N3 under the control of the signals of the first node N1 and the second node N2; the light-emitting control sub-circuit is electrically connected to the light-emitting signal line EM, the first power supply line VDD, the second node N2, the third node N3, and the fourth node N4 respectively, and is configured to provide the signal of the first power supply line VDD to the second node N2 and provide the signal of the third node N3 to the fourth node N4 under the control of the signal of the light-emitting signal line EM.

[0103] In an exemplary embodiment, the light-emitting device can be electrically connected to the fourth node N4 and the second power supply line VSS respectively.

[0104] In one exemplary embodiment, the first power supply line VDD can continuously provide a high-voltage power signal, and the second power supply line VSS can continuously provide a low-voltage power signal.

[0105] In one exemplary embodiment, the light-emitting device can be an organic light-emitting diode (OLED), including a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode). Exemplarily, the anode of the organic light-emitting diode is electrically connected to the fourth node N4, and the cathode of the organic light-emitting diode is electrically connected to the second power supply line VSS.

[0106] In an exemplary embodiment, the organic light-emitting layer may include a stacked hole injection layer (Hole Injection Layer, abbreviated as HIL), a hole transport layer (Hole Transport Layer, abbreviated as HTL), an electron blocking layer (EMectron Block Layer, abbreviated as EBL), a light-emitting layer (Emitting Layer, abbreviated as EML), a hole blocking layer (HoleBlock Layer, abbreviated as HBL), an electron transport layer (EMectron Transport Layer, abbreviated as ETL), and an electron injection layer (EMectron Injection Layer, abbreviated as EIL). In an exemplary embodiment, the hole injection layers of all sub-pixels may be a common layer connected together, the electron injection layers of all sub-pixels may be a common layer connected together, the hole transport layers of all sub-pixels may be a common layer connected together, the electron transport layers of all sub-pixels may be a common layer connected together, the hole blocking layers of all sub-pixels may be a common layer connected together, the light-emitting layers of adjacent sub-pixels may have a small overlap, or may be isolated, and the electron blocking layers of adjacent sub-pixels may have a small overlap, or may be isolated.

[0107] The pixel circuit provided by the embodiments of the present disclosure includes: a first node control sub-circuit, a second node control sub-circuit, a light emission control sub-circuit, and a driving sub-circuit. The pixel circuit is configured to drive a light-emitting device to emit light. The first node control sub-circuit is electrically connected to a scan signal line, a data signal line, a first reset signal line, a second reset signal line, an initial signal line, a first power supply line, a first node, a second node, a third node, and a fourth node respectively, and is configured to provide the signal of the first power supply line or the signal of the second node to the first node, provide the signal of the data signal line to the third node, and provide the signal of the initial signal line to the fourth node under the control of the signals of the scan signal line, the first reset signal line, and the second reset signal line. The second node control sub-circuit is electrically connected to the scan signal line, the first node, and the fourth node respectively, and is configured to store the signals of the first node and the fourth node, and drive the signal of the first node to change under the control of the signal of the scan signal line. The driving sub-circuit is electrically connected to the first node, the second node, and the third node respectively, and is configured to provide a driving current to the third node under the control of the signals of the first node and the second node. The light emission control sub-circuit is electrically connected to a light emission signal line, the first power supply line, the second node, the third node, and the fourth node respectively, and is configured to provide the signal of the first power supply line to the second node and provide the signal of the third node to the fourth node under the control of the signal of the light emission signal line. The light-emitting device is electrically connected to the fourth node and a second power supply line respectively. By setting the second node control sub-circuit to drive the signal of the first node to change under the control of the signal of the scan signal line, the present disclosure can reduce the jump of the first node under the control of the signal of the scan signal line, reduce the brightness during low gray-scale display, increase the contrast, and improve the display effect of the display product.

[0108] In an exemplary embodiment, the time when the signal of the second reset signal line Reset2 is at an effective level signal may include: a first time period and a second time period that occur in sequence and are continuous. Here, the continuity of the first time period and the second time period means that the end time of the first time period is the start time of the second time period.

[0109] In an exemplary embodiment, the signal of the first reset signal line Reset1 is at an effective level signal during the first time period and at an invalid level signal during the second time period. The signal of the scan signal line Gate is at an invalid level signal during the first time period and at an effective level signal during the second time period.

[0110] In an exemplary embodiment, when the signal of the second reset signal line Reset2 is at an effective level signal, the signal of the light emission signal line EM is at an invalid level signal. When the signal of the light emission signal line EM is at an effective level signal, the signals of the first reset signal line Reset1, the second reset signal line Reset2, and the scan signal line Gate are all at invalid level signals.

[0111] In an exemplary embodiment, the capacitance value C1 of the first capacitor and the capacitance value C2 of the second capacitor satisfy:

[0112] C2 = C1 / (ΔV1 + V OLED -V init )

[0113] where ΔV1 is the voltage value of the jump of the signal at the first node N1, V OLED is the anode voltage of the light-emitting device, and V init is the voltage value of the signal of the initial signal line.

[0114] In an exemplary embodiment, the voltage value of the signal of the initial signal line INIT is less than the voltage value of the signal of the second power supply line VSS. Exemplarily, the voltage value of the signal of the initial signal line INIT may be slightly less than the voltage value of the signal of the second power supply line VSS. The fact that the voltage value of the signal of the initial signal line INIT is less than the voltage value of the signal of the second power supply line VSS can ensure that the light-emitting device does not emit light when the anode of the light-emitting device is reset, and can improve the display effect.

[0115] Figure 2 FIG. is a schematic structural diagram of a first node control sub-circuit provided for an exemplary embodiment. As Figure 2 shown, in an exemplary embodiment, the first node control sub-circuit may include: a reset sub-circuit, a compensation sub-circuit, and a write sub-circuit.

[0116] As Figure 2 shown, the reset sub-circuit may be electrically connected to the first reset signal line Reset1, the second reset signal line Reset2, the first power supply line VDD, the initial signal line INIT, the first node N1, and the fourth node N4 respectively, and is configured to provide the signal of the first power supply line VDD to the first node N1 under the control of the signal of the first reset signal line Reset1, and provide the signal of the initial signal line INIT to the fourth node N4 under the control of the signal of the second reset signal line Reset2; the compensation sub-circuit is electrically connected to the scan signal line Gate, the first node N1, and the second node N2 respectively, and is configured to provide the signal of the second node N2 to the first node N1 under the control of the signal of the third scan signal line Gate; the write sub-circuit is electrically connected to the scan signal line Gate, the data signal line Data, and the third node N3 respectively, and is configured to provide the signal of the data signal line Data to the third node N3 under the control of the scan signal line Gate.

[0117] Figure 3 FIG. is an equivalent circuit diagram of a first node control sub-circuit provided for an exemplary embodiment. As Figure 3As shown, in an exemplary embodiment, the reset sub - circuit may include: a first transistor T1 and a seventh transistor T7, the compensation sub - circuit may include: a second transistor T2, and the write transistor may include: a fourth transistor T4.

[0118] As Figure 3 shown, the control electrode of the first transistor T1 is electrically connected to the first reset signal line Reset1, the first electrode of the first transistor T1 is electrically connected to the first power supply line VDD, and the second electrode of the first transistor T1 is electrically connected to the first node N1; the control electrode of the second transistor T2 is electrically connected to the scan signal line Gate, the first electrode of the second transistor T2 is electrically connected to the first node N1, and the second electrode of the second transistor T2 is electrically connected to the second node N2; the control electrode of the fourth transistor T4 is electrically connected to the scan signal line Gate, the first electrode of the fourth transistor T4 is electrically connected to the data signal line Data, and the second electrode of the fourth transistor T4 is electrically connected to the third node N3; the control electrode of the seventh transistor T7 is electrically connected to the second reset signal line Reset2, the first electrode of the seventh transistor T7 is electrically connected to the initial signal line INIT, and the second electrode of the seventh transistor T7 is electrically connected to the fourth node N4.

[0119] Figure 4 This is an equivalent circuit diagram of the second - node control sub - circuit provided for an exemplary embodiment. As Figure 4 shown, in an exemplary embodiment, the second - node control sub - circuit may include: a first capacitor C1 and a second capacitor C2, and both the first capacitor C1 and the second capacitor C2 include: a first plate and a second plate.

[0120] As Figure 4 shown, the first plate C11 of the first capacitor C1 is electrically connected to the first node N1, the second plate C12 of the first capacitor C1 is electrically connected to the fourth node N4; the first plate C21 of the second capacitor C2 is electrically connected to the scan signal line Gate, and the second plate C22 of the second capacitor C2 is electrically connected to the first node N1.

[0121] Figure 5 This is an equivalent circuit diagram of a pixel circuit. As Figure 5 shown, in an exemplary embodiment, the first - node control sub - circuit includes: a first transistor T1, a second transistor T2, a fourth transistor T4, and a seventh transistor T7, the second - node control sub - circuit may include: a first capacitor C1 and a second capacitor C2, the drive sub - circuit may include: a third transistor T3, the light - emitting control sub - circuit may include: a fifth transistor T5 and a sixth transistor T6, and both the first capacitor C1 and the second capacitor C2 include: a first plate and a second plate.

[0122] As Figure 5As shown, the control electrode of the first transistor T1 is electrically connected to the first reset signal line Reset1, the first electrode of the first transistor T1 is electrically connected to the first power supply line VDD, and the second electrode of the first transistor T1 is electrically connected to the first node N1; the control electrode of the second transistor T2 is electrically connected to the scan signal line Gate, the first electrode of the second transistor T2 is electrically connected to the first node N1, and the second electrode of the second transistor T2 is electrically connected to the second node N2; the control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3; the control electrode of the fourth transistor T4 is electrically connected to the scan signal line Gate, the first electrode of the fourth transistor T4 is electrically connected to the data signal line Data, and the second electrode of the fourth transistor T4 is electrically connected to the third node N3; the control electrode of the fifth transistor T5 is electrically connected to the light-emitting signal line, the first electrode of the fifth transistor T5 is electrically connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is electrically connected to the second node N2; the control electrode of the sixth transistor T6 is electrically connected to the light-emitting signal line, the first electrode of the sixth transistor T6 is electrically connected to the third node N3, and the second electrode of the sixth transistor T6 is electrically connected to the fourth node N4; the control electrode of the seventh transistor T7 is electrically connected to the second reset signal line Reset2, the first electrode of the seventh transistor T7 is electrically connected to the initial signal line INIT, and the second electrode of the seventh transistor T7 is electrically connected to the fourth node N4; the first plate C11 of the first capacitor C1 is electrically connected to the first node N1, and the second plate C12 of the first capacitor C1 is electrically connected to the fourth node N4; the first plate C21 of the second capacitor C2 is electrically connected to the scan signal line Gate, and the second plate C22 of the second capacitor C2 is electrically connected to the first node N1.

[0123] In an exemplary embodiment, the third transistor T3 may be referred to as a driving transistor. The third transistor T3 determines the driving current flowing between the first power supply line VDD and the second power supply line VSS according to the potential difference between its control electrode and its first electrode.

[0124] In an exemplary embodiment, the fourth transistor T4 may be referred to as a writing transistor. When the signal of the scan signal line Gate is an effective level signal, the signal of the data signal line Data is written into the second node N2.

[0125] In an exemplary embodiment, the fifth transistor T5 and the sixth transistor T6 may be referred to as light-emitting transistors. When the signal of the light-emitting signal line EM is an effective level signal, the fifth transistor T5 and the sixth transistor T6 cause the light-emitting device to emit light by forming a driving current path between the first power supply line VDD and the second power supply line VSS.

[0126] Figure 5An exemplary structure of a first node control sub - circuit, a second node control sub - circuit, a driving sub - circuit, and a light - emitting control sub - circuit is shown. It is easily understood by those skilled in the art that the implementation manners of the first node control sub - circuit, the second node control sub - circuit, the driving sub - circuit, and the light - emitting control sub - circuit are not limited thereto.

[0127] Transistors can be classified into N - type transistors and P - type transistors according to their characteristics. When a transistor is a P - type transistor, the turn - on voltage is a low - level voltage (e.g., 0V, - 5V, - 10V or other suitable voltages), and the turn - off voltage is a high - level voltage (e.g., 5V, 10V or other suitable voltages). When a transistor is an N - type transistor, the turn - on voltage is a high - level voltage (e.g., 5V, 10V or other suitable voltages), and the turn - off voltage is a low - level voltage (e.g., 0V, - 5V, - 10V or other suitable voltages).

[0128] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 can be N - type transistors. Using transistors of the same type in the pixel circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product.

[0129] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 can adopt oxide thin - film transistors, and the active layer of the oxide thin - film transistor adopts an oxide semiconductor (Oxide). Low - temperature polycrystalline silicon thin - film transistors have advantages such as high mobility and fast charging, and oxide thin - film transistors have advantages such as low leakage current, which can improve the display quality.

[0130] Figure 6 It is a timing diagram of the operation of a pixel driving circuit. The following Figure 5 illustrates the exemplary embodiments of the present disclosure through the operation process of the exemplary pixel circuit. Figure 5 The pixel circuit in it includes 7 transistors (the first transistor T1 to the seventh transistor T7) and 2 capacitors (the first capacitor C1 and the second capacitor C2), and all 7 transistors are N - type transistors.

[0131] In an exemplary embodiment, the operation process of the pixel circuit can include:

[0132] The first stage P1, called the initialization stage, the signals of the first reset signal line Reset1 and the second reset signal line Reset2 are high-level signals, and the signals of the scan signal line Gate and the emission signal line EM are low-level signals. The first reset signal line Reset1 is at a high-level signal, the first transistor T1 is turned on, and the high-voltage power supply signal of the first power supply line VDD is written to the first node N1 through the turned-on first transistor T1 to initialize (reset) the first node N1, clear the pre-stored voltage inside it, and complete the initialization. The second reset signal line Reset2 is at a high-level signal, the seventh transistor T7 is turned on, and the initial signal of the initial signal line INIT is written to the fourth node N4 through the turned-on seventh transistor T7 to initialize (reset) the fourth node N4, clear the pre-stored voltage inside it, and complete the initialization. The signals of the scan signal line Gate and the emission signal line EM are low-level signals, and the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are turned off. At this stage, the voltage value V1 of the signal of the first node N1 = V dd ,V dd is the voltage value of the high-voltage power supply signal, and the voltage value V4 of the signal of the fourth node N4 = V init ,V init is the voltage value of the initial signal. Since the voltage value of the signal of the initial signal line INIT is slightly less than the voltage value of the signal of the second power supply line VSS, the light-emitting device L does not emit light.

[0133] The second stage P2, called the data writing and threshold compensation stage, the signals of the scan signal line Gate and the second reset signal line Reset2 are high-level signals, the signals of the first reset signal line Reset1 and the emission signal line EM are low-level signals, and the data signal line Data outputs a data signal. The second reset signal line Reset2 is at a high-level signal, the seventh transistor T7 remains turned on, and the initial signal of the initial signal line INIT is written to the fourth node N4 through the turned-on seventh transistor T7. The signal of the scan signal line Gate is at a high-level signal, the second transistor T2 and the fourth transistor T4 are turned on, and the signal of the data signal line Data charges the first node N1 through the turned-on fourth transistor T4, the third node N3, the turned-on third transistor T3, the second node N2, and the turned-on second transistor T2 until the voltage value of the signal of the first node N1 jumps to V data +V th ,V data is the voltage value of the data signal. The signals of the first reset signal line Reset1 and the emission signal line EM are low-level signals, and the first transistor T1, the fifth transistor T5, and the sixth transistor T6 are turned off. At this stage, the voltage value V1 of the signal of the first node N1 = V data +V th, the voltage value V4 of the signal of the fourth node N4 = V init , since the voltage value of the signal of the initial signal line INIT is slightly less than the voltage value of the signal of the second power supply line VSS, the light-emitting device L does not emit light.

[0134] After the second stage P2 and before the third stage P3, the signal of the scan signal line Gate jumps from a high-level signal to a low-level signal. Under the action of the second capacitor C2, the voltage value of the signal of the first node N1 undergoes a first jump, and the jump value ΔV1 satisfies ΔV1 = {C2 / (C2 + C1)} * (VGH - VGL). At this time, the voltage value V1 of the signal of the first node N1 = V data +V th -ΔV1, where VGH is the voltage value of the signal of the scan signal line Gate when it is a high-level signal, VGL is the voltage value of the signal of the scan signal line Gate when it is a low-level signal, C1 is the capacitance value of the first capacitor C1, and C2 is the capacitance value of the second capacitor C2. That is to say, after the second stage P2 and before the third stage P3, the voltage value of the signal of the first node N1 is pulled down by ΔV1 under the action of the scan signal line Gate.

[0135] The third stage P3, called the light-emitting stage, the signal of the light-emitting signal line EM is a high-level signal, and the signals of the scan signal line Gate, the first reset signal line Reset1, and the second reset signal line Reset2 are low-level signals. The signal of the light-emitting signal line EM is a high-level signal, the fifth transistor T5 and the sixth transistor T6 are turned on, and the high-voltage power supply signal output by the first power supply line VDD passes through the turned-on fifth transistor T5, the second node N2, the turned-on third transistor T3, the third node N3, the turned-on sixth transistor T6, and the fourth node N4 to provide a driving voltage for the first pole of the light-emitting device L, driving the light-emitting device L to emit light. The signals of the scan signal line Gate, the first reset signal line Reset1, and the second reset signal line Reset2 are low-level signals, and the first transistor T1, the second transistor T2, the fourth transistor T4, and the seventh transistor T7 are turned off. In this stage, the light-emitting device L emits light. In this stage, the voltage value V3 of the signal of the third node N3 = V OLED , V OLED is the anode voltage of the light-emitting device L, and the voltage value of the signal of the first node N1 undergoes a second jump under the action of the first capacitor C1, and the jump value ΔV2 satisfies

[0136] ΔV2 = {C gs / (C gs + C1)} * (V OLED - V data ) + {C1 / (C gs + C1)} * (V OLED - V init) = V OLED -{C gs

[0137] / (C gs + C1)} * Vdata - {C1 / (C gs + C1)} * V init

[0138] Where C gs is the parasitic capacitance between the gate electrode and the second pole of the third transistor. At this stage, the voltage value V1 of the signal at the first node N1 satisfies:

[0139] V1 = Vdata + Vth - ΔV1 + ΔV2 = V data + V th -{C2 / (C2 + C1)} * (VGH - VGL) + V OLED

[0140] -{C gs / (C gs + C1)} * V data -{C1 / (C gs + C1)} * V init

[0141] The voltage difference V gs between the control electrode and the first electrode of the third transistor T3 gs satisfies: V OLED = V1 - V data = V th + V gs -{C2 / (C2 + C1)} * (VGH - VGL) - {C gs / (C data + C1)} * V gs -{C1 / (C init

[0142] During the driving process of the pixel circuit, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between the control electrode and the first electrode. Therefore, the driving current I of the third transistor T3 is:

[0143] I = K * (Vgs - Vth) 2 = K * [V data -{C2 / (C2 + C1)} * (VGH - VGL) - {C gs / (C gs +

[0144] C1)} * V data -{C1 / (C gs + C1)} * V init 2 ​

[0145] Wherein, I is the driving current flowing through the third transistor T3, which is also the driving current for driving the light-emitting device L, and K is a constant.

[0146] It can be seen from the derivation result of the above current formula that during the light-emitting stage, the driving current of the third transistor T3 is no longer affected by the threshold voltage of the third transistor T3, thereby eliminating the influence of the threshold voltage of the third transistor T3 on the driving current, ensuring the uniform display brightness of the display product, and improving the display effect of the entire display product.

[0147] In the present disclosure, by providing the second node control sub-circuit, the second capacitor C2 can, after the second stage and before the dot stage, when the signal on the scanning signal line Gate changes from a high-level signal to a low-level signal, pull down the voltage value of the signal at the first node N1, causing the first node N1 to jump, thereby reducing the brightness during low gray-scale display, increasing the contrast, and improving the display effect of the display product.

[0148] The embodiment of the present disclosure also provides a display substrate. Figure 7 It is a schematic structural diagram of the display substrate provided by the embodiment of the present disclosure. As Figure 7 shown, the display substrate may include: a substrate, and a driving circuit layer and a light-emitting structure layer sequentially disposed on the substrate. The driving circuit layer includes a pixel circuit, a light-emitting signal line EM, an initial signal line INIT, a first scanning signal line Gate, a first reset signal line Reset1, a second reset signal line Reset2, a first power supply line VDD, and a data signal line Data. The light-emitting structure layer includes: a light-emitting device. Figure 7 That is, the display substrate includes Figure 5 The pixel circuit is taken as an example for illustration.

[0149] The pixel circuit is the pixel circuit provided in any of the foregoing embodiments, and the implementation principle and implementation effect are similar, and will not be elaborated herein.

[0150] In an exemplary embodiment, the display substrate may further include a packaging structure layer disposed on the side of the light-emitting structure layer away from the substrate. The display substrate may include other film layers, such as a touch control structure layer, etc., which are not limited in the present disclosure.

[0151] In an exemplary embodiment, in a plane parallel to the display substrate, the display substrate may include: a plurality of sub-pixels, and at least one sub-pixel may include: a pixel circuit and a light-emitting device. The pixel circuit is configured to output a corresponding current to the connected light-emitting device, causing the light-emitting device to emit light of a corresponding brightness.

[0152] In an exemplary embodiment, a plurality of sub-pixels may include a plurality of pixel rows and a plurality of pixel columns. The plurality of sub-pixels arranged in sequence along the horizontal direction may be referred to as pixel rows, and the plurality of sub-pixels arranged in sequence along the vertical direction may be referred to as pixel columns. The plurality of pixel rows and the plurality of pixel columns form a pixel array arranged in an array.

[0153] In an exemplary embodiment, a plurality of sub-pixels form a pixel unit. The pixel unit may include a first sub-pixel, a second sub-pixel, and a third sub-pixel, or a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel.

[0154] In an exemplary embodiment, when the pixel unit includes a first sub-pixel, a second sub-pixel, and a third sub-pixel, the first sub-pixel may be a red sub-pixel (R) that emits red light, the second sub-pixel may be a blue sub-pixel (B) that emits blue light, and the third sub-pixel P3 may be a green sub-pixel (G) that emits green light. The shapes of the three sub-pixels may be triangular, rectangular, rhombic, pentagonal, hexagonal, etc., and the present disclosure does not limit this here. In the pixel row direction, the first sub-pixel, the second sub-pixel, and the third sub-pixel may be sequentially arranged in an aligned manner. In the pixel column direction, the first sub-pixel, the second sub-pixel, and the third sub-pixel may be sequentially arranged in a staggered manner to form a triangular layout of the sub-pixels. For example, the first sub-pixel in odd rows may be located between the adjacent second sub-pixel and third sub-pixel in even rows, or the first sub-pixel in even rows may be located between the adjacent second sub-pixel and third sub-pixel in odd rows. Another example is that the second sub-pixel in odd rows may be located between the adjacent first sub-pixel and third sub-pixel in even rows, or the second sub-pixel in even rows may be located between the adjacent first sub-pixel and third sub-pixel in odd rows. Still another example is that the third sub-pixel in odd rows may be located between the adjacent first sub-pixel and second sub-pixel in even rows, or the third sub-pixel in even rows may be located between the adjacent first sub-pixel and second sub-pixel in odd rows.

[0155] In an exemplary embodiment, when the pixel unit includes a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel, the first sub-pixel may be a red sub-pixel (R) that emits red light, the second sub-pixel may be a blue sub-pixel (B) that emits blue light, the third sub-pixel and the fourth sub-pixel may be green sub-pixels (G) that emit green light. The shapes of the three sub-pixels may be triangular, rectangular, rhombic, pentagonal, hexagonal, etc., and the present disclosure does not limit this here. In an exemplary embodiment, the four sub-pixels may be arranged in a horizontal juxtaposition, a vertical juxtaposition, a square, etc., and the present disclosure does not limit this here. The four sub-pixels may be arranged in a square (Square) manner to form a GGRB pixel arrangement. In another exemplary embodiment, the four sub-pixels may be arranged in a diamond (Diamond) manner to form an RGGB pixel arrangement.

[0156] In an exemplary embodiment, the encapsulation structure layer may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked on top of each other. The first encapsulation layer and the third encapsulation layer may use inorganic materials, and the second encapsulation layer may use an organic material. The second encapsulation layer is disposed between the first encapsulation layer and the third encapsulation layer, which can ensure that external moisture cannot enter the light-emitting structure layer.

[0157] In an exemplary embodiment, the substrate may be a rigid substrate or a flexible substrate. Among them, the rigid substrate may be, but is not limited to, one or more of glass and conductive foil; the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyether ether ketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber. In an exemplary embodiment, the light-emitting structure layer includes: an anode layer, a pixel definition layer, an organic structure layer, and a cathode layer sequentially stacked on the substrate; the anode layer includes: an anode, the organic structure layer includes: an organic light-emitting layer, and the cathode layer includes: a cathode.

[0158] In an exemplary embodiment, the driving circuit layer may include a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a fourth insulating layer, and a planarization layer sequentially disposed on the substrate; the pixel circuit may include: a plurality of transistors, a first capacitor, and a second capacitor. The first capacitor and the second capacitor respectively include: a first electrode plate and a second electrode plate;

[0159] The semiconductor layer may at least include the active layers of a plurality of transistors;

[0160] The first conductive layer may at least include a first reset signal line, a scan signal line, a light-emitting signal line, a second reset signal line, the control electrodes of a plurality of transistors, the first electrode plate of the first capacitor, and the second electrode plate of the second capacitor;

[0161] The second conductive layer may at least include an initial signal line and a second electrode plate of the first capacitor;

[0162] The third conductive layer may at least include a data signal line, a first power supply line, a second electrode plate of the second capacitor, and first and second poles of a plurality of transistors.

[0163] In an exemplary embodiment, the driving circuit layer may include a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a fourth insulating layer, and a planar layer sequentially disposed on a substrate; the pixel circuit includes: a first transistor to a seventh transistor, a first capacitor, and a second capacitor, and the first capacitor and the second capacitor respectively include: a first electrode plate and a second electrode plate;

[0164] The semiconductor layer may at least include active layers of a plurality of transistors;

[0165] The first conductive layer may at least include a first reset signal line, a scan signal line, a light-emitting signal line, and a second reset signal line, and control electrodes of the first transistor to the seventh transistor, a first electrode plate of the first capacitor, and a second electrode plate of the second capacitor, and the first reset signal line, the scan signal line, the light-emitting signal line, and the second reset signal line extend along a first direction;

[0166] The second conductive layer may at least include an initial signal line and a second electrode plate of the first capacitor;

[0167] The third conductive layer may at least include a data signal line, a first power supply line, a second electrode plate of the second capacitor, and first and second poles of the first transistor, a first pole of the second transistor, a first pole of the fourth transistor, a first pole of the fifth transistor, a second pole of the sixth transistor, and first and second poles of the seventh transistor, the data signal line and the first power supply line extend along a second direction, and the first direction intersects with the second direction.

[0168] In an exemplary embodiment, a region where the scan signal line overlaps with the active layer of the second transistor serves as a control electrode of the second transistor, a region where the scan signal line overlaps with the active layer of the fourth transistor serves as a control electrode of the fourth transistor, and a region where the scan signal line overlaps with the second pole of the first transistor serves as a first electrode plate of the second capacitor.

[0169] In an exemplary embodiment, the second electrode plate of the first capacitor may include: a capacitor main body portion and a capacitor connection portion, the capacitor connection portion is located on a side of the capacitor main body portion close to the initial signal line, and is interconnected with the capacitor main body portion;

[0170] The orthographic projection of the capacitor main body on the substrate at least partially overlaps with the orthographic projection of the first electrode plate of the first capacitor on the substrate; an opening is provided on the capacitor main body, and the opening exposes the first electrode plate covering the first capacitor; the orthographic projection of the capacitor connection part on the substrate respectively partially overlaps with the orthographic projection of the light-emitting signal line and the active layer of the sixth transistor on the substrate.

[0171] In an exemplary embodiment, the driving circuit layer further includes: a first via to a sixth via provided on the first insulating layer to the third insulating layer, a seventh via provided on the second insulating layer and the third insulating layer, an eighth via and a ninth via provided on the third insulating layer;

[0172] The orthographic projection of the first via on the substrate is within the range of the orthographic projection of the active layer of the first transistor on the substrate, the orthographic projection of the second via on the substrate is within the range of the orthographic projection of the active layer of the first transistor on the substrate, the orthographic projection of the third via on the substrate is within the range of the orthographic projection of the active layer of the fourth transistor on the substrate, the orthographic projection of the fourth via on the substrate is within the range of the orthographic projection of the active layer of the fifth transistor on the substrate, the orthographic projection of the fifth via on the substrate is within the range of the orthographic projection of the active layer of the sixth transistor on the substrate, the orthographic projection of the sixth via on the substrate is within the range of the orthographic projection of the active layer of the seventh transistor on the substrate, the orthographic projection of the seventh via on the substrate is within the range of the orthographic projection of the opening on the substrate, the orthographic projection of the eighth via on the substrate is within the range of the orthographic projection of the initial signal line on the substrate, and the orthographic projection of the ninth via on the substrate is within the range of the orthographic projection of the second electrode plate of the first capacitor on the substrate.

[0173] In an exemplary embodiment, a virtual straight line extending in the second direction passes through the first via and the fourth via, a virtual straight line extending in the first direction passes through the second via and the third via, a virtual straight line extending in the second direction passes through the fifth via and the ninth via, and a virtual straight line extending in the first direction passes through the sixth via and the eighth via.

[0174] In an exemplary embodiment, the orthographic projection of the first power supply line on the substrate at least partially overlaps with the orthographic projections of the first via and the fourth via on the substrate. The area where the first power supply line overlaps with the first via serves as the first pole of the first transistor, and the area where the first power supply line overlaps with the fourth via serves as the first pole of the fifth transistor.

[0175] In an exemplary embodiment, the data signal line may include: a first data connection portion, a second data connection portion, a third data connection portion, a fourth data connection portion, and a fifth data connection portion arranged in sequence along a second direction. The second data connection portion is respectively connected to the first data connection portion and the third data connection portion. The fourth data connection portion is respectively connected to the third data connection portion and the fifth data connection portion. A virtual straight line extending along the second direction passes through the first data connection portion and the fifth data connection portion. The third data connection portion is located on a side of the first data connection portion and the fifth data connection portion away from the first power supply line;

[0176] The first data connection portion extends along the second direction, and the included angle between the first data connection portion and the second data connection portion is greater than 90 degrees and less than 180 degrees. The third data connection portion extends along the second direction, and the included angles between the third data connection portion and the second data connection portion and the fourth data connection portion are both greater than 90 degrees and less than 180 degrees. The fifth data connection portion extends along the second direction, and the included angle between the fifth data connection portion and the fourth data connection portion is greater than 90 degrees and less than 180 degrees.

[0177] In an exemplary embodiment, the orthographic projection of the second data connection portion on the substrate partially overlaps with the orthographic projection of the first reset signal line on the substrate. The orthographic projection of the third data connection portion on the substrate partially overlaps with the orthographic projections of the third via hole and the scan signal line on the substrate. The region where the third data connection portion overlaps with the third via hole serves as the first pole of the fourth transistor. The orthographic projection of the fourth data connection portion on the substrate partially overlaps with the orthographic projections of the light-emitting signal line and the second electrode plate of the first capacitor on the substrate. The orthographic projection of the fifth data connection portion on the substrate partially overlaps with the orthographic projections of the second reset signal line and the initial signal line on the substrate.

[0178] In an exemplary embodiment, the second pole of the first transistor and the first pole of the second transistor are the same electrode, and the orthographic projection of the same electrode on the substrate partially overlaps with the orthographic projections of the second via hole, the seventh via hole, the second electrode plate of the first capacitor, and the scan signal line on the substrate. The region where the second pole of the first transistor overlaps with the scan signal line serves as the second electrode plate of the second capacitor;

[0179] The second pole of the sixth transistor and the second pole of the seventh transistor are the same electrode, and the orthographic projection of the same electrode on the substrate at least partially overlaps with the orthographic projections of the fifth via hole and the ninth via hole on the substrate;

[0180] The orthographic projection of the first pole of the seventh transistor on the substrate at least partially overlaps with the orthographic projections of the sixth via hole and the eighth via hole on the substrate.

[0181] An exemplary illustration is provided below through the preparation process of the display substrate. The "patterning process" as referred to in the present disclosure, for metal materials, inorganic materials, or transparent conductive materials, includes processes such as coating photoresist, mask exposure, development, etching, and photoresist stripping. For organic materials, it includes processes such as coating organic materials, mask exposure, and development. Deposition can be carried out using any one or more of sputtering, evaporation, and chemical vapor deposition. Coating can be carried out using any one or more of spraying, spin coating, and inkjet printing. Etching can be carried out using any one or more of dry etching and wet etching. The present disclosure does not make any limitations here. A "thin film" refers to a thin film made of a certain material on a substrate using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire manufacturing process, the "thin film" can also be referred to as a "layer". If the "thin film" requires a patterning process during the entire manufacturing process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The statement "A and B are disposed on the same layer" as referred to in the present disclosure means that A and B are formed simultaneously through the same patterning process. The "thickness" of a film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In an exemplary embodiment of the present disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0182] The preparation process of the display substrate is described below with a pixel circuit of one row and one column. Figure 7 The preparation process of the display substrate provided by an exemplary embodiment may include:

[0183] (1) Form a semiconductor layer pattern on the substrate. In an exemplary embodiment, forming the semiconductor layer pattern may include: sequentially depositing a semiconductor thin film on the substrate, and patterning the semiconductor thin film through a patterning process to form a semiconductor layer pattern, as Figure 8 shown, Figure 8 is a schematic diagram after forming the semiconductor layer pattern.

[0184] In an exemplary embodiment, as Figure 8 shown, the semiconductor layer pattern of each sub-pixel may at least include: the active layers T11 of the first transistor to the active layers T71 of the seventh transistor.

[0185] In an exemplary embodiment, as Figure 8 shown, the active layers T11 of the first transistor to the active layers T71 of the seventh transistor may be an integrally connected structure.

[0186] In an exemplary embodiment, as Figure 8As shown, in the first direction X, the active layer T11 of the first transistor, the active layer T21 of the second transistor, and the active layer T61 of the fifth transistor can be located on the same side of the active layer T31 of the third transistor in this sub-pixel. The active layer T41 of the fourth transistor and the active layer T61 of the sixth transistor can be located on the same side of the active layer T31 of the third transistor in this sub-pixel. The active layer T21 of the second transistor and the active layer T41 of the fourth transistor can be located on different sides of the active layer T31 of the third transistor in this sub-pixel. In the second direction Y, the active layer T11 of the first transistor, the active layer T21 of the second transistor, and the active layer T41 of the fourth transistor can be located on the same side of the active layer T31 of the third transistor in this sub-pixel. The active layer T51 of the fifth transistor, the active layer T61 of the sixth transistor, and the active layer T71 of the seventh transistor can be located on the other side of the active layer T31 of the third transistor in this sub-pixel.

[0187] In an exemplary embodiment, as Figure 8 shown, the shape of the main body portions of the active layer T11 of the first transistor, the active layer T21 of the second transistor, the active layer T41 of the fourth transistor, the active layer T51 of the fifth transistor, and the active layer T61 of the sixth transistor can be linear extending along the second direction Y. The shape of the active layer T31 of the third transistor can be linear extending along the first direction X. The shape of the active layer T71 of the seventh transistor can be in an "L" shape.

[0188] In an exemplary embodiment, as Figure 8 shown, the active layer of each transistor can include a first region, a second region, and a channel region located between the first region and the second region. In an exemplary embodiment, the second region T11_2 of the active layer T11 of the first transistor can serve as the first region T21_1 of the active layer T21 of the second transistor. The first region T31_1 of the active layer T31 of the third transistor can simultaneously serve as the second region T21_2 of the active layer T21 of the second transistor and the second region T51_2 of the active layer T51 of the fifth transistor. The second region T31_2 of the active layer T31 of the third transistor can simultaneously serve as the second region T41_2 of the active layer T41 of the fourth transistor and the first region T61_1 of the active layer T61 of the sixth transistor. The second region T61_2 of the active layer T61 of the sixth transistor can serve as the second region T71_2 of the active layer T71 of the seventh transistor. The first regions T11_1 of the active layer T11 of the first transistor, T41_1 of the active layer T41 of the fourth transistor, T51_1 of the active layer T51 of the fifth transistor, and T71_1 of the active layer T71 of the seventh transistor can be separately provided.

[0189] (2) Form a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: sequentially depositing a first insulating film and a first conductive film on the substrate on which the foregoing pattern is formed, patterning the first conductive film through a patterning process to form a first insulating layer covering the semiconductor layer pattern, and a first conductive layer pattern located on the first insulating layer, as Figure 9 and Figure 10 shown, wherein, Figure 9 is a schematic diagram of the first conductive layer pattern, Figure 10 is a schematic diagram after forming the first conductive layer pattern. In an exemplary embodiment, the first conductive layer may be referred to as the first gate metal (Gate1) layer.

[0190] In an exemplary embodiment, the first conductive layer pattern of each sub-pixel may at least include: a first reset signal line Reset1 extending along the first direction X, a scan signal line Gate, a light-emitting signal line EM, a second reset signal line Reset2, and control electrodes T12 to T72 of the first transistor to the seventh transistor, a first electrode plate C11 of the first capacitor, and a second electrode plate C21 of the second capacitor.

[0191] In an exemplary embodiment, as Figure 9 and Figure 10 shown, the shape of the first electrode plate C11 of the first capacitor may be rectangular, and chamfers may be provided at the corners of the rectangular shape. The orthographic projection of the first electrode plate C11 of the first capacitor on the substrate overlaps at least partially with the orthographic projection of the active layer of the third transistor T3 on the substrate. In an exemplary embodiment, the first electrode plate C11 of the first capacitor may simultaneously serve as the control electrode T32 of the third transistor T3.

[0192] In an exemplary embodiment, as Figure 9 and Figure 10 shown, the shape of the first reset signal line Reset1 may be linear extending along the first direction X. The first reset signal line Reset1 may be located on a side of the first electrode plate C11 of the first capacitor (which is also the control electrode T32 of the third transistor) away from the light-emitting signal line EM. The overlapping region between the first reset signal line Reset1 and the active layer of the first transistor T1 serves as the control electrode T12 of the first transistor.

[0193] In an exemplary embodiment, as Figure 9 and Figure 10As shown, the shape of the scan signal line Gate can be linear extending along the first direction X. The scan signal line Gate can be located on one side of the first reset signal line Reset1 close to the first electrode plate C11 of the first capacitor (which is also the control electrode T32 of the third transistor). The scan signal line Gate is multiplexed as the control electrode T12 of the second transistor, the control electrode T42 of the fourth transistor, and the first electrode plate C21 of the second capacitor. The region where the scan signal line Gate overlaps with the active layer of the second transistor serves as the control electrode T12 of the second transistor. The region where the scan signal line Gate overlaps with the active layer of the fourth transistor serves as the control electrode T42 of the fourth transistor. The region where the scan signal line Gate overlaps with the second pole of the first transistor (which is also the first pole of the second transistor) serves as the first electrode plate C21 of the second capacitor.

[0194] In an exemplary embodiment, as Figure 9 and Figure 10 shown, the shape of the light-emitting signal line EM can be linear extending along the first direction X. The light-emitting signal line EM is located on the side of the first electrode plate C11 of the first capacitor (which is also the control electrode T32 of the third transistor) away from the scan signal line Gate. The region where the light-emitting signal line EM overlaps with the active layer of the fifth transistor T5 serves as the control electrode T52 of the fifth transistor. The region where the light-emitting signal line EM overlaps with the active layer of the sixth transistor T6 serves as the control electrode T62 of the sixth transistor.

[0195] In an exemplary embodiment, as Figure 9 and Figure 10 shown, the shape of the second reset signal line Reset2 can be linear extending along the first direction X. The second reset signal line Reset2 can be located on the side of the light-emitting signal line EM away from the first electrode plate C11 of the first capacitor (which is also the control electrode T32 of the third transistor). The region where the second reset signal line Reset2 overlaps with the active layer of the seventh transistor T7 serves as the control electrode T72 of the seventh transistor.

[0196] In an exemplary embodiment, the first reset signal line Reset1, the second reset signal line Reset2, the scan signal line Gate, and the light-emitting signal line EM can be designed with equal widths, or can be designed with unequal widths, can be straight lines, or can be broken lines, which can not only facilitate the layout of the pixel structure, but also reduce the parasitic capacitance between the signal lines. The present disclosure does not limit this here.

[0197] In an exemplary embodiment, after forming the first conductive layer pattern, the semiconductor layer can be made conductive using the first conductive layer as a mask. The semiconductor layer in the region shielded by the first conductive layer forms the channel regions of the first transistor T1 to the seventh transistor T7, and the semiconductor layer in the region not shielded by the first conductive layer is made conductive, that is, the first regions and the second regions of the active layers of the first transistor to the seventh transistor are all made conductive. Moreover, the first region of the active layer of the third transistor (which is also the second region of the active layer of the second transistor and the second region of the active layer of the fifth transistor) can simultaneously serve as the second pole T24 of the second transistor, the first pole T33 of the third transistor, and the second pole T54 of the fifth transistor. The second region T31_2 of the active layer T31 of the third transistor after being made conductive (which is also the second region T41_2 of the active layer T41 of the fourth transistor and the first region T61_1 of the active layer T61 of the sixth transistor) also simultaneously serves as the second pole T34 of the third transistor, the second pole T44 of the fourth transistor, and the first pole T63 of the sixth transistor.

[0198] (3) Form the second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include: depositing a second insulating layer film and a second conductive film on the substrate on which the foregoing pattern is formed, patterning the second conductive film using a patterning process, and forming the second conductive layer pattern on the second insulating layer. Figure 11 and Figure 12 as shown Figure 11 is a schematic diagram of the second conductive layer pattern, Figure 12 is a schematic diagram after forming the second conductive layer pattern. In an exemplary embodiment, the second conductive layer may be referred to as the second gate metal (Gate2) layer.

[0199] In an exemplary embodiment, as Figure 11 and Figure 12 shown, the second conductive layer pattern of each sub-pixel may at least include: an initial signal line INIT and a second electrode plate C12 of the first capacitor.

[0200] In an exemplary embodiment, as Figure 11 and Figure 12 shown, the second electrode plate C12 of the first capacitor may include: a capacitor main body portion C12A and a capacitor connection portion C12B. The capacitor connection portion C12B may be located on a side of the capacitor main body portion C12A close to the initial signal line INIT and connected to the capacitor main body portion C12A.

[0201] In an exemplary embodiment, as Figure 11 and Figure 12As shown, the shape of the capacitor main body C12A can be rectangular, and chamfers can be provided at the corners of the rectangular shape. The orthographic projection of the capacitor main body C12A on the substrate at least partially overlaps with the orthographic projection of the first electrode plate of the first capacitor on the substrate. An opening V0 is provided on the capacitor main body C12A. The shape of the opening V0 can be rectangular and can be located in the middle of the second electrode plate C12 of the first capacitor, so that the second electrode plate C12 of the first capacitor forms an annular structure. The opening V0 exposes the second insulating layer covering the first electrode plate of the first capacitor, and the orthographic projection of the first electrode plate of the first capacitor on the substrate includes the orthographic projection of the opening V0 on the substrate.

[0202] In an exemplary embodiment, as Figure 11 and Figure 12 shown, the shape of the capacitor connection portion C12B can be "L"-shaped, and the orthographic projection of the capacitor connection portion C12B on the substrate can respectively partially overlap with the orthographic projection of the light-emitting signal line and the second region of the active layer of the sixth transistor (which is also the second region of the active layer of the seventh transistor) on the substrate.

[0203] (4) Form a third insulating layer pattern. In an exemplary embodiment, forming the third insulating layer pattern may include: depositing a third insulating thin film on the substrate on which the foregoing patterns are formed, and patterning the third insulating thin film by a patterning process to form a third insulating layer covering the second conductive layer. A plurality of vias are provided on the third insulating layer, as Figure 13 shown, Figure 13 is a schematic diagram after forming the third insulating layer.

[0204] In an exemplary embodiment, as Figure 13 shown, the plurality of vias of the third insulating layer of each sub-pixel may at least include: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, and a ninth via V9.

[0205] In an exemplary embodiment, the orthographic projection of the first via V1 on the substrate is within the range of the orthographic projection of the first region of the active layer of the first transistor on the substrate. The first insulating layer and the second insulating layer in the first via V1 are etched away, exposing the surface of the first region of the active layer of the first transistor. The first via V1 is configured to connect the first pole of the subsequently formed first transistor T1 to the first region of the active layer of the first transistor through the via.

[0206] In an exemplary embodiment, the positive projection of the second via V2 on the substrate is within the range of the positive projection of the second region of the active layer of the first transistor (which is also the first region of the active layer of the second transistor) on the substrate. The first insulating layer and the second insulating layer within the second via V2 are etched away to expose the surface of the second region of the active layer of the first transistor (which is also the first region of the active layer of the second transistor). The second via V2 is configured to connect the second pole of the subsequently formed first transistor T1 (which is also the first pole of the second transistor) to the first region of the active layer of the first transistor (which is also the first region of the active layer of the second transistor) through this via.

[0207] In an exemplary embodiment, the positive projection of the third via V3 on the substrate is within the range of the positive projection of the first region of the active layer of the fourth transistor on the substrate. The first insulating layer and the second insulating layer within the third via V3 are etched away to expose the surface of the first region of the active layer of the fourth transistor. The third via V3 is configured to connect the first pole of the subsequently formed fourth transistor to the first region of the active layer of the fourth transistor through this via.

[0208] In an exemplary embodiment, the positive projection of the fourth via V4 on the substrate is within the range of the positive projection of the first region of the active layer of the fifth transistor on the substrate. The first insulating layer and the second insulating layer within the fourth via V4 are etched away to expose the surface of the first region of the active layer of the fifth transistor. The fourth via V4 is configured to connect the first pole of the subsequently formed fifth transistor to the first region of the active layer of the fifth transistor through this via.

[0209] In an exemplary embodiment, the positive projection of the fifth via V5 on the substrate is within the range of the positive projection of the second region of the active layer of the sixth transistor (which is also the second region of the active layer of the seventh transistor) on the substrate. The first insulating layer and the second insulating layer within the fifth via V5 are etched away to expose the surface of the second region of the active layer of the sixth transistor (which is also the second region of the active layer of the seventh transistor). The fifth via V5 is configured to connect the second pole of the subsequently formed sixth transistor T1 (which is also the second pole of the seventh transistor) to the second region of the active layer of the sixth transistor (which is also the second region of the active layer of the seventh transistor) through this via.

[0210] In an exemplary embodiment, the positive projection of the sixth via V6 on the substrate is within the range of the positive projection of the first region of the active layer of the seventh transistor on the substrate. The first insulating layer and the second insulating layer within the sixth via V6 are etched away to expose the surface of the first region of the active layer of the seventh transistor. The sixth via V6 is configured to connect the first pole of the subsequently formed seventh transistor to the first region of the active layer of the seventh transistor through this via.

[0211] In an exemplary embodiment, the positive projection of the seventh via V7 on the substrate is within the range of the positive projection of the opening on the substrate. The second insulating layer in the seventh via V7 is etched away to expose the surface of the first electrode plate of the first capacitor (which is also the control electrode of the third transistor). The seventh via V7 is configured to connect the second electrode of the first transistor (which is also the first electrode of the second transistor) formed subsequently to the first electrode plate of the first capacitor (which is also the control electrode of the third transistor) through this via.

[0212] In an exemplary embodiment, the positive projection of the eighth via V8 on the substrate is within the range of the positive projection of the initial signal line INIT on the substrate. The eighth via V8 exposes the surface of the initial signal line INIT. The eighth via V8 is configured to connect the first electrode of the seventh transistor formed subsequently to the initial signal line INIT through this via.

[0213] In an exemplary embodiment, the positive projection of the ninth via V9 on the substrate is within the range of the positive projection of the second electrode plate of the first capacitor on the substrate. The ninth via V9 exposes the surface of the second electrode plate of the first capacitor. The ninth via V9 is configured to connect the second electrode of the sixth transistor (which is also the second electrode of the seventh transistor) formed subsequently to the second electrode plate of the first capacitor through this via. In an exemplary embodiment.

[0214] In an exemplary embodiment, a virtual straight line extending along the second direction Y can pass through the first via V1 and the fourth via V4.

[0215] In an exemplary embodiment, a virtual straight line extending along the first direction X can pass through the second via V2 and the third via V3.

[0216] In an exemplary embodiment, a virtual straight line extending along the second direction Y passes through the fifth via V5 and the ninth via V9.

[0217] In an exemplary embodiment, a virtual straight line extending along the first direction X can pass through the sixth via V6 and the eighth via V8.

[0218] (5) Form the third conductive layer. In an exemplary embodiment, forming the third conductive layer may include: depositing a third conductive thin film on the substrate on which the foregoing pattern is formed, and patterning the third conductive thin film using a patterning process to form the third conductive layer disposed on the third insulating layer. Figure 14 and Figure 15 as shown Figure 14 is a schematic diagram of the third conductive layer pattern. Figure 15 is a schematic diagram after forming the third conductive layer pattern. In an exemplary embodiment, the third conductive layer may be referred to as a source-drain metal (SD) layer.

[0219] In an exemplary embodiment, asFigure 14 and Figure 15 As shown in Figure 15 , the third conductive layer pattern of each sub-pixel may at least include: data signal line Data, first power supply line VDD, second electrode plate C22 of the second capacitor, first pole T13 and second pole T14 of the first transistor, first pole T23 of the second transistor, first pole T43 of the fourth transistor, first pole T53 of the fifth transistor, second pole T64 of the sixth transistor, first pole T73 and second pole T74 of the seventh transistor.

[0220] In an exemplary embodiment, as Figure 14 and Figure 15 shown, the second pole T14 of the first transistor may simultaneously serve as the first pole T23 of the second transistor and the second electrode plate C22 of the second capacitor, the second pole T64 of the sixth transistor may simultaneously serve as the second pole T74 of the seventh transistor, and the first pole T73 of the seventh transistor may be separately provided.

[0221] In an exemplary embodiment, as Figure 14 and Figure 15 shown, the second pole T14 of the first transistor (which is also the first pole T23 of the second transistor and the second electrode plate C22 of the second capacitor) is located between the first power supply line VDD and the data signal line Data, and the second pole T64 of the sixth transistor (which is also the second pole T74 of the seventh transistor) and the first pole T73 of the seventh transistor may be located on the side of the data signal line Data away from the first power supply line VDD.

[0222] In an exemplary embodiment, as Figure 14 and Figure 15 shown, the shape of the first power supply line VDD may be linear extending along the second direction Y. The positive projection of the first power supply line VDD on the substrate may at least partially overlap with the positive projections of the first via hole and the fourth via hole on the substrate. The overlapping region of the first power supply line VDD and the first via hole may serve as the first pole T13 of the first transistor, the overlapping region of the first power supply line VDD and the fourth via hole V4 may serve as the first pole T53 of the fifth transistor, the first pole T13 of the first transistor is connected to the first region of the active layer of the first transistor through the first via hole, and the first pole T53 of the fifth transistor may be connected to the first region of the active layer of the fifth transistor through the fourth via hole.

[0223] In an exemplary embodiment, as Figure 14 and Figure 15As shown, the data signal line Data may include: a first data connection portion Data1, a second data connection portion Data2, a third data connection portion Data3, a fourth data connection portion Data4, and a fifth data connection portion Data5 arranged in sequence along the second direction Y. The second data connection portion Data2 is respectively connected to the first data connection portion Data1 and the third data connection portion Data3, and the fourth data connection portion Data4 is respectively connected to the third data connection portion Data3 and the fifth data connection portion Data5.

[0224] In an exemplary embodiment, a virtual straight line extending along the second direction Y may pass through the first data connection portion Data1 and the fifth data connection portion Data5. The third data connection portion Data3 may be located on a side of the first data connection portion Data1 and the fifth data connection portion Data5 away from the first power supply line VDD.

[0225] In an exemplary embodiment, as Figure 14 and Figure 15 shown, the shape of the first data connection portion Data1 may be linear extending along the second direction Y, and the angle between it and the second data connection portion Data2 is greater than 90 degrees and less than 180 degrees.

[0226] In an exemplary embodiment, as Figure 14 and Figure 15 shown, the positive projection of the second data connection portion Data1 on the substrate partially overlaps with the positive projection of the first reset signal line on the substrate.

[0227] In an exemplary embodiment, as Figure 14 and Figure 15 shown, the shape of the third data connection portion Data3 may be linear extending along the second direction Y, and the angles between it and the second data connection portion Data2 and the fourth data connection portion Data4 are both greater than 90 degrees and less than 180 degrees. The positive projection of the third data connection portion Data3 on the substrate partially overlaps with the positive projection of the third via and the scan signal line on the substrate. The region where the third data connection portion Data2 overlaps with the third via may serve as the first pole T43 of the fourth transistor, and the first pole T43 of the fourth transistor is connected to the first region of the active layer of the fourth transistor through the third via.

[0228] In an exemplary embodiment, as Figure 14 and Figure 15 shown, the positive projection of the fourth data connection portion Data4 on the substrate partially overlaps with the positive projection of the light-emitting signal line and the second electrode plate of the first capacitor on the substrate.

[0229] In an exemplary embodiment, as Figure 14 and Figure 15As shown, the shape of the fifth data connection part Data5 can be linear extending along the second direction Y, and the angles between the fifth data connection part Data5 and the fourth data connection part Data4 are all greater than 90 degrees and less than 180 degrees. The orthographic projections of the fifth data connection part Data5 on the substrate respectively overlap with the orthographic projections of the second reset signal line and the initial signal line on the substrate.

[0230] In an exemplary embodiment, as Figure 14 and Figure 15 shown, the shape of the main body part of the second pole T14 of the first transistor (which is also the first pole T23 of the second transistor) can be linear extending along the second direction Y. The orthographic projection of the second pole T14 of the first transistor (which is also the first pole T13 of the second transistor) on the substrate can overlap with the orthographic projections of the second via, the seventh via, the second electrode plate of the first capacitor, and the scan signal line on the substrate at least partially. The overlapping area between the second pole T14 of the first transistor (which is also the first pole T13 of the second transistor) and the scan signal line can be used as the second electrode plate C22 of the second capacitor. The second pole T14 of the first transistor (which is also the first pole T23 of the second transistor) is connected to the second region of the active layer of the first transistor (which is also the first region of the active layer of the second transistor) through the second via, and is connected to the first electrode plate of the first capacitor through the seventh via.

[0231] In the present disclosure, the overlapping area between the scan signal line and the second pole T14 of the first transistor (which is also the first pole T13 of the second transistor) can be the first electrode plate of the second capacitor. The overlapping area between the second pole T14 of the first transistor (which is also the first pole T13 of the second transistor) and the scan signal line can be used as the second electrode plate C22 of the second capacitor. The setting manner of the second capacitor in the present disclosure can save the space occupied by the pixel circuit and can achieve a narrow border.

[0232] In an exemplary embodiment, as Figure 14 and Figure 15 shown, the second pole T64 of the sixth transistor (the second pole T74 of the seventh transistor) can be a block structure. The orthographic projection of the second pole T64 of the sixth transistor (the second pole T74 of the seventh transistor) on the substrate can overlap with the orthographic projections of the fifth via and the ninth via on the substrate at least partially. The second pole T64 of the sixth transistor (the second pole T74 of the seventh transistor) is connected to the second region of the active layer of the sixth transistor (which is also the second region of the active layer of the seventh transistor) through the fifth via, and is connected to the second electrode plate of the first capacitor through the ninth via.

[0233] In an exemplary embodiment, as Figure 14 and Figure 15As shown, the first pole T73 of the seventh transistor may be in a linear shape extending along the first direction X. The positive projection of the first pole T73 of the seventh transistor on the substrate at least partially overlaps with the positive projections of the sixth via hole and the eighth via hole on the substrate. The first pole of the seventh transistor is connected to the first region of the active layer of the seventh transistor through the sixth via hole and is connected to the initial signal line through the eighth via hole.

[0234] In an exemplary embodiment, the data signal line Data and the first power supply line VDD may be designed with equal widths, or may be designed with unequal widths, may be straight lines, or may be broken lines, which can not only facilitate the layout of the pixel structure, but also reduce the parasitic capacitance between the signal lines. The present disclosure does not make a limitation herein.

[0235] (6) Form a planarization layer pattern. In an exemplary embodiment, forming the planarization layer pattern may include: coating a fourth insulating film and a planarizing film on the substrate on which the foregoing patterns are formed, and patterning the planarizing film by a patterning process to form a fourth insulating layer covering the third conductive layer pattern and a planarization layer covering the fourth insulating layer.

[0236] So far, the driving circuit layer of the display substrate provided is fabricated on the substrate. Figure 7 The driving circuit layer of the display substrate provided. In a plane parallel to the display substrate, the driving circuit layer may include a plurality of circuit units, each circuit unit may include a pixel circuit, and the driving circuit layer further includes: a scanning signal line, a light-emitting signal line, an initial signal line, a first reset signal line, a second reset signal line, a data signal line, and a first power supply line connection. In a plane perpendicular to the display substrate, the driving circuit layer may be disposed on the substrate, and the substrate may include a stacked first flexible layer, a barrier layer, a substrate conductive layer, and a second flexible layer.

[0237] The driving circuit layer may include a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a fourth insulating layer, and a planarization layer sequentially disposed on the substrate. The semiconductor layer may at least include the active layers of the first transistor to the seventh transistor, the first conductive layer may at least include the first reset signal line, the scanning signal line, the light-emitting signal line, the second reset signal line, and the control poles of the first transistor to the seventh transistor, the first electrode plate of the first capacitor, and the second electrode plate of the second capacitor, the second conductive layer may at least include the initial signal line and the second electrode plate of the first capacitor, and the third conductive layer may at least include the data signal line, the first power supply line, the second electrode plate of the second capacitor, and the first and second poles of a plurality of transistors.

[0238] In an exemplary embodiment, the first conductive layer, the second conductive layer, and the third conductive layer may be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or an alloy material of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb). It may be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo, etc.

[0239] In an exemplary embodiment, the first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON). It may be a single layer, a multi-layer, or a composite layer. The first insulating layer may be referred to as a buffer layer, the second insulating layer and the third insulating layer may be referred to as gate insulating (GI) layers, and the fourth insulating layer may be referred to as an interlayer dielectric (ILD) layer. The planarization layer may be made of an organic material, such as resin, etc.

[0240] In an exemplary embodiment, after the driving circuit layer is prepared, a light-emitting structure layer is prepared on the driving circuit layer. The preparation process of the light-emitting structure layer may include the following operations.

[0241] (7) Form an anode conductive layer pattern. In an exemplary embodiment, forming the anode conductive layer pattern may include: depositing an anode conductive thin film on the substrate on which the foregoing pattern is formed, and patterning the anode conductive thin film using a patterning process to form an anode conductive layer provided on the second planarization layer. The anode conductive layer includes at least a plurality of anode patterns.

[0242] In an exemplary embodiment, the anode conductive layer has a single-layer structure, such as indium tin oxide ITO or indium zinc oxide IZO, or may have a multi-layer composite structure, such as ITO / Ag / ITO, etc.

[0243] (8) Form a pixel definition layer pattern. In an exemplary embodiment, forming the pixel definition layer pattern may include: coating a pixel definition thin film on the substrate on which the foregoing pattern is formed, and patterning the pixel definition thin film using a patterning process to form a pixel definition layer. A pixel opening is provided on the pixel definition layer of each sub-pixel, and the pixel definition thin film within the pixel opening is removed to expose the anode of the sub-pixel where it is located.

[0244] In an exemplary embodiment, the subsequent preparation process may include: first forming an organic light-emitting layer using an evaporation or inkjet printing process, then forming a cathode on the organic light-emitting layer, and then forming a packaging structure layer. The packaging structure layer may include a stacked first packaging layer, a second packaging layer, and a third packaging layer. The first packaging layer and the third packaging layer may be made of an inorganic material, and the second packaging layer may be made of an organic material. The second packaging layer is provided between the first packaging layer and the third packaging layer, which can ensure that external moisture cannot enter the light-emitting structure layer.

[0245] The display substrate adopted in the embodiments of the present disclosure can be applied to display products with any resolution.

[0246] The embodiments of the present disclosure further provide a driving method for a pixel circuit. By setting a driving pixel circuit, the driving method for the pixel circuit provided by the embodiments of the present disclosure may include the following steps:

[0247] Step 100: Under the control of signals of a scan signal line, a first reset signal line, and a second reset signal line, a first node control sub-circuit provides a signal of a first power supply line or a signal of a second node to a first node, provides a signal of a data signal line to a third node, and provides a signal of an initial signal line to a fourth node.

[0248] Step 200: A second node control sub-circuit stores signals of the first node and the fourth node, and drives a change in the signal of the first node under the control of the signal of the scan signal line.

[0249] Step 300: Under the control of the first node and the second node, a driving sub-circuit provides a driving current to the third node. Under the control of a light-emitting signal line, a light-emitting control sub-circuit provides a signal of the first power supply line to the second node and provides a signal of the third node to the fourth node.

[0250] The embodiments of the present disclosure further provide a display device, including: a display substrate.

[0251] The display substrate is the display substrate provided in any of the foregoing embodiments, and the implementation principle and implementation effect are similar, which will not be elaborated here.

[0252] In an exemplary embodiment, the display device may be: a liquid crystal panel, an electronic paper, an OLED panel, an active-matrix organic light emitting diode (AMOLED) panel, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, or any other product or component with a display function.

[0253] The drawings in the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures may refer to the general design.

[0254] For clarity, in the drawings used to describe the embodiments of the present disclosure, the thickness and size of layers or microstructures are enlarged. It can be understood that when an element such as a layer, a film, a region, or a substrate is referred to as being "on" or "under" another element, the element can be "directly" on or under the other element, or there may be intermediate elements.

[0255] Although the embodiments disclosed in this disclosure are as above, the content described is only the embodiments adopted for the convenience of understanding this disclosure and is not intended to limit this disclosure. Any person skilled in the art within the scope of this disclosure may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed in this disclosure. However, the scope of patent protection of this disclosure shall still be subject to the scope defined by the appended claims.

Claims

1. A pixel circuit, characterized in that, Including: A first node control sub-circuit, a second node control sub-circuit, a light-emitting control sub-circuit, and a driving sub-circuit, wherein the pixel circuit is configured to drive a light-emitting device to emit light; The first node control sub-circuit is electrically connected to a scan signal line, a data signal line, a first reset signal line, a second reset signal line, an initial signal line, a first power supply line, a first node, a second node, a third node, and a fourth node respectively, and is configured to provide the signal of the first power supply line or the signal of the second node to the first node, provide the signal of the data signal line to the third node, and provide the signal of the initial signal line to the fourth node under the control of the signals of the scan signal line, the first reset signal line, and the second reset signal line; The second node control sub-circuit is electrically connected to the scan signal line, the first node, and the fourth node respectively, and is configured to store the signals of the first node and the fourth node, and drive the signal of the first node to change under the control of the signal of the scan signal line; The driving sub-circuit is electrically connected to the first node, the second node, and the third node respectively, and is configured to provide a driving current to the third node under the control of the signals of the first node and the second node; The light-emitting control sub-circuit is electrically connected to a light-emitting signal line, the first power supply line, the second node, the third node, and the fourth node respectively, and is configured to provide the signal of the first power supply line to the second node and provide the signal of the third node to the fourth node under the control of the signal of the light-emitting signal line; The light-emitting device is electrically connected to the fourth node and a second power supply line respectively.

2. The pixel circuit according to claim 1, wherein The first node control sub-circuit includes: a reset sub-circuit, a compensation sub-circuit, and a writing sub-circuit; The reset sub-circuit is electrically connected to the first reset signal line, the second reset signal line, the first power supply line, the initial signal line, the first node, and the fourth node respectively, and is configured to provide the signal of the first power supply line to the first node under the control of the signal of the first reset signal line, and provide the signal of the initial signal line to the fourth node under the control of the signal of the second reset signal line; The compensation sub-circuit is electrically connected to the scan signal line, the first node, and the second node respectively, and is configured to provide the signal of the second node to the first node under the control of the signal of the third scan signal line; The writing sub-circuit is electrically connected to the scan signal line, the data signal line, and the third node respectively, and is configured to provide the signal of the data signal line to the third node under the control of the signal of the scan signal line.

3. The pixel circuit according to claim 2, wherein The reset sub-circuit includes: a first transistor and a seventh transistor, the compensation sub-circuit includes: a second transistor, and the writing sub-circuit includes: a fourth transistor; The control electrode of the first transistor is electrically connected to the first reset signal line, the first electrode of the first transistor is electrically connected to the first power supply line, and the second electrode of the first transistor is electrically connected to the first node; The control electrode of the second transistor is electrically connected to the scan signal line, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the second node; The control electrode of the fourth transistor is electrically connected to the scan signal line, the first electrode of the fourth transistor is electrically connected to the data signal line, and the second electrode of the fourth transistor is electrically connected to the third node; The control electrode of the seventh transistor is electrically connected to the second reset signal line, the first electrode of the seventh transistor is electrically connected to the initial signal line, and the second electrode of the seventh transistor is electrically connected to the fourth node.

4. The pixel circuit according to claim 1, wherein The second node control sub-circuit includes: a first capacitor and a second capacitor, and both the first capacitor and the second capacitor include: a first electrode plate and a second electrode plate; The first electrode plate of the first capacitor is electrically connected to the first node, and the second electrode plate of the first capacitor is electrically connected to the fourth node; The first electrode plate of the second capacitor is electrically connected to the scan signal line, and the second electrode plate of the second capacitor is electrically connected to the first node.

5. The pixel circuit according to claim 1, wherein The first node control sub-circuit includes: a first transistor, a second transistor, a fourth transistor, and a seventh transistor, the second node control sub-circuit includes: a first capacitor and a second capacitor, the driving sub-circuit includes: a third transistor, and the light emission control sub-circuit includes: a fifth transistor and a sixth transistor, and both the first capacitor and the second capacitor include: a first electrode plate and a second electrode plate; The control electrode of the first transistor is electrically connected to the first reset signal line, the first electrode of the first transistor is electrically connected to the first power supply line, and the second electrode of the first transistor is electrically connected to the first node; The control electrode of the second transistor is electrically connected to the scan signal line, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the second node; The control electrode of the third transistor is electrically connected to the first node, the first electrode of the third transistor is electrically connected to the second node, and the second electrode of the third transistor is electrically connected to the third node; The control electrode of the fourth transistor is electrically connected to the scan signal line, the first electrode of the fourth transistor is electrically connected to the data signal line, and the second electrode of the fourth transistor is electrically connected to the third node; The control electrode of the fifth transistor is electrically connected to the light emission signal line, the first electrode of the fifth transistor is electrically connected to the first power supply line, and the second electrode of the fifth transistor is electrically connected to the second node; The control electrode of the sixth transistor is electrically connected to the light emission signal line, the first electrode of the sixth transistor is electrically connected to the third node, and the second electrode of the sixth transistor is electrically connected to the fourth node; The control electrode of the seventh transistor is electrically connected to the second reset signal line, the first electrode of the seventh transistor is electrically connected to the initial signal line, and the second electrode of the seventh transistor is electrically connected to the fourth node; The first electrode plate of the first capacitor is electrically connected to the first node, and the second electrode plate of the first capacitor is electrically connected to the fourth node; The first electrode plate of the second capacitor is electrically connected to the scan signal line, and the second electrode plate of the second capacitor is electrically connected to the first node.

6. The pixel circuit according to claim 1, wherein The transistor types of the first transistor to the seventh transistor are the same, and they are all oxide transistors.

7. The pixel circuit according to claim 1, wherein The time when the signal of the second reset signal line is an effective level signal includes: a first time period and a second time period that occur in sequence and continuously; The signal of the first reset signal line is an effective level signal in the first time period and an invalid level signal in the second time period, and the signal of the scan signal line is an invalid level signal in the first time period and an effective level signal in the second time period; When the signal of the second reset signal line is an active level signal, the signal of the light-emitting signal line is an inactive level signal. When the signal of the light-emitting signal line is an active level signal, the signals of the first reset signal line, the second reset signal line, and the scan signal line are all inactive level signals.

8. The pixel circuit according to claim 1, wherein The capacitance value C1 of the first capacitor and the capacitance value C2 of the second capacitor satisfy: C2 = C1 / (ΔV1 + V OLED -V init ) Among them, ΔV1 is the voltage value of the signal transition of the first node, and V OLED is the anode voltage of the light-emitting device, and V init is the voltage value of the signal of the initial signal line; The voltage value of the signal of the initial signal line is less than the voltage value of the signal of the second power supply line.

9. A display substrate, characterized in that, including: The pixel circuit according to any one of claims 1 to 8.

10. The display substrate according to claim 9, wherein including: a substrate and a driving circuit layer and a light-emitting structure layer provided on the substrate. The driving circuit layer includes: a pixel circuit, a light-emitting signal line, an initial signal line, a first scan signal line, a first reset signal line, a second reset signal line, a first power supply line, and a data signal line. The light-emitting structure layer includes: a light-emitting device.

11. The display substrate according to claim 10, wherein The driving circuit layer includes a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a fourth insulating layer, and a planarization layer sequentially provided on the substrate; The pixel circuit includes: a plurality of transistors, a first capacitor, and a second capacitor. The first capacitor and the second capacitor respectively include: a first electrode plate and a second electrode plate; The semiconductor layer at least includes the active layers of a plurality of transistors; The first conductive layer at least includes the first reset signal line, the scan signal line, the light-emitting signal line, the second reset signal line, the control electrodes of a plurality of transistors, the first electrode plate of the first capacitor, and the second electrode plate of the second capacitor; The second conductive layer at least includes the initial signal line and the second electrode plate of the first capacitor; The third conductive layer at least includes the data signal line, the first power supply line, the second electrode plate of the second capacitor, and the first pole and the second pole of a plurality of transistors.

12. The display substrate according to claim 10, wherein, The driving circuit layer includes a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a fourth insulating layer, and a planarization layer sequentially provided on the substrate; The pixel circuit includes: a first transistor to a seventh transistor, a first capacitor, and a second capacitor. The first capacitor and the second capacitor respectively include: a first electrode plate and a second electrode plate; The semiconductor layer at least includes the active layers of a plurality of transistors; The first conductive layer at least includes the first reset signal line, the scan signal line, the light-emitting signal line, and the second reset signal line, and the control electrodes of the first transistor to the seventh transistor, the first electrode plate of the first capacitor, and the second electrode plate of the second capacitor. The first reset signal line, the scan signal line, the light-emitting signal line, and the second reset signal line extend along a first direction; The second conductive layer at least includes the initial signal line and the second electrode plate of the first capacitor; The third conductive layer at least includes the data signal line, the first power supply line, the second electrode plate of the second capacitor, and the first pole and the second pole of the first transistor, the first pole of the second transistor, the first pole of the fourth transistor, the first pole of the fifth transistor, the second pole of the sixth transistor, the first pole and the second pole of the seventh transistor. The data signal line and the first power supply line extend along a second direction, and the first direction intersects the second direction.

13. The display substrate according to claim 12, wherein The region where the scanning signal line overlaps with the active layer of the second transistor serves as the control electrode of the second transistor, the region where the scanning signal line overlaps with the active layer of the fourth transistor serves as the control electrode of the fourth transistor, and the region where the scanning signal line overlaps with the second electrode of the first transistor serves as the first electrode plate of the second capacitor.

14. The display substrate according to claim 12, wherein The second electrode plate of the first capacitor includes: a capacitor main body portion and a capacitor connection portion. The capacitor connection portion is located on the side of the capacitor main body portion close to the initial signal line and is interconnected with the capacitor main body portion; The orthographic projection of the capacitor main body portion on the substrate at least partially overlaps with the orthographic projection of the first electrode plate of the first capacitor on the substrate; an opening is provided on the capacitor main body portion, and the opening exposes the first electrode plate covering the first capacitor; the orthographic projection of the capacitor connection portion on the substrate partially overlaps with the orthographic projections of the light-emitting signal line and the active layer of the sixth transistor on the substrate respectively.

15. The display substrate according to claim 12, wherein It further includes: The first via to the sixth via provided on the first insulating layer to the third insulating layer, the seventh via provided on the second insulating layer and the third insulating layer, the eighth via and the ninth via provided on the third insulating layer; The orthographic projection of the first via on the substrate is within the range of the orthographic projection of the active layer of the first transistor on the substrate, the orthographic projection of the second via on the substrate is within the range of the orthographic projection of the active layer of the first transistor on the substrate, the orthographic projection of the third via on the substrate is within the range of the orthographic projection of the active layer of the fourth transistor on the substrate, the orthographic projection of the fourth via on the substrate is within the range of the orthographic projection of the active layer of the fifth transistor on the substrate, the orthographic projection of the fifth via on the substrate is within the range of the orthographic projection of the active layer of the sixth transistor on the substrate, the orthographic projection of the sixth via on the substrate is within the range of the orthographic projection of the active layer of the seventh transistor on the substrate, the orthographic projection of the seventh via on the substrate is within the range of the orthographic projection of the opening on the substrate, the orthographic projection of the eighth via on the substrate is within the range of the orthographic projection of the initial signal line on the substrate, and the orthographic projection of the ninth via on the substrate is within the range of the orthographic projection of the second electrode plate of the first capacitor on the substrate.

16. The display substrate according to claim 15, wherein A virtual straight line extending in the second direction passes through the first via and the fourth via, a virtual straight line extending in the first direction passes through the second via and the third via, a virtual straight line extending in the second direction passes through the fifth via and the ninth via, and a virtual straight line extending in the first direction passes through the sixth via and the eighth via.

17. The display substrate according to claim 15 or 16, characterized in that, The orthographic projection of the first power supply line on the substrate at least partially overlaps with the orthographic projections of the first via and the fourth via on the substrate. The region where the first power supply line overlaps with the first via serves as the first electrode of the first transistor, and the region where the first power supply line overlaps with the fourth via serves as the first electrode of the fifth transistor.

18. The display substrate according to claim 15 or 16, characterized in that, The data signal line includes: a first data connection portion, a second data connection portion, a third data connection portion, a fourth data connection portion, and a fifth data connection portion arranged in sequence along a second direction. The second data connection portion is respectively connected to the first data connection portion and the third data connection portion. The fourth data connection portion is respectively connected to the third data connection portion and the fifth data connection portion. A virtual straight line extending along the second direction passes through the first data connection portion and the fifth data connection portion. The third data connection portion is located on a side of the first data connection portion and the fifth data connection portion away from the first power supply line; The first data connection portion extends along the second direction, and the angle between the first data connection portion and the second data connection portion is greater than 90 degrees and less than 180 degrees. The third data connection portion extends along the second direction, and the angles between the third data connection portion and the second data connection portion and the fourth data connection portion are both greater than 90 degrees and less than 180 degrees. The fifth data connection portion extends along the second direction, and the angle between the fifth data connection portion and the fourth data connection portion is greater than 90 degrees and less than 180 degrees.

19. The display substrate according to claim 18, wherein The positive projection of the second data connection portion on the substrate overlaps with the positive projection of the first reset signal line on the substrate. The positive projection of the third data connection portion on the substrate overlaps with the positive projection of the third via and the scan signal line on the substrate. The region where the third data connection portion overlaps with the third via serves as the first pole of the fourth transistor. The positive projection of the fourth data connection portion on the substrate overlaps with the positive projection of the light-emitting signal line and the second electrode plate of the first capacitor on the substrate. The positive projection of the fifth data connection portion on the substrate overlaps with the positive projections of the second reset signal line and the initial signal line on the substrate respectively.

20. The display substrate according to claim 15 or 16, characterized in that, The second pole of the first transistor and the first pole of the second transistor are the same electrode, and the positive projection of the second pole of the first transistor on the substrate overlaps with the positive projections of the second via, the seventh via, the second electrode plate of the first capacitor, and the scan signal line on the substrate. The region where the second pole of the first transistor overlaps with the scan signal line serves as the second electrode plate of the second capacitor; The second pole of the sixth transistor and the second pole of the seventh transistor are the same electrode, and the positive projection of the second pole of the sixth transistor on the substrate overlaps with the positive projections of the fifth via and the ninth via on the substrate at least partially; The positive projection of the first pole of the seventh transistor on the substrate overlaps with the positive projections of the sixth via and the eighth via on the substrate at least partially.

21. A display device, characterized in that, Including: The display substrate according to any one of claims 9 to 20.

22. A driving method for a pixel circuit, characterized in that, Configured to drive the pixel circuit according to any one of claims 1 to 8, the method includes: The first node control sub-circuit, under the control of the signals of the scan signal line, the first reset signal line, and the second reset signal line, provides the signal of the first power supply line or the signal of the second node to the first node, provides the signal of the data signal line to the third node, and provides the signal of the initial signal line to the fourth node; The second node control sub-circuit stores the signals of the first node and the fourth node, and drives the signal of the first node to change under the control of the signal of the scan signal line; The driving sub-circuit provides a driving current to the third node under the control of the signals at the first node and the second node. The light-emitting control sub-circuit provides the signal of the first power supply line to the second node and the signal of the third node to the fourth node under the control of the signal on the light-emitting signal line.

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