A driving circuit, a display panel, a driving method thereof, and a display device

Abstract

The present invention discloses a driving circuit, a display panel, a driving method thereof, and a display device, and relates to the field of display technology. The driving circuit includes: a plurality of driving units corresponding to light-emitting units, each driving unit including a first asynchronous D flip-flop and a second asynchronous D flip-flop; the first asynchronous D flip-flops are cascaded, and the input pin of the first-stage first asynchronous D flip-flop is used to receive a first control signal; the clock pin of each first asynchronous D flip-flop is used to receive a second control signal; in one driving unit, the output pin of the first asynchronous D flip-flop is coupled to the input pin of the second asynchronous D flip-flop, the clock pin of the second asynchronous D flip-flop is used to receive a third control signal, and the output pin of the second asynchronous D flip-flop is used to couple to the anode of the corresponding light-emitting unit, effectively reducing the number of binding pins, thereby reducing the width of the externally connected FPC and the cost of external driving circuit components, and saving material costs.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a driving circuit, a display panel and a driving method thereof, and a display device. Background Art

[0002] OLED (Organic Light-Emitting Diode) lighting components are semiconductor-based surface light sources. They provide uniform, detailed light with extremely high contrast and flexible brightness adjustment. Furthermore, their light source can be freely configured and precisely segmented and switched.

[0003] The current design of OLED display panels usually adopts the following Figure 1 The design shown is to lead out the anode of each OLED light-emitting device separately, connect it to an external FPC (Flexible Printed Circuit) through binding pins, and drive and control it through the external FPC. This design causes the number of pins used to connect to the external FPC to increase as the number of driven OLED light-emitting devices increases, thereby increasing the number of pins on the external FPC and the number of driving circuit components, increasing the width of the FPC, and increasing the component BOM cost. Summary of the Invention

[0004] In view of this, embodiments of the present invention provide a driving circuit, a display panel and a driving method thereof, and a display device to solve the problem of a large external FPC width caused by an excessive number of binding pins in existing OLED display panels.

[0005] Therefore, an embodiment of the present invention provides a driving circuit, comprising: a plurality of driving units corresponding to light-emitting units, each of the driving units comprising a first asynchronous D flip-flop and a second asynchronous D flip-flop;

[0006] The first asynchronous D flip-flops are cascaded, and the input pin of the first asynchronous D flip-flop is used to receive the first control signal;

[0007] The clock pin of each of the first asynchronous D flip-flops is used to receive a second control signal;

[0008] In one of the above-mentioned driving units, the output pin of the above-mentioned first asynchronous D flip-flop is coupled to the input pin of the above-mentioned second asynchronous D flip-flop, the clock pin of the above-mentioned second asynchronous D flip-flop is used to receive a third control signal, and the output pin of the above-mentioned second asynchronous D flip-flop is used to couple to the anode of the corresponding light-emitting unit.

[0009] In a possible implementation, in the driving circuit provided by an embodiment of the present invention, a reset pin of each of the first asynchronous D flip-flops is configured to receive a fourth control signal.

[0010] In a possible implementation, in the driving circuit provided by an embodiment of the present invention, each of the driving units further includes a tri-state buffer;

[0011] In one of the above-mentioned driving units, the output pin of the above-mentioned second asynchronous D flip-flop is coupled to the input pin of the above-mentioned tri-state buffer, the output pin of the above-mentioned tri-state buffer is used to couple to the anode of the corresponding light-emitting unit, and the control pin of the above-mentioned tri-state buffer is used to receive the fifth control signal.

[0012] In a possible implementation, the driving circuit provided in the embodiment of the present invention further includes a first input buffer, a second input buffer, a third input buffer, a fourth input buffer, and a fifth input buffer;

[0013] The input pin of the first asynchronous D flip-flop of the first stage is coupled to the output end of the first input buffer, and the input end of the first input buffer is used to receive the first control signal;

[0014] The clock pins of the first asynchronous D flip-flops are coupled to each other and then to the output end of the second input buffer, and the input end of the second input buffer is used to receive the second control signal;

[0015] The reset pins of the first asynchronous D flip-flops are coupled to each other and then to the output end of the fourth input buffer, and the input end of the fourth input buffer is used to receive the fourth control signal;

[0016] The clock pins of the second asynchronous D flip-flops are coupled to each other and then to the output end of the third input buffer, and the input end of the third input buffer is used to receive the third control signal;

[0017] The control pins of the tri-state buffers are coupled to each other and then to the output end of the fifth input buffer. The input end of the fifth input buffer is used to receive a fifth control signal.

[0018] In a possible implementation, in the driving circuit provided by an embodiment of the present invention, an inverter is installed on the fourth input buffer.

[0019] On the other hand, an embodiment of the present invention further provides a display panel, comprising the above-mentioned driving circuit provided by an embodiment of the present invention and a plurality of light-emitting units arranged in an array;

[0020] Each driving unit in the driving circuit is coupled to the anode of the corresponding light emitting unit.

[0021] In a possible implementation, in the display panel provided by an embodiment of the present invention, the driving circuit includes a first input buffer, a second input buffer, a third input buffer, a fourth input buffer, and a fifth input buffer;

[0022] The display panel further comprises: a first binding pin, a second binding pin, a third binding pin, a fourth binding pin and a fifth binding pin;

[0023] The first binding pin is coupled to the input terminal of the first input buffer, and the first binding pin is used to output the first control signal;

[0024] The second binding pin is coupled to the input terminal of the second input buffer, and the second binding pin is used to output the second control signal;

[0025] The third binding pin is coupled to the input end of the third input buffer, and the third binding pin is used to output the third control signal;

[0026] The fourth binding pin is coupled to the input end of the fourth input buffer, and the fourth binding pin is used to output the fourth control signal;

[0027] The fifth binding pin is coupled to the input terminal of the fifth input buffer, and the fifth binding pin is used to output the fifth control signal.

[0028] In a possible implementation, the display panel provided by the embodiment of the present invention further includes at least one ground pin;

[0029] The at least one ground pin is coupled to each other and then coupled to the cathode of each light emitting unit.

[0030] On the other hand, an embodiment of the present invention further provides a display device, comprising the above-mentioned display panel provided by an embodiment of the present invention.

[0031] On the other hand, an embodiment of the present invention further provides a method for driving the display panel, comprising:

[0032] A first control signal is loaded onto the input pin of the first asynchronous D flip-flop of the first stage, a second control signal is loaded onto the clock pin of each of the above-mentioned first asynchronous D flip-flops, and a third control signal is loaded onto the clock pin of each of the above-mentioned second asynchronous D flip-flops; wherein the above-mentioned first control signal is a data signal, and the above-mentioned second control signal and the above-mentioned third control signal are clock signals.

[0033] The beneficial effects of the embodiments of the present invention include:

[0034] A driving circuit provided in an embodiment of the present invention realizes the control of multiple light-emitting units through fewer control signals, effectively reducing the number of binding pins, thereby reducing the width of the externally connected FPC, saving material costs, and increasing product reliability and module design flexibility; and, compared with the design of external driving circuits in the prior art, this driving circuit reduces component and module costs, saving external circuit driving costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 A schematic diagram of the structure of an OLED display panel in the prior art;

[0036] Figure 2 A schematic structural diagram of a driving circuit provided in an embodiment of the present invention;

[0037] Figure 3 A schematic diagram of the structure of an asynchronous D flip-flop provided in an embodiment of the present invention;

[0038] Figure 4 A schematic structural diagram of a display panel provided by an embodiment of the present invention;

[0039] Figure 5 A schematic diagram of a display interface of a display device provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0040] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0041] The shapes and sizes of the components in the drawings do not reflect the actual proportions of the driving circuit, display panel and display device, and are only intended to illustrate the contents of the present invention.

[0042] It should be noted that, in the embodiments of the present application, except for the reverse output pin specifically mentioned, the output pins of the asynchronous D flip-flop mentioned below all refer to the forward output pins.

[0043] like Figure 2 As shown, an embodiment of the present application provides a driving circuit, including:

[0044] A plurality of driving units 200 corresponding to the light-emitting units, each of the driving units 200 including a first asynchronous D flip-flop and a second asynchronous D flip-flop;

[0045] The light emitting device may have various structures, which can be selected according to actual needs. For example, the light emitting device may be an OLED, a quantum dot light emitting diode (QLED), or a micro light emitting diode (Micro LED).

[0046] In a specific implementation, the structures of the first asynchronous D flip-flop and the second asynchronous D flip-flop are the same, such as Figure 3 As shown in the figure, each includes an input pin, a clock pin, a reset pin, an output (positive output) pin, and a reverse output pin. When the reset pin is set to a low level, the asynchronous D flip-flop is reset; when the clock pin is set to a rising edge, the data at the input pin is transferred to the output pin; the output signal of the reverse pin is opposite to that of the output pin.

[0047] Each of the above-mentioned first asynchronous D flip-flops is cascaded, and the first asynchronous D flip-flop (such as Figure 2 The input pin of the first asynchronous D flip-flop in the dotted box is used to receive the first control signal, that is, the input pin of the first asynchronous D flip-flop except the first stage is connected to the output pin of the first asynchronous D flip-flop of the previous stage;

[0048] The clock pin of each of the above-mentioned first asynchronous D flip-flops is used to receive the second control signal, and when the second control signal is a rising edge, the data at the input pin of the first asynchronous D flip-flop is transmitted to the output pin;

[0049] In a driving unit 200, the output pin of the first asynchronous D flip-flop is coupled to the input pin of the second asynchronous D flip-flop, the clock pin of the second asynchronous D flip-flop is used to receive a third control signal, and the output pin of the second asynchronous D flip-flop is used to couple to the anode of the corresponding light-emitting unit. When the third control signal is a rising edge, the data of the input pin of the second asynchronous D flip-flop is transmitted to the output pin, that is, the data of the output pin of the first asynchronous D flip-flop is transmitted to the anode of the corresponding light-emitting unit.

[0050] It is worth noting that in the embodiment of the present invention, Figure 2 In the schematic diagram, only the example of four driving units 200 in the driving circuit is used for illustration. In a specific implementation, each driving unit 200 is used to provide a data signal for the corresponding light-emitting unit. The number of driving units 200 is consistent with the number of light-emitting units, that is, the number of driving units 200 is determined by the number of light-emitting units.

[0051] In specific implementation, the design of the driving circuit in the embodiment of the present application realizes the control of multiple light-emitting units through fewer control signals, effectively reducing the number of binding pins, thereby reducing the width of the externally connected FPC, saving material costs, and increasing product reliability and module design flexibility; and, compared with the design of the external driving circuit in the prior art, the driving circuit reduces the cost of components and modules, and saves the cost of external circuit driving.

[0052] In some possible embodiments, the reset pin of each of the above-mentioned first asynchronous D flip-flops is used to receive a fourth control signal, and the above-mentioned fourth control signal is used to reset the first asynchronous D flip-flop. Since the asynchronous D flip-flop is reset at a low level, when the fourth control signal received by the reset pin of each first asynchronous D flip-flop is at a low level, each first asynchronous D flip-flop is reset.

[0053] In some possible implementations, such as Figure 2 As shown, each of the above-mentioned driving units 200 also includes a three-state buffer; the three-state buffer includes three pins: an input pin, an output pin, and a control pin. When the control pin is at a low level, the output pin of the three-state buffer is in a high-impedance state, and the data of the input pin cannot be transmitted to the output pin. When the control pin is at a high level, the data of the input pin of the three-state buffer cannot be transmitted to the output pin, and the data of the output pin is consistent with the input pin.

[0054] In one of the driving units 200, the output pin of the second asynchronous D flip-flop is coupled to the input pin of the tri-state buffer, the output pin of the tri-state buffer is coupled to the anode of the corresponding light-emitting unit, and the control pin of the tri-state buffer is used to receive a fifth control signal;

[0055] The above-mentioned fifth control signal is used to control the state of the three-state buffer. When the fifth control signal is at a low level, since the output pin of the three-state buffer is in a high-impedance state, the anode of the corresponding light-emitting unit connected thereto is also in a high-impedance state. At this time, all light-emitting units cannot emit light, and the light-emitting state (switch state) of the light-emitting unit can be controlled by the fifth control signal.

[0056] In some possible implementations, such as Figure 2 As shown, the driving circuit further includes a first input buffer, a second input buffer, a third input buffer, a fourth input buffer and a fifth input buffer; the input buffer includes an input pin and an output pin, and data from the input pin can be directly transmitted to the output pin;

[0057] The input pin of the first asynchronous D flip-flop of the first stage is coupled to the output end of the first input buffer, and the input end of the first input buffer is used to receive the first control signal;

[0058] The clock pins of the first asynchronous D flip-flops are coupled to each other and then to the output end of the second input buffer, and the input end of the second input buffer is used to receive the second control signal;

[0059] The reset pins of the first asynchronous D flip-flops are coupled to each other and then to the output end of the fourth input buffer, and the input end of the fourth input buffer is used to receive the fourth control signal;

[0060] The clock pins of the second asynchronous D flip-flops are coupled to each other and then to the output end of the third input buffer, and the input end of the third input buffer is used to receive the third control signal;

[0061] The control pins of the tri-state buffers are coupled to each other and then to the output end of the fifth input buffer. The input end of the fifth input buffer is used to receive a fifth control signal.

[0062] In a specific implementation, the above-mentioned input buffer temporarily stores the control signal input from the external device, so that devices such as the asynchronous D flip-flop and the tri-state buffer can obtain the corresponding control signal from it, which can prevent the signal from changing too quickly and play a better signal filtering role.

[0063] In some possible implementations, since the first asynchronous D flip-flop has a low-level reset mechanism, when the control signal received by the reset pin of each first asynchronous D flip-flop is at a low level, each first asynchronous D flip-flop is reset. To facilitate the reset operation of the first asynchronous D flip-flop, an inverter is installed on the fourth input buffer in an embodiment of the present application, that is, when the fourth control signal is at a high level, the first asynchronous D flip-flop is reset.

[0064] Based on the same inventive concept, an embodiment of the present invention further provides a display panel. Since the principle of solving the problem of the display panel is the same as that of the aforementioned driving circuit, the implementation of the display panel can refer to the implementation of the driving circuit, and the repeated parts will not be repeated.

[0065] Specifically, the display panel provided by the embodiment of the present invention is as follows: Figure 4 As shown, it includes: the above-mentioned driving circuit 401 provided by the embodiment of the present invention. Figure 4 As shown, it generally also includes: a plurality of light-emitting units 402 arranged in an array.

[0066] Each driving unit in the driving circuit corresponds to a light-emitting unit, and each driving unit is coupled to the anode of the corresponding light-emitting unit through an output pin.

[0067] Of course, since the driving circuit includes a first input buffer, a second input buffer, a third input buffer, a fourth input buffer, and a fifth input buffer, the display panel may further include the following multiple binding pins 403 for correspondingly coupling with the multiple input buffers of the driving unit, and the multiple binding pins 403 specifically include: a first binding pin, a second binding pin, a third binding pin, a fourth binding pin, and a fifth binding pin;

[0068] Specifically, the first binding pin is coupled to the input end of the first input buffer, and the first binding pin is used to output the first control signal;

[0069] The second binding pin is coupled to the input terminal of the second input buffer, and the second binding pin is used to output the second control signal;

[0070] The third binding pin is coupled to the input end of the third input buffer, and the third binding pin is used to output the third control signal;

[0071] The fourth binding pin is coupled to the input end of the fourth input buffer, and the fourth binding pin is used to output the fourth control signal;

[0072] The fifth binding pin is coupled to the input terminal of the fifth input buffer, and the fifth binding pin is used to output the fifth control signal.

[0073] In a specific implementation, the plurality of binding pins 403 in the display panel further include at least one ground pin; the at least one ground pin is coupled to each other and then coupled to the cathode of each light emitting unit.

[0074] It is worth noting that in the embodiment of the present invention, Figure 4 In the schematic diagram, only three ground pins are used as an example for illustration. In a specific implementation, the number of ground pins included in the above display surface is not limited here.

[0075] Based on the above display panel, an embodiment of the present invention further provides a driving method applied to the above display panel, including:

[0076] A first control signal is loaded onto the input pin of the first asynchronous D flip-flop of the first stage, a second control signal is loaded onto the clock pin of each of the above-mentioned first asynchronous D flip-flops, and a third control signal is loaded onto the clock pin of each of the above-mentioned second asynchronous D flip-flops; wherein the above-mentioned first control signal is a data signal, and the above-mentioned second control signal and the above-mentioned third control signal are clock signals.

[0077] In a specific implementation, after the first control signal is loaded onto the input pin of the first asynchronous D flip-flop of the first stage, the second control signal of the rising edge is loaded onto the clock pin of each of the above-mentioned first asynchronous D flip-flops, so that the first control signal is shifted and transmitted between each of the first asynchronous D flip-flops; for example, when the first control signal is 1100, when the second control signal changes to a rising edge for the first time, the first asynchronous D flip-flop of the first stage outputs 0; when the second control signal changes to a rising edge for the second time, the first asynchronous D flip-flop of the first stage outputs 0, and the first asynchronous D flip-flop of the second stage (the first asynchronous D flip-flop of the next stage after the first asynchronous D flip-flop of the first stage) outputs 0; when the second control signal changes to a rising edge for the third time, the first asynchronous D flip-flop of the first level outputs 1, the first asynchronous D flip-flop of the second level outputs 0, and the first asynchronous D flip-flop of the third level (the first asynchronous D flip-flop of the next level of the second-level first asynchronous D flip-flop) outputs 0; when the second control signal changes to a rising edge for the fourth time, the first asynchronous D flip-flop of the first level outputs 1, the first asynchronous D flip-flop of the second level outputs 1, the first asynchronous D flip-flop of the third level outputs 0, and the first asynchronous D flip-flop of the fourth level (the first asynchronous D flip-flop of the next level of the third-level first asynchronous D flip-flop) outputs 0. At this point, the transmission of the first control signal is completed.

[0078] After the transmission of the first control signal is completed, a third control signal with a rising edge is loaded to the clock pin of each of the above-mentioned second asynchronous D flip-flops, so that each of the above-mentioned second asynchronous D flip-flops transmits the data output by the corresponding first asynchronous D flip-flop to a three-state buffer, and then the three-state buffer transmits the data to the anode of the corresponding light-emitting unit, so that the display panel displays the corresponding pattern.

[0079] In a possible embodiment, the driving method further includes: loading a fourth control signal on the reset pin of each of the first asynchronous D flip-flops, and loading a fifth control signal on the control pin of each of the three-state buffers; wherein the fourth control signal and the fifth control signal are data signals.

[0080] In a specific implementation, when an inverter is installed on the fourth input buffer, the reset pin of each of the above-mentioned first asynchronous D flip-flops can be loaded with a high-level fourth control signal to control the reset of each of the above-mentioned first asynchronous D flip-flops; when the display panel is in a non-working state, the three-state buffer can be controlled to be turned off by the fifth control signal, so that the output pin of the three-state buffer remains in a high-impedance state.

[0081] In a possible embodiment, the light emitting unit pattern displayed by the display panel is as follows: Figure 5 As shown in the figure, the black area indicates that the light-emitting unit is in a light-emitting state.

[0082] Based on the same inventive concept, embodiments of the present invention further provide a display device comprising the display panel described above. The display device can be any product or component having a display function, such as an automotive display. The implementation of the display device can refer to the aforementioned display panel embodiments, and any repetitive details will not be repeated.

[0083] Obviously, those skilled in the art may make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if such changes and modifications fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.

Claims

1. A driving circuit, characterized in that: comprising a fifth input buffer, and a plurality of driving units corresponding to the light-emitting units, each of the driving units comprising a first asynchronous D flip-flop, a second asynchronous D flip-flop, and a tri-state buffer; The first asynchronous D flip-flops are cascaded, and the input pin of the first asynchronous D flip-flop is used to receive the first control signal; The clock pin of each of the first asynchronous D flip-flops is used to receive a second control signal; In one of the driving units, an output pin of the first asynchronous D flip-flop is coupled to an input pin of the second asynchronous D flip-flop, a clock pin of the second asynchronous D flip-flop is used to receive a third control signal, and an output pin of the second asynchronous D flip-flop is used to couple to an anode of a corresponding light-emitting unit; In one of the driving units, the output pin of the second asynchronous D flip-flop is coupled to the input pin of the tri-state buffer, the output pin of the tri-state buffer is used to couple to the anode of the corresponding light-emitting unit, and the control pin of the tri-state buffer is used to receive a fifth control signal; The control pins of the tri-state buffers are coupled to each other and then to the output end of the fifth input buffer. The input end of the fifth input buffer is used to receive a fifth control signal.

2. The driving circuit according to claim 1, wherein: The reset pin of each of the first asynchronous D flip-flops is used to receive a fourth control signal.

3. The driving circuit according to claim 2, wherein: Also comprising a first input buffer, a second input buffer, a third input buffer and a fourth input buffer; The input pin of the first asynchronous D flip-flop of the first stage is coupled to the output end of the first input buffer, and the input end of the first input buffer is used to receive the first control signal; The clock pins of each of the first asynchronous D flip-flops are coupled to each other and then to the output end of the second input buffer, and the input end of the second input buffer is used to receive the second control signal; The reset pins of the first asynchronous D flip-flops are coupled to each other and then to the output end of the fourth input buffer, and the input end of the fourth input buffer is used to receive the fourth control signal; The clock pins of each of the second asynchronous D flip-flops are coupled to each other and then to the output end of the third input buffer. The input end of the third input buffer is used to receive the third control signal.

4. The driving circuit according to claim 3, wherein: An inverter is mounted on the fourth input buffer.

5. A display panel, characterized in that: Comprising the driving circuit according to any one of claims 1 to 4, and a plurality of light-emitting units arranged in an array; Each driving unit in the driving circuit is coupled to the anode of the corresponding light emitting unit.

6. The display panel according to claim 5, wherein: The driving circuit includes a first input buffer, a second input buffer, a third input buffer and a fourth input buffer; The display panel further includes: a first binding pin, a second binding pin, a third binding pin, a fourth binding pin and a fifth binding pin; The first binding pin is coupled to an input terminal of the first input buffer, and the first binding pin is used to output the first control signal; The second binding pin is coupled to the input end of the second input buffer, and the second binding pin is used to output the second control signal; The third binding pin is coupled to the input end of the third input buffer, and the third binding pin is used to output the third control signal; The fourth binding pin is coupled to the input end of the fourth input buffer, and the fourth binding pin is used to output a fourth control signal; The fifth binding pin is coupled to the input end of the fifth input buffer, and the fifth binding pin is used to output the fifth control signal.

7. The display panel according to claim 5, wherein: Also comprising at least one ground pin; The at least one ground pin is coupled to each other and then coupled to the cathode of each light emitting unit.

8. A display device, characterized in that: Comprising the display panel according to any one of claims 5 to 7.

9. A method for driving a display panel according to any one of claims 5 to 7, characterized in that: include: A first control signal is loaded onto the input pin of the first-stage first asynchronous D flip-flop, a second control signal is loaded onto the clock pin of each of the first asynchronous D flip-flops, and a third control signal is loaded onto the clock pin of each of the second asynchronous D flip-flops; wherein the first control signal is a data signal, and the second control signal and the third control signal are clock signals.

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