A trench-type MOSFET and a method of manufacturing the same
By integrating an SBR structure inside the trench MOSFET and improving the dielectric constant of the gate dielectric layer, the problem of high-temperature leakage current in the Schottky junction was solved, and the reverse recovery charge was reduced and the leakage current was optimized.
Patent Information
- Application Number
- CN202211188398.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-09-28
- Publication Date
- 2026-01-13
- Estimated Expiration
- 2042-09-28
AI Technical Summary
The high-temperature leakage current of the Schottky junction in trench MOSFETs during reverse freewheeling limits their use.
An SBR structure is integrated inside the trench MOSFET, and the gate dielectric layer of the SBR structure is improved by increasing the dielectric constant of the gate dielectric layer in the second trench to reduce dielectric leakage.
It effectively reduces the reverse recovery charge (Qrr) of trench MOSFETs and solves the problem of excessive leakage current (Idss) in SBR structures while ensuring low Vf.
Smart Images
Figure CN115424939B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and in particular to a trench MOSFET and its fabrication method. Background Technology
[0002] Trench MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) have advantages such as high input impedance, low drive current, fast switching speed, and good high-temperature characteristics, and are widely used in the field of power electronics.
[0003] In a typical trench MOSFET, the source electrode is connected to the source region through a metal conductive channel. This metal conductive channel forms a Schottky barrier rectifier, which has a lower potential barrier, thus reducing the reverse recovery charge (Qrr) of the trench MOSFET. However, during reverse freewheeling, the high-temperature leakage current of the Schottky barrier is relatively large, limiting the use of trench MOSFETs. Summary of the Invention
[0004] In view of the above problems, the purpose of this application is to provide a trench MOSFET and a method for fabricating the same, which improves the dielectric leakage problem of the trench MOSFET by integrating an SBR structure inside the trench MOSFET and improving the gate dielectric layer of the SBR structure.
[0005] The first aspect of this application provides a method for fabricating a trench MOSFET, comprising:
[0006] A first trench and a second trench are formed extending from the upper surface of an epitaxial layer of a first doping type into its interior, wherein the epitaxial layer includes a first region and a second region, the first trench being located within the first region and the second trench being located within the second region;
[0007] A first shielding grid dielectric layer and a first shielding conductor are formed at the lower part of the first trench, and a second shielding grid dielectric layer and a second shielding conductor are formed at the lower part of the second trench;
[0008] A first interlayer dielectric layer is formed on the surfaces of the first shielding gate dielectric layer and the first shielding conductor, and a second interlayer dielectric layer is formed on the surfaces of the second shielding gate dielectric layer and the second shielding conductor.
[0009] A first gate dielectric layer and a first gate conductor are formed on the upper part of the first trench, and a second gate dielectric layer and a second gate conductor are formed on the upper part of the second trench; and
[0010] On the two sides adjacent to the first trench and the second trench in the epitaxial layer, a body region, a source region and a contact region are formed, wherein the source region is of a first doping type and the body region and the contact region are of a second doping type;
[0011] The dielectric constant of the second gate dielectric layer located in the second trench is greater than that of the first gate dielectric layer located in the first trench.
[0012] A second aspect of this application provides a trench MOSFET, comprising:
[0013] Epitaxial layer of the first doping type;
[0014] Epitaxial layer of the first doping type;
[0015] The first trench extends from the upper surface of the epitaxial layer into its interior;
[0016] A first shielding barrier dielectric layer is disposed in the lower part of the first trench and covers the inner surface of the lower part of the first trench;
[0017] A first shielding conductor is disposed at the lower part of the first trench and is isolated from the epitaxial layer by the first shielding gate dielectric layer;
[0018] The first interlayer dielectric layer is disposed on the surface of the first shielding gate dielectric layer;
[0019] A first gate dielectric layer is disposed on the upper part of the first trench and covers the inner surface of the upper part of the first trench;
[0020] A first gate conductor is disposed on the upper part of the first trench and isolated by the first gate dielectric layer and the epitaxial layer;
[0021] The second trench extends from the upper surface of the epitaxial layer into its interior;
[0022] A second shielding barrier dielectric layer is disposed in the lower part of the second trench and covers the inner surface of the lower part of the second trench;
[0023] The second shielding conductor is disposed in the lower part of the second trench and is isolated from the epitaxial layer by the second shielding gate dielectric layer;
[0024] The second interlayer dielectric layer is disposed on the surface of the second shielding gate dielectric layer;
[0025] A second gate dielectric layer is disposed on the upper part of the second trench and covers the inner surface of the upper part of the second trench;
[0026] A second gate conductor is disposed on the upper part of the first trench and isolated from the epitaxial layer by the second gate dielectric layer; and
[0027] The body region, source region, and contact region are located on both sides of the epitaxial layer adjacent to the first trench and the second trench, wherein the source region is of the first doping type, and the body region and the contact region are of the second doping type;
[0028] Wherein, the dielectric constant of the second gate dielectric layer in the second trench is greater than that of the first gate dielectric layer in the first trench. Attached Figure Description
[0029] The above and other objects, features and advantages of this application will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:
[0030] Figure 1 A cross-sectional view of a trench MOSFET is shown.
[0031] Figure 2 A cross-sectional view of a trench MOSFET according to an embodiment of this application is shown;
[0032] Figures 3a to 3j Cross-sectional views of various stages of a method for manufacturing a trench MOSFET device according to an embodiment of this application are shown. Detailed Implementation
[0033] In the following figures, the same elements are represented by similar reference numerals. For clarity, the parts in the figures are not drawn to scale. Furthermore, some well-known parts may not be shown. For simplicity, a semiconductor structure obtained after several steps can be depicted in a single figure.
[0034] When describing the structure of a device, when referring to a layer or region as being "above" or "on top of" another layer or region, it can mean that it is directly above another layer or region, or that it contains other layers or regions between it and another layer or region. Furthermore, if the device is flipped, the layer or region will be located "below" or "under" another layer or region.
[0035] To describe a situation where it is located directly on another layer or another area, this article will use the expressions "directly on top of" or "on and adjacent to".
[0036] like Figure 1As shown, the trench MOSFET 10 includes: a semiconductor substrate 11 of a first conductivity type, an epitaxial layer 12 on the upper surface of the semiconductor substrate 11, and a metal layer 23 formed on the back side of the semiconductor substrate 11. A trench 12a is formed within the epitaxial layer 12, and the sidewalls of the trench 12a are covered by a first dielectric layer 13 and a second dielectric layer 14. A first conductor 15 and a second conductor 16 are present in the trench 12a. The first conductor 15 is located in the lower half of the trench, and the second conductor 16 is located in the upper half of the trench. An interlayer dielectric layer 17 is provided between the first conductor 15 and the second conductor 16. The first conductor 15 is isolated from the epitaxial layer 12 by the first dielectric layer 13, and the second conductor 16 is isolated from the epitaxial layer 12 by the second dielectric layer 14.
[0037] Above the epitaxial layer 12 is a body region 18 of the second conductivity type, and above the body region 18 is a heavily doped region 19 of the second conductivity type. The second conductor 16 is isolated from the body region 18 by a second dielectric layer 14. Above the body region 18 is a heavily doped source region 20 of the first conductivity type, and a conductive channel 21 is formed within the source region 20 and the heavily doped region 19. The conductive channel 21, the second conductor 16, and the source region 20 are isolated by a fourth dielectric layer 22. The conductive channel 21 forms a Schottky barrier rectifier with a lower barrier in the source region 20 to reduce the reverse recovery charge (Qrr) of the trench MOSFET.
[0038] Figure 2 This is a cross-sectional view of a trench MOSFET according to an embodiment of this application. In this application, the first doping type is either N-type or P-type, and the second doping type is either N-type or P-type. An N-type semiconductor layer can be formed by implanting an N-type dopant, such as P or As, into the semiconductor layer. A P-type semiconductor layer can be formed by doping a P-type dopant, such as B, into the semiconductor layer.
[0039] The trench MOSFET 100 includes a substrate 101 and an epitaxial layer 111 thereon. The substrate 101 is of a first doping type, and in this embodiment, the substrate 101 is of a first doping type (e.g., heavily N-type doped). The epitaxial layer 111 is located on a first surface of the substrate 101, and the epitaxial layer 111 is of the first doping type and is lightly doped relative to the substrate 101. A drain electrode 124 is formed on a second surface of the substrate 101.
[0040] The epitaxial layer 111 includes a first region 111a and a second region 111b. A power MOSFET structure is formed in the first region 111a; and an SBR (Super Barrier Rectifier) structure is formed in the second region 111b.
[0041] A first trench 112a is provided in the first region 111a, extending from the upper surface of the epitaxial layer 111 into its interior; a dielectric layer and an electrode conductor are located inside the first trench 112a.
[0042] The dielectric layer within the first trench 112a includes a first shielding gate dielectric layer 1131a, a first gate dielectric layer 1133a, and a first interlayer dielectric layer 1132a. The electrode conductors include a first shielding conductor 115a and a first gate conductor 118a. The first shielding gate dielectric layer 1131a covers the lower inner surface of the first trench 112a, and the first shielding conductor 115a is located within a cavity formed by the first shielding gate dielectric layer 1131a around the lower part of the first trench 112a. The first gate dielectric layer 1133a covers the upper inner surface of the first trench 112a, and the first gate conductor 118a is located within a cavity formed by the first gate dielectric layer 1133a around the upper inner surface of the first trench 112a. The sidewalls of the first gate conductor 118a are isolated from the epitaxial layer 111 via the first gate dielectric layer 1133a. The first interlayer dielectric layer 1132a is located between the first shielding conductor 115a and the first gate conductor 118a, isolating the first shielding conductor 115a and the first gate conductor 118a.
[0043] The second region 111b contains a second trench 112b extending from the upper surface of the epitaxial layer 111 into its interior; a dielectric layer and an electrode conductor located inside the second trench 112b; and a body region 119 located in the epitaxial layer 111 and adjacent to the second trench 112b, wherein the body region 119 is of the second doping type.
[0044] The dielectric layer within the second trench 112b includes a second shielding gate dielectric layer 1131b, a second gate dielectric layer 1133b, and a second interlayer dielectric layer 1132b. The electrode conductors include a second shielding conductor 115b and a second gate conductor 118b. The second shielding gate dielectric layer 1131b covers the lower inner surface of the second trench 112b, and the second shielding conductor 115b is located within a cavity formed by the second shielding gate dielectric layer 1131b around the lower part of the second trench 112b. The second gate dielectric layer 1133b covers the upper inner surface of the second trench 112b, and the second gate conductor 118b is located within a cavity formed by the second gate dielectric layer 1133b around the upper inner surface of the second trench 112b. The sidewalls of the second gate conductor 118b are isolated from the epitaxial layer 111 via the second gate dielectric layer 1133b. The second interlayer dielectric layer 1132b is located between the second shielding conductor 115b and the second gate conductor 118b, isolating the second shielding conductor 115b and the second gate conductor 118b.
[0045] The trench MOSFET 100 further includes a second-doped body region 119, a first-doped source region 121 formed in the body region 119, a second-doped contact region 120 formed in the body region 119, a dielectric layer 122 formed over the source region 121, the first gate conductor 118a, and the second gate conductor 118b, a first conductive channel 125a formed adjacent to the source region 121 that penetrates the dielectric layer 122 and the source region 121 to reach the contact region 120, a second conductive channel 125b formed over the second gate conductor 118b that penetrates the dielectric layer 122 to reach the interior of the second gate conductor 118b, and a source electrode 123 formed over the dielectric layer 122, the source electrode 123 being connected to the contact region 120 via the first conductive channel 125a and to the second gate conductor 118b via the second conductive channel 125b.
[0046] Within the first region 111a, the first trench 112a, the first shielding gate dielectric layer 1131a, the first gate dielectric layer 1133a, the first interlayer dielectric layer 1132a, the first shielding conductor 115a, the first gate conductor 118a, and the body region 119, the source region 121, and the contact region 120 within the first region 111a constitute a power MOSFET structure; within the second region 111b, the second trench 112b, the second shielding gate dielectric layer 1131b, the second gate dielectric layer 1133b, the second interlayer dielectric layer 1132b, the second shielding conductor 115b, the second gate conductor 118b, and the body region 119, the source region 121, and the contact region 120 within the second region 111b constitute an SBR structure.
[0047] The dielectric constant of the second gate dielectric layer 1133b located in the second trench 112b is greater than the dielectric constant of the first gate dielectric layer 1133a located in the first trench 112a. In one embodiment, the first gate dielectric layer 1133a is an oxide layer, such as a silicon oxide layer; the second gate dielectric layer 1133b is a nitride layer, such as a silicon nitride layer, but is not limited thereto.
[0048] In this embodiment, the trench MOSFET integrates an SBR structure, and the SBR structure uses a gate dielectric layer with a high dielectric constant. During reverse freewheeling, in the power MOSFET structure within the first region 111a, the first conductive channel 125a, contact region 120, body region 119, and epitaxial layer 111 form a low-barrier channel; in the SBR structure within the second region 111b, the source region 121, contact region 120, body region 119, and epitaxial layer 111 form a majority carrier low-barrier channel. Compared to a typical trench MOSFET, this effectively reduces Qrr.
[0049] In this embodiment, by increasing the dielectric constant of the gate dielectric layer of the SBR structure and increasing the thickness of the gate dielectric layer of the SBR structure, the leakage current of the gate dielectric layer of the SBR structure is effectively reduced.
[0050] The SBR structure uses a gate dielectric layer with a high dielectric constant, which gives the SBR structure stronger control over the channel. Under the premise of ensuring that the SBR structure has a low Vf (voltage drop of the parasitic body diode), the SBR structure and the power MOSFET structure can use the same body region, which solves the problem of the large leakage current Idss of the general SBR structure.
[0051] Figures 3a to 3g Cross-sectional views of various stages of a method for manufacturing a trench MOSFET device according to an embodiment of this application are shown.
[0052] like Figure 3a As shown, an epitaxial layer 111 is formed on a substrate 101, and a first trench 112a is formed in a first region 111a of the epitaxial layer 111, and a second trench 112b is formed in a second region 111b of the epitaxial layer 111.
[0053] In this step, an epitaxial layer 111 is formed on a substrate 101. The substrate 101 serves as the drain region of the final device and has a first doping type. In this embodiment, the material of the substrate 101 can be a single-crystal silicon substrate doped with N-type. The epitaxial layer 111 includes a first region 111a and a second region 111b.
[0054] A patterned first mask is formed on the first surface of the epitaxial layer 111, and a first trench 112a is formed in the first region 111a of the epitaxial layer 111 via the patterned first mask, and a second trench 112b is formed in the second region 111b of the epitaxial layer 111.
[0055] In this step, for example, a mask layer is formed using a deposition process, and a patterned first mask including openings of a first trench 112a and a second trench 112b is formed using photolithography. Then, the epitaxial layer 111 not covered by the first mask is etched to form the first trench 112a in a first region 111a of the epitaxial layer 111 and the second trench 112b in a second region 111b. In one embodiment, the etching can be dry etching, such as ion milling, plasma etching, reactive ion etching, laser ablation, or wet etching. In this embodiment, the first mask can be a photoresist mask. After forming the first trench 112a and the second trench 112b, the first mask is removed.
[0056] In one embodiment, a shielding gate dielectric layer 1131 is formed inside the first trench 112a, inside the second trench 112b, and on the upper surface of the epitaxial layer 111 by thermal oxidation or chemical vapor deposition. That is, the shielding gate dielectric layer 1131 covers the bottom and sidewalls of the first trench 112a, the bottom and sidewalls of the second trench 112b, and the upper surface of the epitaxial layer 111.
[0057] In one embodiment, the shielding gate dielectric layer 1131 may be composed of oxides or nitrides, such as silicon oxide or silicon nitride. Thermal oxidation includes hydrothermal oxidation (HTO) or selective reactive oxidation (SRO), and chemical vapor deposition (CVD) includes low-pressure chemical vapor deposition (LPCVD) or subatmospheric pressure chemical vapor deposition (SACVD).
[0058] like Figure 3b As shown, a polycrystalline silicon layer 115 is formed inside the first trench 112a, inside the second trench 112b, and on the upper surface of the epitaxial layer 111.
[0059] In this step, a polysilicon layer 115 is formed inside the first trench 112a, inside the second trench 112b, and on the upper surface of the epitaxial layer 111 by low-pressure chemical vapor deposition. The shielding gate dielectric layer 1131 isolates the polysilicon layer 115 from the epitaxial layer 111.
[0060] like Figure 3c As shown, the shielding gate dielectric layer and polysilicon layer are etched back.
[0061] In this step, the polysilicon layer is chemically mechanically polished and etched back, removing the polysilicon layer from the upper surface of the epitaxial layer 111, the upper part of the first trench 112a, and the upper part of the second trench 112b. The remaining polysilicon layer in the first trench 112a becomes the first shielding conductor 115a, i.e., the first shielding conductor 115a is located in the lower part of the first trench 112a; the remaining polysilicon layer in the second trench 112b becomes the second shielding conductor 115b, i.e., the second shielding conductor 115b is located in the lower part of the second trench 112b. In one embodiment, the etch back can be performed using dry etching.
[0062] The shielding gate dielectric layer is etched to remove the shielding gate dielectric layer located on the upper surface of the epitaxial layer 111, the upper part of the first trench 112a, and the upper part of the second trench 112b. This results in the following arrangement: in the first region 111a, the first shielding gate dielectric layer 1131a is located between the sidewall of the first trench 112a and the first shielding conductor 115a, and the first shielding gate dielectric layer 1131a does not cover the top of the first shielding conductor 115a; in the second region 111b, the second shielding gate dielectric layer 1131b is located between the sidewall of the second trench 112b and the second shielding conductor 115b, and the second shielding gate dielectric layer 1131b does not cover the top of the second shielding conductor 115b. In the first trench 112a, the surface of the first shielding gate dielectric layer 1131a is lower than the surface of the first shielding conductor 115a; in the second trench 112b, the surface of the second shielding gate dielectric layer 1131b is lower than the surface of the second shielding conductor 115b.
[0063] In one embodiment, the etching process can be wet etching, which is used to etch a textured surface on a relatively flat film surface, thereby increasing the optical path and reducing light reflection. Wet etching can use diluted HF or BOE (Buffered-Oxide-Etch), etc.
[0064] A conformal interlayer dielectric layer is formed on the tops of the first shielding conductor 115a and the first shielding gate dielectric layer 1131a in the first trench 112a, and on the tops of the second shielding conductor 115b and the second shielding gate dielectric layer 1131b in the second trench 112b, respectively, using a plasma-enhanced chemical vapor deposition method. The interlayer dielectric layer covers the tops of the first shielding conductor 115a and the first shielding gate dielectric layer 1131a in the first trench 112a, the second shielding conductor 115b and the second shielding gate dielectric layer 1131b in the second trench 112b, and is located on the upper sidewalls of the first trench 112a, the upper sidewalls of the second trench 112b, and the upper surface of the epitaxial layer 111. The interlayer dielectric layer may be composed of oxides or nitrides, such as silicon oxide or silicon nitride.
[0065] The interlayer dielectric layer on the upper surface of the epitaxial layer 111 is removed by chemical mechanical polishing. Then, the interlayer dielectric layer in the first trench 112a is etched back using BOE (Buffered-Oxide-Etch) solution, so that a certain thickness of the first interlayer dielectric layer 1132a is retained on top of the first shielding gate dielectric layer 1131a and the first shielding conductor 115a in the first trench 112a. The interlayer dielectric layer in the second trench 112b is etched back, so that a certain thickness of the second interlayer dielectric layer 1132b is retained on top of the second shielding gate dielectric layer 1131b and the second shielding conductor 115b in the second trench 112b.
[0066] like Figure 3d As shown, a first dielectric layer 1133 is formed.
[0067] In this step, a first dielectric layer 1133 is formed on the surface of the first interlayer dielectric layer 1132a in the first trench 112a, the upper sidewall of the first trench 112a, the surface of the second interlayer dielectric layer 1132a in the second trench 112b, the upper sidewall of the second trench 112b, and the upper surface of the epitaxial layer 111. The first dielectric layer 1133 is a high-k dielectric layer, such as a nitride layer or a silicon nitride layer.
[0068] like Figure 3e As shown, a second mask S is formed.
[0069] In this step, for example, a mask layer is formed on the surface of the first dielectric layer 1133 by deposition process, and a second mask S is formed on the surface of the first dielectric layer 1133 in the second region 111b by photolithography. That is, the second mask S covers the surface of the first dielectric layer 1133 in the second region 111b and exposes the surface of the first dielectric layer 1133 in the first region 111a.
[0070] like Figure 3f As shown, the first dielectric layer 1133 in the first region 111a is removed to form the second gate dielectric layer 1133b.
[0071] In this step, the first dielectric layer 1133 in the first region 111a of the epitaxial layer 111 is etched through the second mask S to remove the first dielectric layer 1133 in the first region 111a of the epitaxial layer 111, and the remaining first dielectric layer 1133 in the second region 111b forms the second gate dielectric layer 1133b.
[0072] In one embodiment, a BOE (Buffered-Oxide-Etch) solution is used to etch the first dielectric layer 1133 within the first region 111a. In this embodiment, the second mask S can be a photoresist mask, and the second mask S is removed after the first dielectric layer 1133 within the first region 111a is removed.
[0073] like Figure 3g As shown, a first gate dielectric layer 1133a is formed in the first region 112a of the epitaxial layer 111.
[0074] In this step, for example, thermal oxidation technology is used to form an oxide layer, namely, a first gate dielectric layer 1133a, on the upper sidewall of the first trench 112a and the surface of the epitaxial layer 111 in the first region 112a. The first gate dielectric layer 1133a covers the upper sidewall of the first trench 112a and the surface of the epitaxial layer 111 in the first region 112a. Thermal oxidation technology generally involves a chemical reaction between silicon and a gas containing oxidizing substances, such as water vapor and oxygen, at high temperature to produce a dense silicon dioxide (SiO2) film on the silicon wafer surface.
[0075] like Figure 3h As shown, a polysilicon layer is filled in a first trench 112a covered with a first gate dielectric layer 1133a and a second trench 112b covered with a second gate dielectric layer 1133b using low-pressure chemical vapor deposition. The polysilicon layer extends above the epitaxial layer 111. The polysilicon layer above the epitaxial layer 111 is removed by etch-back or chemical mechanical polishing to form a first gate conductor 118a in the first trench 112a and a second gate conductor 118b in the second trench 112b. The upper surfaces of the first gate conductor 118a and the second gate conductor 118b are flush with or slightly lower than the surface of the epitaxial layer 111.
[0076] like Figure 3i As shown, a body region 119 is formed adjacent to the first trench 112a and the second trench 112b. The body region 119 is of a second doping type, which is the opposite of the first doping type.
[0077] Using volume implantation and drive-in techniques, a first ion implantation is performed to form a volume region 119 in the first region 111a adjacent to the first trench 112a and in the second region 111b adjacent to the second trench 112b.
[0078] A second ion implantation is performed to form a source region 121 of the first doped type in the body region 119. By controlling the ion implantation parameters, such as implantation energy and dose, the desired depth and doping concentration can be achieved.
[0079] In the first region 111a, the depth of the body region 119 does not exceed the extension depth of the first gate conductor 118a in the first trench 112a. The body region 119 and the source region 121 are adjacent to the first trench 112a, and the body region 119 and the source region 121 are isolated from the first gate conductor 118a by the first gate dielectric layer 1133a. In the second region 111b, the depth of the body region 119 does not exceed the extension depth of the second gate conductor 118b in the second trench 112b. The body region 119 and the source region 121 are adjacent to the second trench 112b, and the body region 119 and the source region 121 are isolated from the second gate conductor 118b by the second gate dielectric layer 1133b.
[0080] like Figure 3j As shown, a dielectric layer 122 is formed above the source region 121 through a deposition process, and can be further chemically mechanically polished to obtain a smooth surface. The interlayer dielectric layer 122 covers the top surfaces of the source region 121, the first gate conductor 118a, and the second gate conductor 118b. The portion of the first gate dielectric layer 1133a in the first region 111a located on the upper surface of the epitaxial layer 111 and the portion of the second gate dielectric layer 1133b in the second region 111b located on the upper surface of the epitaxial layer 111 can be removed by etching after the formation of the source region 121, or it can remain there. It conforms to the interlayer dielectric layer 122 and is located above the source region 121.
[0081] Through etching and ion implantation processes, a second doped contact region 120 is formed in the body region 119. Through etching, a first conductive channel 125a is formed in the first region 111a, the second region 111b, and between the first region 111a and the second region 111b, penetrating the dielectric layer 122 and the source region 121 to reach the contact region 120. A second conductive channel 125b is formed in the second region 111b, penetrating the dielectric layer 122 to reach the second gate conductor 118b.
[0082] A source electrode 123 is formed above the dielectric layer 122. The source electrode 123 is connected to the contact region 120 via a first conductive channel 125a and to the second gate conductor 118b via a second conductive channel 125b.
[0083] A drain electrode 124 is formed on the second surface of the substrate 101 by a deposition process.
[0084] In this application, the source electrode 123, the first gate conductor 118a, the second gate conductor 118b, the first shield conductor 115a, the second shield conductor 115b, and the drain electrode 124 can be formed of conductive materials, and in one embodiment, they can be metal materials such as aluminum alloy or copper.
[0085] As described above, these embodiments of this application do not exhaustively cover all details, nor do they limit the application to merely the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of this application, thereby enabling those skilled in the art to effectively utilize this application and its modifications. This application is limited only by the claims and their full scope and equivalents.
Claims
1. A method for fabricating a trench MOSFET, comprising: A first trench and a second trench are formed extending from the upper surface of an epitaxial layer of a first doping type into its interior, wherein the epitaxial layer includes a first region and a second region, the first trench is located in the first region for forming a power MOSFET structure, and the second trench is located in the second region for forming an SBR structure; A first shielding grid dielectric layer and a first shielding conductor are formed at the lower part of the first trench, and a second shielding grid dielectric layer and a second shielding conductor are formed at the lower part of the second trench; A first interlayer dielectric layer is formed on the surfaces of the first shielding gate dielectric layer and the first shielding conductor, and a second interlayer dielectric layer is formed on the surfaces of the second shielding gate dielectric layer and the second shielding conductor. A first gate dielectric layer and a first gate conductor are formed on the upper part of the first trench, and a second gate dielectric layer and a second gate conductor are formed on the upper part of the second trench; and On the two sides adjacent to the first trench and the second trench in the epitaxial layer, a body region, a source region and a contact region are formed, wherein the source region is of a first doping type and the body region and the contact region are of a second doping type; The dielectric constant of the second gate dielectric layer located in the second trench is greater than that of the first gate dielectric layer located in the first trench.
2. The method according to claim 1, wherein, Methods for forming the second gate dielectric layer include: A first dielectric layer is formed covering the surface of the first interlayer dielectric layer in the first trench, the sidewall of the first trench, the surface of the second interlayer dielectric layer in the second trench, the sidewall of the second trench, and the upper surface of the epitaxial layer. A mask is formed, which covers the surface of the second interlayer dielectric layer in the second trench, the sidewalls of the second trench, and the surface of the epitaxial layers in the second region; The dielectric layer on the surface of the first interlayer dielectric layer, the sidewalls of the first trench, and the surface of the epitaxial layers in the first region are removed via the mask.
3. The method according to claim 2, wherein, After the second gate dielectric layer is formed, the sidewalls above the first trench and the surface of the epitaxial layer in the first region are oxidized to form the first gate dielectric layer.
4. The method according to claim 1, wherein, Following the formation of the source region, the following is also included: A dielectric layer is formed covering the first gate dielectric layer, the first gate conductor, the second gate dielectric layer, and the second gate conductor.
5. The method according to claim 4, wherein, Also includes: A first conductive channel is formed that penetrates the dielectric layer and the source region to reach the contact region, and a second conductive channel is formed that penetrates the dielectric layer to reach the second gate conductor in the second trench.
6. The method according to claim 5, wherein, Also includes: A source electrode is formed above the dielectric layer, the source electrode is connected to the contact area via the first conductive channel, and is connected to the second gate conductor in the second trench via the second conductive channel.
7. A trench MOSFET, comprising: Epitaxial layer of the first doping type; A first trench extends from the upper surface of the epitaxial layer into its interior, and the first trench is used to form a power MOSFET structure; A first shielding barrier dielectric layer is disposed in the lower part of the first trench and covers the inner surface of the lower part of the first trench; A first shielding conductor is disposed at the lower part of the first trench and is isolated from the epitaxial layer by the first shielding gate dielectric layer; The first interlayer dielectric layer is disposed on the surface of the first shielding gate dielectric layer; A first gate dielectric layer is disposed on the upper part of the first trench and covers the inner surface of the upper part of the first trench; A first gate conductor is disposed on the upper part of the first trench and isolated by the first gate dielectric layer and the epitaxial layer; A second trench extends from the upper surface of the epitaxial layer into its interior, and the second trench is used to form an SBR structure; A second shielding barrier dielectric layer is disposed in the lower part of the second trench and covers the inner surface of the lower part of the second trench; The second shielding conductor is disposed in the lower part of the second trench and is isolated from the epitaxial layer by the second shielding gate dielectric layer; The second interlayer dielectric layer is disposed on the surface of the second shielding gate dielectric layer; A second gate dielectric layer is disposed on the upper part of the second trench and covers the inner surface of the upper part of the second trench; A second gate conductor is disposed on the upper part of the second trench and is isolated by the second gate dielectric layer and the epitaxial layer; as well as The body region, source region, and contact region are located on both sides of the epitaxial layer adjacent to the first trench and the second trench, wherein the source region is of the first doping type, and the body region and the contact region are of the second doping type; Wherein, the dielectric constant of the second gate dielectric layer in the second trench is greater than that of the first gate dielectric layer in the first trench.
8. The trench MOSFET according to claim 7, wherein, The epitaxial layer includes a first region and a second region, wherein the first trench is located within the first region and the second trench is located within the second region; The gate dielectric layer includes a first gate dielectric layer and a second gate dielectric layer; The first gate dielectric layer covers the surface of the interlayer dielectric layer inside the first trench, the sidewall of the upper part of the first trench, and the upper surface of the epitaxial layer in the first region; The second gate dielectric layer covers the surface of the interlayer dielectric layer inside the second trench, the sidewalls of the upper part of the second trench, and the upper surface of the epitaxial layer in the second region.
9. The trench MOSFET according to claim 7, wherein, Also includes: A dielectric layer is located above the source region; as well as The source electrode is located above the dielectric layer; The contact region of the second doping type is located in the body region; as well as A first conductive channel penetrates the dielectric layer and the source region to reach the contact region; as well as The second conductive channel penetrates the dielectric layer to reach the second gate conductor in the second trench; The source electrode is connected to the contact area via the first conductive channel and to the second gate conductor in the second trench via the second conductive channel.
10. The trench MOSFET according to claim 7, wherein, Also includes: A substrate, wherein the epitaxial layer is located on the upper surface of the substrate; as well as The drain electrode is located on the lower surface of the substrate.
Citation Information
Patent Citations
Groove type field effect transistor structure and preparation method thereof
CN113130633A