Semiconductor device and manufacturing method thereof

Abstract

Embodiments of the present disclosure are a semiconductor device and a method of manufacturing the same, the semiconductor device including: a first channel region and a second channel region disposed over a semiconductor substrate; a gate structure having a longitudinal axis in the first direction and extending across the first channel region and the second channel region, and including an interface layer, a gate dielectric layer, and a gate electrode; first and second epitaxial features between which the first channel region and the gate structure are interposed in a second direction perpendicular to the first direction; and an isolation structure extending between the first channel region and the second channel region. The isolation structure has a first sidewall facing the first channel region, and a portion of the first sidewall between a top of the first channel region and a bottom of the first channel region is covered by a gate dielectric layer and an interface layer.

Description

Technical Field

[0001] Embodiments of this application relate to semiconductor devices and methods of manufacturing the same. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have yielded multiple generations of ICs, each featuring smaller and more complex circuitry than the previous generation. Throughout IC development, functional density (i.e., the number of interconnect devices per chip area) has generally increased, while geometry (i.e., the smallest component (or line) that can be created using manufacturing processes) has decreased. This miniaturization typically provides benefits through increased production efficiency and reduced associated costs. However, such miniaturization also increases the complexity of handling and manufacturing ICs.

[0003] Therefore, there is a need to improve the processing and manufacturing of ICs. Summary of the Invention

[0004] Some embodiments of this application provide a semiconductor device comprising: a first channel region and a second channel region disposed above a semiconductor substrate; a gate structure having a longitudinal axis in a first direction and extending across the first channel region and the second channel region, wherein the gate structure includes an interface layer, a gate dielectric layer, and a gate electrode, wherein the gate electrode comprises a Ti-based material; a first epitaxial member and a second epitaxial member, wherein the first channel region and the gate structure are located between the first epitaxial member and the second epitaxial member in a second direction perpendicular to the first direction, wherein the first epitaxial member comprises two layers comprising the same semiconductor material with different concentrations; a third epitaxial member and a fourth epitaxial member, wherein the second channel region and the gate structure are located between the third epitaxial member and the fourth epitaxial member in the second direction; and an isolation structure extending between the first channel region and the second channel region, wherein the isolation structure has a first sidewall facing the first channel region, wherein a portion of the first sidewall located between the top and bottom of the first channel region is covered by the gate dielectric layer and the interface layer.

[0005] Other embodiments of this application provide a semiconductor device including: a first channel region, a second channel region, a third channel region, and a fourth channel region disposed above a semiconductor substrate and subsequently arranged in a row in a first direction, wherein the distance between the first channel region and the second channel region and the distance between the third channel region and the fourth channel region are less than the distance between the second channel region and the third channel region; and a gate structure having a longitudinal axis in the first direction and spanning the first channel region, the second channel region, the third channel region, and the fourth channel region. The extension includes, wherein the gate structure comprises a first interface layer, a second interface layer, a gate dielectric layer, and a gate electrode, wherein the gate electrode comprises a Ti-based material; a first epitaxial component and a second epitaxial component, wherein the first channel region is located between the first epitaxial component and the second epitaxial component; a third epitaxial component and a fourth epitaxial component, wherein the second channel region is located between the third epitaxial component and the fourth epitaxial component; a fifth epitaxial component and a sixth epitaxial component, wherein the third channel region is located between the fifth epitaxial component and the sixth epitaxial component; a seventh epitaxial component and an eighth epitaxial component, wherein the fourth channel region is located between the first epitaxial component and the second epitaxial component. Between the seventh epitaxial member and the eighth epitaxial member; a first isolation structure comprising a first portion extending between the first channel region and the second channel region, a second portion extending between the first epitaxial member and the third epitaxial member, and a third portion extending between the second epitaxial member and the fourth epitaxial member, wherein the first portion of the first isolation structure is located between the second portion of the first isolation structure and the third portion of the first isolation structure; a second isolation structure comprising a first portion of the second isolation structure extending between the third channel region and the fourth channel region, a second portion extending between the fifth epitaxial member and the seventh epitaxial member, and a third portion extending between the sixth epitaxial member and the eighth epitaxial member, wherein the first portion of the second isolation structure is located between the second portion of the second isolation structure and the third portion of the second isolation structure; a first contact disposed on the first epitaxial member and electrically coupled to the first epitaxial member, wherein the conductivity of the first contact is greater than the conductivity of the first epitaxial member; and a second contact disposed on the third epitaxial member and electrically coupled to the third epitaxial member.

[0006] Further embodiments of this application provide a method for manufacturing a semiconductor device, the method comprising: forming a plurality of nanostructures disposed above a semiconductor substrate; forming a first epitaxial structure and a second epitaxial structure, interposed in a second direction perpendicular to the first direction, wherein the first epitaxial structure comprises two layers comprising the same semiconductor material having different concentrations; forming an isolation structure to divide the nanostructures into the first nanostructure and the second nanostructure, such that the first nanostructure and the second nanostructure are separated by the isolation structure in the first direction; forming a gate structure spanning the first nanostructure and the second nanostructure; and forming a first contact above the first epitaxial component and a second contact above the second epitaxial component, wherein the conductivity of the first contact is greater than the conductivity of the first epitaxial structure. Attached Figure Description

[0007] Various aspects of the embodiments of this disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0008] Figures 1 to 6 These are perspective views of various stages of manufacturing a semiconductor device according to some embodiments.

[0009] Figures 7A to 20D These are plan and cross-sectional views of various stages of manufacturing a semiconductor device according to some embodiments.

[0010] Figures 21A to 21C These are plan and cross-sectional views of intermediate stages in the manufacture of semiconductor devices according to some embodiments.

[0011] Figures 22A to 28D These are plan and cross-sectional views of intermediate stages in the manufacture of semiconductor devices according to some embodiments. Detailed Implementation

[0012] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify embodiments of this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component on or over a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of embodiments of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0013] Furthermore, for ease of description, this document may use spatial relative terms such as “below,” “under,” “lower,” “above,” “above,” “on,” “top,” and “upper” to describe the relationship between one element or component and another (or other elements or components) as shown in the figures. In addition to the orientations depicted in the figures, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0014] Embodiments of this disclosure provide a semiconductor device and a method of manufacturing the same. The semiconductor device includes a gate structure spanning one or more channel regions and source / drain epitaxial components intervening therebetween (between source / drain epitaxial components). The semiconductor device also includes an isolation wall extending through the gate structure and the source / drain components. Adjacent source / drain epitaxial components can be separated by the isolation wall, thus resolving the problem of undesirable bridging between adjacent epitaxial components. Furthermore, the formation of the isolation wall is compatible with common metal cutting processes, and therefore provides greater flexibility in circuit design.

[0015] While embodiments of this disclosure are discussed with respect to nanostructured channel FETs, such as gate-all-around (GAA) FETs, such as horizontal gate-all-around (HGAA) FETs or vertical gate-all-around (VGAA) FETs, implementations of some aspects of the embodiments of this disclosure can be used in other processes and / or other devices, such as planar FETs, FinFETs, and other suitable devices. Those skilled in the art will readily understand that other modifications are contemplated within the scope of the embodiments of this disclosure. In the case of a gate-all-around (GAA) transistor structure, the GAA transistor structure can be patterned by any suitable method. For example, the structure can be patterned using one or more photolithography processes, including dual-patterning or multi-patterning processes. Typically, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, thereby allowing the creation of patterns with a pitch, for example, smaller than that achievable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the GAA structure.

[0016] Figures 1 to 28D An exemplary process for manufacturing a semiconductor device according to embodiments of the present disclosure is illustrated. It should be understood that... Figures 1 to 28D Additional operations are provided before, during, and after the process shown, and some of the operations described below may be replaced or eliminated for additional embodiments of the method. The order of operations / processes is not limiting and may be interchanged.

[0017] Figures 1 to 20D An exemplary process for manufacturing a semiconductor device 100 according to some embodiments is shown. Figures 1 to 6This is a perspective view of an intermediate stage in the fabrication of semiconductor device 100. Semiconductor device 100 also includes a multilayer stack 102 formed over substrate 101. Substrate 101 may be a semiconductor substrate. Substrate 101 may include crystalline semiconductor materials such as, but not limited to, silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), indium antimonide (InSb), gallium phosphide (GaP), gallium antimonide (GaSb), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), gallium antimony phosphide (GaSbP), gallium antimony arsenide (GaAsSb), and indium phosphide (InP). In some embodiments, substrate 101 is a silicon-on-insulator (SOI) substrate having an insulating layer (not shown) disposed between two silicon layers for reinforcement. In one aspect, the insulating layer is an oxygen-containing layer. Substrate 101 may include various regions in substrate 101 that have been doped with impurities (e.g., dopants having p-type or n-type conductivity). Depending on the circuit design, substrate 101 may include a p-type doped well for an n-type field-effect transistor (NFET) and an n-type doped well for a p-type field-effect transistor (PFET).

[0018] The multilayer stack 102 includes alternating semiconductor layers made of different materials to facilitate the formation of nanostructured channels in multi-gate devices, such as nanostructured channel FETs. In some embodiments, the multilayer stack 102 includes a first semiconductor layer 104 and a second semiconductor layer 106 alternately stacked over a substrate 101. For example, for illustrative purposes, the multilayer stack 102 is shown as three layers including a first semiconductor layer 104 and a second semiconductor layer 106. It should be understood that any number of first semiconductor layers 104 and second semiconductor layers 106 may be included in the multilayer stack 102. In some embodiments, the first semiconductor layer 104 is formed of a first semiconductor material, and the second semiconductor layer 106 is formed of a second semiconductor material different from the first semiconductor material. The second semiconductor material may have a different etch selectivity and / or oxidation rate than the first semiconductor material. In some embodiments, either the first semiconductor material or the second semiconductor material is or includes materials such as SiGe, SiC, GeAs, GaP, InP, InAs, InSb, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, GaInAsP, combinations thereof, etc. In some embodiments, the first semiconductor material is formed of Si, and the second semiconductor material is formed of SiGe, or vice versa.

[0019] Each first semiconductor layer 104 may have a thickness ranging from about 5 nm to about 30 nm. Each second semiconductor layer 106 may have a thickness equal to, less than, or greater than the thickness of the first semiconductor layer 104. In some embodiments, each second semiconductor layer 106 has a thickness ranging from about 2 nm to about 50 nm. The first semiconductor layer 104 and the second semiconductor layer 106 are formed by any suitable deposition process, such as epitaxial deposition. For example, the epitaxial deposition of the multilayer stack 102 may be implemented by vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), chemical vapor deposition (CVD), metal-organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), and / or other suitable epitaxial growth processes.

[0020] exist Figure 2 In some embodiments, the multilayer stack 102 and substrate 101 are patterned by one or more etching processes to form semiconductor strips 108. Each semiconductor strip 108 may include a first nanostructure 110 patterned by a first semiconductor layer 104 and a second nanostructure 112 patterned by a second semiconductor layer 106. After the etching process, the substrate 101 may include a plurality of fins 114. The semiconductor strips 108 are respectively disposed above the fins 114. The term nanostructure is used herein to refer to any portion of material having a nanometer-scale or even micrometer-scale size and having an elongated shape, regardless of the cross-sectional shape of the portion. Thus, the term refers to elongated portions of material with circular and substantially circular cross-sections, as well as beam-shaped or rod-shaped portions of material including, for example, cylindrical or substantially rectangular cross-sections.

[0021] Semiconductor strips 108 can be formed by patterning a hard mask layer (not shown) on a multilayer stack 102 using a multi-patterning operation including photolithography and etching processes. The etching process can include dry etching, wet etching, and / or other suitable processes such as reactive ion etching (RIE) or neutral beam etching (NBE). The photolithography process can include: forming a photoresist layer (not shown) over the hard mask layer; exposing the photoresist layer to the pattern; performing a post-exposure baking process; and developing the photoresist layer to form a masking element including the photoresist layer. In some embodiments, patterning the photoresist layer to form the masking element can be performed using electron beam (e-beam) lithography. The etching process forms trenches 116 in unprotected areas that penetrate the hard mask layer, through the multilayer stack 102, and into the substrate 101, thereby leaving semiconductor strips 108 and fins 114. The trenches 116 extend in the X direction. In some embodiments, semiconductor strips 108 and fins 114 have a longitudinal axis in the X direction.

[0022] Semiconductor device 100 may include multiple transistor structures. A first nanostructure 110 or a portion thereof may be formed into a nanostructure channel of the transistor structure in a later manufacturing stage, while a second nanostructure 112 may be used as a sacrificial layer in a later manufacturing stage to allow the nanostructure channel to be surrounded by a gate structure. The transistor structure having a nanostructure channel may be referred to as a nanostructure transistor, nanosheet transistor, nanowire transistor, gate-all-aspect (GAA) transistor, multi-bridge-channel (MBC) transistor, or any transistor having a gate electrode surrounding the channel.

[0023] exist Figure 3 In this process, after forming the semiconductor strips 108, an insulating material 118 is formed over the substrate 101. The insulating material 118 fills the trenches 116 between adjacent semiconductor strips 108 until the semiconductor strips 108 are embedded in the insulating material 118. Then, planarization operations, such as chemical mechanical polishing (CMP) and / or etching-back methods, are performed to expose the top of the semiconductor strips 108. The insulating material 118 can be made of silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN, fluorine-doped silicate glass (FSG), a low-k dielectric material (dielectric constant less than about 3.5), or any suitable dielectric material. The insulating material 118 can be formed by any suitable method, such as flowable CVD (FCVD), low-pressure chemical vapor deposition (LPCVD), or plasma-enhanced CVD (PECVD).

[0024] exist Figure 4 In this process, insulating material 118 is recessed to form a shallow trench isolation (STI) region 120. The recessed insulating material 118 exposes portions of the semiconductor strip 108 and the substrate 101. The recessed insulating material 118 also exposes trenches 116 between adjacent semiconductor strips 108. The STI region 120 can be formed using suitable processes, such as dry etching, wet etching, or combinations thereof. The top surface of the STI region 120 may be flush with or below the top surface of the fin 114 and in contact with the fin 114.

[0025] exist Figure 5 In this embodiment, one or more dummy gate structures 126 (only one shown) are formed over a semiconductor device 100. The dummy gate structure 126 is formed over a portion of the semiconductor strip 108. Each dummy gate structure 126 may include a dummy gate dielectric 128, a dummy gate electrode 130, and an optional hard mask 132. The dummy gate dielectric 128, the dummy gate electrode 130, and the hard mask 132 can be formed by sequentially depositing a blanket layer of the dummy gate dielectric 128, the dummy gate electrode 130, and the hard mask 132, and then patterning those layers into the dummy gate structure 126. The dummy gate structure 126 may have a direction substantially perpendicular to the longitudinal direction of the semiconductor strip 108 (e.g., ...). Figure 5 The longitudinal direction of the X direction (e.g., the X direction in the equation). Figure 5 (in the Y direction). The dummy gate structure 126 can be placed on the STI region 120 and span over one or more semiconductor strips 108.

[0026] The dummy gate dielectric 128 may include one or more dielectric material layers, such as deposited oxide-based materials (e.g., silicon oxide) or materials oxidized by the substrate 101. The dummy gate electrode 130 may include silicon, such as polycrystalline silicon or amorphous silicon. The hard mask 132 may include one or more dielectric layers. For example, the hard mask 132 may be a combination of oxide layers and nitride layers.

[0027] Then, a gate spacer 134 is formed on the sidewall of the dummy gate structure 126. The gate spacer 134 can be formed by conformally depositing one or more layers for the gate spacer 134 and anisotropically etching (e.g., RIE) one or more layers. Materials such as silicon nitride (SiN), silicon oxide (SiO), silicon carbide (SiC), and silicon oxide (SiO2) are used. x Dielectric materials such as silicon carbonitride (SiCN), silicon oxynitride (SiON), silicon carbonitride (SiOCN), and combinations thereof can be used for gate spacers 134.

[0028] exist Figure 6 In some embodiments, a first opening 138 is formed in the semiconductor strip 108, fin 114, and substrate 101. The first opening 138 can be formed by removing at least a portion of the semiconductor strip 108 and substrate 101 not protected by the gate spacer 134 and dummy gate structure 126. The remaining portion of the semiconductor strip 108 below the dummy gate structure 126 can form a nanostructure stack 108A. Each of the nanostructure stacks 108A can be located between the first openings 138. Therefore, the first openings 138 can be formed in the X direction between adjacent dummy gate structures 126, such as... Figure 6 As shown (or Figure 7D (See the cross-sectional view shown). The first opening 138 may be recessed below the top surface of the STI region 120, but it may also be recessed to be flush with or above the top surface of the STI region 120. The first opening 138 may be formed by an etching process, either isotropic or anisotropic, and the etching process may be selective relative to one or more crystal planes of the substrate 101. The etching process may be dry etching (such as RIE, NBE, etc.) or wet etching. The etchant from the etching process may include fluorocarbons or chlorocarbons.

[0029] The process of manufacturing semiconductor device 100 is in Figures 7A to 20DThe process will continue and will be shown in the plan and section views. Figure 7A It is a plan view of semiconductor device 100, and Figure 7B , Figure 7C and Figure 7D They are respectively along Figure 6 Sections AA, BB and Figure 6 A cross-sectional view of semiconductor device 100 taken along the direction of section CC. Throughout the description (including semiconductor devices 100, 200, and 300), figures with reference to "A" are plan views of the semiconductor devices; figures with reference to "B" are referenced from [reference missing]. Figure 6 or Figure 7A Section AA is shown in the figure; figures with drawing numbers including "C" are referenced from [source missing]. Figure 6 or Figure 7A The section BB shown; and figures with figure numbers including "D" are referenced from [source missing]. Figure 6 or Figure 7A The cross-section CC is shown. For clarity, source / drain components, dielectric (or insulating) layers, or insulating regions may not be shown in these planar diagrams of semiconductor devices. Although Figure 6 A dummy gate structure 126 and two semiconductor strips 108 are shown, but it should be understood that the semiconductor device 100 may include more dummy gate structures 126 and more semiconductor strips 108. Figure 7A In the middle, the active region 100a can be surrounded by the STI region 120 ( Figure 7A (Not shown in the image). For example... Figure 7B and Figure 7C As shown, a pseudo-gate structure 126 with a longitudinal axis extending in the Y direction is provided, and each pseudo-gate structure 126 may extend across one or more nanostructure stacks 108A in one or more active regions 100a. Figure 7D In some embodiments, a first opening 138 extends through the nanostructure stack 108A and into the substrate 101. The first opening 138 may be located between opposing gate spacers 134 and expose the fin 114 / substrate 101.

[0030] Next step, refer to Figures 8A to 8DAccording to some embodiments, the second nanostructure 112 is etched to form the second opening 142. That is, the second opening 142 can be a space occupied by the second nanostructure 112, including the space between vertically adjacent first nanostructures 110 and the space between the bottommost first nanostructure 110 and the fin 114 / substrate 101. When using an etchant that is selective for etching the second semiconductor material of the second nanostructure 112, the first nanostructure 110 and the substrate 101 remain relatively unetched. In embodiments where the second semiconductor material includes, for example, SiGe, an etching process is used that employs a hydroxide etchant, such as tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), etc.

[0031] exist Figures 9A to 9D In some embodiments, an insulating nanostructure 144 is formed in the second opening 142. The insulating nanostructure 144 may comprise an oxide-containing material, such as silicon oxide, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric material, or any suitable dielectric material. In some embodiments, the insulating nanostructure 144 comprises materials similar to those of the STI region 120. The formation of the insulating nanostructure 144 may include depositing an insulating layer in the first opening 138 and the second opening 142, such as by FCVD, ALD, PECVD, LPCVD, combinations thereof, etc. The insulating layer may be a conformal layer in the first opening 138. Furthermore, given the dimensional difference between the first opening 138 and the second opening 142, the insulating layer may substantially or completely fill the second opening 142. Subsequently, an etching process is performed to remove the insulating layer in the first opening 138 and to laterally recess the insulating layer in the second opening 142. The etching process may use an etchant selective for etching the insulating layer, and the first nanostructure 110 and the substrate 101 may remain relatively unetched. In some embodiments, an etching process or another etching process causes the insulating layer to be laterally recessed from the first opening 138. Internal spacers 150 can be formed in the laterally recessed areas created by the etching process and on the sidewalls of the insulating nanostructure 144. The internal spacers 150 may include insulating materials such as SiO, SiOC, SiC, SiN, SiON, or combinations thereof. The internal spacers 150 can serve as isolation components between the subsequently formed gate structure and the epitaxial structure.

[0032] exist Figures 10A to 10DIn some embodiments, an epitaxial structure 158 is formed in a first opening 138. The epitaxial structure 158 may be a source / drain region of the semiconductor device 100, and may also be referred to as an epitaxial source / drain structure 158. In embodiments of this disclosure, the source region and drain region are used interchangeably, and their structures are substantially the same. Furthermore, the source / drain region may refer to either a source or a drain, individually or collectively, depending on the context. The epitaxial structure 158 can be formed using epitaxial growth methods such as CVD, ALD, MBE, combinations thereof. In some embodiments, impurities may be doped in situ when the epitaxial structure 158 is epitaxially deposited. The epitaxial structure 158 may have an area of ​​approximately 1 × 10⁻⁶. 19 atoms / cm 3 1×10 21 atoms / cm 3 The impurity concentration between [variable values]. The epitaxial structure 158 can apply stress to the first nanostructure 110, thereby improving device performance. The epitaxial structure 158 can have small facets. For example... Figure 10C As shown, according to some embodiments, an extensional structure 158 includes at least two upwardly inclined surfaces opposite each other and two downwardly inclined surfaces opposite each other.

[0033] In some embodiments, the epitaxial structure 158 includes more than one epitaxial semiconductor layer. For example, each of the epitaxial structures 158 may include a first semiconductor material layer, a second semiconductor material layer, and a third semiconductor material layer. Any number of semiconductor material layers can be used for the epitaxial structure 158. Each of the first, second, and third semiconductor material layers may be formed of the same or different semiconductor materials and may be doped to different dopant concentrations. In embodiments, the first, second, and third semiconductor material layers include the same semiconductor material with different concentrations. For example, in an embodiment where the semiconductor material is SiGe, the Ge concentrations in the first, second, and third semiconductor material layers are different. In some embodiments, the first semiconductor material layer may have a dopant concentration less than that of the second semiconductor material layer and greater than that of the third semiconductor material layer. In embodiments where the epitaxial structure 158 includes three semiconductor material layers, a first semiconductor material layer may be deposited, a second semiconductor material layer may be deposited over the first semiconductor material layer, and a third semiconductor material layer may be deposited over the second semiconductor material layer.

[0034] The epitaxial structure 158 can be an n-type epitaxial structure for an n-type FET (e.g., NMOS) and a p-type epitaxial structure for a p-type FET (e.g., PMOS). In some embodiments, the n-type epitaxial structure for an n-type FET includes Si, SiP, SiC, SiCP, and SiAs, and the p-type epitaxial structure for a p-type FET includes Si, SiGe, and Ge. For a p-type FET, p-type impurities, such as boron, boron fluoride, indium, etc., can be included in the p-type epitaxial structure 158. For an n-type FET, n-type impurities, such as phosphorus, arsenic, antimony, etc., can be included in the n-type epitaxial structure 158.

[0035] exist Figures 11A to 11D In some embodiments, a contact etch stop layer (CESL) 160 is conformally formed on the exposed surface of the semiconductor device 100. CESL 160 covers the sidewalls of the STI region 120, the epitaxial structure 158, and the gate spacer 134. CESL 160 may include oxygen-containing or nitrogen-containing materials, such as silicon nitride, silicon carbonitride, silicon oxynitride, silicon oxycarbide, combinations thereof, etc. CESL 160 can be formed by CVD, PECVD, ALD, or any suitable deposition technique. Next, a first interlayer dielectric (ILD) layer 162 is formed on the CESL 160 above the semiconductor device 100. The material used for the first ILD layer 162 may include compounds including Si, O, C, and / or H, such as silicon oxide, SiOCH, SiOC, PSG, BSG, BPSG, and combinations thereof. Organic materials such as polymers may also be used for the first ILD layer 162. The first ILD layer 162 can be deposited by FCVD, PECVD, or other suitable deposition techniques. In some embodiments, after depositing the first ILD layer 162, a thermal process is performed to cure the first ILD layer 162. After curing, a recessing step, such as an etching step, is performed to recess the first ILD layer 162 below the top surface of the epitaxial structure 158. Therefore, portions of the CESL 160 (including the portion of the CESL 160 located on the upper inclined surface of the epitaxial structure 158) can be exposed from the first ILD layer 162.

[0036] exist Figures 12A to 12D In some embodiments, a dielectric layer 164 is formed over the first ILD layer 162 and the epitaxial structure 158, covering the first ILD layer 162 and the epitaxial structure 158. The dielectric layer 164 may include silicon nitride, silicon oxynitride, or other suitable materials. The dielectric layer 164 may be formed by CVD, PECVD, LPCVD, or other suitable deposition processes. In some embodiments, a planarization process such as CMP may be performed to remove portions of the dielectric layer 164 until the dummy gate structure 126 is exposed.

[0037] exist Figures 13A to 13D In some embodiments, isolation walls 165 (or also referred to as isolation structures) are formed to cleave the epitaxial structure 158, the dummy gate structure 126, and the dielectric layer 164. Each of the isolation walls 165 may have a direction substantially perpendicular to the longitudinal axis of the dummy gate structure 126 (e.g., Figure 6 The longitudinal axis (extending in the X direction) is used. For example, the isolation wall 165 can extend through the dummy gate structure 126 and cut the dummy gate structure 126 into multiple segments. The isolation wall 165 can extend vertically from the top surface of the dummy gate structure 126, through the first nanostructure 110 and the insulating nanostructure 144, into the fin 104 / substrate 101. Therefore, as Figures 13A to 13C As shown, a partition wall 165 may include a plurality of alternating first portions and a plurality of second portions. Each first portion of the partition wall 165 will house a nanostructure stack 108A (see Figure 108A). Figure 12B The epitaxial structure 158 is divided into two separate nanostructure stacks 108B, and each second portion of the isolation wall 165 divides one epitaxial structure 158 into two separate epitaxial portions 158'. In some embodiments, the outer sidewalls (including inclined surfaces) of the two epitaxial portions 158' may be substantially symmetrical with respect to the isolation wall 165. For example, in... Figures 13A to 13D In the illustrated embodiment, a first nanostructure 110 in one nanostructure stack 108A is separated into a first channel region 110A and a second channel region 110B by an isolation wall 165, and a first nanostructure 110 in another nanostructure stack 108A is separated into a third channel region 110C and a fourth channel region 110D by another isolation wall 165. Therefore, the distance between the first channel region 110A and the second channel region 110B, and the distance between the third channel region 110C and the fourth channel region 110D, are determined by the width of the isolation wall 165, which is smaller than the distance between the second channel region 110B and the third channel region 110C. The isolation wall 165 may have a width of approximately 10 nm to approximately 30 nm.

[0038] In some embodiments, forming the isolation wall 165 includes: performing an etching process to form an opening corresponding to the shape of the isolation wall 165; and then depositing a dielectric layer into the opening. The etching process may include anisotropic etching processes, such as RIE or NBE. Although Figure 13B and Figure 13CThe isolation wall 165 is shown to have straight sidewalls, but it can also have curved or non-linear sidewalls. For example, the width of the isolation wall 165 can decrease towards the bottom. Optionally, the sidewalls of a first portion of the isolation wall 165 can have a first slope relative to the vertical axis (e.g., the portion adjacent to the first nanostructure 110), and the sidewalls of a second portion of the isolation wall 165 can have a second slope relative to the vertical axis that differs from the first slope (the portion adjacent to the insulating nanostructure 144), because etching the material of the first channel regions 110A to the fourth channel regions 110D and etching the material of the insulating nanostructure 144 can produce different etching behaviors. Each of the isolation walls 165 can include a pad 165A and an isolation filler 165B. The pad 165A can include a dielectric material, such as silicon oxide, silicon oxycarbide, silicon oxynitride, low-k dielectrics, combinations thereof, etc. The pad 165A can have a thickness of about 1 nm to about 5 nm. The isolation filler 165B may include dielectric materials such as SiN, SiON, SiC, SiCN, combinations thereof, etc. In some embodiments, a planarization process such as CMP may be performed after the deposition of the pad 165A and the isolation filler 165B to remove excess material from the pad 165A and the isolation filler 165B above the top surface of the dummy gate structure 126. In some embodiments, the planarization process also removes portions of the dummy gate structure 126 and the dielectric layer 164, if desired. In embodiments, each of the isolation walls 165 may extend partially or completely through the fin 114.

[0039] exist Figures 14A to 14D In some embodiments, the insulating nanostructure 144, the dummy gate electrode 130, and the dummy gate dielectric 128 are removed by one or more etching processes to form the third opening 166. In some embodiments, a portion of the pad 165A of the isolation wall 165 is also removed during the etching process. For example, as... Figure 14B As shown, according to some embodiments, the portion of pad 165A above the fin 114 in the third opening 166 can be removed, such that the top surface of pad 165A is flush with the top of the fin 114 / substrate 101. In other embodiments, the top surface of pad 165A is lower than the top of the fin 114 / substrate 101. In some embodiments, the etching process includes an isotropic etching process, such as wet etching comprising an etchant that selectively etches the insulating nanostructure 144, the dummy gate electrode 130, the dummy gate dielectric 128, and the isolation wall 165 at a rate faster than the first ILD layer 162 or the gate spacer 134.

[0040] exist Figures 15A to 15DIn some embodiments, an interface layer 167, a gate dielectric layer 168, and a gate electrode 170 are subsequently formed in a third opening 166. The interface layer 167 and the gate dielectric layer 168 are conformally formed on the exposed surfaces of the first nanostructure 110, the isolation wall 165, and the fin 114 / substrate 101. The interface layer 167 may comprise silicon oxide, silicon oxynitride, or a combination thereof. In some embodiments, each of the first nanostructures 110 is enclosed by the interface layer 167. In some embodiments, an interface layer 167 includes a thick portion 167A disposed on an inner sidewall of a first nanostructure 110 (e.g., the sidewall of the first nanostructure 110 facing the isolation wall 165) and a thin portion 167B conformally disposed on the top, bottom, and outer sidewalls of adjacent first nanostructures 110 (e.g., the sidewall of the first nanostructure 110 opposite the isolation wall 156). In one embodiment, the thin portion 167B of the interface layer 167 also extends to the inner sidewall of the first nanostructure 110, so the inner sidewall of the first nanostructure 110 is covered by both the thick portion 167A and the thin portion 167B of the interface layer 167. The thick portion 167A of the interface layer 167 may have a vertical thickness at least twice that of the thin portion 167B (e.g., the thickness of the interface layer 167 on the top surface of the first nanostructure 110). In some embodiments, the thick portion 167A of the interface layer 167 may have a horizontal thickness at least twice that of the thin portion 167B of the interface layer 167 (e.g., about 1 nm to about 5 nm). In some embodiments, the vertical thickness of one thick portion 167A of the interface layer is less than the vertical thickness of the adjacent first nanostructure 110.

[0041] A gate dielectric layer 168 may be formed over the thin portion 167B of the interface layer 167, the sidewalls of the isolation wall 165, and the top and sidewalls of the fin 114 / substrate 101. In an embodiment, the gate dielectric layer 168 also extends into the gap between the first nanostructure 110 and the isolation wall 165, and contacts the top and bottom surfaces of the thick portion 167A of the interface layer 167. Therefore, in such a way... Figure 15BIn the cross-sectional view shown, the first nanostructure 110 is completely enclosed by the interface layer 167 and partially enclosed by the gate dielectric layer 168. In an embodiment, the portion of the isolation wall 165 located between the top and bottom of the channel region (e.g., 110A-110D) is covered by the interface layer 167 and the gate dielectric layer 168. In some embodiments, the gate dielectric layer 168 comprises one or more layers of dielectric material, such as silicon oxide, silicon nitride, or a high-k dielectric material (e.g., dielectric constant > 10), other suitable dielectric materials, and / or combinations thereof. Examples of high-k dielectric materials include HfO, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO, AlO, TiO, other suitable high-k dielectric materials, and / or combinations thereof. The gate dielectric layer 168 may be formed by CVD, ALD, or any suitable deposition technique.

[0042] Gate electrodes 170 are deposited over gate dielectric layer 168 and fill the remainder of third opening 166. Gate electrodes 170 may comprise metal-containing materials such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multilayers thereof. In some embodiments, gate electrodes 170 comprise at least a Ti-based material. Although in Figure 15B A single-layer gate electrode 170 is shown, but the gate electrode 170 may include any number of pad layers, any number of power function adjustment layers, and filler material. The gate electrode 170 may be formed by CVD, ALD, electroplating, or other suitable deposition techniques. After filling the third opening 166, excess material of the gate dielectric layer 168 and the gate electrode 170 above the top surface of the dielectric layer 164 is removed by a planarization process (such as CMP) until the top surface of the dielectric layer 164 is exposed. Thus, the remaining portion of the gate electrode 170 and the gate dielectric layer 168 forms an alternative gate structure of the semiconductor device 100. The gate electrode 170 and the gate dielectric layer 168 may be collectively referred to as gate structure 172. Gate structure 172 may surround a channel region of the semiconductor device 100 (e.g., a first channel region 110A to a fourth channel region 110D formed by a first nanostructure 110).

[0043] like Figures 16A to 16DAs further shown, according to some embodiments, the opening 174 is formed by partially removing one or more of the isolation walls 165. A mask with a pattern defining the shape of the opening 174 is provided on the gate structure 172 and the dielectric layer 164, and the pattern may expose one or more isolation walls 165 that are intended to be partially removed. The opening 174 may extend from the top surface of the gate electrode 170 to a level above the first nanostructure 110. That is, the subsequently deposited conductive material may have a gap with the first nanostructure 110 to avoid forming a short circuit with the first nanostructure 110. The mask may be removed after the opening 174 is formed. In some embodiments, the opening 174 may have a width in the Y direction that is substantially equal to or greater than the width of the isolation wall 165.

[0044] exist Figures 17A to 17D In some embodiments, a conductive component 176 is formed in the opening 174. In some embodiments, the conductive component 176 may comprise a material that is the same as or different from the material of the gate electrode 170. The conductive component 176 may comprise a conductive material, such as Ru, W, Co, Cu, or other suitable metal. The formation of the conductive component 176 may comprise depositing one or more layers of conductive material in the opening 174 and on the top surface of the gate structure 172. Thereafter, a planarization process such as CMP may be performed to remove excess portions of the conductive material above the top surface of the gate structure 172. Thus, the conductive component 176 is formed in the opening 174 and may have a top surface flush with the gate structure 172 and the dielectric layer 164, and a bottom surface higher than the top surface of the topmost one of the first nanostructures 110 (i.e., the top of the channel region). With the formation of the conductive component 176 in the opening 174, some segments of the gate electrode 170 electrically isolated by the isolation wall 165 may be electrically connected via the conductive component 176. Therefore, some sections of the gate electrode 170 can be electrically connected within the layer of the gate electrode 170 without relying on upper-level interconnects, thereby providing improved density and / or flexibility for wiring. For example, with the formation of conductive component 176, second channel region 110B, third channel region 110C, and fourth channel region 110D (see...) Figure 13B It can be operated together with the section of the gate electrode 170 electrically connected by the conductive component 176 (collectively referred to as gate electrode 170A).

[0045] exist Figures 18A to 18DIn some embodiments, the portion of the isolation wall 165 not covered by the conductive component 176 is removed and filled with a high-k material to form an isolation cap 180. For example, the isolation cap 180 has a longitudinal axis along the X direction. In some embodiments, the isolation cap 180 may extend over and cover the first and second portions of the isolation wall 165. The isolation cap 180 may include a material that is etch-selective to the dielectric layer 164. The isolation cap 180 may include a high-k material (e.g., dielectric constant > 10). The isolation cap 180 may include the same material as the gate dielectric layer 168, but in some embodiments, their materials may be different. Forming the isolation cap 180 may include performing an etching process (without forming a mask) to remove the exposed isolation. The isolation wall 165 may be partially removed by a dry etching process such as RIE or NBE, where the etching depth is controlled by using etching time. In some embodiments, the isolation cap 180 is designed to have a bottom surface higher than the top surface of the topmost first nanostructure 110 (i.e., the top of the channel region) to avoid damaging the first nanostructure 110. On the other hand, the bottom surface of the isolation cap 180 can be flush with or lower than the top surface of the epitaxial member 158'. The isolation cap 180 can have a width equal to or greater than the width of the isolation wall 165 in the Y direction. In an example, the isolation cap 180 has a height of about 1 nm to about 19 nm. The isolation cap 180 can be formed by a deposition process such as CVD, and then planarized to remove excess material from the isolation cap 180 above the top surface of the gate electrode 170. Therefore, the isolation cap 180 can have a top surface flush with the top surface of the gate electrode 170.

[0046] In some embodiments, an optional dicing metal gate process is implemented to form the isolation structure 184, according to some examples. The dicing metal gate process may include etching one or more gate structures 172 to form a trench extending in the X direction, and then filling the trench with the isolation structure 184. In some embodiments, the isolation structure 184 may include silicon nitride, silicon oxide, silicon oxynitride, or a combination thereof. For example, the isolation structure 184 may have the same or similar material as the first ILD layer 162 or dielectric layer 164. The optional dicing metal gate process and the isolation structure 184 can provide flexibility in circuit design.

[0047] exist Figures 19A to 19DIn some embodiments, source / drain contacts 190 are formed in dielectric layer 164. Forming the source / drain contacts 190 may include: forming openings to expose epitaxial components by etching dielectric layer 164 and CESL 160; filling the openings with conductive material; and removing the conductive material above dielectric layer 164 and isolation cap 180 by a planarization process such as CMP. In some embodiments, isolation cap 180 serves as a mask when etching dielectric layer 164 and CESL 160, and source / drain contacts 190 may be formed in a self-aligned manner. For example, a first source / drain contact 190A disposed on one epitaxial component 158' and a second source / drain contact 190B disposed on another epitaxial component 158' may be isolated by isolation wall 165. In some embodiments, the opening for receiving the first source / drain contact 190A and the opening for receiving the second source / drain contact 190B may be created by the same etching process. Therefore, the inclined sidewalls of the first source / drain contact 190A and the second source / drain contact 190B can be symmetrical with respect to the isolation wall 165.

[0048] exist Figures 20A to 20D In some embodiments, an upper layer contact 192 and a second ILD layer 196 are formed above the source / drain contact 190 and the dielectric layer 164. The upper layer contact 192 may be disposed on and electrically connected to the corresponding source / drain contact 190 and gate electrode 170. In some embodiments, the upper layer contact 192 is allowed to overlap with the isolation cap 180, thereby reducing photolithography and design requirements and increasing the process window.

[0049] Because of the isolation wall 165, a relatively large epitaxial structure 158 can be grown, and then separated into epitaxial structures 158 or epitaxial parts 158' with relatively small dimensions. This approach helps prevent or reduce unwanted bridging between adjacent source / drain epitaxial parts 158', a problem that can occur when directly growing source / drain epitaxial parts 158'. Furthermore, the isolation wall 165 can cleave the gate structure 172 into multiple segments and provides similar functionality to the isolation structure 184 formed by a diced metal gate process. The isolation wall 165 is compatible with the diced metal gate process and therefore provides greater process and design flexibility. Additionally, etching the dummy gate structure 126 used to form the isolation wall 165 may be easier to control than etching the metal gate electrode 170. Therefore, the isolation wall 165 can provide substantially vertical sidewalls. While the sidewalls of gate structure 172 can be self-aligned with the substantially perpendicular sidewalls of isolation wall 165, the process window separating gate structures 172 can be increased, especially when the allowable distance between adjacent gate structures 172 is small in advanced manufacturing nodes (e.g., less than about 30 nm in the Y direction). In some embodiments, along with the formation of isolation wall 165 and isolation cap 180, source / drain contacts 190 can also be formed in a self-aligned manner on the corresponding epitaxial portion 158'.

[0050] Figures 21A to 21C Cross-sectional and plan views of various stages of manufacturing a semiconductor device 200 according to some embodiments are shown. Semiconductor device 200 is similar to semiconductor device 100, and at least one of the conductive members 276 can be disposed in the source / drain region when it is necessary to combine epitaxial components 158'. Therefore, some of adjacent source / drain contacts 290 can be separated by conductive members 276. Adjacent source / drain contacts 290 and conductive members 276 can collectively form a single contact structure electrically connected to two adjacent epitaxial components 158' isolated by isolation wall 165.

[0051] Figures 22A to 28D Cross-sectional and plan views of various stages of manufacturing a semiconductor device 300 according to some embodiments are shown. The semiconductor device 300 is similar to the semiconductor device 100. Figures 22A to 22D The process for manufacturing the semiconductor device 300 shown assumes that the previously implemented steps are true. Figures 1 to 12D The processing is shown above. Therefore, refer to the above. Figures 12A to 12D After the discussion, processing can proceed. Figures 22A to 22D .

[0052] exist Figures 22A to 22DIn this process, an isolation wall 365 (or also referred to as an isolation structure) is formed to cleave the dummy gate structure 126 and the dielectric layer 164. Isolation wall 365 is similar to isolation wall 165 except for its length in the X direction. For example, isolation wall 365 may comprise the same material as isolation wall 165 and may be formed using methods similar to those used to form isolation wall 165. Isolation wall 365 may also comprise a pad 365A similar to pad 165A and an isolation filler 365B similar to isolation filler 165B. Isolation wall 365 may have the same length in the X direction as the width of dummy gate structure 126, or may be slightly wider in the X direction than the width of dummy gate structure 126. Therefore, the epitaxial structure 158 is not separated by isolation wall 365. Figure 22B As shown, a partition wall 365 can cut a nanostructure stack 108A into two nanostructure stacks. For example, in... Figures 22A to 22D In the embodiment shown, one nanostructure stack 108A is divided into two nanostructure stacks 108B, each comprising a first channel region 110A and a second channel region 110B separated by an isolation wall 365, and another nanostructure stack 108A is divided into two nanostructure stacks 108B, each comprising a third channel region 110C and a fourth channel region 110D separated by another isolation wall 365.

[0053] exist Figures 23A to 23D In China, implement similar Figures 14A to 15D The process involves forming an interface layer 167, a gate dielectric layer 168, and a gate electrode 170. For example... Figures 23A to 23D The resulting structure shown is similar to that of... Figures 15A to 15D The structure shown is such that, except that the isolation wall 365 does not extend into the source / drain region, the epitaxial structure 158 is not cut by the isolation wall.

[0054] exist Figures 24A to 24D In some embodiments, the upper portion of the isolation wall 365 is replaced with a conductive component 376. Forming the conductive component 376 may include: etching the upper portion of the isolation wall 365 to form an opening in the gate electrode 170; and filling the opening with a conductive material to form the conductive component 376. Excess conductive material above the gate electrode 170 can be removed by a planarization process such as CMP. In embodiments, the etching process for etching the isolation wall 365 includes dry etching such as RIE or NBE, and a mask may be provided on the gate electrode 170 and the dielectric layer 164 prior to etching. In some embodiments, such as Figure 24B As shown, the opening has a length in the Y direction equal to or greater than the length of the partition wall 365 (see...). Figure 7ATherefore, the subsequently formed conductive component 376 may have a length in the Y direction equal to or greater than the length of the isolation wall 365. In an embodiment, the length of the conductive component 376 in the Y direction may be approximately 1.2 to approximately 1.8 times the length of the isolation wall 365.

[0055] Next step, in Figures 25A to 25D In some embodiments, a partition wall 381 is formed. The partition wall 381 may have a longitudinal axis extending along the X direction (see...). Figure 7A For example, an isolation wall 381 may extend through the epitaxial structure 158, such as an isolation wall 381 separating an epitaxial structure 158 into two separate epitaxial parts 158'. The isolation wall 381 may be or comprise the same material as the isolation filler 365B, such as SiN, SiON, SiC, SiCN, SiOCN, or combinations thereof. In some embodiments, the isolation wall 381 may have a bottom surface flush with or shallower than the bottom surface of the isolation wall 365. In some embodiments, the formation of the isolation wall 381 may include one or more etching processes. The etching process may involve etching the dielectric layer 164, CESL 160, epitaxial structure 158, and fin 114 with a mask disposed on the dielectric layer 164 and gate electrode 170 provided prior to the etching process. A suitable insulating material is then filled into the opening created by the etching process to form the isolation wall 381. Excess insulating material above the top surfaces of the gate electrode 170 and dielectric layer 164 is removed, allowing the isolation wall 381 to have a top surface flush with the top surfaces of the gate electrode 170 and dielectric layer 164. Isolation walls 381 and 365 can collectively form an isolation wall similar to isolation wall 165 as shown in semiconductor device 100, with isolation wall 365 corresponding to a first portion of isolation wall 165 and isolation wall 381 corresponding to a second portion of isolation wall 365. Therefore, the isolation wall composed of isolation walls 365 and 381 in semiconductor device 300 can provide similar functionality and advantages to isolation wall 165 in semiconductor device 100. In some embodiments, an optional metal-cutting process to cut the metal gate can be performed by one or more etching processes before or after forming isolation wall 381. A suitable insulating material is then filled into the opening created by the etching process to form isolation structure 184.

[0056] Next step, in Figures 26A to 26D In some embodiments, some of the conductive components 376 are replaced with isolation caps 382. With the formation of isolation caps 382, ​​some of the gate electrodes 170 can be electrically isolated, and their underlying channel regions can be independently controlled by those gate electrodes 170. For example, in Figure 26BIn this system, the first channel region 110A, the second channel region 110B, the third channel region 110C, and the fourth channel region 110D (see...) can be controlled independently. Figure 13B It can be operated together with the section of the gate electrode 170 electrically connected by the conductive member 376 (collectively referred to as gate electrode 370A). The conductive member 376 may comprise the same material as the conductive member 176 and is formed by a method similar to those used to form the conductive member 176.

[0057] Next step, in Figures 27A to 27D In some embodiments, source / drain contacts 190 are formed in dielectric layer 164. Forming the source / drain contacts 190 may include: forming openings to expose epitaxial components by etching dielectric layer 164 and CESL 160; filling the openings with conductive material; and removing the conductive material over dielectric layer 164 and isolation wall 381 by a planarization process such as CMP. In some embodiments, isolation wall 381 acts as a mask when etching dielectric layer 164 and CESL 160, and the source / drain contacts 190 may be formed in a self-aligned manner. For example, a first source / drain contact 190A disposed on one epitaxial component 158' and a second source / drain contact 190B disposed on another epitaxial component 158' may be isolated by isolation wall 381. In some embodiments, the opening for receiving the first source / drain contact 190A and the opening for receiving the second source / drain contact 190B may be created by the same etching process. Therefore, the inclined sidewalls of the first source / drain contact 190A and the second source / drain contact 190B can be symmetrical with respect to the isolation wall 381.

[0058] exist Figures 28A to 28D In some embodiments, an upper layer contact 192 and a second ILD layer 196 are formed above the source / drain contact 190 and the dielectric layer 164. The upper layer contact 192 may be disposed on and electrically connected to the corresponding source / drain contact 190 and gate electrode 170. In some embodiments, the upper layer contact 192 is allowed to overlap with the isolation wall 381, thereby reducing photolithography and design requirements and increasing the process window.

[0059] Because of the isolation wall 381, a relatively large source / drain epitaxial structure 158 can be grown, and then the source / drain epitaxial components 158' are separated. This approach helps prevent or reduce unwanted bridging between adjacent source / drain epitaxial components 158', a problem that can occur when directly growing source / drain epitaxial components 158'. Furthermore, the isolation wall 365 can cleave the gate structure 172 into multiple segments and provides similar functionality to the isolation structure 184 formed by a diced metal gate process. Isolation walls 365 and 381 are compatible with diced metal gate processes, and therefore offer greater process and design flexibility. Moreover, etching the dummy gate structure 126 used to form the isolation wall 365 may be easier to control than etching the metal gate electrode 170. Therefore, the isolation wall 365 can provide substantially vertical sidewalls. While the sidewalls of gate structure 172 can be self-aligned with the substantially perpendicular sidewalls of isolation wall 365, the process window separating gate structures 172 can be increased, especially when the allowable distance between adjacent gate structures 172 is small in advanced manufacturing nodes (e.g., less than about 30 nm in the Y direction). In some embodiments, forming isolation wall 381 may also allow source / drain contacts 190 to be formed in a self-aligned manner on the respective epitaxial portion 158'.

[0060] Embodiments of this disclosure provide a semiconductor device and a method of manufacturing the same. The semiconductor device includes a gate structure spanning one or more channel regions and source / drain epitaxial components interposed therebetween. The semiconductor device also includes an isolation wall extending through the gate structure and the source / drain components. Adjacent source / drain epitaxial components can be separated by the isolation wall, thus resolving the problem of undesirable bridging between adjacent epitaxial components. Furthermore, the formation of the isolation wall is compatible with common metal cutting processes, and therefore provides greater flexibility in circuit design.

[0061] The embodiment is a semiconductor device. The semiconductor device includes: a first channel region and a second channel region disposed above a semiconductor substrate; a gate structure having a longitudinal axis in a first direction and extending across the first and second channel regions, wherein the gate structure includes an interface layer, a gate dielectric layer, and a gate electrode, wherein the gate electrode includes a Ti-based material; a first epitaxial member and a second epitaxial member, wherein in a second direction perpendicular to the first direction, the first channel region and the gate structure are located between the first epitaxial member and the second epitaxial member, wherein the first epitaxial member includes two layers comprising the same semiconductor material with different concentrations; a third epitaxial member and a fourth epitaxial member, wherein in the second direction, the second channel region and the gate structure are located between the third epitaxial member and the fourth epitaxial member; and an isolation structure extending between the first and second channel regions, wherein the isolation structure has a first sidewall facing the first channel region, wherein a portion of the first sidewall located between the top and bottom of the first channel region is covered by the gate dielectric layer and the interface layer. In one embodiment, the isolation structure extends along a second direction and between the first and second epitaxial members and between the third and fourth epitaxial members. In another embodiment, the semiconductor device further includes an isolation cap disposed above the isolation structure, wherein the isolation cap has a longitudinal axis extending along the second direction. In another embodiment, the isolation cap extends at least along the second direction through the gate electrode. In another embodiment, the isolation cap has a top surface flush with the top surface of the gate electrode. In another embodiment, the first channel region includes a plurality of vertically stacked nanostructures, each of which is encapsulated by an interface layer. In another embodiment, each of the nanostructures is partially encapsulated by a gate dielectric layer. In another embodiment, the interface layer has a first portion disposed on a first side of one of the nanostructures and a second portion disposed on a second side of one of the nanostructures, wherein the second side is opposite to the first side and closer to the isolation structure than the first side, wherein the first portion has a first thickness in the horizontal direction, and the second portion of the interface layer has a second thickness in the horizontal direction that is thicker than the first thickness.

[0062] Another embodiment is a semiconductor device. The semiconductor device includes: a first channel region, a second channel region, a third channel region, and a fourth channel region disposed above a semiconductor substrate and subsequently arranged in a row in a first direction, wherein the distance between the first channel region and the second channel region, and the distance between the third channel region and the fourth channel region, is less than the distance between the second channel region and the third channel region; a gate structure having a longitudinal axis in the first direction and extending across the first channel region, the second channel region, the third channel region, and the fourth channel region, wherein the gate structure includes a first interface layer, a second interface layer, a gate dielectric layer, and a gate electrode, wherein the gate electrode comprises a Ti-based material; a first epitaxial member and a second epitaxial member, the first channel region being located between the first epitaxial member and the second epitaxial member; a third epitaxial member and a fourth epitaxial member, the second channel region being located between the third epitaxial member and the fourth epitaxial member; a fifth epitaxial member and a sixth epitaxial member, the third channel region being located between the fifth epitaxial member and the sixth epitaxial member; a seventh epitaxial member and an eighth epitaxial member, the fourth channel region being located between... Between the seventh and eighth epitaxial components; a first isolation structure including a first portion extending between a first channel region and a second channel region, a second portion extending between the first and third epitaxial components, and a third portion extending between the second and fourth epitaxial components, wherein the first portion of the first isolation structure is located between the second and third portions of the first isolation structure; a second isolation structure including a first portion extending between the third and fourth channel regions, a second portion extending between the fifth and seventh epitaxial components, and a third portion extending between the sixth and eighth epitaxial components, wherein the first portion of the second isolation structure is located between the second and third portions of the second isolation structure; a first contact disposed on and electrically coupled to the first epitaxial component, wherein the conductivity of the first contact is greater than the conductivity of the first epitaxial component; and a second contact disposed on and electrically coupled to the third epitaxial component. In an embodiment, the first isolation structure has a top surface higher than the top of the first channel region and a bottom surface lower than the bottom of the first channel region. In one embodiment, the sidewall of the first isolation structure is in direct contact with the first interface layer and the gate dielectric layer, and the sidewall of the second isolation structure is in direct contact with the second interface layer and the gate dielectric layer. In another embodiment, the semiconductor device further includes isolation caps disposed above the first portion, the second portion, and the third portion of the first isolation structure, wherein the first contact and the second contact are separated by the isolation caps. In yet another embodiment, the semiconductor device further includes a conductive cap disposed above the first portion of the second isolation structure.In one embodiment, the semiconductor device further includes an isolation cap disposed above a first portion of the first isolation structure and a conductive cap disposed above the first portion of the isolation structure, wherein the isolation cap has a top surface flush with the top surface of the gate electrode, and wherein the second portion and the third portion of the first isolation structure each have a top surface flush with the top surface of the gate electrode. In another embodiment, the second portion and the third portion of the second isolation structure each have a top surface flush with the top surface of the gate electrode.

[0063] A further embodiment is a method of manufacturing a semiconductor device. The method includes: forming a plurality of nanostructures disposed above a semiconductor substrate; forming a first epitaxial structure and a second epitaxial structure interposed in a second direction perpendicular to a first direction, wherein the first epitaxial structure includes two layers comprising the same semiconductor material with different concentrations; forming an isolation structure to divide the nanostructures into the first nanostructure and the second nanostructure, such that the first nanostructure and the second nanostructure are separated by the isolation structure in the first direction; forming a gate structure spanning the first nanostructure and the second nanostructure; and forming a first contact above the first epitaxial member and a second contact above the second epitaxial member, wherein the conductivity of the first contact is greater than the conductivity of the first epitaxial structure. In an embodiment, the gate structure includes an interface layer, a gate dielectric layer, and a gate electrode, wherein the sidewalls of the isolation structure are in direct contact with the interface layer and the gate dielectric layer. In an embodiment, the isolation structure divides the first epitaxial structure into a first epitaxial member and a second epitaxial member, and further divides the second epitaxial structure into a third epitaxial member and a fourth epitaxial member. In one embodiment, the method further includes: etching an upper portion of the isolation structure to form an opening in the gate electrode; and depositing an insulating material in the opening to form an isolation cap, wherein the first contact and the second contact are separated by the isolation cap. In another embodiment, the first epitaxial member and the second epitaxial member are disposed in an interlayer dielectric layer and covered by the dielectric layer, wherein the isolation cap, the gate electrode, the first contact, the second contact, and the dielectric layer have coplanar top surfaces.

[0064] Some embodiments of this application provide a semiconductor device comprising: a first channel region and a second channel region disposed above a semiconductor substrate; a gate structure having a longitudinal axis in a first direction and extending across the first channel region and the second channel region, wherein the gate structure includes an interface layer, a gate dielectric layer, and a gate electrode, wherein the gate electrode comprises a Ti-based material; a first epitaxial member and a second epitaxial member, wherein the first channel region and the gate structure are located between the first epitaxial member and the second epitaxial member in a second direction perpendicular to the first direction, wherein the first epitaxial member comprises two layers comprising the same semiconductor material with different concentrations; a third epitaxial member and a fourth epitaxial member, wherein the second channel region and the gate structure are located between the third epitaxial member and the fourth epitaxial member in the second direction; and an isolation structure extending between the first channel region and the second channel region, wherein the isolation structure has a first sidewall facing the first channel region, wherein a portion of the first sidewall located between the top and bottom of the first channel region is covered by the gate dielectric layer and the interface layer.

[0065] In some embodiments, the isolation structure extends along the second direction and between the first epitaxial member and the second epitaxial member, and between the third epitaxial member and the fourth epitaxial member. In some embodiments, the semiconductor device further includes an isolation cap disposed above the isolation structure, wherein the isolation cap has a longitudinal axis extending along the second direction. In some embodiments, the isolation cap extends at least along the second direction through the gate electrode. In some embodiments, the isolation cap has a top surface flush with the top surface of the gate electrode. In some embodiments, the first channel region includes a plurality of vertically stacked nanostructures, each of which is enveloped by the interface layer. In some embodiments, each of the nanostructures is partially enveloped by the gate dielectric layer. In some embodiments, the interface layer has a first portion disposed on a first side of one of the nanostructures and a second portion disposed on a second side of one of the nanostructures, wherein the second side is opposite to the first side and closer to the isolation structure than the first side, wherein the first portion has a first thickness in the horizontal direction, and the second portion of the interface layer has a second thickness in the horizontal direction that is thicker than the first thickness.

[0066] Other embodiments of this application provide a semiconductor device including: a first channel region, a second channel region, a third channel region, and a fourth channel region disposed above a semiconductor substrate and subsequently arranged in a row in a first direction, wherein the distance between the first channel region and the second channel region and the distance between the third channel region and the fourth channel region are less than the distance between the second channel region and the third channel region; and a gate structure having a longitudinal axis in the first direction and spanning the first channel region, the second channel region, the third channel region, and the fourth channel region. The extension includes, wherein the gate structure comprises a first interface layer, a second interface layer, a gate dielectric layer, and a gate electrode, wherein the gate electrode comprises a Ti-based material; a first epitaxial component and a second epitaxial component, wherein the first channel region is located between the first epitaxial component and the second epitaxial component; a third epitaxial component and a fourth epitaxial component, wherein the second channel region is located between the third epitaxial component and the fourth epitaxial component; a fifth epitaxial component and a sixth epitaxial component, wherein the third channel region is located between the fifth epitaxial component and the sixth epitaxial component; a seventh epitaxial component and an eighth epitaxial component, wherein the fourth channel region is located between the first epitaxial component and the second epitaxial component. Between the seventh epitaxial member and the eighth epitaxial member; a first isolation structure comprising a first portion extending between the first channel region and the second channel region, a second portion extending between the first epitaxial member and the third epitaxial member, and a third portion extending between the second epitaxial member and the fourth epitaxial member, wherein the first portion of the first isolation structure is located between the second portion of the first isolation structure and the third portion of the first isolation structure; a second isolation structure comprising a first portion of the second isolation structure extending between the third channel region and the fourth channel region, a second portion extending between the fifth epitaxial member and the seventh epitaxial member, and a third portion extending between the sixth epitaxial member and the eighth epitaxial member, wherein the first portion of the second isolation structure is located between the second portion of the second isolation structure and the third portion of the second isolation structure; a first contact disposed on the first epitaxial member and electrically coupled to the first epitaxial member, wherein the conductivity of the first contact is greater than the conductivity of the first epitaxial member; and a second contact disposed on the third epitaxial member and electrically coupled to the third epitaxial member.

[0067] In some embodiments, the first isolation structure has a top surface higher than the top of the first channel region and a bottom surface lower than the bottom of the first channel region. In some embodiments, the sidewalls of the first isolation structure are in direct contact with the first interface layer and the gate dielectric layer, and the sidewalls of the second isolation structure are in direct contact with the second interface layer and the gate dielectric layer. In some embodiments, the semiconductor device further includes an isolation cap disposed above the first portion, the second portion, and the third portion of the first isolation structure, wherein the first contact and the second contact are separated by the isolation cap. In some embodiments, the semiconductor device further includes a conductive cap disposed above the first portion of the second isolation structure. In some embodiments, the semiconductor device further includes an isolation cap disposed above the first portion of the first isolation structure and a conductive cap disposed above the first portion of the isolation structure, wherein the isolation cap has a top surface flush with the top surface of the gate electrode, wherein the second portion and the third portion of the first isolation structure each have a top surface flush with the top surface of the gate electrode. In some embodiments, the second portion and the third portion of the second isolation structure each have a top surface flush with the top surface of the gate electrode.

[0068] Further embodiments of this application provide a method for manufacturing a semiconductor device, the method comprising: forming a plurality of nanostructures disposed above a semiconductor substrate; forming a first epitaxial structure and a second epitaxial structure, interposed in a second direction perpendicular to the first direction, wherein the first epitaxial structure comprises two layers comprising the same semiconductor material having different concentrations; forming an isolation structure to divide the nanostructures into the first nanostructure and the second nanostructure, such that the first nanostructure and the second nanostructure are separated by the isolation structure in the first direction; forming a gate structure spanning the first nanostructure and the second nanostructure; and forming a first contact above the first epitaxial component and a second contact above the second epitaxial component, wherein the conductivity of the first contact is greater than the conductivity of the first epitaxial structure.

[0069] In some embodiments, the gate structure includes an interface layer, a gate dielectric layer, and a gate electrode, wherein the sidewalls of the isolation structure are in direct contact with the interface layer and the gate dielectric layer. In some embodiments, the isolation structure divides the first epitaxial structure into a first epitaxial member and a second epitaxial member, and divides the second epitaxial structure into a third epitaxial member and a fourth epitaxial member. In some embodiments, the method further includes: etching an upper portion of the isolation structure to form an opening in the gate electrode, and depositing an insulating material in the opening to form an isolation cap, wherein the first contact and the second contact are separated by the isolation cap. In some embodiments, the first epitaxial member and the second epitaxial member are disposed in an interlayer dielectric layer and covered by the dielectric layer, wherein the isolation cap, the gate electrode, the first contact, the second contact, and the dielectric layer have coplanar top surfaces.

[0070] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of the embodiments of this disclosure. Those skilled in the art should understand that they can readily use the embodiments of this disclosure as a basis to design or modify other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the embodiments of this disclosure, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the embodiments of this disclosure.

Claims

1. A semiconductor device, comprising: The first channel region and the second channel region are disposed above the semiconductor substrate; A gate structure having a longitudinal axis in a first direction and extending across a first channel region and a second channel region, wherein the gate structure includes an interface layer, a gate dielectric layer and a gate electrode, wherein the gate electrode comprises a Ti-based material; In a second direction perpendicular to the first direction, the first channel region and the gate structure are located between the first epitaxial component and the second epitaxial component, wherein the first epitaxial component comprises two layers containing the same semiconductor material with different concentrations. The third epitaxial member and the fourth epitaxial member, wherein, in the second direction, the second channel region and the gate structure are located between the third epitaxial member and the fourth epitaxial member; and An isolation structure extends between a first channel region and a second channel region, wherein the isolation structure has a first sidewall facing the first channel region, wherein a portion of the first sidewall located between the top and bottom of the first channel region is covered by the gate dielectric layer and the interface layer.

2. The semiconductor device according to claim 1, wherein, The isolation structure extends along the second direction and between the first and second epitaxial members and between the third and fourth epitaxial members.

3. The semiconductor device according to claim 1, further comprising an isolation cap disposed above the isolation structure, wherein, The isolation cap has a longitudinal axis extending along the second direction.

4. The semiconductor device according to claim 3, wherein, The isolation cap extends through the gate electrode at least along the second direction.

5. The semiconductor device according to claim 3, wherein, The isolation cap has a top surface that is flush with the top surface of the gate electrode.

6. The semiconductor device according to claim 1, wherein, The first channel region comprises a plurality of vertically stacked nanostructures, and each of the nanostructures is encapsulated by the interface layer.

7. The semiconductor device according to claim 6, wherein, Each part of the nanostructure is encapsulated by the gate dielectric layer.

8. The semiconductor device according to claim 7, wherein, The interface layer has a first portion disposed on a first side of one of the nanostructures and a second portion disposed on a second side of one of the nanostructures, wherein the second side is opposite to the first side and closer to the isolation structure than the first side, wherein the first portion has a first thickness in the horizontal direction, and the second portion of the interface layer has a second thickness in the horizontal direction that is thicker than the first thickness.

9. A semiconductor device, comprising: A first channel region, a second channel region, a third channel region, and a fourth channel region are disposed above a semiconductor substrate and subsequently arranged in a row in a first direction, wherein the distance between the first channel region and the second channel region and the distance between the third channel region and the fourth channel region are less than the distance between the second channel region and the third channel region. A gate structure having a longitudinal axis in the first direction and extending across the first channel region, the second channel region, the third channel region and the fourth channel region, wherein the gate structure includes a first interface layer, a second interface layer, a gate dielectric layer and a gate electrode, wherein the gate electrode includes a Ti-based material; A first epitaxial component and a second epitaxial component, wherein the first channel region is located between the first epitaxial component and the second epitaxial component; The third epitaxial component and the fourth epitaxial component, wherein the second channel region is located between the third epitaxial component and the fourth epitaxial component; A fifth epitaxial component and a sixth epitaxial component, wherein the third channel region is located between the fifth epitaxial component and the sixth epitaxial component; A seventh epitaxial component and an eighth epitaxial component, wherein the fourth channel region is located between the seventh epitaxial component and the eighth epitaxial component; A first isolation structure includes a first portion extending between a first channel region and a second channel region, a second portion extending between a first epitaxial member and a third epitaxial member, and a third portion extending between the second epitaxial member and a fourth epitaxial member, wherein the first portion of the first isolation structure is located between the second portion of the first isolation structure and the third portion of the first isolation structure. The second isolation structure includes a first portion extending between the third channel region and the fourth channel region, a second portion extending between the fifth and seventh extensional members, and a third portion extending between the sixth and eighth extensional members, wherein the first portion of the second isolation structure is located between the second portion and the third portion of the second isolation structure. A first contact is disposed on and electrically coupled to the first epitaxial member, wherein the conductivity of the first contact is greater than the conductivity of the first epitaxial member; and A second contact is disposed on the third epitaxial member and electrically coupled to the third epitaxial member.

10. A method for manufacturing a semiconductor device, the method comprising: Multiple nanostructures are formed on the semiconductor substrate; A first epitaxial structure and a second epitaxial structure are formed in a second direction perpendicular to the first direction, with the nanostructure located therebetween, wherein the first epitaxial structure comprises two layers containing the same semiconductor material with different concentrations. An isolation structure is formed to divide the nanostructure into a first nanostructure and a second nanostructure, such that the first nanostructure and the second nanostructure are separated by the isolation structure in the first direction; Forming a gate structure spanning the first nanostructure and the second nanostructure; and A first contact is formed above the first epitaxial member, and a second contact is formed above the second epitaxial member, wherein the conductivity of the first contact is greater than the conductivity of the first epitaxial structure.

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