Semiconductor structure and method of fabricating the same

Abstract

A transistor device of an embodiment of the invention includes a source electrode and a drain electrode; a fin structure extending between and contacting respective sidewalls of the source electrode and the drain electrode; a semiconductor channel layer over upper and side surfaces of the fin structure and including first and second vertical portions over the side surfaces of the fin structure, both of which first and second vertical portions of the semiconductor channel layer contacting the respective sidewalls of the source electrode and the drain electrode; a gate dielectric layer over the semiconductor channel layer; and a gate electrode over the gate dielectric layer. By forming the semiconductor channel layer over the fin structure extending between the sidewalls of the source electrode and the drain electrode, the contact area between the semiconductor channel layer and the source and drain electrodes can be increased, which can provide the transistor device with increased drive current without increasing the size of the device.

Description

Technical Field

[0001] This invention relates to a semiconductor structure and its fabrication method. Background Technology

[0002] Various transistor structures have been developed to meet a wide range of design criteria. Thin film transistors (TFTs) (including TFTs with oxide semiconductor channel layers) are an attractive option for back-end-of-line (BEOL) integration because TFT fabrication processes typically operate at lower temperatures, are compatible with existing BEOL processes, and do not damage previously fabricated devices. Summary of the Invention

[0003] According to an embodiment of the present invention, a semiconductor structure includes: a source electrode, a drain electrode, a fin structure, a semiconductor channel layer, a gate dielectric layer, and a gate electrode. The fin structure extends between and contacts the respective sidewalls of the source electrode and the drain electrode. The semiconductor channel layer is located above the upper surface, a first side surface, and a second side surface of the fin structure, wherein the semiconductor channel layer includes a first vertical portion located above the first side surface of the fin structure and a second vertical portion located above the second side surface of the fin structure, and wherein the first vertical portion and the second vertical portion of the semiconductor channel layer contact the respective sidewalls of the source electrode and the drain electrode. The gate dielectric layer is located above the semiconductor channel layer. The gate electrode is located above the gate dielectric layer.

[0004] According to an embodiment of the present invention, a semiconductor structure includes: a layer stack, a gate dielectric layer, and a pair of conductive word lines. The layer stack, located above the first dielectric layer, includes a first electrode, a pair of second electrodes, a pair of fin structures, and a semiconductor channel layer. The pair of second electrodes are located on opposite sides of the first electrode and laterally spaced from the first electrode along a first horizontal direction. The pair of fin structures extend along the first horizontal direction, each fin extending between a sidewall of the first electrode and a sidewall of a corresponding second electrode in the pair of second electrodes, and contacting the sidewall of the first electrode and the sidewall of the corresponding second electrode. The semiconductor channel layer is located above the upper surface and sidewall of one of the second electrodes, the upper surface and side surface of the first fin structure in the pair of fin structures, the upper surface and two opposite sidewalls of the first electrode, the upper surface and side surface of the second fin structure in the pair of fin structures, and the sidewall and upper surface of the other second electrode in the pair of second electrodes. The gate dielectric layer is located above the upper surface and side surface of the layer stack. The pair of conductive word lines are located above the gate dielectric layer and extend along a second horizontal direction perpendicular to the first horizontal direction, and are laterally spaced from each other along the first horizontal direction, wherein each of the pair of conductive word lines extends above a corresponding fin structure in the pair of fin structures of the layer stack.

[0005] According to an embodiment of the present invention, a method for fabricating a semiconductor structure includes the following steps: A source electrode and a drain electrode are formed on a supporting substrate. A fin structure is formed between the source electrode and the drain electrode, wherein the fin structure contacts corresponding sidewalls of the source electrode and the drain electrode. A semiconductor channel layer is formed on an upper surface, a first side surface, and a second side surface of the fin structure, wherein the semiconductor channel layer includes a first vertical portion located on the first side surface of the fin structure and a second vertical portion located on the second side surface of the fin structure, and the first vertical portion and the second vertical portion of the semiconductor channel layer contact the corresponding sidewalls of the source electrode and the drain electrode. A gate dielectric layer is formed on the semiconductor channel layer. A gate electrode is formed on the gate dielectric layer. Attached Figure Description

[0006] The best understanding of all aspects of this disclosure will be achieved by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of explanation.

[0007] Figure 1AThis is a vertical cross-sectional view of a first exemplary structure prior to the formation of an array of transistor devices according to embodiments of the present disclosure.

[0008] Figure 1B This is a vertical cross-sectional view of a first exemplary structure during the formation of an array of transistor devices according to embodiments of the present disclosure.

[0009] Figure 1C This is a vertical cross-sectional view of a first exemplary intermediate structure after the formation of an upper-level metal interconnect structure, according to an embodiment of the present disclosure.

[0010] Figure 2A This is a top view of an exemplary structure during the process of forming a plurality of transistor devices according to embodiments of the present disclosure.

[0011] Figure 2B It is along Figure 2A A vertical sectional view of an exemplary structure along line A-A'.

[0012] Figure 2C It is along Figure 2A A vertical cross-sectional view of an exemplary structure of line B-B' in the diagram.

[0013] Figure 3A This is a top view of an exemplary structure during the process of forming a plurality of transistor devices according to embodiments of the present disclosure, showing a first electrode and a second electrode embedded in a dielectric layer.

[0014] Figure 3B It is along Figure 3A A vertical sectional view of an exemplary structure along line A-A'.

[0015] Figure 3C It is along Figure 3A A vertical cross-sectional view of an exemplary structure of line B-B' in the diagram.

[0016] Figure 4A This is a top view of an exemplary structure during a process of forming a plurality of transistor devices according to embodiments of the present disclosure, showing a patterned mask located above the upper surface of a first electrode, the upper surface of a second electrode, and the upper surface of a dielectric layer.

[0017] Figure 4B It is along Figure 4A A vertical sectional view of an exemplary structure along line A-A'.

[0018] Figure 4C It is along Figure 4A A vertical cross-sectional view of an exemplary structure of line B-B' in the diagram.

[0019] Figure 5A This is a top view of an exemplary structure during a process of forming multiple transistor devices after an etching process, according to an embodiment of the present disclosure, wherein the etching process removes a portion of the dielectric layer and forms a fin structure that contacts a first electrode and a second electrode.

[0020] Figure 5B It is along Figure 5A A vertical sectional view of an exemplary structure along line A-A'.

[0021] Figure 5C It is along Figure 5A A vertical cross-sectional view of an exemplary structure of line B-B' in the diagram.

[0022] Figure 5D It is along Figure 5A A vertical cross-sectional view of an exemplary structure with line C-C' in the figure.

[0023] Figure 5E This is a perspective view showing a fin structure located above a dielectric layer according to an embodiment of the present disclosure.

[0024] Figure 6A This is a top view of an exemplary structure during a process of forming a plurality of transistor devices according to embodiments of the present disclosure, showing a semiconductor channel layer formed over the upper surface of a first electrode and the upper surface of a second electrode, as well as over the upper surface and side surface of a fin structure.

[0025] Figure 6B It is along Figure 6A A vertical sectional view of an exemplary structure along line A-A'.

[0026] Figure 6C It is along Figure 6A A vertical cross-sectional view of an exemplary structure of line B-B' in the diagram.

[0027] Figure 6D It is along Figure 6A A vertical cross-sectional view of an exemplary structure with line C-C' in the figure.

[0028] Figure 6E It is along Figure 6A A vertical cross-sectional view of an exemplary structure of line D-D' in the diagram.

[0029] Figure 6F It is along Figure 6A A vertical sectional view of an exemplary structure along line E-E'.

[0030] Figure 6G This is a perspective view showing a semiconductor channel layer located above the fin structure according to an embodiment of the present disclosure.

[0031] Figure 7AThis is a top view of an exemplary structure during a process of forming a plurality of transistor devices according to embodiments of the present disclosure, showing a gate dielectric layer formed over the upper and side surfaces of a plurality of stacked layers and over the upper surface of a dielectric layer.

[0032] Figure 7B It is along Figure 7A A vertical sectional view of an exemplary structure along line A-A'.

[0033] Figure 7C It is along Figure 7A A vertical cross-sectional view of an exemplary structure of line B-B' in the diagram.

[0034] Figure 7D It is along Figure 7A A vertical cross-sectional view of an exemplary structure with line C-C' in the figure.

[0035] Figure 7E It is along Figure 7A A vertical cross-sectional view of an exemplary structure of line D-D' in the diagram.

[0036] Figure 7F It is along Figure 7A A vertical sectional view of an exemplary structure along line E-E'.

[0037] Figure 7G This is a perspective view showing the gate dielectric layer located above the fin structure according to an embodiment of the present disclosure.

[0038] Figure 8A This is a top view of an exemplary structure during a process of forming a plurality of transistor devices according to embodiments of the present disclosure, showing word line fill material and dielectric material layers formed on a gate dielectric layer.

[0039] Figure 8B It is along Figure 8A A vertical sectional view of an exemplary structure along line A-A'.

[0040] Figure 8C It is along Figure 8A A vertical cross-sectional view of an exemplary structure of line B-B' in the diagram.

[0041] Figure 8D It is along Figure 8A A vertical cross-sectional view of an exemplary structure with line C-C' in the figure.

[0042] Figure 8E It is along Figure 8A A vertical cross-sectional view of an exemplary structure of line D-D' in the diagram.

[0043] Figure 8F It is along Figure 8A A vertical sectional view of an exemplary structure along line E-E'.

[0044] Figure 8G This is a perspective view showing the letter line filling material located above the fin structure according to an embodiment of the present disclosure.

[0045] Figure 9A This is a top view of an exemplary structure during the process of forming a plurality of transistor devices according to embodiments of the present disclosure, showing a plurality of word lines separated by dielectric material layers and surrounding the device laterally.

[0046] Figure 9B It is along Figure 9A A vertical sectional view of an exemplary structure along line A-A'.

[0047] Figure 9C It is along Figure 9A A vertical cross-sectional view of an exemplary structure of line B-B' in the diagram.

[0048] Figure 9D It is along Figure 9A A vertical cross-sectional view of an exemplary structure with line C-C' in the figure.

[0049] Figure 9E It is along Figure 9A A vertical cross-sectional view of an exemplary structure of line D-D' in the diagram.

[0050] Figure 9F This is a perspective view showing the letter lines located above the fin structure according to an embodiment of the present disclosure.

[0051] Figure 10A This is a top view of an exemplary structure according to an embodiment of the present disclosure, showing a plurality of transistor devices including vias formed through a dielectric material layer.

[0052] Figure 10B It is along Figure 10A A vertical sectional view of an exemplary structure along line A-A'.

[0053] Figure 10C It is along Figure 10A A vertical cross-sectional view of an exemplary structure of line B-B' in the diagram.

[0054] Figure 11A This is a top view of an exemplary structure during the process of forming a plurality of transistor devices according to embodiments of the present disclosure, showing a first electrode and a second electrode embedded in a dielectric material layer having a recessed upper surface.

[0055] Figure 11B It is along Figure 11A A vertical sectional view of an exemplary structure along line A-A'.

[0056] Figure 11C It is along Figure 11AA vertical cross-sectional view of an exemplary structure of line B-B' in the diagram.

[0057] Figure 12A This is a top view of an exemplary structure during a process of forming a plurality of transistor devices according to embodiments of the present disclosure, showing a patterned mask located above the upper surface of a first electrode, the upper surface of a second electrode, and the upper surface of a dielectric material.

[0058] Figure 12B It is along Figure 12A A vertical sectional view of an exemplary structure along line A-A'.

[0059] Figure 13A This is a top view of an exemplary structure during a process of forming multiple transistor devices after an etching process, according to an embodiment of the present disclosure, wherein the etching process removes a portion of the dielectric layer and forms a fin structure that contacts a first electrode and a second electrode.

[0060] Figure 13B It is along Figure 13A A vertical sectional view of an exemplary structure along line A-A'.

[0061] Figure 13C It is along Figure 13A A vertical cross-sectional view of an exemplary structure of line B-B' in the diagram.

[0062] Figure 13D It is along Figure 13A A vertical cross-sectional view of an exemplary structure with line C-C' in the figure.

[0063] Figure 14A This is a top view of an exemplary structure during a process of forming a plurality of transistor devices according to an embodiment of the present disclosure, showing a semiconductor channel layer formed over the upper surfaces of a first electrode and a second electrode, as well as the upper and side surfaces of a fin structure, and contacting the sidewalls of the first electrode and the second electrode over vertical and horizontal portions of the semiconductor channel layer.

[0064] Figure 14B It is along Figure 14A A vertical sectional view of an exemplary structure along line A-A'.

[0065] Figure 14C It is along Figure 14A A vertical cross-sectional view of an exemplary structure of line B-B' in the diagram.

[0066] Figure 14D It is along Figure 14A A vertical cross-sectional view of an exemplary structure with line C-C' in the figure.

[0067] Figure 15This is a flowchart illustrating the steps of a method for forming a TFT device according to various embodiments of the present disclosure. Detailed Implementation

[0068] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description of a first feature forming on or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. Such repetition is for the purpose of brevity and clarity and is not, in itself, intended to indicate a relationship between the various embodiments and / or configurations discussed.

[0069] Furthermore, for ease of explanation, spatially relative terms such as "beneath," "below," "lower," "above," and "upper" may be used herein to describe the relationship between one element or feature shown in the figures and another element or feature. These spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein shall be interpreted accordingly. Unless otherwise expressly stated, each element having the same reference number is considered to have the same material composition and a thickness within the same thickness range.

[0070] Generally, the structures and methods of this disclosure can be used to form semiconductor structures including at least one transistor (e.g., a thin-film transistor (TFT)) (e.g., multiple transistors (e.g., multiple TFTs)). Transistors can be formed on any substrate (which may be an insulating substrate, a conductive substrate, or a semiconductor substrate). In embodiments utilizing a conductive or semiconductor substrate, at least one insulating layer can be used to provide electrical isolation between the thin-film transistor and the underlying substrate. In embodiments using a semiconductor substrate, such as a single-crystal silicon substrate, a field-effect transistor (FET) using a portion of the semiconductor substrate as a semiconductor channel can be formed on the semiconductor substrate, and a metal interconnect structure embedded in an interconnect-level dielectric layer can be formed on the FET. Transistors can be formed on the FET including the semiconductor channel and on the metal interconnect structure, which is referred to herein as a lower-level metal interconnect structure. In some embodiments, transistors according to various embodiments of this disclosure can form a semiconductor memory device or can be part of a semiconductor memory device.

[0071] The fabrication of transistor devices (such as TFT devices, including oxide semiconductors) is an attractive option for back-to-line (BEOL) integration because TFTs can be processed at low temperatures and therefore will not damage previously fabricated devices.

[0072] One problem with some TFT devices (including those fabricated using back-to-end (BEOL) processes) is that the transistor drive current can be relatively small. One way to increase the drive current is to increase the contact area between the source and drain electrodes and the semiconductor channel of the TFT device. However, for planar TFT devices (where the source and drain electrodes contact the semiconductor channel on a horizontal surface extending parallel to the surface of the supporting substrate), increasing the contact area between the source and drain electrodes and the semiconductor channel generally results in a larger TFT device occupying additional space on the chip.

[0073] Alternative designs include rotating the TFT device structure by 90°, such that the contact areas between the source and drain electrodes and the semiconductor channel extend in a direction perpendicular to the surface of the supporting substrate. This design may help preserve valuable real estate on the chip. However, maintaining effective contact between the semiconductor channel and the source and drain electrodes along the vertical direction may be difficult. Such vertical devices are prone to misalignment errors between the surface of the semiconductor channel and the corresponding surfaces of the source and / or drain electrodes, which may render the TFT device inoperable.

[0074] Accordingly, various embodiments provide transistor devices (e.g., TFT devices) and methods of forming transistor devices, the transistor devices having a finned semiconductor channel layer contacting respective sidewalls of a source electrode and a respective sidewall of a drain electrode. In various embodiments, the semiconductor channel layer may be formed on a fin structure that extends between and contacts the respective sidewalls of the source and drain electrodes. By forming the channel layer on the fin structure extending between the sidewalls of the source and drain electrodes, the semiconductor channel layer may have a finned structure including a pair of vertically extending portions on opposite side surfaces of the fin structure and a horizontally extending portion on an upper surface of the fin structure. The vertically extending portions of the finned semiconductor channel layer may contact the respective sidewalls of the source and drain electrodes. In some embodiments, both the vertically extending portions and the horizontally extending portions of the finned semiconductor channel layer may contact the sidewalls of the source and drain electrodes. The semiconductor channel layer may also contact the upper surfaces of the source and drain electrodes. Transistor devices (e.g., TFT devices) with finned semiconductor channel layers according to various embodiments can increase the contact area between the semiconductor channel layer and the source and drain electrodes, which can result in an increase in the drive current of the transistor device without requiring any significant increase in the size of the transistor device. Furthermore, since the semiconductor channel layer can be deposited on a fin structure extending between and contacting the respective sidewalls of the source and drain electrodes, misalignment between the semiconductor channel layer and the source and drain electrodes can be avoided, and effective contact between the semiconductor channel layer and the source and drain electrodes can be maintained.

[0075] Reference Figure 1A This image shows a vertical cross-sectional view of a first exemplary structure according to various embodiments of the present disclosure prior to the formation of an array of thin-film transistor (TFT) devices. The first exemplary structure includes a substrate 8 comprising a semiconductor material layer 10. The substrate 8 may include: a bulk semiconductor substrate (e.g., a silicon substrate) wherein the semiconductor material layer extends continuously from a top surface of the substrate 8 to a bottom surface of the substrate 8; or a semiconductor-on-insulator layer, including the semiconductor material layer 10 as a top semiconductor layer overlying a buried insulating layer (e.g., a silicon oxide layer). The exemplary structure may include various device regions 50 and 52. In a non-limiting embodiment, device region 50 may be a memory array region, wherein at least one array of volatile or non-volatile memory cells may subsequently be formed. Device region 52 may be a peripheral logic region, wherein electrical connections between the array of memory cells and peripheral circuitry including field-effect transistors may subsequently be formed. Regions of device region 50 (e.g., a memory array region) and device region 52 (e.g., a logic region) may be used to form various elements of the peripheral circuitry.

[0076] During front-end-of-line (FEOL) operation, semiconductor devices such as field-effect transistors (FETs) can be formed on and / or within the semiconductor material layer 10. For example, a shallow trench isolation structure 12 can be formed in the upper portion of the semiconductor material layer 10 by forming shallow trenches and subsequently filling the shallow trenches with a dielectric material such as silicon oxide. Other suitable dielectric materials are also within the scope of this disclosure. Various doped wells (not explicitly shown) can be formed in the various regions of the upper portion of the semiconductor material layer 10 by performing a masked ion implantation process.

[0077] A gate structure 20 can be formed on the top surface of a substrate 8 by depositing and patterning a gate dielectric layer, a gate electrode layer, and a gate cap dielectric layer. Each gate structure 20 may include a vertical stack (referred to herein as a gate stack) of a gate dielectric 22, a gate electrode 24, and a gate cap dielectric 28. An ion implantation process can be performed to form extended implantation regions, which may include source extension regions and drain extension regions. Dielectric gate spacers 26 may be formed around the gate stack. Each assembly of the gate stack and the dielectric gate spacers 26 constitutes a gate structure 20. An additional ion implantation process may be performed using the gate structure 20 as a self-aligned implantation mask to form a deep active region. Such a deep active region may include a deep source region and a deep drain region. The upper portion of the deep active region may overlap with a portion of the extended implantation region. Each combination of the extended implantation region and the deep active region may constitute an active region 14, which may be a source region or a drain region depending on the electrical bias. A semiconductor channel 15 may be formed between adjacent pairs of active regions 14 under each gate stack. A metal-semiconductor alloy region 18 may be formed on the top surface of each active region 14. Field-effect transistors (FETs) may be formed on the semiconductor material layer 10. Each FET may include a gate structure 20, a semiconductor channel 15, a pair of active regions 14 (one of which serves as the source region and the other as the drain region), and an optional metal-semiconductor alloy region 18. Complementary metal-oxide-semiconductor (CMOS) circuitry 75 may be disposed on the semiconductor material layer 10. The CMOS circuitry 75 may include peripheral circuitry for an array of transistors (e.g., thin-film transistors (TFTs)) and memory devices to be subsequently formed.

[0078] Various interconnect hierarchy structures can then be formed, which are formed prior to the formation of the array of field-effect transistors and are referred to herein as lower interconnect hierarchy structures. In the case where a two-dimensional array of TFTs and memory devices will subsequently be formed on the two interconnect hierarchy metal lines, the lower interconnect hierarchy structure may include a contact hierarchy structure L0, a first interconnect hierarchy structure L1, and a second interconnect hierarchy structure L2. The contact hierarchy structure L0 may include a planarization dielectric layer 31A and various contact via structures 41V. The planarization dielectric layer 31A contains a planarizable dielectric material such as silicon oxide. The contact via structures 41V contact one of the active region 14 or the gate electrode 24 and are formed within the planarization dielectric layer 31A. The first interconnect hierarchy structure L1 includes a first interconnect level dielectric (ILD) layer 31B and a first metal line 41L formed within the first ILD layer 31B. The first ILD layer 31B is also referred to as the first line-level dielectric layer. The first metal line 41L can contact a corresponding one of the contact via structures 41V. The second interconnect layer structure L2 includes a second ILD layer 32, which may include a stack of the first via-level dielectric material layer and the second line-level dielectric material layer or the line and via-level dielectric material layers. The second ILD layer 32 may form a second interconnect layer metal interconnect structure, which includes the first metal via structure 42V and the second metal line 42L. The top surface of the second metal line 42L may be coplanar with the top surface of the second ILD layer 32.

[0079] Figure 1B This is a vertical cross-sectional view of a first exemplary structure during the formation of an array of TFT devices according to an embodiment of the present disclosure. (Refer to...) Figure 1B An array 95 of TFT devices can be formed in device region 50 above the second interconnect layer structure L2. The structure and processing steps of the TFT device array 95 will be described in detail below. A third ILD layer 33 can be formed during the formation process of the TFT device array 95. The collection of all structures formed above the TFT device array 95 is referred to herein as the third interconnect layer structure L3.

[0080] Figure 1C This is a vertical cross-sectional view of a first exemplary structure after the formation of the upper-level metal interconnect structure according to an embodiment of the present disclosure. (Refer to...) Figure 1CA third interconnect layer metal interconnect structure can be formed in the third ILD layer 33. The third interconnect layer metal interconnect structure may include a second metal via structure 43V and a third metal line 43L. Subsequently, additional interconnect layer structures can be formed; these additional interconnect layer structures are referred to herein as upper interconnect layer structures. For example, the upper interconnect layer structure may include a fourth interconnect layer structure L4, a fifth interconnect layer structure L5, a sixth interconnect layer structure L6, and a seventh interconnect layer structure L7. The fourth interconnect layer structure L4 may include a fourth ILD layer 34 in which the fourth interconnect layer metal interconnect structure is formed, and the fourth interconnect layer metal interconnect structure may include a third metal via structure 44V and a fourth metal line 44L. The fifth interconnect hierarchy L5 may include a fifth ILD layer 35 in which a fifth interconnect hierarchy metal interconnect structure is formed, the fifth interconnect hierarchy metal interconnect structure may include a fourth metal via structure 45V and a fifth metal line 45L. The sixth interconnect hierarchy L6 may include a sixth ILD layer 36 in which a sixth interconnect hierarchy metal interconnect structure is formed, the sixth interconnect hierarchy metal interconnect structure may include a fifth metal via structure 46V and a sixth metal line 46L. The seventh interconnect hierarchy L7 may include a seventh ILD layer 37 in which a sixth metal via structure 47V (the sixth metal via structure 47V is a seventh interconnect hierarchy metal interconnect structure) and a metal bonding pad 47B are formed. The metal bonding pad 47B may be configured for solder bonding (which may employ controlled collapse chip connection (C4) ball bonding or wire bonding) or may be configured for metal-to-metal bonding (e.g., copper-to-copper bonding).

[0081] Each ILD layer may be referred to as ILD layer 30. Each of the interconnect hierarchy metal interconnect structures may be referred to as metal interconnect structure 40. Each successive combination of metal via structures and overlying metal lines located within the same interconnect hierarchy (e.g., interconnect hierarchy L2 to L7) may be sequentially formed into two different structures using two single damascene processes, or may be simultaneously formed into a monolithic structure using a dual damascene process. Each of the metal interconnect structures 40 may include a respective metal pad (e.g., a layer of TiN, TaN, or WN having a thickness ranging from 2 nanometers (nm) to 20 nm) and a respective metal filler material (e.g., W, Cu, Co, Mo, Ru, other elemental metals, or alloys or combinations thereof). Other suitable materials for use as metal pads and metal fillers are also contemplated within the scope of this disclosure. Various etch-stop dielectric layers and dielectric capping layers may be interposed between adjacent pairs of ILD layers 30 in the vertical direction, or may be incorporated into one or more of the ILD layers 30.

[0082] Although this disclosure is illustrated using an embodiment in which an array 95 of TFT devices can be formed as an assembly of a third interconnect hierarchy L3, embodiments in which the array 95 of TFT devices can be formed as an assembly of any other interconnect hierarchy (e.g., interconnect hierarchies L1 through L7) are explicitly contemplated herein. Furthermore, although this disclosure is illustrated using an embodiment in which a set of eight interconnect hierarchies is formed, embodiments in which different numbers of interconnect hierarchies are used are explicitly contemplated herein. Additionally, embodiments in which two or more arrays 95 of TFT devices can be provided within multiple interconnect hierarchies are explicitly contemplated herein. Although this disclosure is illustrated using an embodiment in which an array 95 of TFT devices can be formed in a single interconnect hierarchy, embodiments in which an array 95 of TFT devices can be formed over two vertically adjacent interconnect hierarchies are explicitly contemplated herein. Furthermore, embodiments in which an array 95 of TFT devices can be formed on or within a semiconductor material layer 10 (e.g., in front-end (FEOL) operation) are explicitly contemplated herein.

[0083] Figures 2A to 10C This is a sequential view of exemplary structures during the process of forming a plurality of TFT devices according to various embodiments of the present disclosure. The plurality of TFT devices may form all or part of an array 95 of TFT devices, such as... Figure 1C As shown in the image.

[0084] Figure 2A This is a top view of an exemplary structure during the process of forming a plurality of TFT devices according to various embodiments of the present disclosure. Figure 2B It is along Figure 2A A vertical sectional view of an exemplary structure along line A-A'. Figure 2C It is along Figure 2A A vertical cross-sectional view of an exemplary structure of line B-B' in the diagram.

[0085] Reference Figures 2A to 2C It can be on a substrate ( Figures 2A to 2C A first dielectric layer 102 is deposited on the substrate (not shown). The substrate can be any suitable substrate, such as... Figures 1A to 1C The substrate 8 is shown. The substrate may include device structures formed on or in the substrate 8 during the FEOL process. In some embodiments, one or more additional dielectric layers (e.g., ILD layers) may be deposited between the substrate 8 and the first dielectric layer 102. In this embodiment, the first dielectric layer 102 may be deposited over the ILD layer, which may be as described above for... Figures 1A to 1C The ILD layer discussed.

[0086] The first dielectric layer 102 may be formed from any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, phosphosilicate glass (PSG), undoped silicate glass (USG), doped silicate glass, organosilicon glass, amorphous fluorinated carbon, porous variations thereof, or combinations thereof. Other dielectric materials are also within the scope of this disclosure. Any suitable deposition process may be used to deposit the first dielectric layer 102. Suitable deposition processes may include chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high-density plasma CVD (HDPCVD), metal-organic CVD (MOCVD), plasma-enhanced CVD (PECVD), sputtering, laser ablation, etc. Other suitable deposition processes are also within the scope of this disclosure.

[0087] Refer again Figure 2B and Figure 2C Optionally, a second dielectric layer 104 may be deposited over the upper surface of the first dielectric layer 102. The second dielectric layer 104 may be made of a suitable dielectric material as described above and may be deposited using a suitable deposition process as described above. In various embodiments, the second dielectric layer 104 may be made of a different dielectric material than the first dielectric layer 102. In some embodiments, the second dielectric layer 104 may be an etch stop layer having etch characteristics (i.e., a higher etch rate) different from those of the first dielectric layer 102. In a non-limiting embodiment, the first dielectric layer 102 may comprise silicon oxide, and the second dielectric layer 104 may comprise silicon nitride.

[0088] In some embodiments, the second dielectric layer 104 may be omitted, and Figures 2A to 2C The upper surface of the exemplary structure shown may include the upper surface of the first dielectric layer 102.

[0089] Refer again Figures 2A to 2C Multiple metal features 101 (which may be referred to as conductive metal lines / metal lines / bit lines) and 103 (which may be referred to as vias / metal features) may contact the first dielectric layer 102 and / or the second dielectric layer 104. In some embodiments, the metal features 101 and 103 may be at least partially embedded within the first dielectric layer 102 and / or the second dielectric layer 104. (Refer to...) Figure 2B and Figure 2C Multiple metal features 101 (e.g., multiple conductive metal lines) may contact the first dielectric layer 102 and may extend along a horizontal direction hd2. The metal features 101 (e.g., conductive metal lines) may extend parallel to each other and may be spaced apart from each other along a horizontal direction hd1 perpendicular to the horizontal direction hd2. In an embodiment, each of the metal features 101 (e.g., conductive metal lines) may contact the first dielectric layer 102 above its upper surface and may optionally be laterally surrounded by the first dielectric layer 102. Alternatively, a separate dielectric material layer (…) may be located beneath the first dielectric layer 102. Figures 2A to 2C (Not shown) may be laterally surrounding the metal feature 101 (e.g., a metal wire). In various embodiments, the metal feature 101 (e.g., a conductive metal wire) may also be referred to as a "bit line".

[0090] In various embodiments, the metallic feature 101 (e.g., a conductive metal line) can be formed by: depositing a first dielectric layer 102 material layer; etching the first dielectric layer 102 material layer using a patterned mask to form trenches extending in the horizontal direction hd2 within the first dielectric layer 102 material layer; and depositing metallic material (which may include, for example, a metal pad material and a metal filler material located on top of the metal pad material) over the upper surface of the first dielectric layer 102 material layer and within the trenches. A planarization process, such as chemical mechanical planarization (CMP), can be used to remove portions of the metallic material from the upper surface of the first dielectric layer 102 material layer, thereby leaving discrete metallic features 101 (e.g., metal lines) that fill the trenches and are laterally spaced from each other by the first dielectric layer 102 material layer. An additional layer of the first dielectric layer 102 material can be deposited on the upper surface of the metal feature 101 (e.g., a metal wire) and on the upper surface of the previously deposited first dielectric layer 102 material layer to form the first dielectric layer 102, wherein the metal feature 101 (e.g., a conductive metal wire) can contact the first dielectric layer 102.

[0091] Metal feature 101 (e.g., conductive metal wire) may comprise any suitable conductive material, such as copper (Cu), aluminum (Al), zirconium (Zr), titanium (Ti), titanium nitride (TiN), tungsten (W), tantalum (Ta), tantalum nitride (TaN), molybdenum (Mo), ruthenium (Ru), palladium (Pd), platinum (Pt), cobalt (Co), nickel (Ni), iridium (Ir), iron (Fe), beryllium (Be), chromium (Cr), antimony (Sb), osmium (Os), thorium (Th), vanadium (V), alloys thereof, and combinations thereof. Other suitable conductive materials for metal feature 101 (e.g., conductive metal wire) are also within the scope of this disclosure.

[0092] Any suitable deposition process can be used to deposit the metallic feature 101 (e.g., a conductive metal line). For example, suitable deposition processes may include physical vapor deposition (PVD), sputtering, chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma-enhanced chemical vapor deposition (PECVD), electrochemical deposition, or combinations thereof. Other suitable deposition processes are also within the scope of this disclosure.

[0093] Reference Figures 2A to 2C Multiple metal features 103 (e.g., vias) can extend through the second dielectric layer 104 and the first dielectric layer 102 and can contact the upper surface of the metal feature 101 (e.g., a metal wire). Figure 2C As shown in the vertical cross-sectional view of the exemplary structure, a pair of metal features 103 (e.g., vias) may extend through the second dielectric layer 104 and the first dielectric layer 102 and contact a corresponding metal feature 101 (e.g., a metal line). The upper surface of each of the metal features 103 (e.g., vias) may be substantially coplanar with the upper surface of the second dielectric layer 104.

[0094] In various embodiments, a patterned mask can be formed over the second dielectric layer 104 (or the first dielectric layer 102 in embodiments where the second dielectric layer 104 is not used). Figures 2A to 2C(Not shown) to form a metal feature 103 (e.g., a via), wherein the patterned mask includes an opening through the mask corresponding to the location of the via to be subsequently formed. A photolithography technique can be used to pattern a mask, which may include a photoresist layer and / or a hard mask, to form an opening through the mask corresponding to the location of the via to be subsequently formed. An etching process, such as anisotropic etching, can be used to etch the second dielectric layer 104 and the first dielectric layer 102 through the mask to form a via opening extending through the second dielectric layer 104 and the first dielectric layer 102. The etching process can expose the upper surface of the metal feature 101 (e.g., a metal line) at the bottom of each of the via openings. After the etching process, the patterned mask can be removed using a suitable process (e.g., by ashing or by dissolution using a solvent). Metallic material (which may include, for example, a metal backing material and a metal filler material situated on top of the metal backing material) can be deposited on the upper surface of the second dielectric layer 104 and within the via opening to contact the exposed upper surface of the metallic feature 101 (e.g., a metal wire). A planarization process, such as chemical mechanical planarization (CMP), can be used to remove portions of the metallic material from the upper surface of the second dielectric layer 104, leaving discrete metallic features 103 (e.g., vias) extending through the second dielectric layer 104 and the first dielectric layer 102 and contacting the metallic feature 101 (e.g., a metal wire). The metallic features 103 (e.g., vias) may comprise any suitable conductive material as described above and can be deposited using any suitable deposition process as described above.

[0095] Figure 3A This is a top view of an exemplary structure during the process of forming a plurality of TFT devices according to various embodiments of the present disclosure, showing a first electrode 105a and a second electrode 105b embedded in a third dielectric layer 106. Figure 3B It is along Figure 3A A vertical sectional view of an exemplary structure along line A-A'. Figure 3C It is along Figure 3A A vertical cross-sectional view of an exemplary structure of line B-B' in the diagram.

[0096] Reference Figures 3A to 3CA first electrode 105a and a second electrode 105b may be formed on the second dielectric layer 104. In embodiments where the second dielectric layer 104 is absent, the first electrode 105a and the second electrode 105b may be formed on the first dielectric layer 102. The first electrode 105a may be formed on the upper surface of a metal feature 103 (e.g., a via), such that the lower surface of each first electrode 105a contacts the upper surface of the corresponding metal feature 103 (e.g., a via). The second electrode 105b may not contact the upper surface of the metal feature 103 (e.g., a via). In a non-limiting embodiment, the first electrode 105a may form the drain electrode of a subsequently formed TFT device, and the second electrode 105b may form the source electrode of a subsequently formed TFT device. Alternatively, the first electrode 105a may form the source electrode of a subsequently formed TFT device, and the second electrode 105b may form the drain electrode of a subsequently formed TFT device.

[0097] exist Figures 3A to 3C In the exemplary structure shown, a pair of first electrodes 105a (which may also be referred to as "drain electrodes" for ease of illustration) may be located above corresponding metal features 103 (e.g., vias) and may be laterally spaced from each other along the horizontal direction hd1. A pair of second electrodes 105b (which may also be referred to as "source electrodes" for ease of illustration) may be located on opposite sides of each of the first electrodes 105a and may be laterally spaced from the first electrodes 105a along the horizontal direction hd2. A third dielectric layer 106 may laterally surround each of the first electrodes 105a and the second electrodes 105b. The upper surface of the third dielectric layer 106 may be substantially coplanar with the upper surfaces of each of the first electrodes 105a and the second electrodes 105b.

[0098] In various embodiments, a third dielectric layer 106 can be fabricated by depositing a third dielectric layer 106 over the upper surface of the second dielectric layer 104 and the upper surface of the metal feature 103 (e.g., a via). Figures 3A to 3C The exemplary structure is shown. In embodiments where the second dielectric layer 104 is absent, a third dielectric layer 106 may be deposited over the upper surface of the first dielectric layer 102 and the upper surface of the metal feature 103 (e.g., a via). The third dielectric layer 106 may be made of a suitable dielectric material as described above and may be deposited using any suitable deposition process as described above. In some embodiments, the third dielectric layer 106 may be made of the same dielectric material as the first dielectric layer 102. Alternatively, the third dielectric layer 106 may be made of a different dielectric material than the first dielectric layer 102.

[0099] In various embodiments, the third dielectric layer 106 may be made of a different dielectric material than the second dielectric layer 104. In some embodiments, the second dielectric layer 104 may be an etch stop layer having different etch characteristics (i.e., a higher etch rate) than the material of the third dielectric layer 106. In a non-limiting embodiment, the third dielectric layer 106 may comprise silicon oxide, and the second dielectric layer 104 may comprise silicon nitride.

[0100] In various embodiments, a patterned mask can be formed on the upper surface of the third dielectric layer 106. Figures 3A to 3C (Not shown) to form the first electrode 105a and the second electrode 105b. A patterned mask may include openings through the mask corresponding to the locations where the first electrode 105a and the second electrode 105b will subsequently be formed. A patterned mask, which may include a photoresist material layer and / or a hard mask, may be patterned using photolithography to form openings through the mask corresponding to the locations where the electrodes 105a and 105b will subsequently be formed. An etching process, such as anisotropic etching, may be used to etch the portion of the third dielectric layer 106 exposed through the mask. The etching process may stop at the second dielectric layer 104, thereby forming a plurality of openings through the third dielectric layer 106, wherein the upper surface of the second dielectric layer 104 may be exposed in the bottom surface of each of the openings. The upper surface of a metallic feature 103 (e.g., a via) may also be exposed in the bottom surface of the opening corresponding to the location where the first electrode 105a will subsequently be formed. After the etching process, the patterned mask can be removed using a suitable process (such as by ashing or by dissolving it with a solvent).

[0101] Then, a metallic material (which may include, for example, a metal pad material and a metal filler material located on top of the third dielectric layer 106) can be deposited on the upper surface of the third dielectric layer 106 and within the plurality of openings formed through the third dielectric layer 106. The metallic material may be made of any suitable conductive material as described above and can be deposited using a suitable deposition process as described above. After depositing the metallic material, a planarization process, such as chemical mechanical planarization (CMP), can be used to remove portions of the metallic material from the upper surface of the third dielectric layer 106, thereby leaving discrete first electrodes 105a and second electrodes 105b laterally surrounded by the third dielectric layer 106. Each of the first electrodes 105a may have a lower surface that contacts the upper surface of the second dielectric layer 104 (or, in embodiments where the second dielectric layer 104 is absent, the upper surface of the first dielectric layer 102) and the exposed upper surface of the metallic feature 103 (e.g., a via). Each of the second electrodes 105b may have a lower surface that contacts the upper surface of the second dielectric layer 104 (or, in embodiments where the second dielectric layer 104 is absent, the upper surface of the first dielectric layer 102).

[0102] Figure 4A This is a top view of an exemplary structure during the process of forming multiple TFT devices, showing a patterned mask 107 located above the upper surface of the first electrode 105a, the upper surface of the second electrode 105b, and the upper surface of the third dielectric layer 106. Figure 4B It is along Figure 4A A vertical sectional view of an exemplary structure along line A-A'. Figure 4C It is along Figure 4A A vertical cross-sectional view of an exemplary structure of line B-B' in the diagram.

[0103] Reference Figures 4A to 4C The patterned mask 107 may include strip mask portions 107a and 107b extending along the horizontal direction hd2. Each of the strip mask portions 107a and 107b may extend over a portion of the third dielectric layer 106 and the central portion of the first electrode 105a and the central portions of the pair of second electrodes 105b located on opposite sides of the first electrode 105a. The remaining portions of the third dielectric layer 106, the remaining portions of the first electrode 105a, and the remaining portions of the second electrodes 105b may be exposed through the patterned mask 107.

[0104] In various embodiments, the patterned mask 107 may comprise a suitable mask material (e.g., a photoresist material). The patterned mask 107 can be formed by depositing a continuous layer of mask material (e.g., a photoresist material) over the upper surface of the third dielectric layer 106, the upper surface of the first electrode 105a, and the upper surface of the second electrode 105b; and by using photolithography to pattern the mask material to remove portions of the mask material and leave strip mask portions 107a and 107b, such as... Figures 4A to 4C As shown in the image.

[0105] Figure 5A This is a top view of an exemplary structure during a process that forms multiple TFT devices after an etching process, in which a portion of the third dielectric layer 106 is removed and a fin structure 108 is formed that contacts the first electrode 105a and the second electrode 105b. Figure 5B It is along Figure 5A A vertical sectional view of an exemplary structure along line A-A'. Figure 5C It is along Figure 5A A vertical cross-sectional view of an exemplary structure of line B-B' in the diagram. Figure 5D It is along Figure 5A A vertical cross-sectional view of an exemplary structure with line C-C' in the figure. Figure 5E This is a perspective view showing the fin structure 108 located above the second dielectric layer 104.

[0106] Reference Figures 5A to 5EEtching processes can be used to penetrate Figures 4A to 4C The patterned mask 107 shown etches the exemplary structure. The etching process may use etching chemicals that have higher etch selectivity to the material of the third dielectric layer 106 relative to the materials of the first electrode 105a and the second electrode 105b. In various embodiments, the etching rate of the third dielectric layer 106 during the etching process may be at least 5 times greater than the etching rates of the first electrode 105a and the second electrode 105b during the etching process, for example, at least 10 times greater (including 100 times or more). The etching process may etch through the portion of the third dielectric layer 106 exposed by the patterned mask 107 and expose the upper surface of the second dielectric layer 104. In embodiments where the second dielectric layer 104 is absent, the etching process may expose the upper surface of the first dielectric layer 102.

[0107] The strip mask portions 107a and 107b of the patterned mask 107 protect portions of the third dielectric layer 106 from etching during the etching process. After the etching process, the remaining portion of the third dielectric layer 106 can form fin structures 108 extending along the horizontal direction hd2. Each fin structure 108 can contact at least one sidewall 109 of the electrodes 105a and 105b. (Refer to...) Figure 5A and Figure 5B The fin structure 108 can extend continuously along the horizontal direction hd2 between the sidewalls 109 of adjacent electrodes 105a and 105b. (Refer to...) Figure 5A , Figure 5C and Figure 5D The width of the fin structure 108 along the horizontal direction hd1 may be smaller than the width of the electrodes 105a and 105b along the horizontal direction hd1. Therefore, after the etching process, the portion of the sidewalls 109 of the electrodes 105a and 105b that are contacted by the fin structure 108 may include the exposed surfaces laterally adjacent to the fin structure 108. After the etching process, the patterned mask 107 can be removed by a suitable process (e.g., by ashing or by dissolution using a solvent) (see [link to relevant documentation]). Figures 4A to 4C ).

[0108] Figure 6A This is a top view of an exemplary structure during the process of forming multiple TFT devices, showing a semiconductor channel layer 110 formed on the upper surface of the first electrode 105a and the upper surface of the second electrode 105b, as well as on the upper surface and side surface of the fin structure 108. Figure 6B It is along Figure 6A A vertical sectional view of an exemplary structure along line A-A'. Figure 6C It is along Figure 6A A vertical cross-sectional view of an exemplary structure of line B-B' in the diagram. Figure 6D It is along Figure 6AA vertical cross-sectional view of an exemplary structure with line C-C' in the figure. Figure 6E It is along Figure 6A A vertical cross-sectional view of an exemplary structure of line D-D' in the diagram. Figure 6F It is along Figure 6A A vertical sectional view of an exemplary structure along line E-E'. Figure 6G This is a perspective view showing the semiconductor channel layer 110 located above the fin structure 108.

[0109] Reference Figures 6A to 6G The semiconductor channel layer 110 may comprise, for example, suitable semiconductor materials such as indium zinc oxide (IZO), indium tin oxide (ITO), indium oxide (In2O3), gallium oxide (Ga2O3), indium gallium zinc oxide (IGZO), indium tungsten oxide (IWO), titanium oxide, aluminum-doped zinc oxide (AZO), oxide semiconductor materials, group III-V semiconductor materials (e.g., InP, InAs, GaAs, GaN, GaP, InSb, InGaAs, etc.), alloys thereof, and / or combinations thereof. Other suitable materials for the semiconductor channel layer 110 are also within the scope of this disclosure. The semiconductor channel layer 110 may be composed of a single layer of semiconductor material or may comprise a multilayer structure. In some embodiments, the semiconductor channel layer 110 comprising a multilayer structure may comprise multiple layers of semiconductor materials that may have different compositions. The semiconductor channel layer 110 may be formed by a suitable deposition process as described above.

[0110] Reference Figures 6A to 6CThe semiconductor channel layer 110 may include a plurality of strip segments extending along the horizontal direction hd2 and spaced apart from each other along the horizontal direction hd1. Each strip segment of the semiconductor channel layer 110 may be located above the upper surface 117 of the first electrode 105a and may contact the sidewall 109 of the first electrode 105a (the sidewall 109 is also contacted by the fin structure 108). Each strip segment of the semiconductor channel layer 110 may extend from the sidewall 109 of the first electrode 105a above the upper surface and side surface of the fin structure 108 and above the upper surface of the second dielectric layer 104 adjacent to the upper surface of the fin structure 108, and may contact the sidewall 109 of the second electrode 105b facing the first electrode 105a. Each strip segment of the semiconductor channel layer 110 may also extend above a portion of the upper surface 117 of the second electrode 105b. The combination of a first electrode 105a, a pair of second electrodes 105b located on opposite sides of the first electrode 105a, a pair of fin structures 108 extending between the sidewalls 109 of the first electrode 105a and the sidewalls 109 of each of the second electrodes 105b, and strip segments of the semiconductor channel layer 110 (the strip segments being located above the upper surface 117 and sidewalls 109 of the first electrode 105a and the upper surface 117 and sidewalls 109 of the pair of second electrodes 105b, above the upper surface and side surface of the fin structures 108, and above a portion of the upper surface of the second dielectric layer 104) can form a layer stack 601, 603 on the upper surface of the second dielectric layer 104. Figure 6A , Figure 6D , Figure 6E and Figure 6F As shown, the exemplary structure may include a pair of layer stacks 601, 603, which may be laterally spaced from each other along a horizontal direction hd1. In various embodiments, the fin structure 108 that contacts the sidewall 109 of the second electrode 105b on the periphery of each layer stack 601, 603 may be removed to provide an isolated layer stack 601, 603 above the upper surface of the second dielectric layer 104.

[0111] In various embodiments, the semiconductor channel layer 110 can be formed by depositing a continuous layer of suitable semiconductor material on exemplary structures, including on the upper and side surfaces of the first electrode 105a and the second electrode 105b, on the upper and side surfaces of the fin structure 108, and on the exposed upper surface of the second dielectric layer 104. A patterned mask can be formed on the upper surface of the continuous layer of semiconductor material. Figures 6A to 6G (Not shown in the image), and the exemplary structure can be etched using a patterned mask to remove portions of the continuous layers of semiconductor material exposed through the mask, and to provide, as Figures 6A to 6GThe diagram shows a strip segment of the semiconductor channel layer 110. The etching process can also remove fin structures 108 that contact the sidewalls 109 of the second electrode 105b on the periphery of each layer stack 601, 603. Alternatively, a separate etching process can be used to remove the fin structures 108 that contact the sidewalls 109 of the second electrode 105b on the periphery of the layer stack 601, 603.

[0112] Figure 6C , Figure 6E and Figure 6F The region of contact between the semiconductor channel layer 110 and the sidewall 109 of the first electrode 105a is shown. Figure 6E This is a vertical cross-sectional view of the fin structure 108 and the semiconductor channel layer 110 along a vertical plane of the sidewall 109 where the fin structure 108 and the semiconductor channel layer 110 contact the first electrode 105a. (See image) Figure 6E As shown, the semiconductor channel layer 110 includes a first vertical portion 110a and a second vertical portion 110b extending vertically above the side surface of the fin structure 108 and contacting the upper surface of the second dielectric layer 104. A first horizontal portion 110c of the semiconductor channel layer 110 extends horizontally along the direction hd1 between the first vertical portion 110a and the second vertical portion 110b of the semiconductor channel layer 110. Therefore, the portion of the semiconductor channel layer 110 extending between the respective sidewalls 109 of the first electrode 105a and the respective sidewalls 109 of the second electrode 105b may have a fin-like structure. In various embodiments, both the first vertical portion 110a and the second vertical portion 110b of the semiconductor channel layer 110 may contact the sidewall 109 of the first electrode 105a over the entire vertical height H1 of the first electrode 105a, such as... Figure 6F As shown in the vertical sectional view. Figures 6A to 6G In the illustrated embodiment, the upper surface 117 of the first electrode 105a is substantially coplanar with the upper surface of the fin structure 108, such that the lower surface of the first horizontal portion 110c of the semiconductor channel layer 110 is substantially coplanar with the upper surface 117 of the first electrode 105a. In this exemplary embodiment, the first horizontal portion 110c of the semiconductor channel layer 110 may not contact the sidewall 109 of the first electrode 105a, but may extend along the horizontal direction hd2 beyond the vertical plane of the sidewall 109 of the first electrode 105a, and may contact the upper surface 117 of the first electrode 105a, such as... Figure 6B and Figure 6C As shown in the diagram. In various embodiments, the semiconductor channel layer 110 may cover the entire upper surface 117 of the first electrode 105a.

[0113] Accordingly, in various embodiments, the two opposing sidewalls 109 of the first electrode 105a, contacted by the fin structure 108, may each contact a pair of vertical portions 110a and 110b of the semiconductor channel layer 110 located on opposite sides of the respective fin structure 108. In embodiments, the vertical portions 110a and 110b of the semiconductor channel layer 110 may contact the sidewalls 109 of the first electrode 105a over the entire vertical height H1 of the first electrode 105a. A first horizontal portion 110c of the semiconductor channel layer 110 may extend between the respective vertical portions 110a and 110b of the semiconductor channel layer 110 and over the upper surface of the fin structure 108, and may extend beyond the vertical plane of the sidewalls 109 of the first electrode 105a to contact the upper surface 117 of the first electrode 105a. In embodiments, the first horizontal portion 110c of the semiconductor channel layer 110 may extend over the entire upper surface 117 of the first electrode 105a.

[0114] Similarly, the sidewall 109 of the contact fin structure 108 of the second electrode 105b may also contact a pair of vertical portions 110a and 110b of the semiconductor channel layer 110 located on opposite sides of the respective fin structure 108. In an embodiment, the vertical portions 110a and 110b of the semiconductor channel layer 110 may contact the sidewall 109 over the entire vertical height H1 of the respective second electrode 105b. A first horizontal portion 110c of the semiconductor channel layer 110 may extend between the respective vertical portions 110a and 110b of the semiconductor channel layer 110 and over the upper surface of the respective fin structure 108, and may extend beyond the vertical plane of the sidewall 109 of the second electrode 105b to contact a portion of the upper surface 117 of the respective second electrode 105b.

[0115] In various embodiments, a channel layer 110 is formed over the upper and side surfaces of the fin structure 108 in each of the layer stacks 601 and 603. A pair of vertical portions 110a and 110b of the channel layer 110 can contact the sidewall 109 of the first electrode 105a and the sidewall 109 of each second electrode 105b facing the first electrode 105a. The channel layer 110 can also contact the upper surface 117 of the first electrode 105a and the upper surface 117 of each second electrode 105b in each of the layer stacks 601 and 603. This increases the contact area between the semiconductor channel layer 110 and the source electrode 105b and drain electrode 105a of the subsequently formed TFT device, which can result in an increase in the drive current of the TFT device without requiring any significant increase in the size of the TFT device. Furthermore, since the semiconductor channel layer 110 is deposited on the upper and side surfaces of the fin structure 108 that are in contact with the sidewalls 109 of the electrodes 105a and 105b, misalignment between the semiconductor channel layer 110 and the electrodes 105a and 105b can be avoided, and effective contact between the semiconductor channel layer 110 and each of the electrodes 105a and 105b can be maintained.

[0116] Reference Figure 6A , Figure 6C , Figure 6D and Figure 6G The semiconductor channel layer 110 may also include a recessed portion 111 located between each of the first electrode 105a and the second electrode 105b in each of the layer stacks 601 and 603. Figure 6A As shown, for example, in each of the stacks 601 and 603, the semiconductor channel layer 110 may include a pair of recessed portions 111 located between each of the first electrode 105a and the second electrode 105b.

[0117] Figure 6D It is along Figure 6A The vertical cross-sectional view along line C-C' shows the recessed portion 111 of the semiconductor channel layer 110 in each of the layer stacks 601 and 603. Figure 6G This is a perspective view showing a portion of the semiconductor channel layer 110 and the fin structure 108 located between the first electrode 105a and the second electrode 105b. (Refer to...) Figure 6D and Figure 6GThe semiconductor channel layer 110 may include a first vertical portion 110a located on a first side surface of the fin structure 108, a second vertical portion 110b located on a second side surface of the fin structure 108, and a first horizontal portion 110c extending between the first vertical portion 110a and the second vertical portion 110b on the upper surface of the fin structure 108. The semiconductor channel layer 110 may also include a second horizontal portion 110d extending from the first vertical portion 110a on the upper surface of the second dielectric layer 104, and a third horizontal portion 110e extending from the second vertical portion 110b on the upper surface of the second dielectric layer 104. A void region may be present above the second horizontal portion 110d and the third horizontal portion 110e of the semiconductor channel layer 110, which may form corresponding recesses 111 of the semiconductor channel layer 110 between adjacent electrodes 105a and 105b within each stack 601, 603. Figure 6D and Figure 6E As shown, at each of the recessed portions 111, the width W1 of the first vertical portion 110a and the second vertical portion 110b of the semiconductor channel layer 110 along the horizontal direction hd1 may be smaller than the width W2 of the first vertical portion 110a and the second vertical portion 110b when the first vertical portion 110a and the second vertical portion 110b of the semiconductor channel layer 110 contacts the first electrode 105a and the second electrode 105b.

[0118] Figure 7A This is a top view of an exemplary structure during the process of forming multiple TFT devices, showing a gate dielectric layer 112 formed on the upper and side surfaces of each of the layer stacks 601 and 603 and on the upper surface of the second dielectric layer 104. Figure 7B It is along Figure 7A A vertical sectional view of an exemplary structure along line A-A'. Figure 7C It is along Figure 7A A vertical cross-sectional view of an exemplary structure of line B-B' in the diagram. Figure 7D It is along Figure 7A A vertical cross-sectional view of an exemplary structure with line C-C' in the figure. Figure 7E It is along Figure 7A A vertical cross-sectional view of an exemplary structure of line D-D' in the diagram. Figure 7F It is along Figure 7A A vertical sectional view of an exemplary structure along line E-E'. Figure 7G This is a perspective view showing the gate dielectric layer 112 located above the fin structure 108.

[0119] Reference Figures 7A to 7GThe gate dielectric layer 112 may comprise: a suitable dielectric material, such as silicon oxide; and / or a high dielectric constant (high-k) dielectric material, such as silicon nitride, hafnium oxide, hafnium silicon oxide, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, tantalum oxide, aluminum oxide, hafnium dioxide-alumina, zirconium oxide, etc. Other suitable dielectric materials are also within the scope of this disclosure.

[0120] In various embodiments, the gate dielectric layer 112 can be formed by conformally depositing dielectric material over the exposed sidewalls 109 and upper surface 117 of the second electrode 105b, over the upper surface and side surfaces of the semiconductor channel layer 110, over the exposed sidewalls of the first electrode 105a, and over the exposed upper surface of the second dielectric layer 104. (Refer to...) Figure 7A , Figure 7C , Figure 7D and Figure 7G In various embodiments, the gate dielectric layer 112 may partially fill the recessed portion 111 of the semiconductor channel layer 110 located between each of the first electrode 105a and the second electrode 105b in each of the stacks 601 and 603. (See also...) Figure 7A and Figure 7F The gate dielectric layer 112 may be located on the sidewalls 701 of electrodes 105a and 105b extending parallel to the horizontal direction hd1, and may cover the upper surface of the second dielectric layer 104 located between adjacent layer stacks 601 and 603. (Refer to...) Figure 7E and Figure 7F A gap 703 may exist between the vertically extending portions of the gate dielectric layer 112 located above the respective side surfaces of adjacent layer stacks 601 and 603. The gate dielectric layer 112 may be deposited using a suitable deposition process as described above.

[0121] Figure 8A This is a top view of an exemplary structure during the process of forming multiple TFT devices, showing word line fill material 113 and dielectric material layer 114 formed on gate dielectric layer 112. Figure 8B It is along Figure 8A A vertical sectional view of an exemplary structure along line A-A'. Figure 8C It is along Figure 8A A vertical cross-sectional view of an exemplary structure of line B-B' in the diagram. Figure 8D It is along Figure 8A A vertical cross-sectional view of an exemplary structure with line C-C' in the figure. Figure 8E It is along Figure 8A A vertical cross-sectional view of an exemplary structure of line D-D' in the diagram. Figure 8F It is along Figure 8A A vertical sectional view of an exemplary structure along line E-E'. Figure 8G This is a perspective view showing the letter line filling material 113 located above the fin structure 108.

[0122] In various embodiments, dielectric layer 114 may comprise any suitable dielectric material as described above. Word line fill material 113 may comprise a sacrificial material that may be removed during a subsequent process of forming the conductive gate electrode (also referred to as the "word line") of the TFT device. Word line fill material 113 may comprise any suitable sacrificial material, which may be a dielectric material, a semiconductor material, or other suitable material. In various embodiments, during a subsequent etching process to remove word line fill material 113, word line fill material 113 may comprise a material with higher etch selectivity than the materials of gate dielectric layer 112 and dielectric layer 114. In a non-limiting embodiment, word line fill material 113 may be composed of a nitride material such as silicon nitride, and dielectric layer 114 may be composed of an oxide material such as silicon oxide. Other suitable materials for word line fill material 113 and dielectric layer 114 are also contemplated within the scope of this disclosure.

[0123] Reference Figures 8A to 8G The character line fill material 113 may include a plurality of strip segments 113a and 113b extending along the horizontal direction hd1 and spaced apart from each other along the horizontal direction hd2. Each strip segment 113a and 113b of the character line fill material 113 may extend continuously over a plurality of layers stacked adjacent to each other along the horizontal direction hd1 601 and 603. (See reference...) Figure 8A , Figure 8B , Figure 8C , Figure 8D , Figure 8E and Figure 8G Strip segments 113a and 113b can contact the gate dielectric layer 112 and can be superimposed on the fin structures 108 in each of the stacks 601 and 603. Strip segments 113a and 113b can also be superimposed on the fin-shaped portions of the semiconductor channel layer 110 and on the portions of the first electrode 105a and the second electrode 105b that contact the corresponding fin structures 108. (Refer to...) Figure 8A , Figure 8C , Figure 8D and Figure 8G The strip segments 113a and 113b of the line fill material 113 can fill the remaining volume of the recessed portion 111 between the first electrode 105a and the adjacent second electrode 105b in each of the layer stacks 601 and 603. (Refer to...) Figure 8E The strip segments 113a and 113b of the line filler material 113 may also fill the gap 703 between adjacent layer stacks 601 and 603 near the interface between the fin structure 108 and each of the electrodes 105a and 105b.

[0124] Reference Figure 8A , Figure 8B , Figure 8C and Figure 8F The remaining portions of the exemplary structure not covered by the word line fill material 113 segments 113a and 113b can be covered by the dielectric material layer 114. The dielectric material layer 114 can be deposited on top of the gate dielectric layer 112 and can cover portions of the upper and side surfaces of the second electrode 105b, portions of the channel layer 110, and portions of the upper and side surfaces of the first electrode 105a. (Refer to...) Figure 8F The dielectric material layer 114 can fill part of the gap 703 between adjacent layer stacks 601 and 603.

[0125] In various embodiments, the word line fill material 113 can be formed by depositing a continuous layer of word line fill material 113 over the gate dielectric layer 112. A patterned mask can be formed over the upper surface of the continuous layer of word line fill material 113. Figures 8A to 8G (not shown in the image), and the exemplary structure can be etched using a patterned mask to remove portions of the continuous layers of word line fill material 113 exposed through the mask and provide, as shown in the image. Figures 8A to 8G The word line fill material 113 shown is composed of discrete strip segments 113a, 113b. An etching process can expose the gate dielectric layer 112 in areas of the exemplary structure not covered by the patterned mask. The etching process can use etching chemicals that have higher etch selectivity for the word line fill material 113 relative to the material of the gate dielectric layer 112. In various embodiments, the etch rate of the word line fill material 113 during the etching process can be at least 5 times greater than the etch rate of the gate dielectric layer 112 during the etching process, for example, at least 10 times greater (including 100 times or more). After the etching process, the patterned mask can be removed using a suitable process (e.g., by ashing or by dissolution using a solvent).

[0126] Following the etching process, a dielectric material layer 114 may be deposited over the exposed portion and side surfaces of the gate dielectric layer 112, and optionally over the upper surfaces of the strip segments 113a and 113b of the word line fill material 113. A planarization process, such as chemical mechanical polishing (CMP), may be optionally used to remove the dielectric material layer 114 from the upper surfaces of the strip segments 113a and 113b and provide, for example, a planarization process. Figures 8A to 8G The exemplary structure shown is shown.

[0127] Figure 9AThis is a top view of an exemplary structure during the process of forming multiple TFT devices, showing multiple electrodes 115a, 115b (e.g., multiple word lines) spaced apart and laterally surrounded by a dielectric material layer 114. Figure 9B It is along Figure 9A A vertical sectional view of an exemplary structure along line A-A'. Figure 9C It is along Figure 9A A vertical cross-sectional view of an exemplary structure of line B-B' in the diagram. Figure 9D It is along Figure 9A A vertical cross-sectional view of an exemplary structure with line C-C' in the figure. Figure 9E It is along Figure 9A A vertical cross-sectional view of an exemplary structure of line D-D' in the diagram. Figure 9F This is a perspective view showing the electrode 115 (e.g., word line) located above the fin structure 108.

[0128] In various embodiments, electrodes 115a, 115b (e.g., word lines) may comprise any suitable conductive material, such as copper (Cu), aluminum (Al), zirconium (Zr), titanium (Ti), titanium nitride (TiN), tungsten (W), tantalum (Ta), tantalum nitride (TaN), molybdenum (Mo), ruthenium (Ru), palladium (Pd), platinum (Pt), cobalt (Co), nickel (Ni), iridium (Ir), iron (Fe), beryllium (Be), chromium (Cr), antimony (Sb), osmium (Os), thorium (Th), vanadium (V), alloys thereof, and combinations thereof. Other suitable conductive materials for electrodes 115a, 115b (e.g., word lines) are also contemplated within the scope of this disclosure.

[0129] Reference Figures 9A to 9F Electrodes 115a and 115b (e.g., word lines) may extend along the horizontal direction hd1 and may be spaced apart from each other along the horizontal direction hd2. Each electrode 115a and 115b (e.g., word lines) may extend continuously over multiple layers stacked adjacent to each other along the horizontal direction hd1 601 and 603. Electrodes 115a and 115b (e.g., word lines) may be surrounded by a dielectric material layer 114 on the lateral side surfaces of electrodes 115a and 115b (e.g., word lines). (Refer to...) Figures 9A to 9F Electrodes 115a and 115b (e.g., word lines) may contact the gate dielectric layer 112 and may be overlaid on the fin structures 108 in each of the stacks 601 and 603. Electrodes 115a and 115b (e.g., word lines) may be overlaid on portions of the upper and side surfaces of the semiconductor channel layer 110 and may serve as gate electrodes for a subsequently formed TFT device. Electrodes 115a and 115b (e.g., word lines) may also be overlaid on portions of the first electrode 105a and the second electrode 105b that contact the corresponding fin structures 108. (See reference...) Figure 9A , Figure 9C , Figure 9D and Figure 9F Electrodes 115a and 115b (e.g., word lines) may fill the remaining volume of the recessed portion 111 located between adjacent first electrodes 105a and second electrodes 105b in each of the layer stacks 601 and 603. The portions of electrodes 115a and 115b (e.g., word lines) located within the recessed portion 111 may be surrounded by a gate dielectric layer 112 and a semiconductor channel layer 110 on the three side surfaces and the bottom surface of electrodes 115a and 115b (e.g., word lines). (Refer to...) Figure 9E Electrodes 115a, 115b (e.g. word lines) may also fill the gap 703 between adjacent layer stacks 601 and 603 near the interface between fin structure 108 and each of electrodes 105a and 105b.

[0130] In various embodiments, electrodes 115a, 115b (e.g., word lines) can be formed by selectively removing word line fill material 113 from an exemplary structure using an etching process such as a wet etching process. The etching process may use etching chemistry that has higher etch selectivity for word line fill material 113 relative to the materials of gate dielectric layer 112 and dielectric material layer 114. In various embodiments, the etch rate of word line fill material 113 during the etching process may be at least 5 times greater than the etch rate of gate dielectric layer 112 and dielectric material layer 114 during the etching process, for example, at least 10 times greater (including 100 times or more). The etching process may provide a plurality of trenches extending along a horizontal direction hd1 and spaced apart from each other along a horizontal direction hd2. Gate dielectric layer 112 may be exposed on the bottom surface of the trenches and dielectric material layer 114 may be exposed along the side surfaces of the trenches.

[0131] Following the etching process, electrodes 115a, 115b (e.g., word lines) can be formed by depositing conductive material on the exemplary structure using a suitable deposition process as described above. The conductive material can be deposited on the upper surface of the dielectric material layer 114 and can fill trenches. After depositing the conductive material, a planarization process, such as chemical mechanical polishing (CMP), can be used to remove the conductive material from the upper surface of the dielectric material layer 114, thereby providing, for example, a... Figures 9A to 9F Discrete electrodes 115a, 115b (e.g. word lines) are shown surrounded laterally by a dielectric material layer 114.

[0132] Figure 10A This is a top view of an exemplary structure according to an embodiment of the present disclosure, showing a plurality of TFT devices 120a to 120d including vias 116a to 116d formed through a dielectric material layer 114. Figure 10B It is along Figure 10A A vertical sectional view of an exemplary structure along line A-A'. Figure 10C It is along Figure 10AA vertical cross-sectional view of an exemplary structure of line B-B' in the diagram.

[0133] Reference Figures 10A to 10C It can be on the upper surface of the dielectric material layer 114 and Figures 9A to 9F Additional dielectric material is deposited on the upper surfaces of the electrodes 115a and 115b (e.g., word lines) to form a dielectric material layer 114 on the side and upper surfaces of the electrodes 115a and 115b (e.g., word lines), and the electrodes 115a and 115b (e.g., word lines) are embedded in the dielectric material layer 114. The additional dielectric material may be... Figures 9A to 9F The dielectric material layer 114 shown may be the same material, or may be a different dielectric material. Additional dielectric material may be deposited using a suitable deposition method as described above.

[0134] A plurality of vias 116a, 116b, 116c, and 116d can be formed through the dielectric material layer 114 and the gate dielectric layer 112, wherein each via 116a, 116b, 116c, and 116d can contact the upper surface of the second electrode 105b. In various embodiments, a patterned mask can be formed on the upper surface of the dielectric material layer 114. Figures 10A to 10C (Not shown) to form vias 116a to 116d, wherein the patterned mask includes openings through the mask corresponding to the locations of the vias to be subsequently formed. A photolithography technique can be used to pattern a mask, which may include a photoresist layer and / or a hard mask, to form openings through the mask corresponding to the locations of the vias to be subsequently formed. An etching process, such as anisotropic etching, can be used to etch the exemplary structure through the mask to form via openings extending through the dielectric material layer 114 and the gate dielectric layer 112. The etching process can expose the upper surface of the second electrode 105b at the bottom of each of the via openings. After the etching process, the patterned mask can be removed using a suitable process (e.g., by ashing or by dissolution using a solvent). A conductive material can then be deposited over the upper surface of the dielectric material layer 114 and within the via openings to contact the exposed upper surface of the second electrode 105b. The conductive material can be any suitable conductive material, such as copper (Cu), aluminum (Al), zirconium (Zr), titanium (Ti), titanium nitride (TiN), tungsten (W), tantalum (Ta), tantalum nitride (TaN), molybdenum (Mo), ruthenium (Ru), palladium (Pd), platinum (Pt), cobalt (Co), nickel (Ni), iridium (Ir), iron (Fe), beryllium (Be), chromium (Cr), antimony (Sb), osmium (Os), thorium (Th), vanadium (V), alloys thereof, and combinations thereof. Other suitable conductive materials for vias 116a to 116d are also within the scope of this disclosure. The conductive material can be deposited using a suitable deposition process as described above.

[0135] A planarization process, such as chemical mechanical planarization (CMP), can be used to remove portions of the conductive material from the upper surface of the dielectric material layer 114, thereby leaving discrete vias 116a to 116d extending through the dielectric material layer 114 and the gate dielectric layer 112 and contacting the second electrode 105b.

[0136] Refer again Figures 10A to 10C The illustration shows a plurality of thin-film transistor (TFT) devices 120a, 120b, 120c, and 120d according to embodiments of the present disclosure. Each TFT device 120a to 120d includes a first electrode 105a, which may be a drain electrode, a second electrode 105b, which may be a source electrode, and a fin structure 108 extending between and contacting the respective sidewalls 109 of the first electrode 105a and the second electrode 105b. The fin structure 108 may include a dielectric layer 106. A fin-shaped semiconductor channel layer 110 may be located above the upper surface and side surfaces of the fin structure 108 and may extend continuously between the respective sidewalls 109 of the first electrode 105a and the second electrode 105b. The fin-shaped semiconductor channel layer 110 may include a first vertical portion 110a and a second vertical portion 110b located on opposite side surfaces of the fin structure 108, the first vertical portion 110a and the second vertical portion 110b contacting each of a corresponding sidewall 109 of the first electrode 105a and a corresponding sidewall 109 of the second electrode 105b. In an embodiment, the first vertical portion 110a and the second vertical portion 110b of the semiconductor channel layer 110 may contact the corresponding sidewall 109 of the first electrode 105a and the corresponding sidewall 109 of the second electrode 105b over the entire vertical height of each of the sidewalls 109. In an embodiment, the semiconductor channel layer may additionally include a first horizontal portion 110c extending over the upper surface of the fin structure 108 and contacting at least a portion of the upper surface of each of the first electrode 105a and the second electrode 105b.

[0137] Each of the TFT devices 120a to 120d may further include: electrodes 115a and 115b (e.g., gate electrodes) located above the fin structure 108 and the fin-shaped semiconductor channel layer 110; and a gate dielectric layer 112 located between the fin-shaped semiconductor channel layer 110 and the electrodes 115a and 115b (e.g., gate electrodes). A first metal feature 103 (e.g., a via) may contact the first electrode 105a and second vias 116a to 116d may contact the second electrode 105b.

[0138] exist Figures 10A to 10CIn the illustrated embodiment, each stack of layers 601 and 603 of the exemplary structure can form part of two TFT devices 120a, 120b, 120c, and 120d that can share a common electrode 105a (which may be a drain electrode). Alternatively, the common electrode 105a can be a source electrode, and each of the second electrodes 105b can be a drain electrode. (Refer to...) Figures 10A to 10C The first electrode 105a of the stacked layers 601 can be used as a common electrode for TFT devices 120a and 120b, and the first electrode 105a of the stacked layers 603 can be used as a common electrode for TFT devices 120c and 120d.

[0139] Figures 11A to 14D This is a sequential view of an exemplary structure during the process of forming a plurality of TFT devices according to alternative embodiments of the present disclosure. Figures 11A to 14D The TFT device in the illustrated embodiment is similar to that described above. Figures 2A to 10C The difference in the TFT device of the illustrated embodiment lies in that the first horizontal portion 110c of the fin semiconductor channel layer 110 can contact the corresponding sidewall 109 of the first electrode 105a and the corresponding sidewall 109 of the second electrode 105b. Therefore, the fin semiconductor channel layer 110 can contact the corresponding sidewall 109 of the first electrode 105a and the corresponding sidewall 109 of the second electrode 105b over a region of the semiconductor channel layer 110, said region of the semiconductor channel layer 110 having a shape resembling an inverted "U," which includes at least a portion of the first vertical portion 110a, the second vertical portion 110b, and the first horizontal portion 110c of the semiconductor channel layer 110. This can further increase the contact area between the channel layer 110 of the TFT device and the source electrode 105b and drain electrode 105a, which can provide an additional increase in the drive current for the TFT device.

[0140] Figure 11A This is a top view of an exemplary structure during the process of forming a plurality of TFT devices according to various embodiments of the present disclosure, showing a first electrode 105a and a second electrode 105b embedded in a third dielectric layer 106. Figure 11B It is along Figure 11A A vertical sectional view of an exemplary structure along line A-A'. Figure 11C It is along Figure 11A A vertical cross-sectional view of an exemplary structure of line B-B' in the diagram.

[0141] Figures 11A to 11C The exemplary structure shown can be obtained from Figures 3A to 3CThe exemplary structure shown is derived from the example structure, therefore repeated discussion of the structure and details of the metal feature 101 (e.g., bit line), the first dielectric layer 102, the second dielectric layer 104, the metal feature 103 (e.g., via), the first electrode 105a, the second electrode 105b and the third dielectric layer 106 is omitted. Figures 11A to 11C The exemplary structure shown is similar to Figures 3A to 3C The difference in the exemplary structure shown is that the upper surface of the third dielectric layer 106 is recessed in the vertical direction relative to the upper surface 117 of the first electrode 105a and the upper surface 117 of the second electrode 105b. In various embodiments, reference may be made as above. Figures 3A to 3C The first electrode 105a and the second electrode 105b are formed. An etching process can then be performed to recess the upper surface of the third dielectric layer 106 relative to the upper surfaces 117 of the first electrode 105a and the second electrode 105b. The etching process may use etching chemicals that have higher etch selectivity to the material of the third dielectric layer 106 relative to the materials of the first electrode 105a and the second electrode 105b. In various embodiments, the etching rate of the third dielectric layer 106 during the etching process may be at least 5 times greater than the etching rates of the first electrode 105a and the second electrode 105b during the etching process, for example, at least 10 times greater (including 100 times or more). After the etching process, the upper portions of the sidewalls 109 of the first electrode 105a and the second electrode 105b may be exposed above the recessed upper surface of the third dielectric layer 106.

[0142] Figure 12A This is a top view of an exemplary structure during the process of forming multiple TFT devices, showing a patterned mask 107 located above the upper surface of the first electrode 105a, the upper surface of the second electrode 105b, and the upper surface of the third dielectric layer 106. Figure 12B It is along Figure 12A A vertical sectional view of an exemplary structure along line A-A'.

[0143] Figure 12A and Figure 12B The exemplary structure shown can be obtained from Figures 4A to 4C The exemplary structure shown is derived from the example structure, and therefore repeated discussion of the structure and details of the patterned mask 107 is omitted. The exemplary structure includes strip mask portions 107a and 107b extending above the upper surface of the third dielectric layer 106, a central portion of the first electrode 105a, and a central portion of the pair of second electrodes 105b located on the opposite side of the first electrode 105a. Figure 12A and Figure 12B The exemplary structure shown is similar to Figures 4A to 4CThe difference in the exemplary structure shown is that the strip mask portions 107a and 107b of the patterned mask 107 extend over the exposed portion of the sidewall 109 of the first electrode 105a and the exposed portion of the sidewall 109 of the second electrode 105b.

[0144] Figure 13A This is a top view of an exemplary structure during a process that forms multiple TFT devices after an etching process, in which a portion of the third dielectric layer 106 is removed and a fin structure 108 is formed that contacts the first electrode 105a and the second electrode 105b. Figure 13B It is along Figure 13A A vertical sectional view of an exemplary structure along line A-A'. Figure 13C It is along Figure 13A A vertical cross-sectional view of an exemplary structure of line B-B' in the diagram. Figure 13D It is along Figure 13A A vertical cross-sectional view of an exemplary structure with line C-C' in the figure.

[0145] Reference Figures 13A to 13D Etching processes can be used to pass through Figures 12A to 12B The patterned mask 107 shown etches the exemplary structure. The etching process may use etching chemicals that have higher etch selectivity to the material of the third dielectric layer 106 relative to the materials of the first electrode 105a and the second electrode 105b. In various embodiments, the etching rate of the third dielectric layer 106 during the etching process may be at least 5 times greater than the etching rates of the first electrode 105a and the second electrode 105b during the etching process, for example, at least 10 times greater (including 100 times or more). The etching process may etch through the portion of the third dielectric layer 106 exposed by the patterned mask 107 and expose the upper surface of the second dielectric layer 104. In embodiments where the second dielectric layer 104 is absent, the etching process may expose the upper surface of the first dielectric layer 102.

[0146] The strip mask portions 107a and 107b of the patterned mask 107 protect portions of the third dielectric layer 106 from etching during the etching process. After the etching process, the remaining portion of the third dielectric layer 106 can form fin structures 108 extending along the horizontal direction hd2. Each fin structure 108 can contact at least one sidewall 109 of the electrodes 105a and 105b. (Refer to...) Figure 13A and Figure 13B The fin structure 108 can extend continuously between the sidewalls 109 of the electrodes 105a and 105b that are adjacent to each other along the horizontal direction hd2. (Refer to...) Figure 13A , Figure 13C and Figure 13DThe width of the fin structure 108 along the horizontal direction hd1 may be smaller than the width of the electrodes 105a and 105b along the horizontal direction hd1. Therefore, after the etching process, the portion of the sidewall 109 of the electrodes 105a and 105b that is contacted by the fin structure 108 may be included on the exposed surface of the fin structure 108 in the lateral direction.

[0147] Reference Figure 13C and Figure 13D The vertical height H2 of the fin structure 108 may be less than the vertical height H1 of each of the first electrode 105a and the second electrode 105b. Therefore, the fin structure 108 may contact the sidewall 109 of the first electrode 105a and the sidewall 109 of the second electrode 105b, such that a portion of the sidewall 109 located above the upper surface of the fin structure 108 is exposed.

[0148] Figure 14A This is a top view of an exemplary structure during the process of forming multiple TFT devices, showing a semiconductor channel layer 110 formed on the upper surface of the first electrode 105a and the upper surface of the second electrode 105b, as well as on the upper surface and side surface of the fin structure 108. Figure 14B It is along Figure 14A A vertical sectional view of an exemplary structure along line A-A'. Figure 14C It is along Figure 14A A vertical cross-sectional view of an exemplary structure of line B-B' in the diagram. Figure 14D It is along Figure 14A A vertical cross-sectional view of an exemplary structure with line C-C' in the figure.

[0149] Figures 14A to 14C The exemplary structure shown can be obtained from Figures 6A to 6C The exemplary structure shown is derived from this, therefore repeated discussion of the structure and details of the semiconductor channel layer 110 is omitted. Figures 14A to 14C The exemplary structure shown is similar to Figures 6A to 6G The difference in the exemplary structure shown is that the vertical height of the fin structure 108 is smaller than the vertical height of the first electrode 105a and the second electrode 105b. Therefore, a portion of the sidewalls 109 of the first electrode 105a and the second electrode 105b located above the upper surface of the fin structure 108 is exposed and contacted by the semiconductor channel layer 110 during the formation of the semiconductor channel layer 110.

[0150] Figure 14D This is a vertical cross-sectional view of the fin structure 108 and the semiconductor channel layer 110 along the vertical plane of the sidewall 109 of the fin structure 108 and the semiconductor channel layer 110 that contacts the first electrode 105a. (See image) Figure 14DAs shown, the vertical height of the fin structure 108 is less than the vertical height H1 of the first electrode 105a. Accordingly, the fin-shaped portion of the semiconductor channel layer 110 contacts the sidewall 109 of the first electrode 105a over the entire region of the semiconductor channel layer 110 below the dashed line 140. Therefore, the fin-shaped semiconductor channel layer 110 can contact the corresponding sidewall 109 of the first electrode 105a and the corresponding sidewall 109 of the second electrode 105b over the region of the semiconductor channel layer 110, which has a shape resembling an inverted "U," including at least a portion of the first vertical portion 110a, the second vertical portion 110b, and the first horizontal portion 110c of the semiconductor channel layer 110. This can further increase the contact area between the channel layer 110 of the TFT device and the source electrode 105b and drain electrode 105a, which can provide an additional increase in the drive current for the TFT device. The semiconductor channel layer 110 is located in Figure 14D The portion above the dashed line 140 shown may extend beyond the vertical plane of the sidewall 109 of electrodes 105a and 105b and may extend above and contact the upper surface 117 of electrodes 105a and 105b.

[0151] Reference Figures 14A to 14C The portion of the semiconductor channel layer 110 located between the corresponding sidewall 109 of the first electrode 105a and the corresponding sidewall 109 of the second electrode 105a may include a recessed upper surface 141. The recessed upper surface 141 of the semiconductor channel layer 110 may be an additional location of the recessed portion 111 of the semiconductor channel layer 110, and may correspond to the location of the recessed portion 111 of the semiconductor channel layer 110, as referred to above. Figures 6A to 6G As stated above.

[0152] Subsequently, it can be implemented Figures 7A to 10C The processing steps shown are as follows: a gate dielectric layer 112 is formed on the stacked layers 601 and 603 and on the upper surface of the second dielectric layer 104; a word line filling material 113 and a dielectric material layer 114 are formed on the gate dielectric layer 112; electrodes 115a and 115b (e.g., word lines) are formed on the fin-shaped portions of the fin structure 108 and the semiconductor channel layer 110; and vias 116a to 116d are formed to contact the upper surface 117 of the second electrode 105b, thereby providing a plurality of TFT devices 120a to 120d.

[0153] Figure 15 This illustrates the formation of thin-film transistor (TFT) devices according to various embodiments of the present disclosure (e.g. Figures 10A to 10C A flowchart of the steps of method 1500 for the TFT devices 120a to 120d shown. (Refer to...) Figures 1A to 3C and Figure 15In step 1501 of method 1500, a source electrode 105b and a drain electrode 105a may be formed on the supporting substrate 8. (Refer to...) Figures 4A to 5B , Figures 11A to 13D and Figure 15 In step 1503 of method 1500, a fin structure 108 may be formed between the source electrode 105b and the drain electrode 105a, wherein the fin structure 108 contacts the corresponding sidewall 109 of the source electrode 105b and the corresponding sidewall 109 of the drain electrode 105a. (Refer to...) Figures 6A to 6G and Figures 14A to 15 In step 1505 of method 1500, a semiconductor channel layer 110 may be formed on the upper surface, first side surface, and second side surface of the fin structure 108. The semiconductor channel layer 110 includes a first vertical portion 110a located on the first side surface of the fin structure 108 and a second vertical portion 110b located on the second side surface of the fin structure 108. The first vertical portion 110a and the second vertical portion 110b of the semiconductor channel layer 110 contact the corresponding sidewall 109 of the source electrode 105b and the corresponding sidewall 109 of the drain electrode 105a. (Refer to...) Figures 7A to 7G and Figure 15 In step 1507 of method 1500, a gate dielectric layer 112 may be formed over the semiconductor channel layer 110. (Refer to...) Figures 8A to 9F In step 1509 of method 1500, electrodes 115a and 115b (e.g., gate electrodes) may be formed on the gate dielectric layer 112.

[0154] Referring to all the drawings and various embodiments of this disclosure, a semiconductor structure (e.g., TFT devices 120a to 120d) may include: a source electrode 105b; a drain electrode 105a; a fin structure 108 extending between and contacting the respective sidewalls 109 of the source electrode 105b and the drain electrode 105a; and a semiconductor channel layer 110 located above the upper surface, first side surface, and second side surface of the fin structure 108, wherein the semiconductor channel... The channel layer 110 may include a first vertical portion 110a located on a first side surface of the fin structure 108 and a second vertical portion 110b located on a second side surface of the fin structure 108, and the first vertical portion 110a and the second vertical portion 110b of the semiconductor channel layer 110 contact the corresponding sidewall 109 of the source electrode 105b and the corresponding sidewall 109 of the drain electrode 105a; a gate dielectric layer 112 located on the semiconductor channel layer 110; and electrodes 115a and 115b (e.g., gate electrodes) located on the gate dielectric layer 112.

[0155] In an embodiment, the fin structure 108 includes a dielectric layer 106.

[0156] In another embodiment, the first vertical portion 110a and the second vertical portion 110b of the semiconductor channel layer 110 contact the corresponding sidewalls 109 of the source electrode 105b and the corresponding sidewalls 109 of the drain electrode 105a over the entire vertical height H1 of the corresponding sidewalls 109 of the source electrode 105b and the corresponding sidewalls 109 of the drain electrode 105a.

[0157] In another embodiment, the upper surface of the fin structure 108 is coplanar with the upper surface 117 of the source electrode 105b and the upper surface 117 of the drain electrode 105a, and the semiconductor channel layer 110 includes a first horizontal portion 110c located above the upper surface of the fin structure 108 and extending between a first vertical portion 110a and a second vertical portion 110b of the semiconductor channel layer 110, and the first horizontal portion 110c of the semiconductor channel layer 110 extends beyond the vertical plane of the respective sidewall 109 of the source electrode 105b and the vertical plane of the respective sidewall 109 of the drain electrode 105a and contacts the respective upper surface 117 of each of the source electrode 105b and the drain electrode 105a.

[0158] In another embodiment, the vertical height H2 of the upper surface of the fin structure 108 is less than the vertical height H1 of the upper surface 117 of the source electrode 105b and the upper surface 117 of the drain electrode 105a, and the semiconductor channel layer 110 includes a first horizontal portion 110c located above the upper surface of the fin structure 108 and extending between the first vertical portion 110a and the second vertical portion 110b of the semiconductor channel layer 110, and the first horizontal portion 110c of the semiconductor channel layer 110 contacts the corresponding sidewall 109 of the source electrode 105b and the corresponding sidewall 109 of the drain electrode 105a above the upper surface of the fin structure 108.

[0159] In another embodiment, a first horizontal portion 110c of the semiconductor channel layer 110 extends beyond the vertical plane of the respective sidewall 109 of the source electrode 105b and the vertical plane of the respective sidewall 109 of the drain electrode 105a and contacts the respective upper surface 117 of each of the source electrode 105b and the drain electrode 105a.

[0160] In another embodiment, the semiconductor channel layer 110 includes a recessed portion 111 located between the source electrode 105b and the drain electrode 105a, wherein the width dimensions of the first vertical portion 110a and the second vertical portion 110b of the semiconductor channel layer 110 located in the recessed portion 111 are smaller than the width dimensions of the first vertical portion 110a and the second vertical portion 110b of the semiconductor channel layer 110 when the first vertical portion 110a and the second vertical portion 110b of the semiconductor channel layer 110 contact the corresponding sidewall 109 of the source electrode 105b and the corresponding sidewall 109 of the drain electrode 105a.

[0161] In another embodiment, the semiconductor channel layer 110 includes a second horizontal portion 110d extending from a first vertical portion 110a and a third horizontal portion 110e extending from the second vertical portion 110b, wherein the recessed portion 111 includes a void region of the semiconductor channel layer 110 located above the second horizontal portion 110d and the third horizontal portion 110e.

[0162] In another embodiment, the gate dielectric layer 112 extends into and partially fills the recessed portion 111 of the semiconductor channel layer 110, and the electrodes 115a, 115b (e.g., gate electrodes) fill the remaining volume of the recessed portion 111, such that the portions of the electrodes 115a, 115b (e.g., gate electrodes) located within the recessed portion 111 are surrounded by the gate dielectric layer 112 and the semiconductor channel layer 110 on the three side surfaces and the bottom surface of the electrodes 115a, 115b (e.g., gate electrodes).

[0163] In another embodiment, the source electrode 105b, drain electrode 105a, fin structure 108, semiconductor channel layer 110 and gate dielectric layer 112 are located above and in contact with the upper surface of the first dielectric layer 104. The semiconductor structure also includes a metal feature 103 (e.g., a via) coupled to a metal feature 101 (e.g., a bit line). The metal feature 103 (e.g., a via) extends through the first dielectric layer 104 and contacts the lower surface of the drain electrode 105a.

[0164] In another embodiment, the semiconductor structure further includes a second dielectric layer 114 and second vias 116a to 116d. The second dielectric layer 114 is located above the upper surface and the lateral surface of electrodes 115a and 115b (e.g., gate electrodes). The second vias 116a to 116d extend through the second dielectric layer 114 and the gate dielectric layer 112 and contact the upper surface 117 of the source electrode 105b.

[0165] An additional embodiment relates to a semiconductor structure comprising: stacked layers 601, 603, situated above a dielectric layer 104; a gate dielectric layer 112, situated above the upper and side surfaces of the stacked layers 601, 603; and a pair of electrodes 115a, 115b (e.g., conductive word lines), situated above the gate dielectric layer 112 and extending along a second horizontal direction hd1 perpendicular to a first horizontal direction hd2, and laterally spaced from each other along the first horizontal direction hd2, wherein each of the pair of electrodes 115a, 115b (e.g., conductive word lines) extends above a corresponding fin structure 108 of a pair of fin structures 108 of the stacked layers 601, 603, the stacked layers 601, 603 comprising: a first electrode 105a, and a pair of second electrodes 105b, situated on opposite sides of the first electrode 105a and extending along the first horizontal direction hd2 and the first... Electrodes 105a are laterally spaced; a pair of fin structures 108 extend along a first horizontal direction hd2, each of the pair of fin structures 108 extending between and contacting the sidewall 109 of the first electrode 105a and the sidewall of the corresponding second electrode 105b in the pair of second electrodes 105b; and a semiconductor channel layer 110 located on the upper surface 117 and sidewall 109 of the second electrode 105b in the pair of second electrodes 105b, the upper surface and side surface of the first fin structure 108 in the pair of fin structures 108, the upper surface 117 and two opposing sidewalls 109 of the first electrode 105a, the upper surface and side surface of the other fin structure 108 in the pair of second electrodes 105b, and the sidewall 109 and upper surface 117 of the other second electrode 105b in the pair of second electrodes 105b.

[0166] In this embodiment, the layer stacks 601 and 603 are first layer stacks 601 and 603, and the semiconductor structure further includes second layer stacks 601 and 603 located above the dielectric layer 104 and laterally spaced from the first layer stacks 601 and 603 along the second horizontal direction hd1. The second layer stacks 601 and 603 include: a first electrode 105a; and a pair of second electrodes 105b located on opposite sides of the first electrode 105a and laterally spaced from the first electrode 105a along the first horizontal direction hd2. Open; a pair of fin structures 108 extending along a first horizontal direction hd2, each of the pair of fin structures 108 extending between and contacting the sidewall 109 of the first electrode 105a and the sidewall of the corresponding second electrode 105b of the pair of second electrodes 105b; and a semiconductor channel layer 110 located on the upper surface 117 and sidewall of the second electrode 105b of the pair of second electrodes 105b. 109. The upper and side surfaces of the fin structure 108 in the pair of fin structures 108, the upper surface 117 and two opposing sidewalls 109 of the first electrode 105a, the upper and side surfaces of the other fin structure 108 in the pair of fin structures 108, and the sidewall 109 and upper surface 117 of the other second electrode 105b in the pair of second electrodes 105b, wherein the gate dielectric layer 112 is above the upper and side surfaces of the second layer stack 601, 603 and the dielectric layer 104 is located on the first Extending above the upper surface between the first stack 601, 603 and the second stack 601, 603, each of the electrodes 115a, 115b (e.g., conductive word lines) in the pair of electrodes 115a, 115b (e.g., conductive word lines) extends continuously along the second horizontal direction hd1 above the corresponding fin structure 108 in the pair of fin structures 108 of the first stack 601, 603 and the corresponding fin structure 108 in the pair of fin structures 108 of the second stack 601, 603.

[0167] In another embodiment, the semiconductor structure further includes: a first conductive metal feature 101 (e.g., a bit line) extending along a first horizontal direction hd2 below the lower surface of the first stack 601, 603; a second conductive metal feature 101 (e.g., a bit line) extending along the first horizontal direction hd2 below the lower surface of the second stack 601, 603; a first metal feature 103 (e.g., a via) extending from the first conductive metal feature 101 (e.g., the bit line) through the dielectric layer 104 and contacting the lower surface of the first electrode 105a of the first stack 601, 603; and a second metal feature 103 (e.g., a via) extending from the second conductive metal feature 101 (e.g., the bit line) through the dielectric layer 104 and contacting the lower surface of the first electrode 105a of the second stack 601, 603.

[0168] In another embodiment, the semiconductor structure further includes: a second dielectric layer 114 located above the gate dielectric layer 112 and laterally surrounding the pair of electrodes 115a, 115b (e.g., conductive word lines); and a plurality of vias 116a to 116d extending through the second dielectric layer 114 and the gate dielectric layer 112 and contacting the upper surface 117 of each of the second electrodes 105b of the first layer stack 601, 603 and the second electrodes 105b of the second layer stack 601, 603.

[0169] In another embodiment, the first electrode 105a of the first layer stack 601, 603 is a common electrode of the first pair of thin-film transistor devices 120a to 120d, and the first electrode 105a of the second layer stack 601, 603 is a common electrode of the second pair of thin-film transistor devices 120a to 120d.

[0170] An additional embodiment relates to a method of fabricating a semiconductor structure, the method comprising: forming a source electrode 105b and a drain electrode 105a on a supporting substrate 8; forming a fin structure 108 between the source electrode 105b and the drain electrode 105a, wherein the fin structure 108 contacts a corresponding sidewall 109 of the source electrode 105b and a corresponding sidewall 109 of the drain electrode 105a; and forming a semiconductor channel layer 110 on the upper surface of the fin structure 108 and on a first side surface and a second side surface, wherein the semiconductor channel layer 110 includes a substrate... A first vertical portion 110a on the first side surface of the fin structure 108 and a second vertical portion 110b on the second side surface of the fin structure 108, wherein the first vertical portion 110a and the second vertical portion 110b of the semiconductor channel layer 110 contact the corresponding sidewall 109 of the source electrode 105b and the corresponding sidewall 109 of the drain electrode 105a; a gate dielectric layer 112 is formed on the semiconductor channel layer 110 and electrodes 115a and 115b (e.g., gate electrodes) are formed on the gate dielectric layer 112.

[0171] In an embodiment, forming the source electrode 105b and drain electrode 105a includes: forming a dielectric layer 106 on a support substrate 8; forming a patterned mask including openings on the dielectric layer 106, the openings passing through the mask to expose the upper surface of the dielectric layer 106 at the bottom of each opening in the openings; performing an etching process through the patterned mask to remove portions of the dielectric layer 106 exposed through the openings in the mask, thereby providing openings through the dielectric layer 106; removing the patterned mask; and forming a conductive material within the openings through the dielectric layer to provide the source electrode 105b and drain electrode 105a laterally surrounded by the dielectric layer 106.

[0172] In another embodiment, forming the fin structure 108 includes: forming a patterned mask 107 on the upper surface of the source electrode 105b, the upper surface of the drain electrode 105a, and the upper surface of the dielectric layer 106, wherein the patterned mask 107 includes strip mask portions 107a and 107b located on the upper surface of the dielectric layer 106 extending between the source electrode 105b and the drain electrode 105a; and performing an etching process through the patterned mask 107 to remove portions of the dielectric layer 106 exposed by the patterned mask 107, wherein the remaining portion of the dielectric layer 106 below the strip mask portions 107a and 107b of the patterned mask 107 forms the fin structure 108 extending between the source electrode 105b and the drain electrode 105a.

[0173] In another embodiment, the method further includes performing an additional etching process to recess the upper surface of the dielectric layer 106 in the vertical direction relative to the upper surface 117 of the source electrode 105b and the upper surface 117 of the drain electrode 105a, such that the vertical height H2 of the fin structure 108 is less than the vertical height H1 of the source electrode 105b and the drain electrode 105a, wherein the semiconductor channel layer 110 further includes a horizontal portion 110c extending above the upper surface of the fin structure 108 between the first vertical portion 110a and the second vertical portion 110b of the semiconductor channel layer 110, and the horizontal portion 110c of the semiconductor channel layer 110 contacts the corresponding sidewall 109 of the source electrode 105b and the corresponding sidewall 109 of the drain electrode 105a.

[0174] In another embodiment, a semiconductor structure includes: a source electrode; a drain electrode; a fin structure extending between and contacting the respective sidewalls of the source electrode and the drain electrode; a semiconductor channel layer located above an upper surface, a first side surface, and a second side surface of the fin structure, wherein the semiconductor channel layer includes a first vertical portion located above the first side surface of the fin structure and a second vertical portion located above the second side surface of the fin structure, and wherein the first vertical portion and the second vertical portion of the semiconductor channel layer contact the respective sidewalls of the source electrode and the drain electrode; a gate dielectric layer located above the semiconductor channel layer; and a gate electrode located above the gate dielectric layer.

[0175] In another embodiment, the fin structure comprises a dielectric material.

[0176] In another embodiment, the first vertical portion and the second vertical portion of the semiconductor channel layer contact the respective sidewalls of the source electrode and the respective sidewalls of the drain electrode over the entire vertical height of the respective sidewalls of the source electrode and the drain electrode.

[0177] In another embodiment, the upper surface of the fin structure is coplanar with the corresponding upper surface of each of the source electrode and the drain electrode, and wherein the semiconductor channel layer includes a first horizontal portion located above the upper surface of the fin structure and extending between the first vertical portion and the second vertical portion of the semiconductor channel layer, and the first horizontal portion of the semiconductor channel layer extends beyond the vertical plane of each of the corresponding sidewalls of the source electrode and the corresponding sidewalls of the drain electrode and contacts the corresponding upper surface of each of the source electrode and the drain electrode.

[0178] In another embodiment, the vertical height of the upper surface of the fin structure is less than the vertical height of the corresponding upper surface of each of the source electrode and the drain electrode, and wherein the semiconductor channel layer includes a first horizontal portion located above the upper surface of the fin structure and extending between the first vertical portion and the second vertical portion of the semiconductor channel layer, and the first horizontal portion of the semiconductor channel layer contacts the corresponding sidewall of the source electrode and the corresponding sidewall of the drain electrode above the upper surface of the fin structure.

[0179] In another embodiment, the first horizontal portion of the semiconductor channel layer extends beyond the vertical plane of each of the respective sidewalls of the source electrode and the drain electrode to contact the respective upper surface of each of the source electrode and the drain electrode.

[0180] In another embodiment, the semiconductor channel layer includes a recessed portion located between the source electrode and the drain electrode, wherein the width dimensions of the first vertical portion and the second vertical portion of the semiconductor channel layer located in the recessed portion are smaller than the width dimensions of each of the first vertical portion and the second vertical portion of the semiconductor channel layer when the first vertical portion and the second vertical portion of the semiconductor channel layer contact the respective sidewalls of the source electrode and the respective sidewalls of the drain electrode.

[0181] In another embodiment, the semiconductor channel layer includes a second horizontal portion extending from the first vertical portion and a third horizontal portion extending from the second vertical portion, wherein the recessed portion includes a void region of the semiconductor channel layer located above the second horizontal portion and the third horizontal portion.

[0182] In another embodiment, the gate dielectric layer extends into and partially fills the recessed portion of the semiconductor channel layer, and the gate electrode fills the remaining volume of the recessed portion such that the portion of the gate electrode located within the recessed portion is surrounded by the gate dielectric layer and the semiconductor channel layer on the three side surfaces and the bottom surface of the gate electrode.

[0183] In another embodiment, the source electrode, the drain electrode, the fin structure, the semiconductor channel layer, and the gate dielectric layer are located above and in contact with the upper surface of the first dielectric layer. The semiconductor structure further includes a via coupled to a line, the via extending through the first dielectric layer and in contact with the lower surface of the drain electrode.

[0184] In another embodiment, a second dielectric layer and a second via are further included, the second dielectric layer being located above the upper surface and the side surface of the gate electrode, and the second via extending through the second dielectric layer and the gate dielectric layer and contacting the upper surface of the source electrode.

[0185] In another embodiment, a semiconductor structure includes: a layer stack over a first dielectric layer, the layer stack including: a first electrode; a pair of second electrodes located on opposite sides of the first electrode and laterally spaced from the first electrode along a first horizontal direction; a pair of fin structures extending along the first horizontal direction, each of the pair of fin structures extending between and contacting a sidewall of the first electrode and a sidewall of a corresponding second electrode of the pair of second electrodes; and a semiconductor channel layer located on the upper surface and sidewall of one of the second electrodes of the pair of second electrodes. The stack includes the upper and side surfaces of the first fin structure, the upper surface and two opposing sidewalls of the first electrode, the upper and side surfaces of the second fin structure in the pair of fin structures, and the sidewall and upper surface of the other second electrode in the pair of second electrodes; a gate dielectric layer located on the upper and side surfaces of the stack; and a pair of conductive word lines located on the gate dielectric layer and extending along a second horizontal direction perpendicular to the first horizontal direction, and laterally spaced from each other along the first horizontal direction, wherein each of the pair of conductive word lines extends on the corresponding fin structure in the pair of stacked fin structures.

[0186] In another embodiment, the layer stack includes a first layer stack, and the semiconductor structure further includes a second layer stack located above the first dielectric layer and laterally spaced from the first layer stack along a second horizontal direction, the second layer stack including: a first electrode; a pair of second electrodes located on opposite sides of the first electrode and laterally spaced from the first electrode along the first horizontal direction; a pair of fin structures extending along the first horizontal direction, each of the pair of fin structures extending between and contacting the sidewall of the first electrode and the sidewall of the corresponding second electrode of the pair of second electrodes; and a semiconductor channel layer located at the pair of second electrodes. The upper surface and sidewall of a second electrode, the upper surface and sidewall of a fin structure in the pair of fin structures, the upper surface and two opposing sidewalls of the first electrode, the upper surface and sidewall of the other fin structure in the pair of fin structures, and the sidewall and upper surface of the other second electrode in the pair of second electrodes, wherein: the gate dielectric layer extends over the upper surface and sidewall of the second layer stack and over the upper surface of the first dielectric layer located between the first layer stack and the second layer stack, and each of the pair of conductive word lines extends continuously along the second horizontal direction over the corresponding fin structure in the pair of fin structures in the first layer stack and the corresponding fin structure in the pair of fin structures in the second layer stack.

[0187] In another embodiment, it further includes: a first conductive bit line extending along the first horizontal direction below the lower surface of the first layer stack; a second conductive bit line extending along the first horizontal direction below the lower surface of the second layer stack; a first via extending from the first conductive bit line through the first dielectric layer and contacting the lower surface of the first electrode of the first layer stack; and a second via extending from the second conductive bit line through the first dielectric layer and contacting the lower surface of the first electrode of the second layer stack.

[0188] In another embodiment, it further includes: a second dielectric layer located above the gate dielectric layer and laterally surrounding the pair of conductive word lines; and a plurality of third vias extending through the second dielectric layer and the gate dielectric layer and contacting the respective upper surfaces of the pair of second electrodes of the first layer stack and the pair of second electrodes of the second layer stack.

[0189] In another embodiment, the first electrode of the first stacked layer includes a common electrode of a first pair of transistor devices, and the first electrode of the second stacked layer includes a common electrode of a second pair of transistor devices.

[0190] In another embodiment, a method of fabricating a semiconductor structure includes: forming a source electrode and a drain electrode on a supporting substrate; forming a fin structure between the source electrode and the drain electrode, wherein the fin structure contacts a corresponding sidewall of the source electrode and a corresponding sidewall of the drain electrode; forming a semiconductor channel layer on an upper surface, a first side surface, and a second side surface of the fin structure, wherein the semiconductor channel layer includes a first vertical portion located on the first side surface of the fin structure and a second vertical portion located on the second side surface of the fin structure, and the first vertical portion and the second vertical portion of the semiconductor channel layer contact the corresponding sidewall of the source electrode and the corresponding sidewall of the drain electrode; forming a gate dielectric layer on the semiconductor channel layer; and forming a gate electrode on the gate dielectric layer.

[0191] In another embodiment, forming the source electrode and the drain electrode includes: forming a dielectric layer on the support substrate; forming a first patterned mask including openings on the dielectric layer, the openings passing through the first patterned mask to expose an upper surface of the dielectric layer at the bottom of each opening in the openings; performing an etching process through the first patterned mask to remove portions of the dielectric layer exposed through the openings in the first patterned mask, thereby providing openings through the dielectric layer; removing the first patterned mask; and forming a conductive material within the openings through the dielectric layer to provide the source electrode and the drain electrode laterally surrounded by the dielectric layer.

[0192] In another embodiment, forming the fin structure includes: forming a second patterned mask over the upper surface of the source electrode, the upper surface of the drain electrode, and the upper surface of the dielectric layer, wherein the second patterned mask includes a strip mask portion of the dielectric layer located over the upper surface extending between the source electrode and the drain electrode; and performing an etching process through the second patterned mask to remove portions of the dielectric layer exposed through the second patterned mask, wherein the remaining portion of the dielectric layer below the strip mask portion of the second patterned mask forms the fin structure extending between the source electrode and the drain electrode.

[0193] In another embodiment, the method further includes performing an additional etching process to recess the upper surface of the dielectric layer in a vertical direction relative to the upper surface of the source electrode and the upper surface of the drain electrode, such that the vertical height of the fin structure is less than the vertical height of the source electrode and the drain electrode, wherein the semiconductor channel layer further includes a horizontal portion extending above the upper surface of the fin structure between the first vertical portion and the second vertical portion of the semiconductor channel layer, and the horizontal portion of the semiconductor channel layer contacts the respective sidewall of the source electrode and the respective sidewall of the drain electrode.

[0194] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or realize the same advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to this document without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor structure, comprising: Source electrode; Drain electrode; A fin structure extends between and contacts the respective sidewalls of the source electrode and the drain electrode. A semiconductor channel layer is located on the upper surface, the first side surface and the second side surface of the fin structure, wherein the semiconductor channel layer includes a first vertical portion located on the first side surface of the fin structure and a second vertical portion located on the second side surface of the fin structure, and wherein the first vertical portion and the second vertical portion of the semiconductor channel layer contact the corresponding sidewall of the source electrode and the corresponding sidewall of the drain electrode. A gate dielectric layer is located above the semiconductor channel layer; as well as The gate electrode is located on the gate dielectric layer.

2. The semiconductor structure according to claim 1, wherein the fin structure comprises a dielectric material.

3. The semiconductor structure of claim 1, wherein the first vertical portion and the second vertical portion of the semiconductor channel layer contact the respective sidewalls of the source electrode and the respective sidewalls of the drain electrode over the entire vertical height of the respective sidewalls of the source electrode and the drain electrode.

4. The semiconductor structure of claim 1, wherein the upper surface of the fin structure is coplanar with a corresponding upper surface of each of the source electrode and the drain electrode, and wherein the semiconductor channel layer includes a first horizontal portion located above the upper surface of the fin structure and extending between a first vertical portion and a second vertical portion of the semiconductor channel layer, and the first horizontal portion of the semiconductor channel layer extends beyond the vertical plane of each of the corresponding sidewalls of the source electrode and the drain electrode and contacts the corresponding upper surface of each of the source electrode and the drain electrode.

5. The semiconductor structure of claim 1, wherein the vertical height of the upper surface of the fin structure is less than the vertical height of the respective upper surface of each of the source electrode and the drain electrode, and wherein the semiconductor channel layer includes a first horizontal portion located above the upper surface of the fin structure and extending between the first vertical portion and the second vertical portion of the semiconductor channel layer, and the first horizontal portion of the semiconductor channel layer contacts the respective sidewall of the source electrode and the respective sidewall of the drain electrode above the upper surface of the fin structure.

6. The semiconductor structure of claim 5, wherein the first horizontal portion of the semiconductor channel layer extends beyond the vertical plane of each of the respective sidewalls of the source electrode and the drain electrode to contact the respective upper surface of each of the source electrode and the drain electrode.

7. The semiconductor structure of claim 1, wherein the semiconductor channel layer includes a recessed portion located between the source electrode and the drain electrode, wherein the width dimension of the first vertical portion and the width dimension of the second vertical portion of the semiconductor channel layer located in the recessed portion are smaller than the width dimension of each of the first vertical portion and the second vertical portion of the semiconductor channel layer when the first vertical portion and the second vertical portion of the semiconductor channel layer contact the respective sidewalls of the source electrode and the respective sidewalls of the drain electrode.

8. The semiconductor structure of claim 7, wherein the semiconductor channel layer includes a second horizontal portion extending from the first vertical portion and a third horizontal portion extending from the second vertical portion, wherein the recessed portion includes a void region of the semiconductor channel layer located above the second horizontal portion and the third horizontal portion.

9. The semiconductor structure of claim 7, wherein the gate dielectric layer extends into and partially fills the recessed portion of the semiconductor channel layer, and the gate electrode fills the remaining volume of the recessed portion such that a portion of the gate electrode located within the recessed portion is surrounded by the gate dielectric layer and the semiconductor channel layer on three side surfaces and the bottom surface of the gate electrode.

10. The semiconductor structure of claim 1, wherein the source electrode, the drain electrode, the fin structure, the semiconductor channel layer and the gate dielectric layer are located above the upper surface of the first dielectric layer and in contact with the upper surface of the first dielectric layer, and the semiconductor structure further includes a via coupled to a line, the via extending through the first dielectric layer and in contact with the lower surface of the drain electrode.

11. The semiconductor structure of claim 10, further comprising a second dielectric layer and a second via, the second dielectric layer being located above the upper surface and the lateral surface of the gate electrode, and the second via extending through the second dielectric layer and the gate dielectric layer and contacting the upper surface of the source electrode.

12. A semiconductor structure, comprising: A layer stack, situated above a first dielectric layer, comprising: First electrode; A pair of second electrodes are located on opposite sides of the first electrode and are laterally spaced from the first electrode along a first horizontal direction; A pair of fin structures extending along the first horizontal direction, each fin structure extending between and contacting the sidewall of the first electrode and the sidewall of the corresponding second electrode in the pair of second electrodes; and A semiconductor channel layer is located on the upper surface and sidewall of one of the pair of second electrodes, the upper surface and sidewall of the first fin structure of the pair of fin structures, the upper surface and two opposite sidewalls of the first electrode, the upper surface and sidewall of the second fin structure of the pair of fin structures, and the sidewall and upper surface of the other of the pair of second electrodes. A gate dielectric layer is located above the top and side surfaces of the layer stack; and A pair of conductive word lines, located above the gate dielectric layer and extending along a second horizontal direction perpendicular to the first horizontal direction, and laterally spaced from each other along the first horizontal direction, wherein each of the pair of conductive word lines extends above a corresponding fin structure in the pair of fin structures of the layer stack.

13. The semiconductor structure of claim 12, wherein the layer stack comprises a first layer stack, and the semiconductor structure further comprises a second layer stack located above the first dielectric layer and laterally spaced from the first layer stack along the second horizontal direction, the second layer stack comprising: First electrode; A pair of second electrodes are located on opposite sides of the first electrode and are laterally spaced from the first electrode along the first horizontal direction; A pair of fin structures extending along the first horizontal direction, each of the pair of fin structures extending between and contacting the sidewall of the first electrode and the sidewall of the corresponding second electrode in the pair of second electrodes; as well as A semiconductor channel layer is located above the upper surface and sidewall of one of the pair of second electrodes, the upper surface and sidewall of one of the pair of fin structures, the upper surface and two opposing sidewalls of the first electrode, the upper surface and sidewall of the other fin structure in the pair of fin structures, and the sidewall and upper surface of the other of the pair of second electrodes, wherein: The gate dielectric layer extends over the upper and side surfaces of the second layer stack and over the upper surface of the first dielectric layer located between the first and second layer stacks. Each of the pair of conductive character lines extends continuously along the second horizontal direction above the corresponding fin structure in the first layer of the stacked pair of fin structures and the corresponding fin structure in the second layer of the stacked pair of fin structures.

14. The semiconductor structure according to claim 13, further comprising: The first conductive bit line extends along the first horizontal direction below the lower surface of the first layer stack; The second conductive bit line extends along the first horizontal direction below the lower surface of the second layer stack; The first via extends from the first conductive bit line through the first dielectric layer and contacts the lower surface of the first electrode stacked in the first layer; as well as The second via extends from the second conductive bit line through the first dielectric layer and contacts the lower surface of the first electrode of the second stacked layers.

15. The semiconductor structure according to claim 14, further comprising: A second dielectric layer is located above the gate dielectric layer and surrounds the pair of conductive word lines laterally. as well as Multiple third vias extend through the second dielectric layer and the gate dielectric layer and contact the respective upper surfaces of each of the pair of second electrodes of the first layer stack and the pair of second electrodes of the second layer stack.

16. The semiconductor structure of claim 15, wherein the first electrode of the first stacked layer includes a common electrode of a first pair of transistor devices, and the first electrode of the second stacked layer includes a common electrode of a second pair of transistor devices.

17. A method for fabricating a semiconductor structure, comprising: The source electrode and drain electrode are formed on the supporting substrate; A fin structure is formed between the source electrode and the drain electrode, wherein the fin structure contacts the corresponding sidewall of the source electrode and the corresponding sidewall of the drain electrode. A semiconductor channel layer is formed on the upper surface, the first side surface and the second side surface of the fin structure, wherein the semiconductor channel layer includes a first vertical portion located on the first side surface of the fin structure and a second vertical portion located on the second side surface of the fin structure, and the first vertical portion and the second vertical portion of the semiconductor channel layer contact the corresponding sidewall of the source electrode and the corresponding sidewall of the drain electrode. A gate dielectric layer is formed on the semiconductor channel layer; as well as A gate electrode is formed on the gate dielectric layer.

18. The method of claim 17, wherein forming the source electrode and the drain electrode comprises: A dielectric layer is formed on the supporting substrate; A first patterned mask including openings is formed on the dielectric layer, the openings passing through the first patterned mask to expose the upper surface of the dielectric layer at the bottom of each opening in the openings; An etching process is performed using the first patterned mask to remove portions of the dielectric layer exposed through the openings in the first patterned mask, thereby providing openings through the dielectric layer. Remove the first patterned mask; as well as Conductive material is formed within the opening through the dielectric layer to provide the source electrode and the drain electrode that are laterally surrounded by the dielectric layer.

19. The method of claim 18, wherein forming the fin structure comprises: A second patterned mask is formed on the upper surface of the source electrode, the upper surface of the drain electrode, and the upper surface of the dielectric layer, wherein the second patterned mask includes a strip mask portion located on the upper surface of the dielectric layer extending between the source electrode and the drain electrode; as well as An etching process is performed using the second patterned mask to remove the portion of the dielectric layer exposed by the second patterned mask, wherein the remaining portion of the dielectric layer below the strip mask portion of the second patterned mask forms the fin structure extending between the source electrode and the drain electrode.

20. The method of claim 19, further comprising: An additional etching process is performed to make the upper surface of the dielectric layer recessed in the vertical direction relative to the upper surface of the source electrode and the upper surface of the drain electrode, such that the vertical height of the fin structure is less than the vertical height of the source electrode and the drain electrode, wherein the semiconductor channel layer further includes a horizontal portion extending above the upper surface of the fin structure between the first vertical portion and the second vertical portion of the semiconductor channel layer, and the horizontal portion of the semiconductor channel layer contacts the respective sidewall of the source electrode and the respective sidewall of the drain electrode.

Images