Electrostatic clamping system and method of operation thereof

Abstract

An electrostatic clamping system and method of operation thereof are provided. An electrostatic clamping system includes a platen, an electrostatic electrode associated with the platen, and a seal cap having a recessed lower surface defining a cavity and having a seal ring extending around a periphery of the lower surface, the seal cap being movable relative to the platen to move onto and away from a wafer disposed on the platen, the seal cap further having an inlet valve for introducing a gas into a space between a body of the seal cap and the wafer.

Description

Technical Field

[0001] The embodiments of this disclosure generally relate to the field of semiconductor device fabrication, and more specifically, to a system and method that facilitates the effective clamping of semiconductor wafers. Background Technology

[0002] During ion implantation and certain other processes performed during semiconductor device fabrication, semiconductor wafers are typically placed on a flat platen. Generally, semiconductor wafers are held to the platen by electrostatic clamping, where a voltage is applied to electrodes embedded in the platen, and the resulting electric field holds the semiconductor wafer to the platen. Electrostatic clamping is preferred over mechanical clamping because mechanical clamping can damage and / or contaminate the semiconductor wafer.

[0003] The ability of a clamping plate to securely hold a semiconductor wafer to itself via electrostatic clamping depends heavily on the proximity of the bottom surface of the wafer to the top surface of the clamping plate. Ideally, these surfaces are flat and positioned in continuous contact with each other. In some cases, the semiconductor wafer may warp (e.g., deflection on the order of 20 milliinches), creating a relatively large gap between the bottom surface of the wafer and the top surface of the clamping plate. This can result in weak or ineffective electrostatic clamping. This problem can be exacerbated if the semiconductor wafer and clamping plate are exposed to high-temperature or low-temperature processes (e.g., during high-temperature or low-temperature ion implantation), where incoherent deflection of the wafer and clamping plate can increase the size of the gap between them.

[0004] Therefore, minimizing the surface-to-surface proximity between the semiconductor wafer and the pressure plate is desirable for ensuring a secure electrostatic clamping between them. The current improvements may be useful considering these and other factors. Summary of the Invention

[0005] The present invention is provided to introduce a series of concepts in a simplified form. The present invention is not intended to identify key or essential features of the claimed subject matter, nor is it intended to help determine the scope of the claimed subject matter.

[0006] According to a non-limiting embodiment of this disclosure, an electrostatic clamping system may include: a pressure plate; an electrostatic electrode associated with the pressure plate; and a sealing cap having a recessed lower surface defining a cavity and a sealing ring extending around the periphery of the lower surface, the sealing cap being movable relative to the pressure plate to move onto and away from a wafer disposed on the pressure plate, the sealing cap further having an inlet valve for introducing gas into the space between the cap body of the sealing cap and the wafer.

[0007] According to another non-limiting embodiment of this disclosure, an electrostatic clamping system may include: a pressure plate; an electrostatic electrode embedded within the pressure plate; a sealing cap having a recessed lower surface defining a cavity and a sealing ring extending around the periphery of the lower surface, the sealing cap being coupled to a hinged support arm adapted to selectively move the sealing cap onto a wafer disposed on the pressure plate and remove the sealing cap from the wafer, the sealing cap further having an inlet valve for introducing gas into a space between the cap body of the sealing cap and the wafer; and a temperature management system integral with the sealing cap and including a temperature control element operable to change the temperature of the sealing cap.

[0008] According to a non-limiting embodiment of this disclosure, a method of operating an electrostatic clamping system (including a pressure plate, an electrostatic electrode associated with the pressure plate, and a sealing cap having a recessed lower surface defining a cavity and a sealing ring extending around the periphery of the lower surface) may include: placing a semiconductor wafer on the pressure plate, wherein the semiconductor wafer is warped and presents a recessed bottom surface to the pressure plate; lowering the sealing cap onto the semiconductor wafer, wherein the sealing ring engages with a top surface of the semiconductor wafer and forms a fluid-impermeable seal between the cap body and the semiconductor wafer; and pumping gas into the space between the cap body and the semiconductor wafer via an inlet valve in the cap body. Attached Figure Description

[0009] For example, various embodiments of the disclosed device will now be described with reference to the accompanying drawings, in which:

[0010] Figure 1 This is a cross-sectional side view showing an electrostatic clamping system according to an exemplary embodiment of the present disclosure.

[0011] Figure 2 It is shown Figure 1 The diagram shows a cross-sectional side view of an electrostatic clamping system, in which a semiconductor wafer is mounted on the clamping plate of the electrostatic clamping system.

[0012] Figure 3 It is shown Figure 1The diagram shows a cross-sectional side view of an electrostatic clamping system, in which the system's sealing cap is lowered to engage with a semiconductor wafer.

[0013] Figure 4 This illustrates the operation used to flatten a semiconductor wafer. Figure 1 The cross-sectional side view of the electrostatic clamping system shown.

[0014] Figure 5 It is shown Figure 1 The diagram shows a cross-sectional side view of the electrostatic clamping system, in which the system's sealing cap has been removed to allow for further processing of a flat semiconductor wafer that is electrostatically clamped and mounted on the system's pressure plate.

[0015] Figure 6 This is a flowchart illustrating a method of operating an electrostatic clamping system according to an exemplary embodiment of the present disclosure. Detailed Implementation

[0016] The embodiments will now be described more fully below with reference to the accompanying drawings, in which some embodiments are illustrated. The subject matter of this disclosure may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. These embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the subject matter to those skilled in the art. Throughout the drawings, like numbers refer to like elements.

[0017] Reference Figure 1 The image shows a cross-sectional side view illustrating an electrostatic clamping system 10 (hereinafter “System 10”) according to an exemplary embodiment of the present disclosure. System 10 is provided to establish a tight clearance relationship between a support surface (or multiple surfaces) of a pressure plate 12 and the bottom surface of a warped or bent semiconductor wafer disposed on the pressure plate 12, to facilitate effective electrostatic clamping between the support surface (or multiple surfaces) and the bottom surface, as further described below.

[0018] The platen 12 of system 10 may be similar to a conventional platen commonly used in ion processing systems (e.g., ion implantation systems, ion etching systems, etc.) for supporting and firmly holding a semiconductor wafer to be processed. The platen 12 may be a generally flat, disc-shaped body and may be disposed within a processing chamber 13. In various embodiments, the platen 12 may include a plurality of vertically extending mesas 16 for engaging with the bottom surface of a semiconductor wafer disposed on the platen 12. This disclosure is not limited in this respect. For example, alternative embodiments of the platen 12 are contemplated, wherein the mesas 16 are omitted and instead a generally flat top surface is provided for the platen 12.

[0019] In various embodiments, the pressure plate 12 may include a back-side gas seal 17 (hereinafter “BSG seal 17”). The BSG seal 17 may be an annular member (e.g., an O-ring or gasket) disposed on the top surface of the pressure plate 12 and adjacent to the periphery of the pressure plate 12. When a semiconductor wafer is placed on the pressure plate 12 (e.g.) Figures 3 to 5 As shown in the diagram, the BSG seal 17 can engage with the bottom surface of the semiconductor wafer and provide a fluid-impermeable seal between the semiconductor wafer and the pressure plate 12. A back-side gas (e.g., a cooling gas) can be supplied to the sealed space between the semiconductor wafer and the pressure plate 12, thereby facilitating either the transfer of heat to or from the semiconductor wafer in a manner familiar to those skilled in the art. This disclosure is not limited in this respect. In various embodiments of this disclosure, the BSG seal 17 may be omitted.

[0020] The pressure plate 12 may also include one or more electrostatic electrodes associated with the pressure plate 12. For example, in Figure 1 In the embodiment of the pressure plate 12 shown, the pressure plate 12 may include an electrostatic electrode 18 disposed at a short distance below the inner platform 16 of the pressure plate 12. The electrostatic electrode 18 may be connected to a power source (not shown) and may be arranged and configured to operate in an electrostatic clamping manner familiar to those skilled in the art. Specifically, by applying a voltage to the electrostatic electrode 18, an electric field may be generated and a semiconductor wafer may be held to the pressure plate 12 by electrostatic force, as further described below.

[0021] As will be understood by those skilled in the art, the pressure plate 12 may also include any of a variety of heating elements (e.g., resistive heating elements or radiative heating elements) for heating or cooling semiconductor wafers disposed on the pressure plate 12 and / or any of a variety of cooling elements (e.g., channels, conduits, tubes, pipes, etc. embedded in or extending through the pressure plate 12 for circulating cooling fluid within the pressure plate 12). Embodiments of such heating and cooling elements in the pressure plate of an ion processing system are well known in the art and will not be described in any further detail herein.

[0022] System 10 may also include a movable sealing cap 26 located within the processing chamber 13 adjacent to the pressure plate 12. Sealing cap 26 may include a dome-shaped or bowl-shaped cap body 27 having a recessed lower surface 28 defining a cavity. In various embodiments, cap body 27 may be formed of aluminum, stainless steel, or ceramic. This disclosure is not limited in this respect. Sealing cap 26 may also include an inlet valve 30 and an outlet valve 32, respectively coupled to the gas supply line 34 and the vacuum line 36, for allowing gas to be introduced into and discharged from the space below cap body 27, as described in more detail below. Sealing cap 26 may also include a sealing ring 37 coupled to the lower peripheral edge of cap body 27. Sealing ring 37 may be an annular member (e.g., an O-ring or gasket) similar to BSG seal 17. When sealing cap 26 is lowered onto the semiconductor wafer, sealing ring 37 may engage with the top surface of the semiconductor wafer and provide a fluid-impermeable seal between the semiconductor wafer and cap body 27. The sealing ring 37 can be formed of any material suitable for establishing a fluid-impermeable seal with the semiconductor wafer when bonded to it. Examples of such materials include, but are not limited to, nitrile rubber, fluoropolymer elastomers, thermoplastic polymers, polyimide plastics, silicone, ethylene propylene, propylene, etc. For high-temperature applications (e.g., where the sealing ring can withstand temperatures exceeding 700 degrees Celsius), the sealing ring 37 can be formed of materials including, but not limited to, ceramics, various metals, silicon, silicon carbide, glass, and glass compounds.

[0023] The sealing cover 26 may also include a temperature control system having one or more temperature control elements 39 for heating and / or cooling the cover body 27 and the sealing ring 37. In various embodiments, the temperature control element 39 may include a resistive heating element, such as wiring, cable, plate, strip, etc., embedded within the sealing cover 26 and connected to one or more power sources (now shown). Additionally or alternatively, the temperature control element 39 may include one or more cooling elements (e.g., channels, conduits, tubes, pipes, conduits, etc. embedded in or extending through the sealing cover 26 for circulating cooling fluid within the sealing cover 26). The temperature control system may also include a temperature sensor 40 (e.g., thermocouple, resistance temperature detector, etc.) for measuring the temperature of the sealing cover 26 and a controller 42 (e.g., microcontroller, application-specific integrated circuit, etc.) connected to the temperature sensor 40 and the temperature control element 39. The controller 42 may be configured to operate the temperature control element 39 to heat or cool the sealing cover 26 until a predetermined target temperature is measured by the temperature sensor 40. For example, controller 42 may be configured to operate temperature control element 39 to heat or cool sealing cap 26 until the temperature of sealing cap 26 is equal to or close to the temperature of pressure plate 12 and / or the temperature of the semiconductor wafer disposed on pressure plate 12 (e.g., within 15 degrees Celsius). This protects pressure plate 12 and / or semiconductor wafer from thermal shock when sealing cap 26 is moved to engage semiconductor wafers as further explained below.

[0024] The sealing cap 26 can be coupled to the inner wall 44 of the processing chamber 13 via a hinged support arm 46 extending between the inner wall 44 and the cap body 27. In an exemplary alternative embodiment, the hinged support arm 46 can couple the cap body 27 to the pressure plate 12 (e.g., Figure 1 (The section of support arm 46 is indicated by the dashed line in the diagram). This disclosure is not limited in this respect. In various embodiments, any type of mechanical arrangement or system capable of moving the sealing cap 26 onto and from the semiconductor wafer disposed on the pressure plate 12, as further described below, may replace support arm 46.

[0025] Support arm 46 is operable to be in contact with Figure 1 The cover 27 is moved in a direction parallel to one or more of the X, Y, and Z axes of the Cartesian coordinate system shown. In various embodiments, the support arm 46 may be thermally isolated from the sealing cover 26 to prevent heat transfer between the support arm 46 and the sealing cover 26. In various examples, this can be achieved by implementing a thermal barrier 50 made of a thermally insulating material (e.g., ceramic, glass, etc.) at or near the junction of the support arm 46 and the cover 27.

[0026] During normal operation of system 10, a semiconductor wafer is introduced into processing chamber 13 and placed on platen 12. Ideally, the semiconductor wafer will be flat or nearly flat and will be positioned smoothly across the platform 16 of platen 12, thus establishing the shortest possible distance between the electrostatic electrode 18 and the entire semiconductor wafer to provide strong electrostatic coupling between the electrostatic electrode 18 and the entire semiconductor wafer. In some cases, the semiconductor wafer (e.g.) Figure 2 The semiconductor wafer 52 shown (hereinafter referred to as "wafer 52") may be warped or bent (e.g., deflected up to 20 thou, and possibly greater than 20 thou), and may present a recessed bottom surface to the pressure plate 12 (e.g., Figure 2 (The deflection of the wafer 52 shown is exaggerated for illustrative purposes.) The resulting gap 54 between the wafer 52 and the pressure plate 12 reduces the electrostatic force acting on the wafer 52, thus resulting in poor electrostatic coupling between the pressure plate 12 and the wafer 52.

[0027] To improve the electrostatic coupling between the pressure plate 12 and the wafer 52, the sealing cover 26 can be lowered onto the wafer 52 via the support arm 46, such as Figure 3 As shown in the diagram. The sealing ring 37 engages with the top surface of the wafer 52 and establishes a fluid-impermeable seal between the cover 27 and the wafer 52. Once the sealing cap 26 is in place and a seal is formed, gas can be pumped into the space 56 between the cover 27 and the wafer 52 via the supply line 34 and the inlet valve 30. In various embodiments, the gas can be an inert gas (e.g., nitrogen, argon, etc.) or a non-inert gas (e.g., hydrogen). This disclosure is not limited in this respect.

[0028] As gas fills space 56, the pressure within space 56 increases and exerts a downward force on wafer 52. Ultimately, the pressure flattens wafer 52, thereby forcing wafer 52 to extend smoothly across mesa 16, as... Figure 4 As shown in the diagram. Therefore, the shortest possible distance is established between the electrostatic electrode 18 and the entire wafer 52, thus facilitating strong electrostatic coupling between the electrostatic electrode 18 and the entire wafer 52. In this respect, electrostatic coupling alone can keep the wafer 52 flatly bonded to the mesa 16. Therefore, gas can be vented from the space 56 to a port outside the processing chamber 13 via the outlet valve 32 and the vacuum line 36. In various embodiments, the vacuum line 36 can be omitted, and gas can be vented directly into the processing chamber 13. This disclosure is not limited in this respect. Finally, the sealing cap 26 can be removed from the wafer 52 and moved away from the wafer 52 by the support arm 46 (e.g., Figure 5 As shown in the figure, the wafer 52 is prepared for subsequent ion processing (e.g., ion implantation, ion etching, etc.).

[0029] Reference Figure 6The flowchart illustrates an exemplary method for implementing the system 10 according to this disclosure to facilitate efficient electrostatic clamping of a warped semiconductor wafer. It will now be combined with... Figures 1 to 5 The method is illustrated by the example of system 10 shown.

[0030] In block 100 of the exemplary method, wafer 52 is introduced into processing chamber 13 of system 10 and placed on pressure plate 12, as follows. Figure 2 As shown in the diagram, the wafer can be warped or bent (e.g., deflected up to 20 thou, and possibly greater than 20 thou), and a recessed bottom surface can be presented to the pressure plate 12 (e.g., Figure 2 The deflection of the chip 52 shown is exaggerated for illustrative purposes.

[0031] At block 110 of the exemplary method, controller 42 is operable temperature control element 39 to heat or cool the sealing cap 26 until the temperature of the sealing cap 26 is equal to or close to the temperature of the pressure plate 12 and / or the temperature of the semiconductor wafer disposed on the pressure plate 12 (e.g., within 15 degrees Celsius). This protects the pressure plate 12 and / or the wafer 52 from thermal shock when the sealing cap 26 is moved to engage with the wafer as further explained above.

[0032] At block 120 of the exemplary method, the sealing cap 26 can be lowered onto the wafer 52 via the support arm 46, as shown below. Figure 3 As shown in the diagram. The sealing ring 37 can engage with the top surface of the wafer 52 and establish a fluid-impermeable seal between the cover 27 and the wafer 52. At block 130 of the method, gas can be pumped into the space 56 between the cover 27 and the wafer 52 via a gas supply line 34 and an inlet valve 30. In various embodiments, the gas can be an inert gas (e.g., nitrogen, argon, etc.) or a non-inert gas (e.g., hydrogen). This disclosure is not limited in this respect. As the gas fills the space 56, the pressure within the space 56 increases and exerts a downward force on the wafer 52. Ultimately, the pressure flattens the wafer 52, thereby forcing the wafer 52 to extend flatly across the mesa 16, as... Figure 4 As shown in the diagram. Therefore, establishing the shortest possible distance between the electrostatic electrode 18 and the entire wafer 52 facilitates strong electrostatic coupling between the electrostatic electrode 18 and the entire wafer 52. At this point, electrostatic coupling alone can maintain the wafer 52 in a flatly bonded position to the mesa 16.

[0033] At block 140 of the exemplary method, gas can be discharged from space 56 to a port outside processing chamber 13 via outlet valve 32 and vacuum line 36. In various embodiments, vacuum line 36 may be omitted, and gas may be discharged directly into processing chamber 13. This disclosure is not limited in this respect. At block 150 of the method, sealing cap 26 can be removed from wafer 52 and moved away from wafer 52 via support arm 46 (e.g., Figure 5 As shown in the figure, the wafer 52 is prepared for subsequent ion processing (e.g., ion implantation, ion etching, etc.).

[0034] As will be understood by those skilled in the art, the system 10 and method described above offer significant advantages over conventional clamping devices and methods for securing semiconductor wafers to a pressure plate. For example, system 10 facilitates effective electrostatic clamping of bent and warped semiconductor wafers. As another advantage, this clamping is achieved with minimal mechanical contact with the semiconductor wafer, thus protecting the wafer from damage or contamination associated with conventional clamping mechanisms and methods.

[0035] The scope of this disclosure is not limited to the specific embodiments described herein. In fact, various other embodiments and modifications of this disclosure, besides those described herein, will become apparent to those skilled in the art from the foregoing description and accompanying drawings. Therefore, these other embodiments and modifications are intended to fall within the scope of this disclosure. Furthermore, although this disclosure has been set forth herein in the context of specific implementations in specific environments for specific purposes, those skilled in the art should recognize that its effectiveness is not limited thereto. Embodiments of this disclosure can be advantageously implemented in any number of environments for any number of purposes. Therefore, the foregoing claims should be interpreted in accordance with the full breadth and spirit of this disclosure as described herein.

Claims

1. An electrostatic clamping system, comprising: Pressure plate; An electrostatic electrode, associated with the pressure plate; as well as A sealing cap has a recessed lower surface defining a cavity and a sealing ring extending around the periphery of the lower surface. The sealing cap is movable relative to the pressure plate to move onto and away from a wafer disposed on the pressure plate. The sealing cap also has an inlet valve for introducing gas into the space between the cap body and the wafer. The sealing cap includes a temperature management system, which includes a temperature control element operable to change the temperature of the sealing cap.

2. The electrostatic clamping system according to claim 1, wherein the gas is selected from nitrogen, argon and hydrogen.

3. The electrostatic clamping system according to claim 1, wherein the sealing cap is coupled to the hinged support arm.

4. The electrostatic clamping system according to claim 3, wherein the hinged support arm is mounted to the inner wall of the processing chamber.

5. The electrostatic clamping system according to claim 3, wherein the hinged support arm is mounted to the pressure plate.

6. The electrostatic clamping system according to claim 3, wherein the hinged support arm is thermally insulated from the sealing cover by a thermally insulating material.

7. The electrostatic clamping system of claim 1, wherein the temperature management system further comprises a controller connected to the temperature control element and configured to operate the temperature control element to change the temperature of the sealing cap until a predetermined temperature is reached, wherein the predetermined temperature differs from the temperature of the pressure plate by within 15 degrees Celsius.

8. The electrostatic clamping system of claim 1, wherein the sealing cover includes an outlet valve for discharging the gas from the space.

9. The electrostatic clamping system according to claim 1, wherein the sealing ring is selected from an O-ring and a washer.

10. An electrostatic clamping system, comprising: Pressure plate; An electrostatic electrode is embedded in the pressure plate; A sealing cap having a recessed lower surface defining a cavity and a sealing ring extending around the periphery of the lower surface, the sealing cap being coupled to a hinged support arm adapted to selectively move the sealing cap onto a wafer disposed on the pressure plate and remove the sealing cap from the wafer, the sealing cap also having an inlet valve for introducing gas into the space between the cap body of the sealing cap and the wafer. as well as A temperature management system, integrated with the sealing cover, includes a temperature control element operable to change the temperature of the sealing cover.

11. A method of operating an electrostatic clamping system, the electrostatic clamping system comprising a pressure plate, an electrostatic electrode associated with the pressure plate, and a sealing cover, the sealing cover having a recessed lower surface defining a cavity and a sealing ring extending around the periphery of the lower surface, the method comprising: A semiconductor wafer is placed on the pressure plate, wherein the semiconductor wafer is warped and presents a concave bottom surface to the pressure plate; The sealing cap is lowered onto the semiconductor wafer, wherein the sealing ring engages with the top surface of the semiconductor wafer and forms a fluid-impermeable seal between the cap body and the semiconductor wafer; as well as Gas is pumped into the space between the cover and the semiconductor wafer via an inlet valve in the cover. The method further includes heating the sealing cap.

12. The method of claim 11, wherein the accumulated pressure in the space between the cover and the semiconductor wafer forces the semiconductor wafer to be flatly joined to the pressure plate.

13. The method of claim 11, further comprising electrostatically clamping the semiconductor wafer to the pressure plate.

14. The method of claim 11, wherein heating the sealing cap comprises: The sealing cap is heated to a temperature within 15 degrees Celsius of the temperature of at least one of the semiconductor wafer and the pressure plate.

15. The method of claim 11, further comprising: The sealing cap is cooled.

16. The method of claim 15, wherein cooling the sealing cap comprises: The sealing cap is cooled to a temperature within 15 degrees Celsius of the temperature of at least one of the semiconductor wafer and the pressure plate.

17. The method of claim 11, further comprising: The gas is discharged from the space between the cover and the semiconductor wafer via an outlet valve in the cover.

18. The method of claim 11, wherein the gas is selected from nitrogen, argon and hydrogen.

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