Wear leveling circuitry for memory and memory

Abstract

The embodiment of the present disclosure discloses a wear leveling circuit applied to a memory and the memory, wherein the circuit comprises: a control module configured to read data write information in the memory and control a leveling module and an address mapping module to perform corresponding operations according to the data write information; the leveling module is configured to update a first parameter and a second parameter in the memory according to the control of the control module in response to the data write information reaching a preset condition, and return the updated first parameter and second parameter to the memory through the control module; and the address mapping module is configured to determine a mapping relationship between a logical storage address and a physical storage address in the memory after the leveling module updates the first parameter and the second parameter each time. The embodiment balances the inconsistency of read-write address distribution, improves the use rate of each physical storage address in the memory, prolongs the use time of the memory, and enhances the durability of the memory.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of data storage, and particularly relates to a wear leveling circuit applied to a memory and the memory. BACKGROUND

[0002] Resistive random access memory (RRAM) is one of the most promising memory technologies. The advantages of RRAM mainly include: easy manufacturing, simple metal-insulator-metal (MIM) structure, excellent scalability, nanosecond speed, long data retention, and compatibility with current CMOS technology. RRAM is a memory based on memristor, and the storage process is roughly as follows: external stimulus (such as voltage) drives ions and changes the local structure of the storage medium, thereby causing the resistance used for subsequent data storage to change. Since the local structure of the storage medium is frequently changed, durability becomes a major problem, although RRAM is reported to have a durability of 1012, which is still insufficient to replace dynamic random access memory (DRAM). RRAM has a fast enough switching speed to replace DRAM, and the materials used to manufacture RRAM are very similar to DRAM, so improving the durability of RRAM is a key challenge. SUMMARY

[0003] To solve the above technical problems, the present disclosure is proposed. Embodiments of the present disclosure provide a wear leveling circuit applied to a memory and the memory.

[0004] According to an aspect of an embodiment of the present disclosure, a wear leveling circuit applied to a memory is provided, comprising:

[0005] a control module configured to read data write information in the memory and control the leveling module and the address mapping module to perform corresponding operations according to the data write information;

[0006] the leveling module configured to, in response to the data write information meeting a preset condition, update a first parameter and a second parameter in the memory according to the control of the control module, and return the updated first parameter and second parameter to the memory through the control module; wherein the first parameter is used to represent a complete migration number of all storage blocks in the memory completing migration operations, and the second parameter is used to represent a physical storage address in the memory completing migration operations in one complete migration operation;

[0007] the address mapping module configured to determine a mapping relationship between a logical storage address and a physical storage address in the memory after the leveling module updates the first parameter and the second parameter each time.

[0008] Optionally, the data write information comprises a data write frequency, and the control module comprises:

[0009] a parameter transmission unit configured to control the equalization module and the address mapping module to perform a reset according to the received reset signal, and read first parameters and second parameters in the memory and transmit the first parameters and the second parameters to the equalization module and the address mapping module;

[0010] a counting unit configured to acquire data read / write signals of the memory, record a data write frequency of the data read / write signals, and start the equalization module in response to the data write frequency reaching a preset condition.

[0011] a table header read / write unit configured to write the updated first parameters and second parameters of the equalization module received to a table header of the memory.

[0012] Optionally, the table header read / write unit is further configured to transmit the updated first parameters and second parameters to the address mapping module.

[0013] Optionally, the equalization module comprises:

[0014] a first updating unit configured to update the first parameters according to a quotient value between a size of an address space in the memory and a size of a storage block in the memory.

[0015] a second updating unit configured to update the second parameters in response to each data read / write signal corresponding to the memory.

[0016] Optionally, the second updating unit is specifically configured to, in response to the second parameters being other than 0, store block shift forward each time the data read / write signal is received, so that the second parameters decrease by a block value; and in response to the second parameters being 0, change the second parameters to a maximum value according to the received data read / write signal; wherein the block value is a number of physical storage addresses included in the storage block, and the maximum value is a maximum physical storage address in all accessible storage blocks in the memory.

[0017] Optionally, the control module is further configured to send a busy signal to an external device when the equalization module updates the first parameters and the second parameters, and control the memory not to receive data read / write signals.

[0018] Optionally, the circuit further comprises:

[0019] a buffer configured to buffer each written data when a data write signal is received, and write all data in the buffer to a storage block determined according to the second parameters in the memory when an amount of data buffered in the buffer reaches the size of the storage block.

[0020] Optionally, the address mapping module comprises:

[0021] a random mapping unit, configured to, in response to the first parameter and the second parameter being updated by the balancing module, process the logical storage address by a random reversible binary matrix to obtain an updated logical storage address, and determine an updated mapping relationship between the updated logical storage address and the physical storage address;

[0022] an address relay unit, configured to receive a data read-write signal, determine a corresponding physical storage address for the updated logical storage address corresponding to the data read-write signal according to the updated mapping relationship, and perform a corresponding read-write operation on the physical storage address in the memory.

[0023] According to another aspect of the embodiments of the present disclosure, a memory is provided, comprising: at least one memory block and a wear leveling circuit applied to the memory as provided in any of the above embodiments;

[0024] The at least one memory block is configured to receive written data according to a data write signal, and read data in a plurality of physical storage addresses one by one according to a data read signal; wherein each of the memory blocks comprises a plurality of the physical storage addresses;

[0025] The wear leveling circuit is configured to balance the number of times of reading and writing data in each of the memory blocks.

[0026] Optionally, the memory is a resistive random memory.

[0027] The wear leveling circuit applied to the memory and the memory provided by the above-mentioned embodiments of the present disclosure comprise a control module configured to read data write information in the memory and control a leveling module and an address mapping module to perform corresponding operations according to the data write information; the leveling module is configured to update a first parameter and a second parameter in the memory according to the control of the control module in response to the data write information reaching a preset condition, and return the updated first parameter and second parameter to the memory through the control module; wherein the first parameter is used to represent the complete moving number of all storage blocks in the memory completing the moving operation, and the second parameter is used to represent the physical storage address in the memory performing the moving operation in one complete moving operation; the address mapping module is configured to determine the mapping relationship between the logical storage address and the physical storage address in the memory after the leveling module updates the first parameter and the second parameter each time; the embodiments of the present disclosure balance the inconsistency of read-write address distribution through the leveling module and the address mapping module, improve the utilization rate of each physical storage address in the memory, avoid the problem that the memory is damaged in advance due to the inconsistency of read-write address, improve the use time of the memory, and enhance the durability of the memory.

[0028] The technical solutions of the present disclosure will be described in further detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0029] The above and other objects, features and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. The drawings provided in the present disclosure serve to provide a further understanding that constitutes a part of the specification and make an explanation of the present disclosure together with the embodiments of the present disclosure, but do not constitute a limitation on the present disclosure. In the drawings, the same reference numerals generally refer to the same components or steps throughout the drawings.

[0030] Figure 1 is a structural schematic diagram of the wear leveling circuit applied to the memory provided by an exemplary embodiment of the present disclosure.

[0031] Figure 2 is a schematic diagram of updating the logical storage address provided by an exemplary embodiment of the present disclosure.

[0032] Figure 3 is a structural schematic diagram of the memory provided by an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0033] Hereinafter, the exemplary embodiments according to the present disclosure will be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments of the present disclosure, and it should be understood that the present disclosure is not limited to the exemplary embodiments described herein.

[0034] It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of this disclosure.

[0035] Those skilled in the art will understand that the terms "first," "second," etc., in the embodiments of this disclosure are only used to distinguish different steps, devices, or modules, and do not represent any specific technical meaning, nor do they indicate a necessary logical order between them.

[0036] It should also be understood that in the embodiments disclosed herein, "a plurality of" may refer to two or more, and "at least one" may refer to one, two or more.

[0037] It should also be understood that any component, data or structure mentioned in the embodiments of this disclosure can generally be understood as one or more unless expressly defined or given to the contrary in the context.

[0038] Furthermore, the term "and / or" in this disclosure is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this disclosure generally indicates that the preceding and following related objects have an "or" relationship. The data referred to in this disclosure can include unstructured data such as text, images, and videos, as well as structured data.

[0039] It should also be understood that the description of the various embodiments in this disclosure emphasizes the differences between the various embodiments, and the similarities or similarities can be referred to each other. For the sake of brevity, they will not be described in detail.

[0040] At the same time, it should be understood that, for ease of description, the dimensions of the various parts shown in the accompanying drawings are not drawn according to actual scale.

[0041] The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit this disclosure or its application or use.

[0042] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.

[0043] It should be noted that similar labels and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0044] Figure 1is a structural schematic diagram of a wear leveling circuit applied to a memory provided by an example embodiment of the present disclosure. As shown in Figure 1 The wear leveling circuit provided by the embodiment can be integrated in the memory or be an independent circuit, and is accessed to the memory through a plug-in interface provided by the memory. The circuit provided by the embodiment includes:

[0045] The control module 101 is configured to read data write information in the memory and control the leveling module and the address mapping module to perform corresponding operations according to the data write information.

[0046] The data write information can include, but is not limited to, at least one of data read information and data write information. The data read information indicates that the data in the memory is obtained externally, and the data write information indicates that the memory receives external write information according to an instruction.

[0047] Optionally, the memory can be a resistive random memory (including an array distributed physical storage address). The working process of reading data of the resistive random memory is as follows: reading one bit at a time, selecting a corresponding row, applying a reading voltage to a corresponding column, and sensing the size of the reading current (corresponding to HRS and LRS) by a sense amplifier to complete reading. The working process of writing data of the resistive random memory is as follows: writing by row, selecting a corresponding row, applying a writing voltage to a corresponding column, and completing the writing process.

[0048] The function of the control module 101 is to realize transmission of storage related information between the memory and the wear leveling module 102, and to control the start and stop of the leveling module 102 and the address mapping module 103.

[0049] The leveling module 102 is configured to update a first parameter and a second parameter in the memory according to the control of the control module in response to the data write information reaching a preset condition, and return the updated first parameter and second parameter to the memory through the control module.

[0050] The first parameter is used to represent the complete migration number of all storage blocks in the memory completing the migration operation, and the second parameter is used to represent the physical storage address in the memory completing the migration operation in one complete migration operation.

[0051] The first parameter and the second parameter are updated by the leveling module 102, so that the memory performs read and write operations based on the updated first parameter and second parameter. By updating the first parameter and the second parameter, the leveling operation of the physical storage address being written is realized, the problem of uneven distribution of read and write of the physical storage address is avoided, and the utilization rate of each address of the memory is improved.

[0052] The address mapping module 103 is configured to determine the mapping relationship between the logical storage address and the physical storage address in the memory after the balancing module updates the first parameter and the second parameter each time.

[0053] The logical storage address and the physical storage address of the untreated memory have a fixed mapping relationship, and thus repeated reading and writing of some physical storage addresses is caused each time, leading to uneven distribution of reading and writing. The embodiment re-determines the mapping relationship between the logical storage address and the physical storage address after each balancing by the address mapping module 103, avoids repeated reading and writing of some addresses, and avoids uneven reading and writing.

[0054] The loss balancing circuit applied to the memory provided in the above embodiment of the present disclosure includes a control module configured to read data write information in the memory and control the balancing module and the address mapping module to perform corresponding operations according to the data write information; the balancing module is configured to update a first parameter and a second parameter in the memory according to the control of the control module in response to the data write information reaching a preset condition, and return the updated first parameter and second parameter to the memory through the control module; wherein the first parameter is used to represent the complete number of moves of all storage blocks in the memory completing the move operation, and the second parameter is a physical storage address performing the move operation; the address mapping module is configured to determine the mapping relationship between the logical storage address and the physical storage address in the memory after the balancing module updates the first parameter and the second parameter each time. The embodiment balances the inconsistency of the distribution of reading and writing addresses by the balancing module and the address mapping module, improves the usage rate of each physical storage address in the memory, avoids the problem that the memory is damaged prematurely due to the inconsistency of the reading and writing addresses, improves the use time of the memory, and enhances the durability of the memory.

[0055] In some optional embodiments, the data write information includes the number of data writes, and the control module 101 includes:

[0056] The parameter transmission unit is configured to control the balancing module and the address mapping module to perform reset according to the received reset signal, and read the first parameter and the second parameter in the memory and transmit them to the balancing module 102 and the address mapping module 103.

[0057] Optionally, the first parameter and the second parameter are stored in the table header of the memory. When read, the first parameter and the second parameter can be read from the table header of the memory. After obtaining the updated first parameter and second parameter, the first parameter and the second parameter are written into the table header of the memory.

[0058] The counting unit is configured to acquire a data read-write signal of the memory, record a data write-in times of the data read-write signal, and start the equalization module in response to the data write-in times reaching a preset condition.

[0059] The preset condition can be a preset data write-in times, and the specific times can be set according to an actual application scenario.

[0060] The table header read-write unit is configured to write the updated first parameter and the second parameter of the equalization module 102 into a table header of the memory.

[0061] In the embodiment, after receiving an external reset signal, the overall circuit starts to reset, and a reset completion signal needs to be given to the control module 101 after the reset of other parts is completed. The control module 101 will send a read signal to read the required first parameter (start) and second parameter (gap) from the memory. After receiving these parameters, the first parameter and the second parameter are output to the equalization module 102 and the address mapping module 103, and the reset of the equalization module 102 is completed. The counting unit is configured to count the number of external input write signals, count the number of external write operations, and output a busy signal to the outside when the number of write operations reaches a set update threshold (for example, 1000 times or the like). At this time, a start signal is sent to the equalization module 102. The table header read-write unit receives a completion signal of the equalization module 102 after each equalization is completed, and writes the changed first parameter and second parameter into the table header of the memory. The purpose is to prevent the parameter value before power failure from being read from the nonvolatile memory after the reset is started again after power failure, and the previous operation is continued.

[0062] Optionally, the table header read-write unit is further configured to transmit the updated first parameter and the second parameter to the address mapping module.

[0063] In the embodiment, after the equalization module 102 updates the first parameter and the second parameter, the table header read-write unit in the control module synchronizes the updated first parameter and the second parameter to the memory and the address mapping module 103, so as to avoid data read-write errors caused by different parameters.

[0064] In some optional embodiments, the equalization module 102 comprises:

[0065] The first updating unit is configured to update the first parameter according to a quotient value between the size of the address space in the memory and the size of the storage block in the memory.

[0066] The second updating unit is configured to update the second parameter in response to each data read-write signal corresponding to the memory.

[0067] In the embodiment, the second parameter is updated after each execution of data read and write, and the first parameter is updated after all physical storage addresses in the memory are read and written once. Alternatively, the updating of the first parameter can be achieved by the following formula (1):

[0068] start' = mod(start+1, addr_space / block_space-1) Formula (1)

[0069] wherein start represents the first parameter, start' represents the updated first parameter; mod represents the remainder obtained after the division of the first item and the second item; addr_space represents the number of physical storage addresses included in the memory (i.e., the size of the storage space of the memory); block_space represents the size of the storage block in the memory; addr_space / block_space-1 in the formula represents that not all storage blocks in the memory can be applied to data storage, and there is a storage block for interval buffering, which is not used for reading and writing data in actual application.

[0070] Alternatively, the second updating unit is specifically configured to, in response to the second parameter being not 0, each time the data read and write signal is received, the storage block is moved forward, so that the value of the second parameter is reduced by the block value; and in response to the second parameter being 0, the second parameter is changed to the maximum value according to the received data read and write signal.

[0071] wherein the block value is the number of physical storage addresses included in the storage block, and the maximum value is the largest physical storage address in all accessible storage blocks in the memory.

[0072] In the embodiment, when the second updating unit updates the second parameter (gap), the following two cases can be included but are not limited to: in one case, when gap = 0, the first storage block and the last storage block are exchanged, for example, when the memory includes physical storage addresses 0-3059, the first storage block and the last storage block are exchanged, and then the transformed second parameter gap becomes 3030, and the transformed second parameter gap and the first parameter start are transmitted back to the control module; in another case, when gap is not equal to 0, the storage block is moved forward, and gap' = gap-30, wherein gap' represents the updated second parameter; start is unchanged.

[0073] Alternatively, the control module 101 is further configured to, when the balancing module 102 updates the first parameter and the second parameter, send a busy signal to the outside to control the memory to not receive the data read and write signal.

[0074] In the embodiment, after the equalization module 102 is started, no external data read / write signal is received due to the output of the busy signal, so as to avoid data read / write errors caused by the adjustment of the equalization module 102.

[0075] In some optional embodiments, the circuit further comprises:

[0076] The buffer is configured to buffer each written data when receiving the data write signal, and write all the data in the buffer into a storage block determined according to the second parameter when the amount of data buffered in the buffer reaches the size of the storage block.

[0077] Optionally, the specific moving process is as follows: xadr is a row of physical storage addresses in the memory, yadr is a column of physical storage addresses in the memory, xadr is unchanged and yadr traverses all columns (for example, when the storage includes 30 rows and 32 columns, yadr traverses 0-31), the data in each physical storage address is read out to the static random access memory (SRAM), and then written into the corresponding address in the memory in one time after completion (realizing the row-by-row writing of the memory), completing the moving of a row in the storage block, and sequentially circulating until the moving of all rows in the block is completed. In the embodiment, the static random access memory is used as a cache area to realize the buffering of the written data, and the row-by-row writing of the data in the memory is completed.

[0078] In some optional embodiments, the address mapping module 103 comprises:

[0079] The random mapping unit is configured to, in response to the equalization module 102 updating the first parameter and the second parameter, process the logical storage addresses through a random invertible binary matrix to obtain updated logical storage addresses, and determine an updated mapping relationship between the updated logical storage addresses and the physical storage addresses.

[0080] Optionally, the embodiment processes a logical storage address vector (an array vector composed of all logical storage addresses) through a random invertible binary matrix. For example, the updated logical storage addresses are obtained by performing matrix multiplication on the random invertible binary matrix and the logical storage address vector. For example, as shown in the following formula: Figure 2The random reversible binary matrix is required to have elements composed of a random sequence of 0 and 1, and the size corresponds to the number of logical storage addresses, so as to ensure that the matrix multiplication can be performed with the logical storage address vector. The random mapping unit transmits the generated random update logical storage address to the address relay unit.

[0081] The address relay unit is configured to receive a data read / write signal, determine a corresponding physical storage address for an update logical storage address corresponding to the data read / write signal according to an update mapping relationship, and perform a corresponding read / write operation on the physical storage address in the memory.

[0082] Optionally, the corresponding logical storage address is determined based on the data read / write signal, the update logical storage address is determined based on the logical storage address, and the physical storage address corresponding to the data read / write signal is determined based on the mapping relationship between the update logical storage address and the physical storage address.

[0083] In the embodiment, the address relay unit is configured to relay an external read / write command when the balancing module is not started, and to adjust a timing delay (two cycles of delay generated when the physical storage address is calculated) generated due to the static address random mapping. A specific read / write address judgment mechanism is as follows: with the aid of two registers and a cache area, each storage block (each storage block includes a plurality of physical storage addresses, and the number of physical storage addresses included is determined according to an actual application scenario) is periodically moved to an adjacent position thereof by the balancing module to achieve wear leveling. In essence, an algebraic relationship is established to complete the mapping of the logical storage address to the physical storage address. The gap records the physical storage address of the cache area, and the start records the number of times (i.e., the number of cycles) that all blocks are moved once.

[0084] Optionally, an algebraic relationship between the logical storage address (LA, logical address) and the physical storage address (PA, physical address) can be expressed as the following formula (2):

[0085] PA=(IA+Start)mod N PA<gap

[0086] PA=PA+1 PA≥gap Formula (2)

[0087] Wherein, N is equal to the number of blocks in the storage excluding the number of blocks in the memory that do not contain the gap buffer; IA represents the updated logical storage address; Start represents the first parameter; PA represents the physical storage address; and gap represents the second parameter.

[0088] The wear leveling circuit provided by any one of the embodiments of the present application records the number of write operations when the physical storage addresses are uneven, and the read and write operation commands are transferred through the address mapping module; when the physical storage addresses are even, the write threshold is reached, the internal data of the memory is moved by the leveling module, the corresponding parameters of the read and write addresses are changed and returned to the control module, and the control module writes the corresponding parameters of the read and write addresses into the table header in the memory, waits for the next leveling operation, and the external data operation cannot be performed when the leveling model performs the leveling operation.

[0089] Figure 3 is a structural schematic diagram of the memory provided by an example embodiment of the present disclosure. As shown in Figure 3 the memory provided by the embodiment is any one of the memories to which the wear leveling circuit is applied, and includes a plurality of storage blocks 301 and the wear leveling circuit 302 applied to the memory provided by any one of the embodiments.

[0090] The plurality of storage blocks 301 are configured to receive the written data according to a data write signal, and read the data in the plurality of physical storage addresses one by one according to a data read signal.

[0091] Each of the storage blocks 301 includes a plurality of physical storage addresses.

[0092] The wear leveling circuit 302 is configured to balance the number of read and write data of each storage block.

[0093] Optionally, the memory is a resistive random memory.

[0094] The existing wear leveling technology is mainly for Flash and PCM, and is not applicable to the emerging resistive random memory with great potential. There is no wear leveling algorithm for resistive random memory at present. The embodiment reduces the shortening of the use time of the resistive random memory caused by the inconsistency of the read and write addresses by adding the wear leveling circuit 302 in the memory without changing the resistive random memory device, so as to approach the maximum service life of the resistive random memory as much as possible and enhance the durability of the resistive random memory.

[0095] The following provides an optional example of a resistive random memory to which a wear leveling circuit is applied, including the following parts: the range (addr_space) of the physical storage address is 0-3059, the size (block_space) of the storage block is 30, and the preset update threshold (write_time) is 1000 times:

[0096] Control module: the parameter start = 0 read from the table head when reset, start range is 0-100, the parameter gap = 3030, gap value is 0, 30, 60, etc. 30 multiple, range is 0-3030. The threshold of the counting module is 1000, after the threshold of the write operation is reached, the equalization module is started, and the counting is based on the instruction completion signal. When working normally, the changed parameters start and gap returned by the equalization module are written into the SRAM, and the parameters are transmitted to the address mapping module.

[0097] Equalization module: when moving, there are two cases: when gap = 0, the first block and the last block are exchanged, gap becomes 3030, and then the transformed parameters gap and start are returned to the control module; when gap is not equal to 0, the block is moved forward, gap = gap - 30, start is unchanged. The specific moving process is: xadr is a row, yadr is a column, xadr is unchanged first, yadr traverses 0-31, and is read into SRAM, after completion, it is written into the corresponding address of the SRAM for moving one row in the block, and the cycle is repeated until 30 rows in the block are moved.

[0098] Address mapping module: the static address randomization module is a static address random mapping: to achieve static randomization processing, a random invertible binary matrix (RIB) can be used. The elements in the RIB are randomly sequenced by 0 and 1. When the logical storage address is multiplied by the matrix, the originally continuous LA value can be dispersed to obtain the address IA, and the physical storage address PA accessed according to the corresponding relationship of the above formula (2).

[0099] The basic principles of the present disclosure are described above in combination with specific embodiments, but it should be pointed out that the advantages, advantages, effects, etc. mentioned in the present disclosure are only examples and cannot be considered as the must-have of each embodiment of the present disclosure. In addition, the above specific details are only for the purpose of example and understanding, and the above details do not limit the present disclosure to the above specific details.

[0100] Each embodiment in the specification is described in a progressive manner, and each embodiment focuses on the difference from other embodiments. The same or similar parts of each embodiment can be referred to. For system embodiments, since they basically correspond to method embodiments, the description is relatively simple, and the relevant parts can be referred to the part of the method embodiment.

[0101] The block diagrams of devices, apparatuses, equipment, systems referred to in this disclosure are merely illustrative examples and are not intended to require or imply that the connection, arrangement, configuration must be as shown in the block diagrams. These devices, apparatuses, equipment, systems can be connected, arranged, configured in any manner as will be appreciated by those skilled in the art. Words such as "include," "contain," "have," and the like are open-ended words that are to be interpreted to mean "including but not limited to," and are not to be interpreted as limiting the described embodiment to features, elements, and / or steps disclosed herein. The words "or" and "and" as used herein are to be interpreted as the word "and / or," and are not to be interpreted as requiring both features, elements, and / or steps disclosed herein. The word "such as" as used herein is to be interpreted as the phrase "such as but not limited to," and is not to be interpreted as limiting the described embodiment to features, elements, and / or steps disclosed herein.

[0102] The methods and apparatuses of this disclosure can be implemented in a number of ways. For example, the methods and apparatuses of this disclosure can be implemented using software, hardware, firmware, or any combination of these. The above described order of steps for the methods is merely illustrative, and the steps of the methods of this disclosure are not limited to the order specifically described above unless otherwise specifically stated. Furthermore, in some embodiments, the disclosure can also be implemented as a program recorded on a recording medium, which includes machine readable instructions for implementing the methods according to the disclosure. Thus, the disclosure also covers a recording medium storing a program for executing the methods according to the disclosure.

[0103] It is also important to note that the devices, equipment, and methods of this disclosure can be embodied in a variety of ways. These variations are contemplated as being within the scope of the present disclosure.

[0104] The above description of the disclosed aspects is given for illustrative purposes and is not intended to limit the scope of the disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein can be applied to other aspects without departing from the scope of the disclosure. Thus, the present disclosure is not intended to be limited to the aspects shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0105] The above description has been given for illustrative and descriptive purposes. In addition, this description is not intended to limit embodiments of the disclosure to the forms disclosed herein. Although a number of example aspects and embodiments have been discussed above, those of skill in the art will recognize certain modifications, permutations, additions, and sub-combinations thereof.

Claims

1. A loss balancing circuit applied to a memory, characterized in that, include: The control module is used to read data write information from the memory and control the equalization module and the address mapping module to perform corresponding operations based on the data write information. The equalization module is used to update the first parameter and the second parameter in the memory according to the control of the control module in response to the data write information reaching the preset condition, and return the updated first parameter and the second parameter to the memory through the control module; wherein, the first parameter is used to characterize the number of complete moves in which all storage blocks in the memory have completed the move operation, and the second parameter is used to characterize the physical storage address in the memory where the move operation is completed in one complete move operation; The address mapping module is used to determine the mapping relationship between logical storage addresses and physical storage addresses in the memory each time the equalization module updates the first parameter and the second parameter. The address mapping module includes: The random mapping unit is used to process the logical storage address through a random invertible binary matrix in response to the equalization module updating the first parameter and the second parameter, to obtain the updated logical storage address, and to determine the update mapping relationship between the updated logical storage address and the physical storage address. The address relay unit is used to receive data read / write signals, determine the corresponding physical storage address for the update logical storage address corresponding to the data read / write signal according to the update mapping relationship, and perform corresponding read / write operations on the physical storage address in the memory.

2. The circuit according to claim 1, characterized in that, The data write information includes the number of data writes, and the control module includes: The parameter transmission unit is used to control the equalization module and the address mapping module to perform a reset according to the received reset signal, and to read the first parameter and the second parameter in the memory and transmit them to the equalization module and the address mapping module. The counting unit is used to acquire the data read / write signal of the memory, record the number of data writes of the data read / write signal, and activate the equalization module in response to the number of data writes reaching the preset condition. The header read / write unit is used to write the received updated first and second parameters from the equalization module into the header of the memory.

3. The circuit according to claim 2, characterized in that, The header read / write unit is also used to transmit the updated first and second parameters to the address mapping module.

4. The circuit according to any one of claims 1-3, characterized in that, The equalization module includes: The first update unit is used to update the first parameter based on the quotient between the address space size in the memory and the storage block size in the memory; The second update unit is used to update the second parameter in response to each data read / write signal corresponding to the memory.

5. The circuit according to claim 4, characterized in that, The second update unit is specifically configured to, in response to the second parameter being non-zero, move the storage block forward each time the data read / write signal is received, thereby reducing the value of the second parameter by the block value; and in response to the second parameter being zero, change the second parameter to its maximum value according to the received data read / write signal; wherein, the block value is the number of physical storage addresses included in the storage block, and the maximum value is the largest physical storage address among all accessible storage blocks in the memory.

6. The circuit according to claim 4, characterized in that, The control module is also used to send a busy signal to the outside when the equalization module updates the first parameter and the second parameter, so as to control the memory not to receive data read / write signals.

7. The circuit according to any one of claims 1-3, characterized in that, The circuit also includes: A buffer is used to buffer each piece of data being written when a data write signal is received. When the amount of data buffered in the buffer reaches the size of the storage block, all the data in the buffer is written into a storage block of the memory determined according to the second parameter.

8. A memory, characterized in that, include: Multiple memory blocks and a loss balancing circuit for a memory as provided in any one of claims 1-7; The plurality of storage blocks are used to receive written data according to a data write signal, and to read data from the plurality of physical storage addresses one by one according to a data read signal; wherein each of the storage blocks includes the plurality of physical storage addresses; The loss balancing circuit is used to balance the number of times each storage block reads and writes data.

9. The memory according to claim 8, characterized in that, The memory is a resistive random access memory.

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