A low power LIGBT device integrated with self-biased PMOS

Abstract

The application relates to a low-power LIGBT device integrated with a self-bias PMOS, and belongs to the technical field of semiconductors. The device comprises a substrate, a buried oxygen layer, a drift region, a P-type buried layer, a common MOS region, a self-bias PMOS region and an anode region. The substrate, the buried oxygen layer and the drift region are sequentially arranged from bottom to top, and the P-type buried layer is arranged in the drift region and is completely wrapped by the drift region. The common MOS region is adjacent to the self-bias PMOS region, and the anode region is located at the upper right side of the device. The self-bias PMOS region can reduce the saturation current of the device when the anode voltage is increased, reduce the off-state loss of the device when the device is turned off, and improve the short-circuit working characteristics of the device when the device is in short-circuit working.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology and relates to a low-power LIGBT device with integrated self-biased PMOS. Background Technology

[0002] LIGBT (Lateral Insulated Gate Bipolar Transistor) is a bipolar semiconductor power device that combines the features of a MOSFET and a BJT. It boasts advantages such as low on-state voltage, low power consumption, and high operating frequency, and is widely used in communication technology, new energy equipment, and various consumer electronics fields. It is a core component of electronic power systems. LIGBTs are easily integrated onto Si substrates and are typically used in SOI-based power intelligent systems.

[0003] The advantage of LIGBT's bipolar operating mode lies in its extremely low on-state voltage drop. However, a disadvantage is the extremely long current tail during turn-off. This current tail occurs because, during turn-off, while electrons are extracted by the anode p-collector region, holes are continuously injected into the n-drift region. The remaining charge carriers within the device are primarily eliminated through recombination of non-equilibrium carriers. This current tail phenomenon further increases the turn-off loss and turn-off time of LIGBT devices. Lowering turn-off loss can be achieved by reducing the amount of holes injected during turn-off or by reducing the lifetime of the n-drift region and n-drift carriers, but this correspondingly increases the on-state voltage drop. This presents a trade-off between turn-off loss and on-state voltage drop.

[0004] Reducing surface electric field intensity (RESURF) technology optimizes the electric field distribution by designing the doping dose of the n-drift region and utilizing the substrate's auxiliary depletion effect, thereby maximizing the breakdown voltage. This technology was first used in LDMOS devices and is also applicable to LIGBT devices. Double-RESURF technology introduces a p-top layer on the surface of the drift region, while Triple-RESURF technology introduces a p-buried layer within the drift region. Both can achieve high voltage withstand over a relatively short n-drift region, thus reducing both on-state voltage drop and turn-off losses.

[0005] Because the nMOS transistors inside a LIGBT have current saturation characteristics, the LIGBT current remains saturated even with a large applied voltage, preventing a significant increase in current even as the applied voltage rises. When the LIGBT is in a short-circuit operating state due to a fault, this current saturation characteristic prevents it from burning out quickly due to excessive current. This buffer time allows external protection circuitry to detect the fault and control the LIGBT to turn off. Reducing the LIGBT's saturation current improves its short-circuit operating reliability and provides more time for external circuitry to detect faults, significantly reducing the practical difficulty and cost of external circuitry design. Therefore, to reduce the design difficulty and cost of external circuitry, the purpose of this invention is to provide an improved LIGBT device to further reduce the LIGBT's saturation current and turn-off losses. Summary of the Invention

[0006] In view of this, the purpose of the present invention is to provide a low-power LIGBT device with integrated self-biased PMOS, which reduces the saturation current of the device when the device is forward conducting, reduces the turn-off loss of the device when the device is off, and extends the normal operation time of the device when the device is short-circuited, so as to improve the reliability of the device.

[0007] To achieve the above objectives, the present invention provides the following technical solution:

[0008] A low-power LIGBT device integrating a self-biased PMOS includes a cathode P+ region 1, a cathode P-well region 2, a drift region 3, a buried oxide layer 4, a substrate 5, a cathode N+ region 6, a conventional MOS oxide layer 7, a conventional MOS polysilicon gate 8, a cathode MOS-P region 9, a PMOS polysilicon gate 10, a PMOS oxide layer 11, a P-type buried layer 14, and an anode region.

[0009] The substrate 5, buried oxide layer 4, and drift region 3 are arranged sequentially from bottom to top; the P-type buried layer 14 is completely enclosed by the drift region 3; the upper and right sides of the anode region are flush with the LIGBT device, and its left and lower sides are adjacent to the drift region 3. The anode region includes an anode P+ region 12 and an anode N-buffer region 13; the anode P+ region 12 is enclosed by the anode N-buffer region 13; the anode N-buffer region 13 is enclosed by the drift region 3.

[0010] The cathode P+ region 1 is adjacent to the cathode N+ region 6, and both are located above the cathode P-well region 2; the cathode P-well region 2 is adjacent to the drift region 3 below; the ordinary MOS oxide layer 7 is adjacent to the cathode N+ region 6 and the cathode P-well region 2 on the left, adjacent to the drift region 3 below, and adjacent to the P-type buried layer 14 and the self-biased PMOS region 15 on the right; the ordinary MOS polysilicon gate 8 is located in the ordinary MOS oxide layer 7 and is completely enclosed by the ordinary MOS oxide layer 7; the cathode MOS-P region 9 is located between the ordinary MOS oxide layer 7 and the PMOS oxide layer 11; the PMOS oxide layer 11 is adjacent to the drift region 3 on the right and adjacent to the P-type buried layer 14 below; the PMOS polysilicon gate 10 is located in the PMOS oxide layer 11 and is completely enclosed by the PMOS oxide layer 11.

[0011] The cathode P+ region 1, cathode P-well region 2, cathode N+ region 6, ordinary MOS oxide layer 7, ordinary MOS polysilicon gate 8, and part of the drift region 3 constitute ordinary MOS region 16. Ordinary MOS region 16 is used to control the injection of cathode electrons and to control the switching on and off of the device.

[0012] The cathode MOS-P region 9, the PMOS polysilicon gate 10, the PMOS oxide layer 11, and part of the drift region 3 and the P-type buried layer 14 constitute the self-biased PMOS region 15. The self-biased PMOS region 15 is used to control the extraction of holes in the drift region and adjust the number of holes in the device.

[0013] Furthermore, both the cathode MOS-P region 9 and the PMOS polysilicon gate 10 are connected to the cathode electrode.

[0014] Furthermore, the source of the ordinary MOS region 16 is the cathode N+ region 6, the drain is the drift region 3, the gate is an ordinary MOS polysilicon gate 8, and the gate oxide layer is an ordinary MOS oxide layer 7.

[0015] Furthermore, the source of the self-biased PMOS region 15 is a P-type buried layer 14, the drain is a cathode MOS-P region 9, the gate is a PMOS polysilicon gate 10, and the gate oxide layer is a PMOS oxide layer 11.

[0016] Furthermore, the P-type buried layer 14 is in direct contact with both the ordinary MOS oxide layer 7 and the PMOS oxide layer 11.

[0017] Furthermore, the thickness of the PMOS oxide layer 11 can be adjusted as needed.

[0018] The beneficial effects of this invention are as follows: This invention introduces a self-biased PMOS region into the cathode of a LIGBT device, which has the following advantages:

[0019] (1) When the device is in forward conduction and the anode voltage is low, the cathode PMOS is turned off, and holes flow away through the cathode P-well region and the cathode P+ region. The on-state voltage drop of the device is consistent with that of the traditional Triple-Resurgence LIGBT device. As the anode voltage gradually increases, the cathode PMOS turns on, and holes can flow away through the cathode P-well region, the cathode P+ region, and the cathode MOS-P region of the PMOS, which reduces the hole concentration and thus reduces the saturation current of the device. The saturation current is reduced by 40% compared with the traditional device, and the short-circuit withstand time is improved by about 3.4 times, thereby improving the reliability of the device.

[0020] (2) When the device is turned off, as the voltage drop of the device increases, the PMOS will automatically open the auxiliary extraction of holes in the drift region, which improves the turn-off speed of the device and reduces the turn-off loss of the device. Its turn-off loss is reduced by 38% compared with traditional devices, which greatly improves the trade-off relationship between the turn-off loss and the on-state voltage drop of the device.

[0021] (3) When operating in a short circuit, the PMOS automatically turns on the hole extraction drift region, which reduces the number of holes passing through the cathode P-well region, thereby delaying the occurrence of the device latch-up effect and improving the short-circuit operating characteristics of the device.

[0022] Other advantages, objectives, and features of the invention will be set forth in part in the description which follows, and in part will be apparent to those skilled in the art from the following examination, or may be learned from practice of the invention. The objectives and other advantages of the invention can be realized and obtained through the following description. Attached Figure Description

[0023] To make the objectives, technical solutions, and advantages of the present invention clearer, the preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings, wherein:

[0024] Figure 1 This is a schematic diagram of the structure of the low-power LIGBT device integrating a self-biased PMOS according to the present invention.

[0025] Figure 2 This is the equivalent circuit diagram of the low-power LIGBT device of the present invention;

[0026] Figure 3 The potential distribution diagrams of the present invention and the conventional Triple-RESURF LIGBT under avalanche breakdown conditions are shown.

[0027] Figure 4 The present invention differs from the conventional Triple-RESURF LIGBT in the drift region length L DThe following are comparison diagrams of the blocking characteristics at 25μm: (a) is the blocking characteristic diagram of the present invention, and (b) is the blocking characteristic diagram of the conventional Triple-RESURF LIGBT.

[0028] Figure 5 The following diagrams show the performance comparison between the present invention and the conventional Triple-RESURF LIGBT, as well as some performance characteristics of the present invention: (a) is a comparison of the saturation current between the present invention and the conventional Triple-RESURF LIGBT; (b) is a comparison of the energy bands of the PMOS when it is turned on and off; and (c) is a comparison of the hole current density flowing through the PMOS channel with the hole current density at other locations.

[0029] Figure 6 This is a comparison diagram of the forward conduction characteristics of the present invention and the traditional Triple-RESURF LIGBT;

[0030] Figure 7 The following are some performance comparison diagrams between the present invention and the conventional Triple-RESURF LIGBT, as well as the energy band changes of the PMOS region when the device is turned off. (a) is the inductive load test circuit of the present invention and the conventional Triple-RESURF LIGBT. (b) is the turn-off characteristic curve under the same on-state voltage drop. (c) is the energy band comparison diagram between the PMOS when it is on and when it is off during the turn-off process.

[0031] Figure 8 To compare the short-circuit operating characteristics of the present invention with those of the conventional Triple-RESURF LIGBT, (a) shows the short-circuit operating test circuits of the present invention and the conventional Triple-RESURF LIGBT, and (b) shows the short-circuit operating characteristic curves.

[0032] Figure 9 This is a schematic diagram of the main process flow for the low-power LIGBR device of the present invention.

[0033] Figure reference numerals: 1-Cathode P+ region; 2-Cathode P-well region; 3-Drift region; 4-Buried oxide layer; 5-Substrate; 6-Cathode N+ region; 7-Ordinary MOS oxide layer; 8-Ordinary MOS polysilicon gate; 9-Cathode MOS-P region; 10-PMOS polysilicon gate; 11-PMOS oxide layer; 12-Anode P+ region; 13-Anode N-buffer region; 14-P-type buried layer; 15-Self-biased PMOS region; 16-Ordinary MOS region. Detailed Implementation

[0034] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0035] The accompanying drawings are for illustrative purposes only and are schematic diagrams, not actual pictures. They should not be construed as limiting the invention. To better illustrate the embodiments of the invention, some parts in the drawings may be omitted, enlarged, or reduced, and do not represent the actual product dimensions. It is understandable to those skilled in the art that some well-known structures and their descriptions may be omitted in the drawings.

[0036] In the accompanying drawings of the embodiments of the present invention, the same or similar reference numerals correspond to the same or similar components. In the description of the present invention, it should be understood that if terms such as "upper," "lower," "left," "right," "front," and "rear" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, they are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the terms used to describe positional relationships in the drawings are only for illustrative purposes and should not be construed as limiting the present invention. For those skilled in the art, the specific meaning of the above terms can be understood according to the specific circumstances.

[0037] This invention improves upon the traditional triple-reserve LIGBT device, proposing a low-power LIGBT device integrating a self-biased PMOS, such as... Figure 1 As shown, the device includes a cathode P+ region 1, a cathode P-well region 2, a drift region 3, a buried oxide layer 4, a substrate 5, a cathode N+ region 6, a conventional MOS oxide layer 7, a conventional MOS polysilicon gate 8, a cathode MOS-P region 9, a PMOS polysilicon gate 10, a PMOS oxide layer 11, an anode P+ region 12, an anode N-buffer region 13, and a P-type buried layer 14.

[0038] Substrate 5 is located at the bottom of the device. Above the substrate is buried oxide layer 4, and above that is drift region 3, in which a P-type buried layer 14 is disposed and completely enclosed. The left and top sides of cathode P+ region 1 are flush with the device surface, and its right and bottom sides are adjacent to cathode N+ region 6 and cathode P-well region 2, respectively. The top of cathode N+ region 6 is flush with the device surface, and its right and bottom sides are adjacent to ordinary MOS oxide layer 7 and cathode P-well region 2, respectively. Below cathode P-well region 2 is drift region 3, with its left side flush with the device surface and its right side adjacent to ordinary MOS oxide layer 7. Ordinary MOS polysilicon gate 8 is completely enclosed by ordinary MOS oxide layer 7. Cathode MOS-P region 9 is located between ordinary MOS oxide layer 7 and PMOS oxide layer 11, with its top side flush with the device surface and its bottom side adjacent to drift region 3. PMOS polysilicon gate 10 is completely enclosed by PMOS oxide layer 11. The anode P+ region 12 is surrounded by the anode N-buffer region 13, and the anode N-buffer region 13 is surrounded by the drift region 3.

[0039] The self-biased PMOS region 15 consists of a cathode MOS-P region 9, a PMOS polysilicon gate 10, a PMOS oxide layer 11, a portion of the drift region 3, and a P-type buried layer 14. The ordinary MOS region 16 consists of a cathode P+ region 1, a cathode P-well region 2, a cathode N+ region 6, an ordinary MOS oxide layer 7, an ordinary MOS polysilicon gate 8, and a portion of the drift region 3. Both the ordinary MOS oxide layer 7 and the PMOS oxide layer 11 are in direct contact with the P-type buried layer 14.

[0040] In this embodiment, regarding device size and doping concentration: the length (X-axis direction) of drift region 3 is 30 μm, the width (Y-axis direction) is 5 μm, and the doping concentration of this region is 4.5 × 10⁻⁶. 15 cm -3 The cathode P+ region 1 has a length of 1 μm, a width of 1 μm, and a doping concentration of 1 × 10⁻⁶. 19 cm -3 The cathode N+ region 6 has a length of 1 μm, a width of 1 μm, and a doping concentration of 1 × 10⁶. 19 cm -3 The cathode P-well region 2 has a length of 2 μm, a width of 1 μm, and a doping concentration of 1 × 10⁻⁶. 17 cm -3 The anode P+ region 12 has a length of 1 μm, a width of 1 μm, and a doping concentration of 1 × 10⁻⁶. 19 cm -3 The anode N-buffer region 13 has a length of 2 μm, a width of 2 μm, and a doping concentration of 1 × 10⁻⁶. 17 cm -3 The cathode MOS-P region 9 has a length of 1 μm, a width of 1 μm, and a doping concentration of 1 × 10⁻⁶.19 cm -3 The P-type buried layer 14 has a length of 21 μm, a width of 2 μm, and a doping concentration of 2 × 10⁻⁶. 15 cm -3 The standard MOS oxide layer 16 has a length and thickness of 0.1 μm. The PMOS oxide layer 11 has a thickness of 0.1 μm. The standard MOS polysilicon gate 8 has a length of 0.8 μm, a width of 2.8 μm, and a doping concentration of 1 × 10⁻⁶. 19 cm -3 The PMOS polysilicon gate 10 has a length of 0.8 μm, a width of 2.8 μm, and a doping concentration of 1 × 10⁻⁶. 19 cm -3 The buried oxide layer 4 has a length of 30 μm and a width of 3 μm. The substrate 5 has a length of 30 μm and a width of 1 μm, with a doping concentration of 1 × 10⁻⁶. 16 cm -3 .

[0041] This embodiment uses SENTAURUS simulation software to perform performance simulation analysis on the structure of the low-power LIGBT device of the present invention, analyze its mechanism, and perform electrical simulation. During the simulation process, all simulation parameters of the device in this embodiment are consistent with those of the conventional device, including a drift region thickness of 5 μm, a carrier lifetime of 10 μs, and an ambient temperature of 300 K.

[0042] Figure 2 The diagram shown is the equivalent circuit diagram of the device in this embodiment, where the LIGBT is equivalent to an NMOS-controlled PNP transistor. The anode P+ region 12, the anode N-buffer region 13, the drift region 3, and the P-type buried layer 14 can be equivalent to a PNP transistor, which is connected in series with a self-biased PMOS. When the applied collector voltage is greater than the threshold voltage of the PMOS, the PMOS will automatically turn on and extract holes.

[0043] Figure 3 The image shows the device in this embodiment compared to a conventional Triple-Resurf LIGBT device with a drift region length of 25 μm and a doping concentration of 4.5 × 10⁻⁶. 15 cm -3 A comparison of avalanche breakdown characteristic curves. Figure 4 The figure shown is a comparison of the blocking characteristics of the device in this embodiment and the conventional Triple-RESURF LIGBT device when the drift region length is 25 μm. Figure 4 As shown in (a), the device in this embodiment has a concentration of 4.5 × 10⁻⁶ in the drift region. 15 cm -3 The breakdown voltage at that time was 345V, while... Figure 4As shown in (b), the traditional Triple-RESURF LIGBT device is 349V, indicating that the two are at the same voltage rating.

[0044] Figure 5 (a) shows the difference between the device in this embodiment and a conventional Triple-RESURF LIGBT device with a drift region length of 25 μm and a doping concentration of 4.5 × 10⁻⁶. 15 cm -3 The comparison of the saturation current characteristic curves shows that, since the self-biased PMOS of the device in this embodiment automatically turns on to extract holes as the applied voltage increases, the saturation current of the device in this embodiment is less than that of the traditional Triple-RESURF LIGBT device. Figure 5 (b) shows a comparison of the energy bands of the self-biased PMOS device in this embodiment when it is turned on and off under forward conduction. Figure 5 (c) shows a comparison of the hole current density flowing through the self-biased PMOS channel with the hole current density at other locations.

[0045] Figure 6 This diagram compares the forward conduction curves of the device in this embodiment with those of a conventional Triple-Resun LIGBT device. Because the applied voltage is relatively small, the PMOS is not turned on and does not draw holes, thus not weakening the conductance modulation effect and not affecting the forward conduction characteristics. Therefore, the forward conduction curves of the device in this embodiment are very similar to those of a conventional Triple-Resun LIGBT device.

[0046] Figure 7 (a) is a shutdown test circuit, where the load is an inductive load. Figure 7 (b) shows the turn-off characteristic curves of the device in this embodiment and the conventional Triple-RESURF LIGBT device under the same on-state voltage drop. Turn-off time refers to the time it takes for the collector current to decrease from 90% to 10%. Compared to the conventional Triple-RESURF LIGBT device, the device in this embodiment has an additional self-biased PMOS region, which can automatically open and extract holes during turn-off, accelerating the extraction of empty blood in the drift region. Therefore, the turn-off loss of the device in this embodiment is reduced. Furthermore, since the polysilicon gate of the PMOS is connected to the cathode and emitter, and the PMOS polysilicon gate is opposite to the ordinary MOS polysilicon gate, the equivalent capacitance of the ordinary MOS polysilicon gate decreases, thus accelerating the turn-off speed of the device in this embodiment. Figure 7 (c) is a comparison of the energy bands of a self-biased PMOS when it is turned on and off under inductive load.

[0047] Figure 8 (a) shows the topology of the short-circuit characteristic test circuit. Figure 8(b) shows the short-circuit characteristic curves of the device in this embodiment and the conventional Triple-RESURF LIGBT device at a power supply voltage of 150V. In the short-circuit operating state, the conventional Triple-RESURF LIGBT device initially saturates and turns on, generating a large current. Then, due to the heat generated by the large current, the thermal resistance of the conventional Triple-RESURF LIGBT device increases, and the current begins to decrease and tends to a stable state. When the parasitic thyristor in the conventional LIGBT device turns on, the current increases instantaneously, causing the LIGBT to thermally break down and the device to fail. In the device of this embodiment, because the self-biased PMOS remains in the on state during short-circuit operation, the short-circuit operating current of the device in this embodiment is consistently lower than that of the conventional Triple-RESURF LIGBT device. The self-biased PMOS shares the hole current that originally passed through the cathode P-well region, making it more difficult for the parasitic thyristor in the device of this embodiment to turn on, thus prolonging the normal operating time of the device.

[0048] The process flow of the device in this embodiment is as follows: Figure 9 As shown, its main processes include: ion implantation, diffusion, etching, oxidation, deposition, polycrystalline filling and annealing, etc. Finally, metal electrodes are deposited to form the anode, gate and cathode.

[0049] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A low-power LIGBT device integrating a self-biased PMOS, comprising a drift region (3), a buried oxide layer (4), a substrate (5), a P-type buried layer (14), and an anode region, wherein the substrate (5), the buried oxide layer (4), and the drift region (3) are arranged sequentially from bottom to top; the P-type buried layer (14) is completely enclosed by the drift region (3); the upper and right sides of the anode region are flush with the LIGBT device, and its left and lower sides are adjacent to the drift region (3); characterized in that: The device also includes a cathode P+ region (1), a cathode P-well region (2), a cathode N+ region (6), a common MOS oxide layer (7), a common MOS polysilicon gate (8), a cathode MOS-P region (9), a PMOS polysilicon gate (10), and a PMOS oxide layer (11). The cathode P+ region (1) is adjacent to the cathode N+ region (6), and both are located above the cathode P-well region (2); the cathode P-well region (2) is adjacent to the drift region (3) below; the ordinary MOS oxide layer (7) is adjacent to the cathode N+ region (6) and the cathode P-well region (2) on the left, adjacent to the drift region (3) below, and adjacent to the P-type buried layer (14) and the self-biased PMOS region (15) on the right; the ordinary MOS polysilicon gate (8) is located in the ordinary MOS oxide layer (7) and is completely wrapped by the ordinary MOS oxide layer (7); the cathode MOS-P region (9) is located between the ordinary MOS oxide layer (7) and the PMOS oxide layer (11); the PMOS oxide layer (11) is adjacent to the drift region (3) on the right and adjacent to the P-type buried layer (14) below; the PMOS polysilicon gate (10) is located in the PMOS oxide layer (11) and is completely wrapped by the PMOS oxide layer (11); The cathode P+ region (1), cathode P-well region (2), cathode N+ region (6), ordinary MOS oxide layer (7), ordinary MOS polysilicon gate (8) and part of the drift region (3) constitute the ordinary MOS region (16). The cathode MOS-P region (9), PMOS polysilicon gate (10), PMOS oxide layer (11), and part of the drift region (3) and P-type buried layer (14) constitute a self-biased PMOS region (15); the cathode MOS-P region (9) and PMOS polysilicon gate (10) are both connected to the cathode electrode.

2. The low-power LIGBT device according to claim 1, characterized in that: The anode region includes an anode P+ region (12) and an anode N-buffer region (13); the anode P+ region (12) is surrounded by the anode N-buffer region (13); the anode N-buffer region (13) is surrounded by the drift region (3).

3. A low-power LIGBT device according to claim 1, characterized in that: The source of the ordinary MOS region (16) is the cathode N+ region (6), the drain is the drift region (3), the gate is the ordinary MOS polysilicon gate (8), and the gate oxide layer is the ordinary MOS oxide layer (7).

4. A low-power LIGBT device according to claim 1, characterized in that: The source of the self-biased PMOS region (15) is a P-type buried layer (14), the drain is a cathode MOS-P region (9), the gate is a PMOS polysilicon gate (10), and the gate oxide layer is a PMOS oxide layer (11).

5. A low-power LIGBT device according to claim 1, characterized in that: The P-type buried layer (14) is in direct contact with both the ordinary MOS oxide layer (7) and the PMOS oxide layer (11).

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