Pixel circuit, driving method and display substrate

Abstract

Embodiments of the present application provide a pixel circuit, a driving method and a display substrate, a first end of a threshold compensation sub-circuit is connected to a first end of a storage sub-circuit; a second end of the threshold compensation sub-circuit is connected to a data writing sub-circuit, a driving sub-circuit and an initialization sub-circuit respectively; a light emitting element is connected to the driving sub-circuit and the initialization sub-circuit respectively, the initialization sub-circuit initializes an anode voltage of the light emitting element, a control end voltage of the driving sub-circuit and a voltage of the first end of the storage sub-circuit in a reset stage, the threshold compensation sub-circuit compensates the voltage of the first end of the storage sub-circuit in a compensation stage, and the data writing sub-circuit writes data to the first end of the storage sub-circuit through the threshold compensation sub-circuit in a data writing stage, so that the voltage compensation time can be autonomously controlled and is not affected by the refresh frequency of the data writing sub-circuit.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a pixel circuit, a driving method and a display substrate. BACKGROUND

[0002] The threshold voltage of the driving transistor in the pixel circuit will cause the display brightness to be uneven. In order to solve this problem, the voltage of the driving transistor needs to be compensated frequently. In the related art, the compensation voltage depends on the control end signal of the refresh data writing sub-circuit, that is, the voltage compensation can only be performed in the signal writing stage. This is greatly limited and the charging rate is low. SUMMARY

[0003] The purpose of the embodiments of the present application is to provide a pixel circuit, a driving method and a display substrate to separate the voltage compensation process and the data writing process. The specific technical solutions are as follows:

[0004] The embodiments of the present application also provide a pixel circuit, which comprises:

[0005] a storage sub-circuit, a data writing sub-circuit, a threshold compensation sub-circuit, a driving sub-circuit, an initialization sub-circuit and a light emitting element;

[0006] The first end of the threshold compensation sub-circuit is connected to the first end of the storage sub-circuit; the second end of the threshold compensation sub-circuit is connected to the data writing sub-circuit, the driving sub-circuit and the initialization sub-circuit respectively; and the light emitting element is connected to the driving sub-circuit and the initialization sub-circuit respectively;

[0007] The initialization sub-circuit is configured to initialize the anode voltage of the light emitting element, the control end voltage of the driving sub-circuit and the voltage of the first end of the storage sub-circuit in a reset stage.

[0008] The threshold compensation sub-circuit is configured to compensate the voltage of the first end of the storage sub-circuit in a compensation stage.

[0009] The data writing sub-circuit is configured to write data to the first end of the storage sub-circuit through the threshold compensation sub-circuit in a data writing stage.

[0010] The driving sub-circuit is configured to generate a driving current for driving the light emitting element to emit light.

[0011] In a possible implementation, the storage sub-circuit comprises a first storage capacitor and a second storage capacitor; the initialization sub-circuit comprises a first initialization sub-circuit, a second initialization sub-circuit and a third initialization sub-circuit; and the driving sub-circuit comprises a driving control branch and a driving transistor.

[0012] The first end of the first storage capacitor is electrically connected with a first power voltage;

[0013] The second end of the first storage capacitor is electrically connected with the first end of the second storage capacitor and the first end of the threshold compensation sub-circuit respectively; the control end of the threshold compensation sub-circuit is connected with a first control signal;

[0014] The control end of the data writing sub-circuit is connected with a frequency updating signal; the first end of the data writing sub-circuit is connected with a data signal; the second end of the data writing sub-circuit is electrically connected with the second end of the threshold compensation sub-circuit, the first end of the driving control branch and the second end of the third initialization sub-circuit respectively;

[0015] The second end of the driving control branch is connected with the first end of the driving transistor; the control end of the driving control branch is connected with a fourth control signal;

[0016] The control end of the third initialization sub-circuit is connected with a third control signal; the first end of the third initialization sub-circuit is connected with a third initialization signal;

[0017] The first end of the first initialization sub-circuit is connected with the control end of the driving transistor and the second end of the second storage capacitor respectively; the second end of the first initialization sub-circuit is connected with a first initialization signal; the control end of the first initialization sub-circuit is connected with a fifth control signal;

[0018] The second end of the driving transistor is electrically connected with the anode of the light emitting element and the second end of the third initialization sub-circuit respectively;

[0019] The first end of the second initialization sub-circuit is connected with a second initialization signal; the control end of the second initialization sub-circuit is connected with a second control signal; the cathode of the light emitting element is connected with a second power voltage;

[0020] In the reset stage, the first initialization sub-circuit is turned on under the control of the fifth control signal; the threshold compensation sub-circuit is turned on under the control of the first control signal; the third initialization sub-circuit is turned on under the control of the second control signal; the second initialization sub-circuit is turned on under the control of the third control signal; the driving control branch is turned off under the control of the fourth control signal; the first initialization signal is written into the control end of the driving sub-circuit; the second initialization signal is written into the anode of the light emitting element; and the second initialization signal is written into the second end of the first storage capacitor.

[0021] In the compensation stage, the second initialization sub-circuit is turned on under the control of the third control signal, the threshold compensation sub-circuit is turned on under the control of the first control signal, the driving control branch is turned on under the control of the fourth control signal, and the second end of the first storage capacitor is point-by-point compensated.

[0022] In the data writing stage, the data writing sub-circuit is turned on under the control of the frequency updating signal, the threshold compensation sub-circuit is turned on under the control of the first control signal, the driving control branch is turned off under the control of the fourth control signal, and data is written into the first end of the storage sub-circuit via the threshold compensation sub-circuit.

[0023] In a possible implementation, the circuit further comprises:

[0024] a scan control signal input sub-circuit;

[0025] The control end of the scan control signal input sub-circuit is connected with a scan control signal, and the second end of the scan control signal input sub-circuit is electrically connected with the second end of the data writing sub-circuit, the second end of the third initialization sub-circuit, the second end of the threshold compensation sub-circuit, and the first end of the driving control branch, respectively.

[0026] In a possible implementation, the threshold compensation sub-circuit comprises a first transistor, the scan control signal input sub-circuit comprises a second transistor, the third initialization sub-circuit comprises a third transistor, the first initialization sub-circuit comprises a fourth transistor, the data writing sub-circuit comprises a fifth transistor, the third initialization sub-circuit comprises a sixth transistor, and the driving control branch comprises a seventh transistor.

[0027] In a possible implementation, the first transistor and the second transistor are N-type transistors, and the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the driving transistor are P-type transistors.

[0028] In a possible implementation, the first initialization signal and the second initialization signal are provided by the same initialization signal source.

[0029] In a possible implementation, the first initialization signal and the second initialization signal are provided by different initialization signal sources.

[0030] In a possible implementation, the fifth control signal and the fourth control signal are provided by the same control signal source.

[0031] In a possible implementation, the fifth control signal and the fourth control signal are provided by different control signal sources.

[0032] In a possible implementation, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor and the driving transistor are P-type transistors.

[0033] In a possible implementation, the fifth control signal and the third control signal are provided by the same control signal source.

[0034] In a possible implementation, the fifth control signal and the third control signal are provided by different control signal sources.

[0035] In a possible implementation, the second control signal and the first control signal are provided by the same control signal source.

[0036] In a possible implementation, the second control signal and the first control signal are provided by different control signal sources.

[0037] The embodiment of the present application further provides a pixel circuit driving method, applied to any of the above-mentioned circuits, and the method comprises the following steps:

[0038] In the reset phase, valid signals are input to the fifth control signal, the first control signal, the second control signal and the third control signal, the first initialization sub-circuit is turned on in response to the fifth control signal, the threshold compensation sub-circuit is turned on in response to the first control signal, the third initialization sub-circuit is turned on in response to the second control signal, and the second initialization sub-circuit is turned on in response to the third control signal; the first initialization signal is written into the control end of the driving sub-circuit, the second initialization signal is written into the anode of the light emitting element, and the second initialization signal is written into the second end of the first storage capacitor;

[0039] In the compensation phase, valid signals are input to the third control signal, the first control signal and the fourth control signal, the second initialization sub-circuit is turned on in response to the third control signal, the threshold compensation sub-circuit is turned on in response to the first control signal, and the driving control branch is turned on in response to the fourth control signal; the second end of the first storage capacitor is subjected to voltage compensation.

[0040] In the data writing phase, valid signals are input to the frequency update signal and the first control signal, the data writing sub-circuit is turned on in response to the frequency update signal, the threshold compensation sub-circuit is turned on in response to the first control signal, and data is written into the first end of the storage sub-circuit via the threshold compensation sub-circuit.

[0041] The embodiment of the present application further provides a display substrate comprising the pixel circuit.

[0042] The embodiment of the present application further provides a display substrate applied to the circuit, and the method comprises:

[0043] In the reset stage, the fifth control signal, the first control signal, the second control signal and the third control signal are inputted with effective signals, the fourth control signal is inputted with an invalid signal, the first initialization sub-circuit is turned on in response to the fifth control signal, the threshold compensation sub-circuit is turned on in response to the first control signal, the third initialization sub-circuit is turned on in response to the second control signal, the second initialization sub-circuit is turned on in response to the third control signal, and the driving control branch is turned off in response to the fourth control signal; the first initialization signal is written into the control end of the driving sub-circuit, the second initialization signal is written into the anode of the light emitting element, and the second initialization signal is written into the second end of the first storage capacitor;

[0044] In the compensation stage, the third control signal, the first control signal and the fourth control signal are inputted with effective signals, the second initialization sub-circuit is turned on in response to the third control signal, the threshold compensation sub-circuit is turned on in response to the first control signal, and the driving control branch is turned on in response to the fourth control signal, and the second end of the first storage capacitor is voltage compensated.

[0045] In the data writing stage, the frequency update signal and the first control signal are inputted with effective signals, the fourth control signal is inputted with an invalid signal, the data writing sub-circuit is turned on in response to the frequency update signal, the threshold compensation sub-circuit is turned on in response to the first control signal, the driving control branch is turned off in response to the fourth control signal, and data is written into the first end of the storage sub-circuit via the threshold compensation sub-circuit.

[0046] The embodiment of the present application has the following beneficial effects:

[0047] The pixel circuit, the driving method and the display substrate provided by the embodiment of the present application have the advantages that the first end of the threshold compensation sub-circuit is connected to the first end of the storage sub-circuit; the second end of the threshold compensation sub-circuit is connected to the data writing sub-circuit, the driving sub-circuit and the initialization sub-circuit respectively; the light emitting element is connected to the driving sub-circuit and the initialization sub-circuit respectively; the initialization sub-circuit initializes the anode voltage of the light emitting element, the control end voltage of the driving sub-circuit and the voltage of the first end of the storage sub-circuit in the reset stage; the threshold compensation sub-circuit compensates the voltage of the first end of the storage sub-circuit in the compensation stage; and the data writing sub-circuit writes data to the first end of the storage sub-circuit through the threshold compensation sub-circuit in the data writing stage. Therefore, the voltage compensation time can be autonomously controlled and is not affected by the refresh frequency of the data writing sub-circuit.

[0048] Of course, implementing any of the products or methods of the present application does not necessarily require all the advantages described above to be achieved at the same time. BRIEF DESCRIPTION OF DRAWINGS

[0049] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and other embodiments can also be obtained by those skilled in the art based on these drawings.

[0050] Figure 1 The first schematic diagram of the pixel circuit provided by the embodiment of the present application;

[0051] Figure 2 The second schematic diagram of the pixel circuit provided by the embodiment of the present application;

[0052] Figure 3 The third schematic diagram of the pixel circuit provided by the embodiment of the present application;

[0053] Figure 4 The fourth schematic diagram of the pixel circuit provided by the embodiment of the present application;

[0054] Figure 5-1 The first signal timing schematic diagram of the pixel circuit provided by the embodiment of the present application;

[0055] Figure 5-2 The second signal timing schematic diagram of the pixel circuit provided by the embodiment of the present application;

[0056] Figure 5-3 The fifth schematic diagram of the pixel circuit provided by the embodiment of the present application;

[0057] Figure 6-1 The sixth schematic diagram of the pixel circuit provided by the embodiment of the present application;

[0058] Figure 6-2 The seventh schematic diagram of the pixel circuit provided by the embodiment of the present application is shown in the following table:

[0059] Figure 6-3 The third signal timing schematic diagram of the pixel circuit provided by the embodiment of the present application is shown in the following table:

[0060] Figure 7 The fourth signal timing schematic diagram of the pixel circuit provided by the embodiment of the present application is shown in the following table:

[0061] Figure 8 The fifth signal timing schematic diagram of the pixel circuit provided by the embodiment of the present application is shown in the following table:

[0062] Figure 9-1 The eighth schematic diagram of the pixel circuit provided by the embodiment of the present application is shown in the following table:

[0063] Figure 9-2 The sixth signal timing schematic diagram of the pixel circuit provided by the embodiment of the present application is shown in the following table. DETAILED DESCRIPTION

[0064] The technical solutions in the embodiments of the present application will be clearly and completely described in connection with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art based on the present application belong to the scope of protection of the present application.

[0065] Firstly, the transistors used in all the embodiments of the present application are described:

[0066] The transistors used in all the embodiments of the present application can be TFTs (Thin Film Transistors), field effect tubes or other devices with the same characteristics. In the present application, for any transistor, the first end of the transistor is the source or the drain, and the second end of the transistor is the drain or the source corresponding to the first end. In one example, each transistor can be a TFT (Thin Film Transistor), and the N-type TFT or the P-type TFT can be selected according to the actual situation. In one example, each transistor in the pixel circuit of the present application can be a MOS tube, which can be an N-type MOS tube or a P-type MOS tube, and the actual situation can be selected.

[0067] The embodiment of the present application provides a pixel circuit, which is shown in the following table: Figure 1 , Figure 1 The first structural schematic diagram of the pixel circuit provided by the embodiment of the present application is shown in the following table, which includes:

[0068] The memory sub-circuit 110, the data writing sub-circuit 120, the threshold compensation sub-circuit 130, the driving sub-circuit 140, the initialization sub-circuit 150, and the light emitting element 160;

[0069] The first end of the threshold compensation sub-circuit 130 is connected to the first end of the memory sub-circuit 110; the second end of the threshold compensation sub-circuit 130 is connected to the data writing sub-circuit 120, the driving sub-circuit 140, and the initialization sub-circuit 150 respectively; and the light emitting element 160 is connected to the driving sub-circuit 140 and the initialization sub-circuit 150 respectively.

[0070] The initialization sub-circuit 150 is configured to initialize the anode voltage of the light emitting element 160, the control end voltage of the driving sub-circuit 140, and the voltage of the first end of the memory sub-circuit 110 in a reset stage.

[0071] The threshold compensation sub-circuit 130 is configured to compensate the voltage of the first end of the memory sub-circuit 110 in a compensation stage.

[0072] The data writing sub-circuit 120 is configured to write data into the memory sub-circuit 110 via the threshold compensation sub-circuit 130 in a data writing stage.

[0073] The driving sub-circuit 140 is configured to generate a driving current for driving the light emitting element 160 to emit light.

[0074] The pixel circuit is a circuit structure for controlling the current flowing through the light emitting element in the pixel circuit by driving the transistor in the pixel circuit. The pixel circuit includes a light emitting element, such as an OLED (Organic Electroluminescence Display), and the pixel circuit structure can be an 8T2C structure or a 9T2C structure, etc. Both are within the protection scope of the present application.

[0075] In the reset stage, the anode voltage of the light emitting element, the control end voltage of the driving sub-circuit, and the voltage of the first end of the memory sub-circuit need to be initialized. For this purpose, the initialization sub-circuit can be used to initialize the anode voltage of the light emitting element, the control end voltage of the driving sub-circuit, and the voltage of the first end of the memory sub-circuit. Specifically, the initialization sub-circuit can be turned on under the control of the control signal at its corresponding control end, and then initialize the anode voltage of the light emitting element, the control end voltage of the driving sub-circuit, and the voltage of the first end of the memory sub-circuit.

[0076] In the compensation phase, the voltage of the first end of the storage sub-circuit is compensated. Specifically, the threshold compensation sub-circuit is turned on under the control of the control signal at the corresponding control end, and then the voltage of the first end of the storage sub-circuit is compensated, so that the voltage difference between the first end of the storage sub-circuit and the control end voltage of the driving sub-circuit is the threshold voltage in the driving sub-circuit.

[0077] In the data writing phase, data is written to the first end of the storage sub-circuit through the threshold compensation sub-circuit. Specifically, the threshold compensation sub-circuit is turned on under the control of the control signal at the corresponding control end, and the data writing sub-circuit is turned on under the control of the control signal at the corresponding control end. The data signal is written to the first end of the storage sub-circuit through the threshold compensation sub-circuit, so that the point potential of the first end of the storage sub-circuit changes to the difference between the data signal and the compensated voltage of the first end of the storage sub-circuit.

[0078] In the light emitting phase, the driving sub-circuit can be used to generate a driving current for driving the light emitting element to emit light.

[0079] The first end of the threshold compensation sub-circuit is connected to the first end of the storage sub-circuit. The second end of the threshold compensation sub-circuit is connected to the data writing sub-circuit, the driving sub-circuit, and the initialization sub-circuit, respectively. The light emitting element is connected to the driving sub-circuit and the initialization sub-circuit, respectively. The initialization sub-circuit initializes the anode voltage of the light emitting element, the control end voltage of the driving sub-circuit, and the voltage of the first end of the storage sub-circuit in the reset phase. The threshold compensation sub-circuit compensates the voltage of the first end of the storage sub-circuit in the compensation phase. The data writing sub-circuit writes data to the first end of the storage sub-circuit through the threshold compensation sub-circuit in the data writing phase. In this way, the voltage compensation time can be autonomously controlled and is not affected by the refresh frequency of the data writing sub-circuit.

[0080] Based on Figure 1 In a possible implementation, referring to FIG. 6, the pixel circuit provided in the embodiment of the present application includes a storage sub-circuit 110, a threshold compensation sub-circuit 120, a data writing sub-circuit 130, a driving sub-circuit 140, and an initialization sub-circuit 150. Figure 2 , Figure 2 FIG. 7 shows a second schematic diagram of a pixel circuit provided in the embodiment of the present application. The storage sub-circuit 110 includes a first storage capacitor 111 and a second storage capacitor 112. The initialization sub-circuit 150 includes a first initialization sub-circuit 151, a second initialization sub-circuit 152, and a third initialization sub-circuit 153. The driving sub-circuit 140 includes a driving control branch 141 and a driving transistor 142.

[0081] The first end of the first storage capacitor 111 is electrically connected to a first power supply voltage.

[0082] The second end of the first storage capacitor 111 is electrically connected with the first end of the second storage capacitor 112 and the first end of the threshold compensation sub-circuit 130 respectively; the control end of the threshold compensation sub-circuit 130 is connected with a first control signal;

[0083] The control end of the data writing sub-circuit 120 is connected with a frequency updating signal, and the first end of the data writing sub-circuit 120 is connected with a data signal; the second end of the data writing sub-circuit 120 is electrically connected with the second end of the threshold compensation sub-circuit 130, the first end of the driving control branch and the second end of the third initialization sub-circuit 153 respectively;

[0084] The second end of the driving control branch is connected with the first end of the driving transistor, and the control end of the driving control branch is connected with a fourth control signal;

[0085] The control end of the third initialization sub-circuit 153 is connected with a third control signal, and the first end of the third initialization sub-circuit 153 is connected with a third initialization signal;

[0086] The first end of the first initialization sub-circuit 151 is connected with the control end of the driving transistor and the second end of the second storage capacitor respectively, the second end of the first initialization sub-circuit 151 is connected with a first initialization signal, and the control end of the first initialization sub-circuit 151 is connected with a fifth control signal;

[0087] The second end of the driving transistor is electrically connected with the anode of the light emitting element 160 and the second end of the second initialization sub-circuit 152 respectively;

[0088] The first end of the second initialization sub-circuit 152 is connected with a second initialization signal, and the control end of the second initialization sub-circuit 152 is connected with a second control signal; the cathode of the light emitting element 160 is connected with a second power supply voltage;

[0089] In the reset stage, the first initialization sub-circuit 151 is turned on under the control of the fifth control signal, the threshold compensation sub-circuit 130 is turned on under the control of the first control signal, the third initialization sub-circuit 153 is turned on under the control of the second control signal, the second initialization sub-circuit 152 is turned on under the control of the third control signal, and the driving control branch 141 is turned off under the control of the fourth control signal; and the first initialization signal is written into the control end of the driving sub-circuit 140, the second initialization signal is written into the anode of the light emitting element 160, and the second initialization signal is written into the second end of the first storage capacitor;

[0090] In the compensation stage, the second initialization sub-circuit 152 is turned on under the control of the third control signal, the threshold compensation sub-circuit 130 is turned on under the control of the first control signal, the driving control branch is turned on under the control of the fourth control signal, and the second end of the first storage capacitor is point-position compensated.

[0091] In the data writing stage, the data writing sub-circuit 120 is turned on under the control of the frequency updating signal, the threshold compensation sub-circuit 130 is turned on under the control of the first control signal, the driving control branch 141 is turned off under the control of the fourth control signal, and data is written into the storage sub-circuit 110 via the threshold compensation sub-circuit 130.

[0092] Based on Figure 2 The embodiment shown in the figure, in a possible implementation, see Figure 3 , Figure 3 A third schematic diagram of a pixel circuit provided by the embodiment of the present application, the circuit further comprises:

[0093] A scan control signal input sub-circuit 170;

[0094] The control end of the scan control signal input sub-circuit 170 is connected with a scan control signal; the second end of the scan control signal input sub-circuit is electrically connected with the second end of the data writing sub-circuit 120, the second end of the third initialization sub-circuit 153, the second end of the threshold compensation sub-circuit 130, and the first end of the driving control branch, respectively.

[0095] As Figure 3 shown in the figure, the pixel circuit further comprises a scan control signal input sub-circuit 170, wherein the control end of the scan control signal input sub-circuit is connected with a scan control signal, so that in the light-emitting stage, the scan control signal input sub-circuit is turned on under the control of the scan control signal, the first power voltage can be sent to the light-emitting element through the scan control signal input sub-circuit, and the light-emitting element can emit light based on the control of the driving sub-circuit.

[0096] Based on Figure 3 The embodiment shown in the figure, in a possible implementation, see Figure 4 , Figure 4 A fourth schematic diagram of a pixel circuit provided by the embodiment of the present application, the threshold compensation sub-circuit 130 comprises a first transistor T1, the scan control signal input sub-circuit comprises a second transistor T2, the second initialization sub-circuit 152 comprises a third transistor T3, the first initialization sub-circuit 151 comprises a fourth transistor T4, the data writing sub-circuit 120 comprises a fifth transistor T5, the third initialization sub-circuit 153 comprises a sixth transistor T6, and the driving control branch comprises a seventh transistor T7.

[0097] The connection relationship between each transistor is as shown in Figure 3

[0098] The control end of the first transistor T1 is connected with the first control signal S1;

[0099] The control end of the second transistor T2 is connected with the scan control signal EM;

[0100] The control end of the third transistor T3 is connected with the second control signal S2;

[0101] The control end of the fourth transistor T4 is connected with the fifth control signal S5;

[0102] The control end of the fifth transistor T5 is connected with the frequency update signal Gp;

[0103] The control end of the sixth transistor T6 is connected with the third control signal S3;

[0104] The control end of the seventh transistor T7 is connected with the fourth control signal S4.

[0105] Data is a data signal, C1 is a first storage capacitor, C2 is a second storage capacitor, VDD is a first power voltage, Vss is a second power voltage. OLED is a light emitting element, Vinit1 is a first initialization signal, Vinit2 is a second initialization signal, and Vinit3 is a third initialization signal.

[0106] Each transistor can be a P-type transistor or an N-type transistor, which can be set based on actual conditions.

[0107] In the reset stage, the nodes N1, N2 and N4 are reset, at this time, T1, T3, T4 and T6 need to be opened at the same time, in addition, in order to avoid the waste of power consumption caused by the closed loop formed between the Vinit3 end and the Vinit2 when T7 is opened, T1, T3, T4 and T6 are opened, T7 needs to be kept closed in the reset stage, then T1 is opened under the control of the first control signal S1, T3 is opened under the control of the second control signal S2, T4 is opened under the control of the fifth control signal S5, T6 is opened under the control of the third control signal S3, and T7 is closed under the control of the fourth control signal S4.

[0108] ​T1, T3, T4 and T6 are turned on at the same time, and T7 is turned off, Vinit1 is written to N2 point, that is, the control end of driving transistor T8, that is, the voltage of the control end of driving transistor T8 is initialized to Vinit1, the anode voltage of the light emitting element is initialized to Vinit2, Vinit3 is written to N3 point, because T1 is turned on, the voltage of N1 point is also Vinit3, that is, the voltage of N1 point and N3 point is initialized to Vinit3. That is, in the reset stage, S1, S6, S5, S3 are valid signals, and S4 is an invalid signal. Among them, the transistor is turned on under the control of the valid signal and is turned off under the control of the invalid signal. For a P-type transistor, the valid signal is a low-level signal, and the invalid signal is a high-level signal; for an N-type transistor, the valid signal is a high-level signal, and the invalid signal is a low-level signal.

[0109] In the compensation stage, T1, T3 and T7 are turned on at the same time, and the voltage of N1 point is Vinit2-Vth, N2=vinit1, wherein Vth is the threshold voltage of driving transistor T8. That is, the voltage difference between the gate and source voltages of driving transistor T8 is the threshold voltage of T8, so as to realize the voltage compensation of driving transistor T8.

[0110] In the data writing stage, T1 and T5 are turned on at the same time, and T7 also needs to be turned off to prevent the data writing process from affecting the source-drain voltage of the driving transistor. After T1 and T5 are turned on at the same time, Data is written to N1 point. T5 and T1 are turned off in turn, and the voltage of N1 point is locked by T1. At this time, the voltage change amount of N1 point is ΔN1=Vdata-(vinit1-Vth), and the change amount of the potential change is fed back to N2 node of the second capacitor C2. Then N2=vinit1+ΔN1=vinit1+Vdata-(vinit1-Vth)=Vdata+Vth.

[0111] In the light emitting stage, the driving transistor generates a conduction between the drain and the source, and the current

[0112]

[0113] Wherein, u and C are both dielectric constants, wherein u and C are related to the material and thickness of the dielectric layer; w / L is the width-to-length ratio of the transistor, and the current flowing through the light emitting element is independent of the threshold voltage Vth of the driving transistor.

[0114] Wherein, VDD is the first power voltage, Vdata is the data signal voltage, Vgs is the gate-source voltage difference of driving transistor T8, and Vth is the threshold voltage of driving transistor T8.

[0115] Based on Figure 4In the shown embodiment, in one possible implementation, the first transistor, the second transistor are N-type transistors, and the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the driving transistor are P-type transistors.

[0116] T1 and T4 in the pixel circuit are N-type transistors, and the rest of the transistors are P-type transistors.

[0117] In one example, T1 and T4 are oxide TFTs.

[0118] Because in the reset stage, T1, T3, T4 and T6 are simultaneously opened, and T7 is closed, based on the characteristics of the P-type transistor, the effective signals input by the first control signal S1, the fourth control signal S4 and the fifth control signal S5 in the reset stage are high-level signals, and the effective signals input by the second control signal S2 and the third control signal S3 in the reset stage are low-level signals.

[0119] Because it is the reset stage, T5 and T2 also remain closed, i.e., the frequency update signal Gp and the EM signal are high-level signals input in the reset stage.

[0120] In the compensation stage, T1, T3 and T7 are simultaneously opened, and the effective signal input by the first control signal S1 in the compensation stage is a high-level signal, and the effective signals input by the second control signal S2 and the fourth control signal S4 in the compensation stage are low-level signals.

[0121] In the compensation stage, the rest of the signals need to be closed, i.e., T2, T4, T5 and T6 need to be closed, and the effective signals input by the EM, the frequency update signal Gp and the third control signal S3 in the compensation stage are high-level signals, and the effective signal input by the fifth control signal S5 in the compensation stage is a low-level signal.

[0122] In the data writing stage, T1 and T5 are simultaneously opened, and T7 is closed, and the effective signals input by the first control signal S1 and the fourth control signal S4 in the compensation stage are high-level signals, and the effective signal input by the frequency update signal Gp in the compensation stage is a low-level signal.

[0123] At this time, T2 and T6 also need to be closed, and the effective signals input by the EM and the third control signal S3 in the compensation stage are high-level signals. T3 and T4 can be closed or opened, and the opening and closing of T3 and T4 do not affect the writing of data, and therefore, the signals input by the second control signal S2 and the fifth control signal S5 can be high-level signals or low-level signals.

[0124] In one example, the first control signal, the second control signal, the third control signal, the fourth control signal, the fifth control signal, the frequency update signal, and the clock pulse of the EM are as shown in FIG. 1. Figure 5-1

[0125] In the reset stage, T1, T3, T4, and T6 are simultaneously turned on, and T2, T7, T5, and T8 are turned off, so as to reset the voltages of nodes N2, N4, and N1.

[0126] In the compensation stage, T1, T3, and T7 are simultaneously turned on, and T2, T4, T5, T6, and T8 are turned off, so as to compensate the voltages of nodes N2, N4, and N1.

[0127] In the data write stage, T1 and T5 are simultaneously turned on, and T2, T4, T3, T6, T7, and T8 are turned off, so as to write the data signal into node N1.

[0128] In one example, the first control signal, the second control signal, the third control signal, the fourth control signal, the fifth control signal, the frequency update signal, and the clock pulse of the EM are as shown in FIG. 1. Figure 5-2

[0129] In the reset stage, T1, T3, T4, and T6 are simultaneously turned on, and T2, T7, T5, and T8 are turned off, so as to reset the voltages of nodes N2, N4, and N1.

[0130] In the compensation stage, T1, T3, and T7 are simultaneously turned on, and T2, T4, T5, T6, and T8 are turned off, so as to compensate the voltages of nodes N2, N4, and N1.

[0131] In the data write stage, T1 and T4 are simultaneously turned on, and T2, T3, T6, T7, and T8 are turned off, so as to write the data signal into node N1.

[0132] Based on the embodiment shown in FIG. 1, in one possible implementation, referring to FIG. 2, Figure 3 Figure 5-3 , Figure 5-3 A fifth schematic diagram of the pixel circuit provided by the embodiment of the present application is shown in FIG. 4, wherein the first initialization signal and the second initialization signal are provided by the same initialization signal source.

[0133] The initial voltage value of the control end of the driving sub-circuit 140 and the initial voltage value of the anode of the light emitting element 160 can be the same, and thus the first initialization signal and the second initialization signal are provided by the same initialization signal source. That is, the second end of the first initialization sub-circuit 151 and the first end of the second initialization sub-circuit 152 are connected to the same initialization signal source, so that the number of initialization signal sources can be reduced.

[0134] Referring to FIG. 4, Figure 6-1 ​​​, Figure 6-1 The fifth schematic diagram of the pixel circuit provided in the embodiment of the present application; the second end of the fourth transistor T4 and the first end of the third transistor T3 are connected with the initialization signal Vinit1.

[0135] In a possible implementation, the first initialization signal and the second initialization signal are provided by different initialization signal sources.

[0136] The initial voltage value of the control end of the driving sub-circuit 140 and the initial voltage value of the anode of the light emitting element 160 can also be different, and thus the first initialization signal and the second initialization signal are provided by different initialization signal sources.

[0137] In a possible implementation, the fifth control signal and the fourth control signal are provided by the same control signal source.

[0138] In the data writing stage, in the case that T4 is in the open state, the fourth control signal and the fifth control signal are time-sequentially identical signals, and thus the fifth control signal and the fourth control signal can be provided by the same control signal source, for example, the fifth control signal and the fourth control signal are both provided by the control signal source 4, that is, the control end of T4 and the control end of T7 are both connected with the control signal source 4, and thus the number of control signal sources can be reduced.

[0139] Referring to Figure 6-2 , Figure 6-2 The fifth schematic diagram of the pixel circuit provided in the embodiment of the present application; the control end of the seventh transistor T7 and the control end of the fourth transistor T4 are both connected with the fourth control signal, and the clock pulses of the control signals are as shown in Figure 6-3 .

[0140] In one example, because the fifth control signal and the fourth control signal are time-sequentially identical signals, the control end of T4 and the control end of T7 are connected with the same gate driving circuit, and thus the number of gate driving circuits can be saved.

[0141] In a possible implementation, the fifth control signal and the fourth control signal are provided by different control signal sources.

[0142] In the data writing stage, in the case that T4 is in the closed state, the fifth control signal and the fourth control signal are time-sequentially different signals, and the fifth control signal and the fourth control signal are provided by different control signal sources.

[0143] Based on Figure 4In the embodiment shown, in one possible implementation, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T3, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the driving transistor T8 are all P-type transistors.

[0144] All the transistors in the pixel circuit can be P-type transistors.

[0145] Because T1, T3, T4, and T6 are all turned on at the reset stage, based on the characteristics of P-type transistors, the effective signals input by the first control signal S1, the second control signal S2, the fifth control signal S5, and the third control signal S3 at the reset stage are low-level signals.

[0146] Because it is the reset stage, T5 and T2 are also kept off, i.e., the effective signals input by the frequency update signal Gp and the EM signal at the reset stage are high-level signals.

[0147] At the compensation stage, T1, T3, and T7 are all turned on, and thus the effective signals input by the first control signal S1, the second control signal S2, and the fourth control signal S4 at the compensation stage are low-level signals.

[0148] At the compensation stage, the remaining signals need to be turned off, i.e., T2, T4, T5, and T6 need to be turned off, and thus the effective signals input by the EM, the frequency update signal Gp, the third control signal S3, and the fifth control signal S5 at the compensation stage are high-level signals.

[0149] At the data writing stage, T1 and T5 are turned on, and thus the effective signals input by the first control signal S1 and the frequency update signal Gp at the data writing stage are low-level signals.

[0150] At this time, T2 and T6 also need to be turned off, and thus the effective signals input by the EM and the third control signal S3 at the data writing stage are high-level signals. T3 and T4 can be turned off or on, and the on-off of T3 and T4 does not affect the writing of data, and thus the signals input by the second control signal S2 and the fifth control signal S5 can be high-level or low-level signals.

[0151] In one example, the clock pulses of the first control signal, the second control signal, the third control signal, the fourth control signal, the fifth control signal, the first control signal, and the frequency update signal are as shown in Figure 7 .

[0152] Based on the embodiment in which all the transistors in the pixel circuit are P-type transistors, in one possible implementation, the fifth control signal and the third control signal are provided by the same control signal source.

[0153] In the data writing stage, when T4 is in the off state, the fifth control signal and the third control signal are signals with the same timing, and the fifth control signal and the third control signal can be provided by the same control signal source, for example, the fifth control signal and the third control signal are provided by the control signal source 3, that is, the control terminal of T4 and the control terminal of T6 are connected to the control signal source 3, so that the number of control signal sources can be reduced.

[0154] In one example, because the fifth control signal and the third control signal are signals with the same timing, the control terminal of T4 and the control terminal of T6 are connected to the same gate drive circuit, so that the number of gate drive circuits can be saved.

[0155] In an embodiment based on all transistors in the pixel circuit being P-type transistors, in one possible implementation, the fifth control signal and the third control signal are provided by different control signal sources.

[0156] In the data writing stage, when T4 is in the on state, the fifth control signal and the third control signal are signals with different timing, and the fifth control signal and the third control signal can also be provided by different control signal sources. That is, the control terminal of T4 and the control terminal of T6 are connected to different gate drive circuits.

[0157] In one example, in the data writing stage, when T4 is in the off state, the fifth control signal and the third control signal are signals with the same timing, and the control terminal of T4 and the control terminal of T6 are connected to different gate drive circuits. In this way, the number of gate drive circuits can be saved. However, the clock signals provided by the two gate drive circuits have the same timing.

[0158] In an embodiment based on all transistors in the pixel circuit being P-type transistors, in one possible implementation, the second control signal and the first control signal are signals provided by the same gate drive circuit.

[0159] Because the second control signal and the first control signal are signals with the same timing in the reset stage and the compensation stage, and in the writing stage, the on-off of T3 does not affect data writing, that is, as long as T4 is off, the level of the second control signal can be high or low, that is, the level of the second control signal in the writing stage can also be low, as shown in Figure 8 When the second control signal is low in the writing stage, the second control signal and the first control signal have the same timing.

[0160] At this time, the second control signal and the first control signal can be provided by the same gate drive circuit, so that the number of gate drive circuits can be saved.

[0161] Referring toFigure 9-1 , Figure 9-1 The fifth schematic diagram of the pixel circuit provided in the embodiment of the present application; the control end of the fourth transistor T4 and the control end of the sixth transistor T6 are connected with the third control signal, the control end of the first transistor T1 and the control end of the third transistor T3 are connected with the second control signal, and the clock pulses of each control signal are as shown in Figure 9-2 .

[0162] Based on the embodiment that all the transistors in the pixel circuit can be P-type transistors, in a possible implementation, the second control signal and the first control signal are signals provided by different gate driving circuits.

[0163] The second control signal only provides an effective signal when T3 needs to be turned on, that is, the second control signal is as shown in Figure 7 , therefore, the second control signal and the first control signal are not completely the same in timing, and then the second control signal and the first control signal are signals provided by different gate driving circuits, that is, the second control signal and the first control signal are clock pulses provided by the corresponding gate driving circuits.

[0164] The embodiment of the present application further provides a pixel circuit driving method, applied to any one of the above-mentioned circuits, and the method comprises the following steps:

[0165] In the reset stage, an effective signal is input to the fifth control signal, the first control signal, the second control signal and the third control signal, and an invalid signal is input to the fourth control signal, the first initialization sub-circuit is turned on in response to the fifth control signal, the threshold compensation sub-circuit is turned on in response to the first control signal, the third initialization sub-circuit is turned on in response to the second control signal, the second initialization sub-circuit is turned on in response to the third control signal, and the driving control branch is turned off in response to the fourth control signal; the first initialization signal is written into the control end of the driving sub-circuit, the second initialization signal is written into the anode of the light emitting element, and the second initialization signal is written into the second end of the first storage capacitor;

[0166] In the compensation stage, an effective signal is input to the third control signal, the first control signal and the fourth control signal, the second initialization sub-circuit is turned on in response to the third control signal, the threshold compensation sub-circuit is turned on in response to the first control signal, and the driving control branch is turned on in response to the fourth control signal; the second end of the first storage capacitor is voltage compensated;

[0167] In the data writing stage, the frequency updating signal and the first control signal are inputted with valid signals, the fourth control signal is inputted with invalid signal, the data writing sub-circuit is turned on in response to the frequency updating signal, the threshold compensation sub-circuit is turned on in response to the first control signal, the driving control branch is turned off in response to the fourth control signal, and data is written into the first end of the storage sub-circuit via the threshold compensation sub-circuit.

[0168] The embodiment of the present application further provides an electronic device, including a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory complete mutual communication through the communication bus,

[0169] The memory is used for storing a computer program.

[0170] The processor is used for executing the program stored on the memory, and the following steps are realized:

[0171] In the reset stage, the fifth control signal, the first control signal, the second control signal and the third control signal are inputted with valid signals, the fourth control signal is inputted with invalid signal, the first initialization sub-circuit is turned on in response to the fifth control signal, the threshold compensation sub-circuit is turned on in response to the first control signal, the third initialization sub-circuit is turned on in response to the second control signal, the second initialization sub-circuit is turned on in response to the third control signal, and the driving control branch is turned off in response to the fourth control signal; the first initialization signal is written into the control end of the driving sub-circuit, the second initialization signal is written into the anode of the light emitting element, and the second initialization signal is written into the second end of the first storage capacitor.

[0172] In the compensation stage, the third control signal, the first control signal and the fourth control signal are inputted with valid signals, the second initialization sub-circuit is turned on in response to the third control signal, the threshold compensation sub-circuit is turned on in response to the first control signal, and the driving control branch is turned on in response to the fourth control signal; the second end of the first storage capacitor is voltage compensated.

[0173] In the data writing stage, the frequency updating signal and the first control signal are inputted with valid signals, the fourth control signal is inputted with invalid signal, the data writing sub-circuit is turned on in response to the frequency updating signal, the threshold compensation sub-circuit is turned on in response to the first control signal, the driving control branch is turned off in response to the fourth control signal, and data is written into the first end of the storage sub-circuit via the threshold compensation sub-circuit.

[0174] The communication bus mentioned in the above electronic device can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The communication bus can be divided into an address bus, a data bus, a control bus, etc. For the convenience of representation, only one thick line is used in the figure, but it does not mean that there is only one bus or one type of bus.

[0175] The communication interface is used for communication between the above electronic device and other devices.

[0176] The memory can include a Random Access Memory (RAM) and can also include a Non-Volatile Memory (NVM), such as at least one disk memory. Optionally, the memory can also be at least one storage device located away from the above-mentioned processor.

[0177] The above-mentioned processor can be a general-purpose processor, including a Central Processing Unit (CPU), a Network Processor (NP), etc.; can also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field-Programmable Gate Array (FPGA) or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component.

[0178] In another embodiment provided in the present application, a computer readable storage medium is also provided, and the computer readable storage medium stores a computer program. When the computer program is executed by a processor, the steps of any of the above pixel circuit driving methods are implemented.

[0179] In another embodiment provided in the present application, a computer program product containing instructions is also provided, and when the computer program product is run on a computer, the computer is caused to execute any of the pixel circuit driving methods in the above embodiments.

[0180] In the embodiments described above, all or some of the steps can be implemented by hardware, software, firmware or any combination thereof. When implemented in software, all or some of the steps can be implemented in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed by a computer, the computer program instructions cause the computer to perform all or some of the steps as described in the embodiments. The computer can be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatuses. The computer instructions can be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another computer readable storage medium, for example, the computer instructions can be transmitted from a website, a computer, a server or a data center to another website, computer, server or data center through a wired (for example, coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (for example, infrared, wireless, microwave, etc.) manner. The computer readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. integrated with one or more available media. The available media can be a magnetic medium (for example, floppy disk, hard disk, magnetic tape), an optical medium (for example, DVD), or a semiconductor medium (for example, solid state disk (SSD)), etc.

[0181] It should be noted that the relative terms such as first and second, etc. are used herein only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed or inherent to such a process, method, article or device. Without more limitations, the element defined by the statement "comprising a" does not exclude the presence of additional identical elements in the process, method, article or device including the element.

[0182] Each of the embodiments in the specification is described in a related manner, and the same or similar parts between each of the embodiments can be referred to each other. Each of the embodiments focuses on the difference from other embodiments.

[0183] The above description is only the preferred embodiment of the present application, and is not intended to limit the protection scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A pixel circuit, characterized in that, The circuit includes: The system includes a storage sub-circuit, a data writing sub-circuit, a threshold compensation sub-circuit, a driving sub-circuit, an initialization sub-circuit, and a light-emitting element. The storage sub-circuit includes a first storage capacitor and a second storage capacitor. The initialization sub-circuit includes a first initialization sub-circuit, a second initialization sub-circuit, and a third initialization sub-circuit. The driving sub-circuit includes a driving control branch and a driving transistor. The first terminal of the first storage capacitor is electrically connected to the first power supply voltage; the second terminal of the first storage capacitor is electrically connected to the first terminal of the second storage capacitor and the first terminal of the threshold compensation sub-circuit; the control terminal of the threshold compensation sub-circuit is connected to the first control signal. The control terminal of the data writing sub-circuit is connected to the frequency update signal, and the first terminal of the data writing sub-circuit is connected to the data signal; the second terminal of the data writing sub-circuit is electrically connected to the second terminal of the threshold compensation sub-circuit, the first terminal of the drive control branch, and the second terminal of the third initialization sub-circuit, respectively. The second end of the drive control branch is connected to the first end of the drive transistor, and the control end of the drive control branch is connected to the fourth control signal. The control terminal of the third initialization sub-circuit is connected to the third control signal, and the first terminal of the third initialization sub-circuit is connected to the third initialization signal. The first terminal of the first initialization sub-circuit is connected to the control terminal of the driving transistor and the second terminal of the second storage capacitor, respectively. The second terminal of the first initialization sub-circuit is connected to the first initialization signal, and the control terminal of the first initialization sub-circuit is connected to the fifth control signal. The second terminal of the driving transistor is electrically connected to the anode of the light-emitting element and the second terminal of the third initialization sub-circuit, respectively. The first terminal of the second initialization sub-circuit is connected to the second initialization signal, and the control terminal of the second initialization sub-circuit is connected to the second control signal; the cathode of the light-emitting element is connected to the second power supply voltage. During the reset phase, the first initialization sub-circuit is turned on under the control of the fifth control signal, the threshold compensation sub-circuit is turned on under the control of the first control signal, the third initialization sub-circuit is turned on under the control of the second control signal, the second initialization sub-circuit is turned on under the control of the third control signal, and the drive control branch is turned off under the control of the fourth control signal; the first initialization signal is written to the control terminal of the drive sub-circuit, the second initialization signal is written to the anode of the light-emitting element, and the second initialization signal is written to the second terminal of the first storage capacitor; During the compensation phase, the second initialization sub-circuit is turned on under the control of the third control signal, the threshold compensation sub-circuit is turned on under the control of the first control signal, and the drive control branch is turned on under the control of the fourth control signal to perform point compensation on the second end of the first storage capacitor. During the data writing phase, the data writing sub-circuit is turned on under the control of the frequency update signal, the threshold compensation sub-circuit is turned on under the control of the first control signal, and the drive control branch is turned off under the control of the fourth control signal, so that the data is written to the first terminal of the storage sub-circuit via the threshold compensation sub-circuit. The driving sub-circuit is used to generate a driving current that drives the light-emitting element to emit light.

2. The circuit according to claim 1, characterized in that, The circuit also includes: Scan control signal input sub-circuit; The control terminal of the scan control signal input sub-circuit is connected to the scan control signal; the second terminal of the scan control signal input sub-circuit is electrically connected to the second terminal of the data writing sub-circuit, the second terminal of the third initialization sub-circuit, the second terminal of the threshold compensation sub-circuit, and the first terminal of the drive control branch.

3. The circuit according to claim 2, characterized in that, The threshold compensation subcircuit includes a first transistor, the scan control signal input subcircuit includes a second transistor, the second initialization subcircuit includes a third transistor, the first initialization subcircuit includes a fourth transistor, the data writing subcircuit includes a fifth transistor, the third initialization subcircuit includes a sixth transistor, and the drive control branch includes a seventh transistor.

4. The circuit according to claim 3, characterized in that, The first transistor and the second transistor are N-type transistors, and the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the driving transistor are P-type transistors.

5. The circuit according to claim 4, characterized in that, The first initialization signal and the second initialization signal are provided by the same initialization signal source.

6. The circuit according to claim 4, characterized in that, The first initialization signal and the second initialization signal are provided by different initialization signal sources.

7. The circuit according to claim 4, characterized in that, The fifth control signal and the fourth control signal are provided by the same control signal source.

8. The circuit according to claim 4, characterized in that, The fifth control signal and the fourth control signal are provided by different control signal sources.

9. The circuit according to claim 4, characterized in that, The first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the driving transistor are P-type transistors.

10. The circuit according to claim 9, characterized in that, The fifth control signal and the third control signal are provided by the same control signal source.

11. The circuit according to claim 9, characterized in that, The fifth control signal and the third control signal are provided by different control signal sources.

12. The circuit according to claim 9, characterized in that, The second control signal and the first control signal are provided by the same control signal source.

13. The circuit according to claim 9, characterized in that, The second control signal and the first control signal are provided by different control signal sources.

14. A pixel circuit driving method, characterized in that, Applied to the circuit according to any one of claims 1 to 13, the method comprises: During the reset phase, valid signals are input to the fifth control signal, the first control signal, the second control signal, and the third control signal, while an invalid signal is input to the fourth control signal. The first initialization sub-circuit is turned on in response to the fifth control signal, the threshold compensation sub-circuit is turned on in response to the first control signal, the third initialization sub-circuit is turned on in response to the second control signal, the second initialization sub-circuit is turned on in response to the third control signal, and the drive control branch is turned off in response to the fourth control signal. The first initialization signal is written to the control terminal of the drive sub-circuit, the second initialization signal is written to the anode of the light-emitting element, and the second initialization signal is written to the second terminal of the first storage capacitor. During the compensation phase, valid signals are input to the third control signal, the first control signal, and the fourth control signal. The second initialization sub-circuit responds to the third control signal and turns on, the threshold compensation sub-circuit responds to the first control signal and turns on, and the drive control branch responds to the fourth control signal and turns on, to perform voltage compensation on the second terminal of the first storage capacitor. During the data writing phase, valid signals are input to the frequency update signal and the first control signal, and invalid signals are input to the fourth control signal. The data writing sub-circuit responds to the frequency update signal being turned on, the threshold compensation sub-circuit responds to the first control signal being turned on, and the drive control branch responds to the fourth control signal being turned off, and writes data to the first terminal of the storage sub-circuit via the threshold compensation sub-circuit.

15. A display substrate, characterized in that, Includes the pixel circuit described in any one of claims 1 to 13.

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