An SOI LIGBT with integrated NMOS and multiple floating field plates

Abstract

This invention belongs to the field of power semiconductor technology and relates to SOI LIGBTs with integrated NMOS and multiple floating field plates. This invention introduces a double-layer floating field plate above the drift region of the SOI LIGBT, utilizing the floating metal field plate to achieve adaptive switching of the auxiliary NMOS integrated on the cathode side. During forward conduction, the lower anode voltage keeps the second NMOS in a high-resistance state, causing the node voltage across the parasitic diode to exceed its built-in potential and turn it on, providing an additional electron injection source for the drift region and reducing the on-state voltage drop. During turn-off, the high anode voltage increases the gate voltage of the second NMOS through capacitive coupling of the floating field plate, enabling it to conduct adaptively, providing a low-resistance path for excess holes in the drift region and reducing turn-off losses. In the saturation state, the second NMOS under the high anode voltage enters a strong inversion state, causing the parasitic diode to exit the forward bias state, cutting off the additional electron injection source, and strictly clamping the saturated anode current at a low level, improving the device's short-circuit withstand capability.

Description

Technical Field

[0001] This invention belongs to the field of power semiconductor technology and relates to a SOILIGBT (Lateral Insulated Gate Bipolar Transistor) with integrated NMOS and multiple floating field plates. Background Technology

[0002] An insulated-gate bipolar transistor (IGBT) is a composite power semiconductor device composed of a metal-oxide-semiconductor field-effect transistor (MOSFET) and a bipolar transistor (BJT), combining the high input impedance of a MOSFET with the conductivity modulation characteristics of a BJT. It features low conduction loss, high current capability, high voltage withstand capability, good thermal stability, and integrability, making it widely used in intelligent power integrated circuits in transportation, energy conversion, industrial control, and consumer electronics. In particular, with the breakthrough in silicon-on-insulator (SOI) technology, the leakage current problem of bulk silicon IGBTs has been completely solved by using a buried oxide layer to isolate the silicon substrate. This allows SOI LIGBTs to demonstrate unique value in high-frequency, high-temperature, and high-reliability scenarios, becoming one of the key technological directions in power semiconductors.

[0003] LIGBT devices utilize conductivity modulation to achieve a low forward conduction voltage drop in their drift region. However, during the turn-off phase, the large number of non-equilibrium carriers stored in the drift region must be depleted through extraction or recombination, a process that causes significant turn-off losses, thus limiting the applicability of the device under high-frequency, high-power-density conditions. Therefore, the key to developing high-speed, low-loss novel LIGBTs lies in coordinating the trade-off between conduction and turn-off losses, and seeking new structures or methods to further reduce the on-state voltage drop or accelerate the turn-off process. To alleviate these contradictions, current research mainly focuses on three approaches: first, controlling the conductivity modulation effect in the drift region and its non-equilibrium carrier storage characteristics during conduction to optimize conduction behavior; second, regulating the electron-hole recombination process by controlling the non-equilibrium carrier lifetime; and third, promoting rapid extraction of non-equilibrium carriers during the turn-off phase to improve turn-off characteristics. Commonly used techniques for these directions include charge storage layer technology, superjunction structures, auxiliary gate design, carrier lifetime control, short-circuit anodes, and electric field modulation techniques.

[0004] Furthermore, there is a significant trade-off between saturation current density and short-circuit withstand time. Under short-circuit conditions, LIGBTs must simultaneously withstand high voltage and extremely high saturation current. This leads to a massive instantaneous Joule heating within the device, causing a significant temperature rise and making the device highly susceptible to thermal breakdown due to overheating. On the other hand, the high current density can easily trigger the conduction of the internal parasitic thyristor, causing the gate to lose its ability to control the current and inducing a latch-up effect. To alleviate this contradiction, researchers typically introduce distributed resistance or current-limiting structures to improve short-circuit withstand capability by reducing the saturation current or optimizing the hole extraction path. However, this often comes at the cost of sacrificing the on-state voltage drop.

[0005] To this end, the present invention proposes an SOI LIGBT with integrated NMOS and multiple floating field plates to achieve low on-state voltage drop, low turn-off loss and long short-circuit withstand time. Summary of the Invention

[0006] To address the aforementioned problems, this invention proposes an SOI LIGBT with integrated NMOS and multiple floating field plates.

[0007] The technical solution of this invention is:

[0008] An SOI LIGBT with integrated NMOS and multiple floating field plates includes a P-type substrate 1, a buried oxide layer 2, and an N-type drift region 3 stacked sequentially from bottom to top; along the lateral direction of the device, the upper layer of the N-type drift region 3 has a first NMOS structure, a second NMOS structure, a cathode structure, a gate structure, a multiple floating field plate structure, and an anode structure sequentially arranged along the lateral direction of the device; the horizontal direction from the first NMOS structure to the anode structure is defined as the x-direction;

[0009] The first NMOS structure, the second NMOS structure, and the gate structure are all planar gate structures; the first dielectric isolation trench 4 completely isolates the first NMOS structure from the second NMOS structure, and the second dielectric isolation trench 5 completely isolates the second MOS structure from the cathode structure; the first NMOS structure / second NMOS structure includes a first P-base region 6 / second P-base region 12, a first P+ source region 7 / second P+ source region 13, a first N+ source region 8 / second N+ source region 14, and a first N+ drain region 9 / second N+ drain region 15, a first gate dielectric layer 10 / second gate dielectric layer 16, and a first gate polysilicon layer 11 / second gate polysilicon layer 17 located on the upper surface of the first gate dielectric layer 10 / second gate dielectric layer 16; the first P+ source region 7 / second P+ source region 9 / 20 ... 13 and the first N+ source region 8 / second N+ source region 14 are arranged sequentially along the x-direction on the side of the upper surface of the first P-base region 6 / second P-base region 12 away from the first dielectric isolation trench 4 / second dielectric isolation trench 5; the first N+ drain region 9 / second N+ drain region 15 is located on the side of the upper surface of the first P-base region 6 / second P-base region 12 close to the first dielectric isolation trench 4 / second dielectric isolation trench 5; the first gate dielectric layer 10 / second gate dielectric layer 16 and the first gate polysilicon layer 11 / second gate polysilicon layer 17 are located on the upper layer of the first P-base region 6 / second P-base region 12 between the first N+ source region 8 / second N+ source region 14 and the first N+ drain region 9 / second N+ drain region 15; the cathode electrode is led out from the surfaces of the first P+ source region 7, the second P+ source region 13, the first N+ source region 8 and the second N+ source region 14.

[0010] The cathode structure includes a P-type well region 18, a P+ body contact region 19, and an N+ cathode region 20 located on the upper surface of the N-type drift region 3; the P+ body contact region 19 and the N+ cathode region 20 are arranged sequentially along the x-direction at the end of the upper surface of the P-type well region 18 away from the N-type drift region 3; the P+ body contact region 19 is connected to the lead-out end of the second N+ drain region 15 by a floating ohmic contact; the N+ cathode region 6 is connected to the lead-out end of the first N+ drain region 9 by a floating ohmic contact.

[0011] The gate structure includes a third gate dielectric layer 21 and a third gate polysilicon layer 22 located on the upper surface of the third gate dielectric layer 21; the third gate dielectric layer 21 is located on the upper layer of the P-type well region 18 between the N+ cathode region 20 and the N-type drift region 3; the third gate polysilicon layer 22 and the first gate polysilicon layer 11 jointly lead out the gate electrode.

[0012] The multi-floating field plate structure includes a field oxide layer 23, a floating polysilicon field plate group 24, and a floating metal field plate group 25. The field oxide layer 23 is located on the upper layer of the N-type drift region 3 between the gate structure and the anode structure. The floating polysilicon field plate group 24 is located in the dielectric layer 26 on the upper surface of the field oxide layer 23, with one side close to the third gate polysilicon layer 22 and the other side close to the anode region, and includes multiple floating polysilicon field plates that are equally spaced in the x-direction. The floating metal field plate group 25 is located above the floating polysilicon field plate group 24, and includes multiple floating metal field plates that are equally spaced in the x-direction and are staggered with the floating polysilicon field plates.

[0013] The first gate polysilicon layer 11 of the first NMOS structure is electrically connected to the floating metal field plate in the floating metal field plate group 25.

[0014] The anode structure includes an N-type buffer layer 26 and a P+ anode region 27 located on the upper surface of the N-type drift region 3; the P+ anode region 27 is located on the upper surface of the N-type buffer layer 26, and the surface of the P+ anode region 27 is led out as an anode electrode.

[0015] The beneficial effects of this invention are as follows: compared to traditional SOI LIGBTs, the LIGBT described in this invention introduces a multi-floating field plate structure for adaptive control of the auxiliary NMOS switching. During conduction, the parasitic diode adaptively turns on to maintain a high-conductivity modulation effect; during turn-off, the auxiliary NMOS adaptively turns on to provide a low-resistance hole discharge path; in a short-circuit state, the parasitic diode is completely turned off to cut off additional electron injection sources, clamping the saturated anode current to a lower level, significantly improving the device's short-circuit withstand capability. Therefore, the new structure coordinates the trade-off between conduction and turn-off losses and achieves a longer short-circuit withstand time. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the cell structure of Embodiment 1 proposed in this invention. Detailed Implementation

[0017] The technical solution of the present invention will now be described in detail with reference to the accompanying drawings and embodiments:

[0018] Example 1

[0019] like Figure 1 As shown, the structure of this example includes an SOI LIGBT with integrated NMOS and multiple floating field plates, comprising a P-type substrate 1, a buried oxide layer 2, and an N-type drift region 3 stacked sequentially from bottom to top; along the lateral direction of the device, the upper layer of the N-type drift region 3 has a first NMOS structure, a second NMOS structure, a cathode structure, a gate structure, a multiple floating field plate structure, and an anode structure sequentially arranged along the lateral direction of the device; the horizontal direction from the first NMOS structure to the anode structure is defined as the x-direction;

[0020] The first NMOS structure, the second NMOS structure, and the gate structure are all planar gate structures; the first dielectric isolation trench 4 completely isolates the first NMOS structure from the second NMOS structure, and the second dielectric isolation trench 5 completely isolates the second MOS structure from the cathode structure; the first NMOS structure / second NMOS structure includes a first P-base region 6 / second P-base region 12, a first P+ source region 7 / second P+ source region 13, a first N+ source region 8 / second N+ source region 14, and a first N+ drain region 9 / second N+ drain region 15, a first gate dielectric layer 10 / second gate dielectric layer 16, and a first gate polysilicon layer 11 / second gate polysilicon layer 17 located on the upper surface of the first gate dielectric layer 10 / second gate dielectric layer 16; the first P+ source region 7 / second P+ source region 9 / 20 ... 13 and the first N+ source region 8 / second N+ source region 14 are arranged sequentially along the x-direction on the side of the upper surface of the first P-base region 6 / second P-base region 12 away from the first dielectric isolation trench 4 / second dielectric isolation trench 5; the first N+ drain region 9 / second N+ drain region 15 is located on the side of the upper surface of the first P-base region 6 / second P-base region 12 close to the first dielectric isolation trench 4 / second dielectric isolation trench 5; the first gate dielectric layer 10 / second gate dielectric layer 16 and the first gate polysilicon layer 11 / second gate polysilicon layer 17 are located on the upper layer of the first P-base region 6 / second P-base region 12 between the first N+ source region 8 / second N+ source region 14 and the first N+ drain region 9 / second N+ drain region 15; the cathode electrode is led out from the surfaces of the first P+ source region 7, the second P+ source region 13, the first N+ source region 8 and the second N+ source region 14.

[0021] The cathode structure includes a P-type well region 18, a P+ body contact region 19, and an N+ cathode region 20 located on the upper surface of the N-type drift region 3; the P+ body contact region 19 and the N+ cathode region 20 are arranged sequentially along the x-direction at the end of the upper surface of the P-type well region 18 away from the N-type drift region 3; the P+ body contact region 19 is connected to the lead-out end of the second N+ drain region 15 by a floating ohmic contact; the N+ cathode region 6 is connected to the lead-out end of the first N+ drain region 9 by a floating ohmic contact.

[0022] The gate structure includes a third gate dielectric layer 21 and a third gate polysilicon layer 22 located on the upper surface of the third gate dielectric layer 21; the third gate dielectric layer 21 is located on the upper layer of the P-type well region 18 between the N+ cathode region 20 and the N-type drift region 3; the third gate polysilicon layer 22 and the first gate polysilicon layer 11 jointly lead out the gate electrode.

[0023] The multi-floating field plate structure includes a field oxide layer 23, a floating polysilicon field plate group 24, and a floating metal field plate group 25. The field oxide layer 23 is located on the upper layer of the N-type drift region 3 between the gate structure and the anode structure. The floating polysilicon field plate group 24 is located in the dielectric layer 26 on the upper surface of the field oxide layer 23, with one side close to the third gate polysilicon layer 22 and the other side close to the anode region, and includes multiple floating polysilicon field plates that are equally spaced in the x-direction. The floating metal field plate group 25 is located above the floating polysilicon field plate group 24, and includes multiple floating metal field plates that are equally spaced in the x-direction and are staggered with the floating polysilicon field plates.

[0024] The first gate polysilicon layer 11 of the first NMOS structure is electrically connected to the floating metal field plate in the floating metal field plate group 25.

[0025] The anode structure includes an N-type buffer layer 26 and a P+ anode region 27 located on the upper surface of the N-type drift region 3; the P+ anode region 27 is located on the upper surface of the N-type buffer layer 26, and the surface of the P+ anode region 27 is led out as an anode electrode.

[0026] The working principle of this example is as follows: The device shown integrates an auxiliary NMOS on the cathode side, which is adaptively controlled by a floating metal field plate. The device performance is optimized by controlling the adaptive turn-on and turn-off of the auxiliary NMOS channel. During forward conduction, the lower anode voltage keeps the second NMOS in a high-resistance state, causing the node voltage across the parasitic diode to exceed its built-in potential and turn it on. This provides an additional electron injection source for the drift region, significantly enhancing the conductivity modulation effect in the drift region and reducing the on-state voltage drop. During turn-off, the higher anode voltage increases the gate voltage of the second NMOS through the capacitive coupling of the floating field plate, enabling it to conduct adaptively. This provides a low-resistance path for excess holes in the drift region, reducing turn-off losses. In the saturation state, the second NMOS under the high anode voltage enters a strong inversion state, causing the parasitic diode to exit the forward bias state, cutting off the additional electron injection source, and strictly clamping the saturated anode current at a low level, thus improving the device's short-circuit withstand capability.

Claims

1. An SOI LIGBT with integrated NMOS and multiple floating field plates, comprising a P-type substrate (1), a buried oxide layer (2), and an N-type drift region (3) stacked sequentially from bottom to top; characterized in that, Along the lateral direction of the device, the upper layer of the N-type drift region (3) has a first NMOS structure, a second NMOS structure, a cathode structure, a gate structure, a multi-floating field plate structure and an anode structure in sequence; the horizontal direction from the first NMOS structure to the anode structure is defined as the x-direction; The first NMOS structure, the second NMOS structure, and the gate structure are all planar gate structures; a first dielectric isolation trench (4) is provided to completely isolate the first NMOS structure from the second NMOS structure, and a second dielectric isolation trench (5) is provided to completely isolate the second MOS structure from the cathode structure; the first NMOS structure includes a first P-base region (6), a first P+ source region (7), a first N+ source region (8), a first N+ drain region (9), a first gate dielectric layer (10), and a first gate polysilicon layer (11) located on the upper surface of the N-type drift region (3); the first P+ source region (7) and the first N+ source region (8) are arranged sequentially along the x-direction on the side of the upper surface of the first P-base region (6) away from the first dielectric isolation trench (4); the first N+ drain region (9) is located on the side of the upper surface of the first P-base region (6) close to the first dielectric isolation trench (4); the first gate dielectric layer (10) and the first gate polysilicon layer (11) are located in the first N+ source region (8). The upper layer of the first P base region (6) between the first N+ drain region (9); The second NMOS structure includes a second P-base region (12), a second P+ source region (13), a second N+ source region (14), a second N+ drain region (15), a second gate dielectric layer (16), and a second gate polysilicon layer (17) located on the upper surface of the N-type drift region (3); the second P+ source region (13) and the second N+ source region (14) are arranged sequentially along the x-direction on the upper surface of the second P-base region (12) away from the second dielectric isolation trench (5). The second N+ drain region (15) is located on the upper surface of the second P base region (12) near the second dielectric isolation trench (5); the second gate dielectric layer (16) and the second gate polysilicon layer (17) are located on the upper layer of the second P base region (12) between the second N+ source region (14) and the second N+ drain region (15); the first P+ source region (7), the second P+ source region (13), the first N+ source region (8) and the second N+ source region (14) jointly lead out the cathode electrode; The cathode structure includes a P-type well region (18), a P+ body contact region (19), and an N+ cathode region (20) located on the upper surface of the N-type drift region (3); the P+ body contact region (19) and the N+ cathode region (20) are arranged sequentially along the x-direction at one end of the upper surface of the P-type well region (18) away from the N-type drift region (3); the P+ body contact region (19) is connected to the lead-out end of the second N+ drain region (15) by a floating ohmic contact; the N+ cathode region (6) is connected to the lead-out end of the first N+ drain region (9) by a floating ohmic contact. The gate structure includes a third gate dielectric layer (21) and a third gate polysilicon layer (22) located on the upper surface of the third gate dielectric layer (21); the third gate dielectric layer (21) is located on the upper layer of the P-type well region (18) between the N+ cathode region (20) and the N-type drift region (3); the third gate polysilicon layer (22) and the first gate polysilicon layer (11) jointly lead out the gate electrode; The multi-floating field plate structure includes a field oxide layer (23), a floating polysilicon field plate group (24), and a floating metal field plate group (25); the field oxide layer (23) is located on the upper layer of the N-type drift region (3) between the gate structure and the anode structure; the floating polysilicon field plate group (24) is located on the upper surface of the field oxide layer (23), one side is close to the third gate polysilicon layer (22), and the other side is close to the anode region, including multiple floating polysilicon field plates that are equally spaced in the x-direction; the floating metal field plate group (25) is located in the dielectric layer (26) on the upper surface of the floating polysilicon field plate group (24), including multiple floating metal field plates that are equally spaced in the x-direction and are staggered with the floating polysilicon field plates; The first gate polysilicon layer (11) of the first NMOS structure is electrically connected to the floating metal field plate in the floating metal field plate group (25); The anode structure includes an N-type buffer layer (26) and a P+ anode region (27) located on the upper surface of the N-type drift region (3); the P+ anode region (27) is located on the upper surface of the N-type buffer layer (26), and the surface of the P+ anode region (27) is led out as an anode electrode.

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