Compressed framework for generating log-likelihood ratios

Abstract

Apparatus, systems, and methods for improving decoding operations in non-volatile memory are described. An example method includes performing a first hard read to obtain a first set of values stored in a plurality of cells, storing the first set of values in a first buffer, performing a plurality of subsequent hard reads on the plurality of cells to obtain a plurality of subsequent sets of values, for each subsequent set of values, performing the following operations: calculating a quality metric; storing a difference between the subsequent set of values and the set of values stored in the first buffer in a second buffer, wherein the difference is stored in a compressed format; and in response to the quality metric exceeding a threshold, storing the subsequent set of values in the first buffer, and generating a log likelihood ratio based on the first buffer and the second buffer.

Description

Technical Field

[0001] This patent document generally relates to non-volatile memory devices, and more particularly to error correction in non-volatile memory devices. Background Technology

[0002] Data integrity is an important feature for any data storage device and data transfer. Strong error correction codes (ECC) are recommended for all types of data storage devices, including NAND flash memory devices.

[0003] Solid-state drives (SSDs) use multi-layer NAND flash memory devices for permanent storage. However, multi-layer NAND flash memory devices can be inherently unreliable and often require ECC to achieve a significant improvement in data reliability, but at the cost of additional storage space and computing resources for ECC parity bits. There is a need for ECC implementations that can provide low-complexity solutions with minimal storage requirements. Summary of the Invention

[0004] Embodiments of the disclosed technology relate to methods, systems, and apparatus for generating log-likelihood (LLR) in compressed form. Among other features and benefits, the methods and apparatus described in this document advantageously support flexible LLR bit widths using the same storage requirements and can accommodate a wide range of bit error conditions that may occur in non-volatile memory devices throughout their lifetime.

[0005] In one exemplary aspect, a method for improving decoding operations in non-volatile memory is described. The method includes performing a first hard read to obtain a first set of values ​​stored in a plurality of cells, storing the first set of values ​​in a first buffer, performing a plurality of subsequent hard reads on the plurality of cells to obtain a plurality of subsequent sets of values, and for each of the values ​​of the plurality of subsequent sets, performing the following operations: (i) calculating a quality metric, (ii) storing the difference between the value of the subsequent set and a set of values ​​stored in the first buffer in a second buffer, wherein the difference is stored in a compressed format, and (iii) in response to the quality metric exceeding a threshold, storing the value of the subsequent set in the first buffer, generating a log-likelihood ratio based on the first and second buffers, and performing a decoding operation based on the log-likelihood ratio.

[0006] In another exemplary aspect, a system for improving decoding operations in non-volatile memory is described. The system includes a processor and a memory including instructions stored thereon, wherein the instructions, when executed by the processor, cause the processor to perform a first hard read to obtain a first set of values ​​stored in a plurality of cells, store the first set of values ​​in a first buffer, perform a plurality of subsequent hard reads on the plurality of cells to obtain a plurality of subsequent sets of values, and for each of the values ​​of the plurality of subsequent sets, perform the following operations: (i) calculate a quality metric, (ii) store the difference between the value of the subsequent set and a set of values ​​stored in the first buffer in a second buffer, wherein the difference is stored in a compressed format, and (iii) in response to the quality metric exceeding a threshold, store the value of the subsequent set in the first buffer, generate a log-likelihood ratio based on the first and second buffers, and perform a decoding operation based on the log-likelihood ratio.

[0007] In another exemplary aspect, these methods may be implemented as processor-executable instructions and stored on a computer-readable program medium.

[0008] The subject matter described in this patent document can be implemented in a specific manner that provides one or more of the following features. Attached Figure Description

[0009] Figure 1 An example of a memory system is shown.

[0010] Figure 2 This is a diagram of an exemplary non-volatile memory device.

[0011] Figure 3 This shows the cell voltage level distribution (V) of a non-volatile memory device. th Example diagram.

[0012] Figure 4 This shows the cell voltage level distribution (V) of a non-volatile memory device. th Another example diagram.

[0013] Figure 5 This shows the cell voltage level distribution (V) of the non-volatile memory device before and after programming interference. th Example diagram.

[0014] Figure 6 This shows the cell voltage level distribution (V) of a non-volatile memory device. th Example graph of the reference voltage as a function.

[0015] Figure 7 An example of a normal read from a memory cell and a bin tag buffer is shown.

[0016] Figure 8 A flowchart of an exemplary method for improving decoding operations in non-volatile memory is shown.

[0017] Figure 9 A flowchart is shown for another exemplary method for improving decoding operations in non-volatile memory. Detailed Implementation

[0018] Low-density parity-check (LDPC) codes are an important part of linear block error-correcting codes (ECC) and are widely used in data storage systems. LDPC codes can be decoded using two classes of decoding algorithms: soft-message message-passing algorithms, such as the minimum sum or total sum algorithm; and hard-decision algorithms, such as the bit-flipping algorithm. Soft-message decoding algorithms offer good decoding performance but require significant computational resources. Therefore, they exhibit high complexity in hardware implementation. Conversely, due to their simpler computational units and smaller interconnect networks, hard-decision decoder hardware implementations exhibit lower complexity and reduced latency requirements, and have been developed to provide similar error-correcting performance. In other systems, a combination of hard and soft decoding implementations is employed.

[0019] Existing ECC implementations in non-volatile memory devices are configured to first use hard reads (including history-based reads, HRR reads, etc.), and when these fail, typically use an eBoost process and soft reads as the next step. During the eBoost process, a center threshold is estimated. As part of the soft read, a number of read thresholds (e.g., seven) are placed around the center threshold to generate a log-likelihood ratio (LLR), which can be input to, for example, a minimum summation (MS) decoder. In other implementations, LLR generation can be used for other data recovery functions, such as chipkill techniques and neighbor-assisted correction (NAC).

[0020] Figures 1 to 6 This paper outlines non-volatile memory systems (e.g., flash memory, NAND flash memory) that can implement embodiments of the disclosed technology.

[0021] Figure 1 This is a block diagram of an example memory system 100 implemented based on some embodiments of the disclosed technology. The memory system 100 includes a memory module 110 that can be used to store information for use by other electronic devices or systems. The memory system 100 can be incorporated into other electronic devices and systems (e.g., located on a circuit board). Alternatively, the memory system 100 can be implemented as an external storage device such as a USB flash drive and a solid-state drive (SSD).

[0022] The memory module 110 included in the memory system 100 may include memory regions (e.g., memory arrays) 102, 104, 106, and 108. Each of the memory regions 102, 104, 106, and 108 may be included in a single memory die or multiple memory dies. The memory dies may be included in an integrated circuit (IC) chip.

[0023] Each of memory regions 102, 104, 106, and 108 includes multiple memory cells. Read operations, programming operations, or erase operations can be performed based on memory units. Therefore, each memory unit may include a predetermined number of memory cells. The memory cells in memory regions 102, 104, 106, and 108 may be included in a single memory die or multiple memory dies.

[0024] Memory cells in each of memory regions 102, 104, 106, and 108 can be arranged in rows and columns within a memory unit. Each memory unit can be a physical unit. For example, a group of multiple memory cells can form a memory unit. Each memory unit can also be a logical unit. For example, a memory unit can be a block or a page that can be identified by a unique address, such as a block address or a page address. As another example, memory regions 102, 104, 106, and 108 can include computer memory comprising logical units of storage, which can be memory units that can be identified by a memory unit address. During a read or write operation, a unique address associated with a particular memory unit can be used to access that particular memory unit. Based on the unique address, information can be written to or retrieved from one or more memory cells in the particular memory unit.

[0025] Memory cells in memory regions 102, 104, 106, and 108 may include non-volatile memory cells. Examples of non-volatile memory cells include flash memory cells, phase-change random access memory (PRAM) cells, magnetoresistive random access memory (MRAM) cells, or other types of non-volatile memory cells. In an exemplary embodiment where the memory cell is configured as a NAND flash memory cell, read or write operations can be performed on a page basis. However, erase operations in the NAND flash memory are performed on a block basis.

[0026] Each of the non-volatile memory cells can be configured as a single-level cell (SLC) or a multi-level memory cell. A single-level cell can store one bit of information per cell. A multi-level memory cell can store more than one bit of information per cell. For example, each of the memory cells in memory regions 102, 104, 106, and 108 can be configured as a multi-level cell (MLC) storing two bits of information per cell, a three-level cell (TLC) storing three bits of information per cell, or a four-level cell (QLC) storing four bits of information per cell. In another example, each of the memory cells in memory regions 102, 104, 106, and 108 can be configured to store at least one bit of information (e.g., one bit or more bits of information), and each of the memory cells in memory regions 102, 104, 106, and 108 can be configured to store more than one bit of information.

[0027] like Figure 1 As shown, the memory system 100 includes a controller module 120. The controller module 120 includes: a memory interface 121 for communicating with the memory module 110; a host interface 126 for communicating with a host (not shown); a processor 124 for running firmware-level code; and a cache 123 and system memory 122 for temporarily or permanently storing executable firmware / instructions and associated information, respectively. In some embodiments, the controller module 120 may include an error correction engine (ECC engine) 125 to perform error correction operations on the information stored in the memory module 110. The error correction engine 125 may be configured to detect / correct single bit errors or multiple bit errors. In another embodiment, the error correction engine 125 may be located within the memory module 110.

[0028] The host can be a device or system including one or more processors that retrieve data from or store data in or write data to the memory system 100. In some embodiments, examples of the host may include a personal computer (PC), a portable digital device, a digital camera, a digital multimedia player, a television, and a wireless communication device.

[0029] In some implementations, controller module 120 may further include host interface 126 for communicating with a host. Host interface 126 may include components conforming to at least one of the host interface specifications, including but not limited to Serial Advanced Technology Attachment (SATA), Serial Small Computer System Interface (SAS) specifications, and High Speed ​​Peripheral Component Interconnect (PCIe).

[0030] Figure 2 Examples of memory cell arrays implemented based on some embodiments of the disclosed technology are shown.

[0031] In some implementations, the memory cell array may include a NAND flash memory array divided into multiple blocks, with each block containing a number of pages. Each block includes multiple memory cell strings, and each memory cell string includes multiple memory cells.

[0032] In some implementations where the memory cell array is a NAND flash memory array, read and write (programming) operations are performed on a page-by-page basis, and erase operations are performed on a block-by-block basis. Before programming any page included in a block, all memory cells within the same block must be erased simultaneously. In one implementation, the NAND flash memory can use an even / odd bit-line structure. In another implementation, the NAND flash memory can use a full bit-line structure. In an even / odd bit-line structure, even and odd bit lines are interleaved and accessed alternately along each word line, allowing each pair of even and odd bit lines to share peripheral circuitry such as a page buffer. In a full bit-line structure, all bit lines are accessed simultaneously.

[0033] Figure 3 An example of a threshold voltage distribution curve in a multi-layer cell device is shown, where the number of cells in each program / erase state is plotted as a function of the threshold voltage. As shown, the threshold voltage distribution curve includes the erase state with the lowest threshold voltage (denoted as "ER" and corresponding to "11") and three program states (denoted as "P1", "P2", and "P3" corresponding to "01", "00", and "10", respectively), with the read voltage between the states (represented by dashed lines). In some embodiments, each of the threshold voltage distributions in the program / erase states has a finite width due to differences in material properties on the memory array.

[0034] although Figure 3 The multi-level cell device is illustrated by way of example, but each of the memory cells can be configured to store any number of bits per cell. In some embodiments, each of the memory cells can be configured as a single-level cell (SLC) to store one bit of information per cell, or as a three-level cell (TLC) to store three bits of information per cell, or as a four-level cell (QLC) to store four bits of information per cell.

[0035] When writing more than one data bit to a memory cell, the threshold voltage levels of the memory cells need to be finely arranged due to the reduced distance between adjacent distributions. This is achieved using Incremental Stepped Pulse Programming (ISPP), which involves repeatedly programming memory cells on the same word line using a programming and verification method, in which a stepped programming voltage is applied to the word line. Each programming state is associated with a verification voltage used in the verification operation, and a target position is set for each threshold voltage distribution window.

[0036] Distorted or overlapping threshold voltage distributions can lead to read errors. Ideal memory cell threshold voltage distributions can be severely distorted or overlapping due to factors such as program / erase (P / E) cycles, inter-cell interference, and data retention errors (which will be discussed below), and in most cases, these read errors can be managed by using error correction codes (ECC).

[0037] Figure 4 Examples of ideal threshold voltage distribution curve 410 and distorted threshold voltage distribution curve 420 are shown. The vertical axis represents the number of memory cells with a specific threshold voltage represented on the horizontal axis.

[0038] For an n-bit multi-layer cell NAND flash memory, the threshold voltage of each cell can be programmed to 2. n There are several possible values. In an ideal multi-cell NAND flash memory, each value corresponds to a non-overlapping threshold voltage window.

[0039] Flash memory P / E cycles damage the tunnel oxide of the floating gate in the charge-harvesting layer of the cell transistors, causing threshold voltage shifts and thus gradually reducing the noise margin of the memory device. As P / E cycles increase, the margin between adjacent distributions of different programming states decreases, and eventually the distributions begin to overlap. The threshold voltage programmed into the memory cells within the overlapping range of adjacent distributions may be misinterpreted as a value other than the original target value.

[0040] Figure 5An example of inter-cell interference in NAND flash memory is shown. Inter-cell interference can also cause threshold voltage distortion in flash memory cells. A threshold voltage shift in a memory cell transistor can affect the threshold voltage of its neighboring memory cell transistors through parasitic capacitive coupling between interfering and sacrificial cells. The amount of inter-cell interference can be affected by the NAND flash memory bitline structure. In an even / odd bitline structure, memory cells on a word line are alternately connected to even and odd bitlines, and within the same word line, even cells are programmed before odd cells. Therefore, even and odd cells experience different amounts of inter-cell interference. Cells in a full bitline structure suffer less inter-cell interference than even cells in an even / odd bitline structure, and the full bitline structure can effectively support high-speed current sensing to improve memory read and verification speeds.

[0041] Figure 5 The dashed lines in the diagram represent the nominal distribution of the P / E states of the considered cell (before programming interference), and "adjacent state values" represent the values ​​of adjacent states that have been programmed. For example... Figure 5 As shown, if the adjacent state is programmed as P1, the threshold voltage distribution of the considered cell shifts by a specific amount. However, if the adjacent state is programmed as P2, where the threshold voltage is higher than P1, this results in a larger shift compared to when the adjacent state is P1. Similarly, the shift in the threshold voltage distribution is greatest when the adjacent state is programmed as P3.

[0042] Figure 6 An example of a retention error in NAND flash memory is shown, comparing a normal threshold voltage distribution with an offset threshold voltage distribution. Data stored in NAND flash memory is susceptible to corruption over time, a phenomenon known as a data retention error. Retention errors are caused by the loss of charge stored in the floating gate or charge-retrieval layer of the cell transistor. Memory cells with more program-erase cycles are more likely to experience retention errors due to the deterioration of the floating gate or charge-retrieval layer. Figure 6 In the example, comparing the voltage distribution of the top row (before the damage) with the distribution of the bottom row (after being corrupted by the error) shows a leftward shift.

[0043] In NAND-based storage systems (e.g., Figures 1 to 6In the example shown, embodiments of the currently disclosed technology provide a compression framework for generating the log-likelihood ratio (LLR). Among other benefits, the described embodiments can significantly reduce memory usage, save gate count and area, and support flexible LLR bit widths without increasing memory consumption. Furthermore, the embodiments disclosed herein are configured to self-detect the optimal read threshold among multiple available read thresholds, which allows for the generation of a better LLR table by modifying the LLR table and retrying MS decoder operations. This advantageously reduces latency and improves reliability and quality of service (QoS).

[0044] Figure 7 An example of an existing LLR generation algorithm is shown, where seven thresholds are used to generate a 3-bit LLR for each data bit. In this example of conventional LLR generation, seven 4KB memory slots are required to generate a 3-bit LLR for each data bit of a 4KB codeword. Of these seven slots, three are used for bin labels, one for storing the current read, and three for storing auxiliary read information.

[0045] Assisted read (AR) is an example of coarse hard slicing used to roughly determine which region of the allowed distribution space each bit cell is defined from. Using this information, the key decoding threshold usage for bit aggregation read from a NAND page can be understood. The reason for using AR is to identify which of the seven valleys in a three-layer cell (TLC) NAND cell a particular cell is located in. This allows for the use of different LLR tables when mapping from bin tags to LLR values. Using different LLR tables is crucial in this paper because different valleys can have different potential PV distributions, and different LLR tables are needed to better address asymmetric PV distributions. However, for client and mobile system-on-chip (SoC) implementations, generating LLR using seven 4KB slots results in unnecessary area and power costs. This situation is exacerbated if chip hunting and NAC are supported, as 21 4KB slots are required. Embodiments of the disclosed technology provide a technical solution to this problem, among other solutions.

[0046] In existing LLR generation implementations, there are no LLR table changes or MS decoder retries, assuming that the center threshold estimated by eBoost is always the most accurate among all available read thresholds. However, in reality, this rarely occurs, especially for pages requiring both eBoost and soft decoding. Because existing LLR generation techniques lack the ability to measure the quality of each read threshold, the LLR table used for soft decoding is often biased.

[0047] Embodiments of the disclosed technology provide an LLR generation framework that uses a single 4KB time slot to track hard read (HR) information to obtain the best read (BR) for execution up to that point. In some embodiments, the best read is used as a center threshold read and can be used as the sign bit of the generated LLR. This advantageously compensates for inaccuracies in eBoost and enables the use of an asymmetric LLR table by explicitly modifying the LLR table and retrying the MS decoder.

[0048] In some embodiments, tracking the best read is implemented as follows:

[0049] 1. For the first read, i = 0, set BR = HR(i)

[0050] 2. For the second and subsequent reads, i≥1, if the quality metric decreases, BR is replaced by HR(i).

[0051] In some embodiments, the quality metric (M) is determined as:

[0052] M = a × CS + b × |N-1 / 2|

[0053] Here, CS is the checksum, N is the percentage of 1s in a predetermined number of cells, which should typically be 50% when using the optimal read threshold, and a and b are non-negative numbers such that a + b = 1.

[0054] Under normal operating conditions, NAND pages will contain less than 1% of original errors, meaning that the majority of bits in the codeword are reliable. Therefore, ( Figure 7 In the context of the existing LLR generation implementation discussed here, the majority (approximately 95%) of the content in the raw bin tag slots will be primarily 0 or 7. These reliable cells will be read consistently for all read thresholds near the center threshold, and only a few percent of the cells will have bin tags between 0 and 7. Therefore, using a full set of three 4KB memory slots to store bin tags may be considered a waste of resources.

[0055] The disclosed embodiments of the technology provide an inline compression and decompression scheme to overcome the resource waste discussed above. This scheme is so simple that it can perform real-time computation and uses only a 4KB time slot to store the reliability information of the compression.

[0056] In some embodiments, instead of counting the number of 1s read and using them as bin tags to generate reliability information, the disclosed embodiments involve counting how inconsistent all reads of a particular cell are with the bit value in the BR buffer (or simply, the BR). In the example, the number of times the value of a particular cell differs from the bit value recorded in the BR across all reads so far is recorded. This information is highly compressible because, across all reads, most cells will typically have the same read value, equal to its value in the BR. The compression algorithm only captures the few cells inconsistent with the BR and records the degree of inconsistency, i.e., the number of times different values ​​are observed. When the consistency information is updated (e.g., by combining the current inconsistency information and the BR with the current read information), the decompression engine can be configured to read a certain number of compressed inconsistencies, such as 256 consecutive bits, update the inconsistency information, and then compress it before writing it back to the 4KB timeslot. On the last read, the updated inconsistency information will be written back to the timeslot. When the MS decoder is available and LLR generation is triggered, the contents of the BR and Compressed Inconsistent Memory (CIM) will be read out in a windowed manner, and an LLR table lookup will be performed to generate the required LLR value and send it to the MS decoder.

[0057] In some embodiments, the described compression algorithm enables the compression-inconsistent memory to be configured to support flexible LLR bit widths. For example, a 4KB slot can support 4-bit or 5-bit LLRs, while existing LLR generation implementations can only support up to 3-bit LLRs, and the required memory consumption increases linearly with the LLR bit width if higher LLR precision is required.

[0058] An example of updating CIM with a compressed window size of 8 (L=8) is shown below:

[0059] First read: HR = [1, 0, 0, 1, 0, 0, 1, 1]. Store HR in the BR slot / buffer.

[0060] Second read: HR = [1, 0, 0, 1, 0, 1 [(5, 1)] No BR replacement occurs. Store [(5, 1)] in CIM, which means that the bit at index 5 is found to be different with respect to the BR buffer for the first time (because only one read has occurred since the BR update).

[0061] Third read: HR = [1, 0, 1 ,1, 1 , 1[(2,1),(4,1),(5,2)] is read from CIM. [(2,1),(4,1),(5,2)] is written to CIM, which means that the bits at index 2 and 4 were found to be different on the first read, and the bit at index 5 was found to be different on the second read (i.e., in the second read and this read).

[0062] Fourth read: HR = [1, 0, 1 ,1,0, 1 [(2,1),(4,1),(5,2)] is read from CIM. [(2,2),(4,1),(5,2)] is written to CIM, which means that the 3rd bit (index 2) has been found to be different for the second time, the 5th bit (index 4) has been found to be different once (on the third read), and the 6th bit (index 5) has been found to be different twice (on the second and third reads).

[0063] As shown in the example above, the flip count is updated cumulatively and can be inferred from the number of reads performed, the bit values ​​in the BR and HR, and whether a BR replacement has occurred.

[0064] In some embodiments, CIM updates are performed each time information for L bits is accessed, using a moving window approach. This advantageously ensures that currently read information is consumed immediately, rather than stored in memory.

[0065] CIM can be organized in various formats to accommodate multiple bit error scenarios. In the example, the window size can be chosen as L = 256, and one NAND page contains 144 such windows. In this case, bit positions within L can be represented using 8 bits. It is assumed that at most 32 unreliable bits (16 / 256 = 6.25%) of the index need to be stored per L bit. For each potentially unreliable bit position, at most 2... 8 -1 = 255 toggle counts, and the total storage capacity required is 144 × 16 × (8 + 8) = 36864, which corresponds exactly to a 4KB time slot.

[0066] The hardware design in the disclosed embodiments can provide several different format options to better handle different types of NAND architectures. The format desired for a specific product can be configured by the firmware. In cases where more bit indices need to be stored (e.g., in overflow situations), some low-flip-count entries can be removed, and storage space can be used to record the indices and counts of high-flip-count entries. This is because these high-flip-count indices have a greater impact on the performance of the software decoder.

[0067] The disclosed embodiments include a format design phase in which the probability of encountering a maximum number of bit flips is evaluated. If the maximum number of possible bit flips is high, the maximum number of flip counts can be reduced, and these bits can be used to store more flip indices. Typically, the hardware design can support multiple formats to cover a wide range of possibilities, and the firmware can configure the format later in development.

[0068] In most cases, software decoding performance is determined by the LLR quality of the worst valley (e.g., the first valley of the Most Significant Bit (MSB) page in a TLC NAND). Therefore, using the same LLR table optimized for all cells simultaneously is as effective as using separate LLR tables for each valley. This advantageously saves storage capacity. To save additional storage capacity, three of the AR slots (or buffers) can be eliminated, requiring only two 4KB slots to generate the LLR—the first for Best Read (BR) tracking and the second for compressing the bin tag. This reduces the total number of required 4KB slots from seven (as in existing LLR generation implementations, e.g.) Figure 7 The number of cases (as described in the document) is reduced to two. These embodiments will achieve significant savings for area- and power-sensitive mobile and client applications.

[0069] Figure 8 A flowchart of a method 800 for improving decoding operations in non-volatile memory is shown. Method 800 includes performing a first hard read (HR) operation (810), setting the best read (BR) buffer to the first HR (820), and then iteratively until an LLR is generated. The method further includes, in each iteration, performing an HR operation (830), replacing the BR with the current HR (840) if the quality metric exceeds a threshold, then performing a Compact Inconsistent Memory (CIM) read and updating the toggle count (850). It should be noted that a quality metric exceeding the threshold (M>T) is equivalent to a quality metric less than the threshold by a negative value, e.g., M<-T, and vice versa. If necessary, the CIM is updated (870) and the next HR operation (830) is performed; otherwise, an LLR can now be generated using, for example, a lookup table (LUT) (860).

[0070] Figure 9 A flowchart of another method 900 for improving decoding operations in non-volatile memory is shown. Method 900 includes, in operation 910, performing a first hard read to obtain a first set of values ​​stored in a plurality of cells.

[0071] Method 900 includes, in operation 920, storing the first set of values ​​in a first buffer.

[0072] Method 900 includes, in operation 930, performing multiple subsequent hard reads on multiple cells to obtain values ​​for multiple subsequent groups.

[0073] Method 900 includes, in operation 940, performing operations 942, 944, and 946 for the value of each of the multiple subsequent groups.

[0074] The operation performed on the value of each subsequent group includes operation 942: calculating the quality metric.

[0075] The operation performed for the value of each subsequent group includes operation 944: storing the difference between the value of the subsequent group and a set of values ​​stored in the first buffer in the second buffer, the difference being stored in a compressed format.

[0076] The operation performed for the value of each subsequent group includes operation 946: in response to the quality metric exceeding a threshold, the value of the subsequent group is stored in the first buffer.

[0077] Method 900 includes, in operation 950, generating a log-likelihood ratio based on the first buffer and the second buffer.

[0078] Method 900 includes performing a decoding operation based on the log-likelihood ratio in operation 960.

[0079] In some embodiments, the quality metric (M) is based on the percentage (N) of cells with a value of 1 among a plurality of cells (CS).

[0080] In some embodiments, the quality metric is determined as

[0081] M = a × CS + b × |N-1 / 2|

[0082] In this paper, a and b are non-negative real numbers such that a + b = 1.

[0083] In some embodiments, the sign bit of the log-likelihood ratio is based on a set of values ​​stored in a first buffer.

[0084] In some embodiments, the compression format includes (i) the index of a bit in the value of a subsequent group and (ii) the number of times the value of a bit differs from the value of the corresponding bit in the first buffer.

[0085] In some embodiments, generating the log-likelihood ratio (LLR) includes reading the log-likelihood ratio from an LLR lookup table (LUT).

[0086] In some embodiments, the size of the first buffer is based on the number of cells in a page of non-volatile memory.

[0087] The embodiments and functional operations of the subject matter described in this patent document can be implemented in various systems, digital electronic circuits including the structures disclosed in this specification and their equivalents, or combinations thereof, or in computer software, firmware, or hardware. Embodiments of the subject matter described in this specification can be implemented as one or more computer program products, i.e., one or more modules of computer program instructions encoded on a tangible and non-transitory computer-readable medium that are run by or control the operation of a data processing device. The computer-readable medium can be a machine-readable storage device, a machine-readable storage substrate, a memory device, a composition of material affecting machine-readable propagation signals, or combinations thereof. The terms "data processing unit" or "data processing device" encompass all devices, apparatuses, and machines for processing data, including, for example, programmable processors, computers, or multiple processors or computers. In addition to hardware, the device may also include code that creates an operating environment for the computer program in question, such as code constituting processor firmware, a protocol stack, a database management system, an operating system, or combinations thereof.

[0088] Computer programs (also known as programs, software, software applications, scripts, or code) can be written in any programming language (including compiled or interpreted languages) and can be deployed in any form, including as standalone programs suitable for use in a computing environment, or as modules, components, subroutines, or other units. A computer program does not necessarily correspond to a file in a file system. A program can be stored as a portion of a file containing other programs or data (e.g., one or more scripts stored in a markup language document), a single file dedicated to the program in question, or multiple coordination files (e.g., files storing portions of one or more modules, subroutines, or code). A computer program can be deployed to run on a single computer or on multiple computers located at one site or distributed across multiple sites and interconnected through a communications network.

[0089] The processes and logic flows described in this specification can be executed by one or more programmable processors running one or more computer programs to perform functions by manipulating input data and generating data. The processes and logic flows can also be executed by special-purpose logic circuitry (e.g., FPGA (Field-Programmable Gate Array) or ASIC (Application-Specific Integrated Circuit)), and the device can also be implemented as special-purpose logic circuitry (e.g., FPGA or ASIC).

[0090] Processors suitable for running computer programs include, for example, both general-purpose microprocessors and special-purpose microprocessors, as well as any one or more processors in any kind of digital computer. Typically, a processor receives instructions and data from read-only memory or random access memory, or both. The basic components of a computer are a processor for executing instructions and one or more memory devices for storing instructions and data. Typically, a computer will also include one or more mass storage devices (e.g., magneto-optical, magneto-optical, or optical disc) for storing data, or operatively coupled to receive data from or transfer data to one or more mass storage devices (e.g., magneto-optical, magneto-optical, or optical disc). However, a computer need not have such devices. Computer-readable media suitable for storing computer program instructions and data include all forms of non-volatile memory, media, and memory devices, including, for example, semiconductor memory devices (e.g., EPROM, EEPROM, and flash memory devices). The processor and memory may be supplemented by or incorporated into special-purpose logic circuitry.

[0091] While this patent document contains numerous details, these details should not be construed as limiting the scope of any invention or any claimable invention, but rather as a description of specific features that may be present in a particular embodiment of a particular invention. Certain features described in the context of individual embodiments in this patent document may also be implemented in combinations of individual embodiments. Conversely, various features described in the context of individual embodiments may also be implemented individually in multiple embodiments, or in any applicable sub-combinations. Furthermore, although features may be described above as functioning in certain combinations and even initially claimed in this way, in some cases one or more features of a claimed combination may be excluded from the combination, and the claimed combination may involve sub-combinations or variations thereof.

[0092] Similarly, although the operations are depicted in a specific order in the accompanying drawings, this should not be construed as requiring the operations to be performed in the specific order shown or in a sequential order, or requiring all of the operations shown, in order to achieve the desired effect. Furthermore, the separation of various system components in the embodiments described in this patent document should not be construed as requiring such separation in all embodiments.

[0093] This patent document describes only a few embodiments and examples, and other embodiments, improvements and variations can be made based on the content described and shown in this patent document.

Claims

1. A method for improving decoding operations in non-volatile memory, comprising: Perform the first hard read to obtain the first set of values ​​stored in multiple cells; Store the first set of values ​​in the first buffer; Perform multiple subsequent hard reads on the plurality of units to obtain values ​​for multiple subsequent groups; For each of the values ​​in the plurality of subsequent groups, perform the following operations: Calculate quality metrics, The difference between the value of the subsequent group and a group of values ​​stored in the first buffer is stored in a second buffer, wherein the difference is stored in a compressed format, and In response to the quality metric exceeding a threshold, the values ​​of the subsequent groups are stored in the first buffer; Generate a log-likelihood ratio based on the first buffer and the second buffer; and The decoding operation is performed based on the log-likelihood ratio.

2. The method of claim 1, wherein the quality metric M is based on the percentage N of the checksum CS and the number of cells with a value of 1 among the plurality of cells.

3. The method of claim 2, wherein the quality metric is determined as M = a × CS + b × |N-1 / 2| Where a and b are non-negative real numbers such that a + b = 1.

4. The method of claim 1, wherein the sign bit of the log-likelihood ratio is based on a set of values ​​stored in the first buffer.

5. The method of claim 1, wherein the compressed format comprises: The index of the bit in the value of the subsequent group; and the number of times the bit value is different from the corresponding bit value in the first buffer.

6. The method of claim 1, wherein generating the log-likelihood ratio (LLR) comprises: The log-likelihood ratio is read from the LLR lookup table LUT.

7. The method of claim 1, wherein the size of the first buffer is based on the number of cells in the page of the non-volatile memory.

8. A system for improving the decoding efficiency of a decoder in a non-volatile memory, comprising: A processor and memory, the memory including instructions stored thereon, wherein the instructions, when executed by the processor, cause the processor to: Perform the first hard read to obtain the first set of values ​​stored in multiple cells; Store the first set of values ​​in the first buffer; Perform multiple subsequent hard reads on the plurality of units to obtain values ​​for multiple subsequent groups; For each of the values ​​in the plurality of subsequent groups, perform the following operations: Calculate quality metrics, The difference between the value of the subsequent group and a group of values ​​stored in the first buffer is stored in a second buffer, wherein the difference is stored in a compressed format, and In response to the quality metric exceeding a threshold, the values ​​of the subsequent groups are stored in the first buffer; A log-likelihood ratio is generated based on the first buffer and the second buffer; and The decoding operation is performed based on the log-likelihood ratio.

9. The system of claim 8, wherein the quality metric M is based on the percentage N of the checksum CS and the number of cells with a value of 1 among the plurality of cells.

10. The system of claim 9, wherein the quality metric is determined as M = a × CS + b × |N-1 / 2| Where a and b are non-negative real numbers such that a + b = 1.

11. The system of claim 8, wherein the sign bit of the log-likelihood ratio is based on a set of values ​​stored in the first buffer.

12. The system of claim 8, wherein the compressed format comprises: The index of the bit in the value of the subsequent group; and the number of times the bit value is different from the corresponding bit value in the first buffer.

13. The system of claim 8, wherein, as part of generating the LLR, the instructions, when executed by the processor, further cause the processor to: The log-likelihood ratio is read from the LLR lookup table LUT.

14. The system of claim 8, wherein the size of the first buffer is based on the number of cells in the page of the non-volatile memory.

15. A non-transitory computer-readable storage medium storing instructions for improving the decoding efficiency of a decoder in a non-volatile memory, the non-transitory computer-readable storage medium comprising: The instruction to perform the first hard read to obtain the first set of values ​​stored in multiple cells; The instruction to store the first set of values ​​in the first buffer; Instructions to perform multiple subsequent hard reads on the plurality of units to obtain values ​​for multiple subsequent groups; Instructions to perform the following operation for each of the plurality of subsequent group values: Calculate quality metrics, The difference between the value of the subsequent group and a group of values ​​stored in the first buffer is stored in a second buffer, wherein the difference is stored in a compressed format, and In response to the quality metric exceeding a threshold, the values ​​of the subsequent groups are stored in the first buffer; Instructions for generating the log-likelihood ratio based on the first buffer and the second buffer; as well as Instructions for performing decoding operations based on the log-likelihood ratio.

16. The storage medium of claim 15, wherein the quality metric M is based on the percentage N of the checksum CS and the number of cells with a value of 1 among the plurality of cells.

17. The storage medium of claim 16, wherein the quality metric is determined as M = a × CS + b × |N-1 / 2| Where a and b are non-negative real numbers such that a + b = 1.

18. The storage medium of claim 15, wherein the sign bit of the log-likelihood ratio is based on a set of values ​​stored in the first buffer.

19. The storage medium of claim 15, wherein the compressed format comprises: The index of the bit in the value of the subsequent group; and the number of times the bit value is different from the corresponding bit value in the first buffer.

20. The storage medium of claim 15, wherein the size of the first buffer is based on the number of cells in the page of the non-volatile memory.

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