Memory device and operating method of the memory device

Abstract

The present disclosure relates to a memory device and a method of operating the memory device. A memory device and a method of operating a memory device include a memory block and include a peripheral circuit, the memory block including strings formed between bit lines and source lines, the peripheral circuit configured to perform a read operation of a selected memory cell included in a selected string among the strings. The peripheral circuit includes a page buffer configured to increase a voltage of a channel of the string by applying a first pre-charge voltage to the bit line in a setup phase of the read operation, to apply a second pre-charge voltage lower than the first pre-charge voltage to the bit line in a read phase of the read operation, and to discharge the bit line in a discharge phase of the read operation.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2022-0066434, filed on May 31, 2022, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] This disclosure generally relates to memory devices and methods of manufacturing such memory devices, and more particularly to memory devices having a three-dimensional structure and methods of operating such memory devices. Background Technology

[0004] A memory device may include a memory cell array and peripheral circuitry, with data stored in the memory cell array and the peripheral circuitry configured to perform programming, reading, and erasing operations.

[0005] A memory cell array may include multiple memory blocks, and each memory block may include multiple memory cells.

[0006] The peripheral circuitry may include: control circuitry for controlling the overall operation of the memory device in response to commands transmitted from an external controller; and circuitry configured to perform programming, reading, and erasing operations under the control of the control circuitry.

[0007] To increase the capacity and reduce the weight of memory devices, the integration level of the memory devices must be increased. As the integration level increases, the size of the components (e.g., transistors and wires) and the distance between them decrease. When the size of the components and the distance between them decrease, the electrical interference between adjacent components increases, and therefore, the reliability of the memory device during programming, reading, and erasing operations may deteriorate. Summary of the Invention

[0008] Some embodiments provide a memory device and a method of operating the memory device, wherein increasing the channel boost level of the string during a read operation of the memory device can improve the reliability of the read operation.

[0009] According to one embodiment of this disclosure, a memory device includes a memory block and peripheral circuitry. The memory block includes strings formed between bit lines and source lines. The peripheral circuitry is configured to perform a read operation on selected memory cells, which are included in a selected string within the strings. The peripheral circuitry includes a page buffer configured to: increase the voltage of a channel of the string by applying a first precharge voltage to the bit lines during the setup phase of a read operation; apply a second precharge voltage lower than the first precharge voltage to the bit lines during the read phase of a read operation; and discharge the bit lines during the discharge phase of a read operation.

[0010] According to this disclosure, there is also a method for operating a memory device. The method includes: increasing a channel voltage by applying a first precharge voltage to a bit line electrically coupled to a channel; applying a second precharge voltage lower than the first precharge voltage to the bit line as the channel voltage increases; applying a read voltage to a selected word line among word lines arranged between the bit line and a source line; and discharging the bit line and the word line. Attached Figure Description

[0011] Exemplary embodiments will now be described more fully below with reference to the accompanying drawings; however, they may be embodied in different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that those skilled in the art will be able to implement this disclosure.

[0012] In the accompanying drawings, dimensions may be exaggerated for clarity. It will be understood that when an element is referred to as being "between" two elements, it can be the only element between the two elements, or there may be one or more intermediate elements. Similar reference numerals always refer to similar elements.

[0013] Figure 1 This is a diagram illustrating a memory device according to an embodiment of the present disclosure.

[0014] Figure 2 It is a diagram illustrating the arrangement of the memory cell array and peripheral circuitry.

[0015] Figure 3 This is a diagram illustrating a memory block.

[0016] Figure 4 This is a view illustrating the structure of a string included in a memory device.

[0017] Figure 5A and Figure 5B It is a diagram. Figure 4 The image shows a view of the turn-on or turn-off operation of a drain-select transistor.

[0018] Figure 6A and Figure 6B It is a diagram. Figure 4 The image shows a view of the on or off operation of a source selection transistor.

[0019] Figure 7 This is a diagram illustrating an operation method of a memory device according to a first embodiment of the present disclosure.

[0020] Figure 8 This is a diagram illustrating an operation method of a memory device according to a second embodiment of the present disclosure.

[0021] Figure 9 This is a diagram illustrating an operation method of a memory device according to a third embodiment of the present disclosure.

[0022] Figure 10 This is a diagram illustrating an operation method of a memory device according to a fourth embodiment of the present disclosure.

[0023] Figure 11 This is a diagram illustrating a memory card system, in which a memory device according to an embodiment of the present disclosure is applied.

[0024] Figure 12 This is a diagram illustrating a solid-state drive (SSD) system, to which a memory device according to an embodiment of the present disclosure is applied. Detailed Implementation

[0025] The specific structural and functional descriptions disclosed herein are merely illustrative and are intended to describe embodiments based on the concept of this disclosure. Additional embodiments based on the concept of this disclosure may be implemented in various forms. Therefore, this disclosure should not be construed as limiting itself to the embodiments set forth herein.

[0026] In the following text, it will be understood that although the terms “first,” “second,” “third,” etc., may be used in this document to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another and do not indicate the number or order of elements.

[0027] Figure 1 This is a diagram illustrating a memory device according to an embodiment of the present disclosure.

[0028] refer to Figure 1 The memory device 100 may include a memory cell array 110 and peripheral circuitry 190.

[0029] Memory cell array 110 may include a plurality of memory cells in which data is stored. In one embodiment, memory cell array 110 may include a three-dimensional memory cell array. The plurality of memory cells may store one bit of data or multi-bit data of two or more bits, depending on a programming configuration. The plurality of memory cells may form a plurality of memory cell strings. For example, each memory cell string may include a plurality of memory cells connected in series via a channel layer. The channel layer may be connected between the bit line BL and the source line.

[0030] The peripheral circuitry 190 can be configured to perform programming operations for storing data in the memory cell array 110, reading operations for outputting data stored in the memory cell array 110, and erasing operations for erasing data stored in the memory cell array 110. The peripheral circuitry 190 may include a row decoder 120, a voltage generation circuit 130, a source line driver 140, a control circuit 150, a page buffer set 160, a column decoder 170, and an input / output circuit 180.

[0031] The row decoder 120 can be connected to the memory cell array 110 via multiple drain select lines DSL, multiple word lines WL, and multiple source select lines SSL. The row decoder 120 can transmit the operating voltage Vop to the multiple drain select lines DSL, multiple word lines WL, and multiple source select lines SSL in response to the row address RADD.

[0032] The voltage generation circuit 130 can generate various operating voltages Vop for programming, reading, or erasing operations in response to the operation signal OP_S.

[0033] In response to the source line control signal SL_S, the source line driver 140 can transfer the source voltage Vs1 supplied therefrom to the source line connected to the memory cell array 110, or float the source line. The source voltage Vs1 can be 0V, a positive voltage above 0V, or a negative voltage below 0V. The source line driver 140 can float the source line by turning off the transistor used to transfer the source voltage Vs1 to the source line.

[0034] In response to the command CMD and the address ADD, the control circuit 150 can output the operation signal OP_S, the row address RADD, the source line control signal SL_S, the page buffer control signal PB_S, and the column address CADD.

[0035] Page buffer group 160 may include multiple page buffers connected to memory cell array 110 via bit lines BL. The page buffers may temporarily store data DATA received via the multiple bit lines BL in response to a page buffer control signal PB_S. The page buffers may sense the voltage or current of the multiple bit lines BL during read operations.

[0036] In response to the column address CADD, the column decoder 170 can transfer data DATA input from the input / output circuit 180 to the page buffer group 160, or transfer data DATA stored in the page buffer group 160 to the input / output circuit 180. The column decoder 170 can exchange data DATA with the input / output circuit 180 via the column line CLL. The column decoder 170 can exchange data DATA with the page buffer group 160 via the data line DTL.

[0037] The input / output circuit 180 can transmit commands (CMD) and addresses (ADD) from an external device (e.g., a controller) of the memory device 100 to the control circuit 150. The input / output circuit 180 can receive data from an external device during programming operations and output data read from a selected memory cell to an external device during read operations.

[0038] Figure 2 It is a diagram illustrating the arrangement of the memory cell array and peripheral circuitry.

[0039] refer to Figure 2 The memory device 100 may include peripheral circuitry 190 and a memory cell array 110. The peripheral circuitry 190 may be disposed above a substrate, and the memory cell array 110 may be disposed above the peripheral circuitry 190. The memory cell array 110 may include first memory blocks BLK1 to j-th memory blocks BLKj. Multiple bit lines BL may be disposed above the first memory blocks BLK1 to j-th memory blocks BLKj.

[0040] Multiple bit lines BL can be spaced apart from each other in the X direction and extend along the Y direction. First memory blocks BLK1 to j-th memory blocks BLKj can be spaced apart from each other in the Y direction. First memory blocks BLK1 to j-th memory blocks BLKj can be configured identically to each other, and therefore, as an example, the first memory block BLK1 will be described in detail below.

[0041] Figure 3 This is a diagram illustrating a memory block.

[0042] refer to Figure 3The first memory block BLK1 includes a string ST connected between the first bit line BL1 to the nth bit line BLn and the source line SL. The first bit lines BL1 to the nth bit line BLn extend along the Y direction and are arranged to be spaced apart from each other along the X direction. Therefore, the string ST can also be arranged to be spaced apart from each other along both the X and Y directions. For example, the string ST can be arranged between the first bit line BL1 and the source line SL, and the string ST can be arranged between the second bit line BL2 and the source line SL. In this way, the string ST can be arranged between the nth bit line BLn and the source line SL. The line ST can extend along the Z direction.

[0043] As an example, any one of the strings ST connected to the nth bit line BLn will be described. The string ST may include first source select transistors SST1 to third source select transistors SST3, first memory cells MC1 to i-th memory cells MCi, and first drain select transistors DST1 to third drain select transistors DST3. Figure 3 The first memory block BLK1 shown in the figure represents a diagram of the structure of the illustrated memory block, and therefore the number of source selection transistors, memory cells and drain selection transistors included in the string ST can be changed according to the memory device.

[0044] The gates of the first source selection transistor SST1 to the third source selection transistor SST3, which are included in different strings, can be connected to the first source selection line SSL1 and the second source selection line SSL2. The gates of the first memory cell MC1 to the i-th memory cell MCI, which are included in different strings, can be connected to the first word line WL1 to the i-th word line WLi. The gates of the first drain selection transistor DST1 to the third drain selection transistor DST3, which are included in different strings, can be connected to the first drain selection line DSL1 to the fourth drain selection line DSL4.

[0045] The lines connected to the first memory block BLK1 will be described in more detail. First source select transistors SST1 to SST3, arranged along the X and Z directions, can be connected to the same source select line, and first source select transistors SST1 to SST3, arranged along the Y direction, can be connected to isolated source select lines. For example, some of the first source select transistors SST1 arranged in the Y direction can be connected to the first source select line SSL1, and other first source select transistors SST1 can be connected to the second source select line SSL2. The second source select line SSL2 is isolated from the first source select line SSL1. Therefore, the voltage applied to the first source select line SSL1 can be different from the voltage applied to the second source select line SSL2. In this way, some of the second and third source select transistors SST2 and SST3 can be connected to the first source select line SSL1, and other second and third source select transistors can be connected to the second source select line SSL2.

[0046] Memory cells formed in the same layer from the first memory cell MC1 to the i-th memory cell MCI can be connected to the same word line. For example, the first memory cell MC1 included in different strings ST can be connected to the first word line WL1, and the i-th memory cell MCI included in different strings ST can be connected to the i-th word line WLi. A group of memory cells included in different strings ST and connected to the same word line becomes a page PG. For example, the first memory cell in string ST connected to the first drain select line DSL1 can become the first page PG1, and the first memory cell MC1 in string ST connected to the second drain select line DSL2 can become the second page PG2.

[0047] The first drain select transistors DST1 to DST3, which are located in different strings ST, can be connected to drain select lines that are isolated from each other. Specifically, the first drain select transistors DST1 to DST3 arranged along the X direction can be connected to the same drain select line, and the first drain select transistors DST1 to DST3 arranged along the Y direction can be connected to drain select lines that are isolated from each other. For example, some of the first drain select transistors DST1 can be connected to the first drain select line DSL1, and other first drain select transistors DST1 can be connected to the second drain select line DSL2. The second drain select line DSL2 is isolated from the first drain select line DSL1. Therefore, the voltage applied to the first drain select line DSL1 can be different from the voltage applied to the second drain select line DSL2. In this way, some of the second drain select transistors DST2 can be connected to the first drain select line DSL1, and other second drain select transistors DST2 can be connected to the second drain select line. Some of the third drain select transistors DST3 can be connected to the first drain select line DSL1, and other third drain select transistors DST3 can be connected to the second drain select line DSL2.

[0048] In programming or reading operations, the selected string ST can be determined by the selected drain selection line Sel_DSL among the first drain selection line DSL1 to the third drain selection line DSL3. Different pages can be determined by the voltage applied to the drain selection line. For example, when the first drain selection line DSL1 is designated as the selected drain selection line Sel_DSL and the second drain selection line DSL2 is designated as the unselected drain selection line Unsel_DSL, the first page PG1 can become the selected page Sel_PG, and the second page PG2 can become the unselected page Unsel_PG. The string ST connected to the selected page Sel_PG can become the selected string. The selected page refers to the page selected as the programming target in the programming operation, and the unselected page can refer to the page that is not programmed in the programming operation of the selected page.

[0049] Figure 4 This is a view illustrating the structure of a string included in a memory device.

[0050] refer to Figure 4The source line SL can be formed on the lower structure UDS, and the stacked structure STK can be formed on the source line SL. The lower structure UDS can be a substrate or peripheral circuitry. The source line SL can be formed of a conductive material. For example, the source line SL can be formed of polysilicon. The stacked structure STK can include a gate line GL and an insulating layer ISL formed between the gate lines GL. The gate line GL can include a first source line SSL1, a first word line WL1 to the i-th word line WLi, and a first drain selection line DSL1. The gate line GL can be formed of a conductive material. For example, the gate line GL can be formed of a conductive material such as tungsten (W), molybdenum (Mo), cobalt (Co), or nickel (Ni), or it can be formed of a semiconductor material such as silicon (Si) or polysilicon (Poly-Si). In addition, the gate line GL can be formed of various metal materials. The insulating layer ISL can be formed of an oxide layer or a silicon oxide layer. For example, some of the lines in the gate line GL that are adjacent to the source line SL can become the first source select line SSL1, some of the gate lines GL stacked above the first source select line SSL1 can become the first word line WL1 to the i-th word line WLi, and the gate line GL formed above the i-th word line WLi can become the first drain select line DSL1.

[0051] The string ST can be configured with cell plugs CPL that penetrate the stacked structure STK. The cell plugs CPL can include a barrier layer BX, a charge trapping layer CT, a tunnel insulating layer TX, a channel layer CH, a core pillar CP, and a capping layer CAP. For example, the barrier layer BX can be formed as a pillar penetrating the stacked structure STK and is formed of an oxide layer or a silicon oxide layer. The charge trapping layer CT can be formed as a pillar along the inner wall of the barrier layer BX and is formed of a nitride layer. The tunnel insulating layer TX can be formed as a pillar along the inner wall of the charge trapping layer CT and is formed of an oxide layer or a silicon oxide layer. The channel layer CH can be formed as a pillar along the inner wall of the tunnel insulating layer TX and is formed of polysilicon. The core pillar CP can be formed as a pillar filling the interior of the channel layer CH and is formed of an insulating material such as an oxide layer or a silicon oxide layer. The capping layer CAP can be formed on top of the core pillar CP and is formed of a conductive material. For example, when the capping layer CAP is formed on top of the core pillar CP, the height of the top surface of the core pillar CP can be formed to be lower than the height of the top surface of the channel layer CH, and the capping layer CAP can be formed in the upper region of the core pillar CP surrounded by the channel layer CH.

[0052] Bit line contacts BC and bit lines BL can be formed on top of the cell plug CPL. For example, bit line contacts BC can be formed of a conductive material and contact the channel layer CH included in the cell plug CPL. Bit lines BL can be formed on top of bit line contacts BC and are also formed of a conductive material.

[0053] The operation method of the above-mentioned memory device will be described below.

[0054] Figure 5A and Figure 5B It is a diagram. Figure 4 The image shows a view of the turn-on or turn-off operation of a drain-select transistor.

[0055] refer to Figure 5A When a turn-off voltage Voff is applied to the first drain select line DSL1, the drain select transistor can be turned off (OFF), and no channel is formed in the channel layer CH of the drain select transistor. When no channel is formed in the channel layer CH, no current path 51 can flow through the channel layer CH of the drain select transistor. Therefore, the channel layer CH and bit line BL of the memory cell can be electrically interrupted. This electrical interruption occurs in... Figure 5A The symbol “X” indicates this. Therefore, the precharge voltage Vpr applied to the bit line BL is applied to the channel layer CH formed on top of the drain select transistor and is not transferred to the channel layer CH of the memory cell.

[0056] refer to Figure 5B When an on-state voltage Von is applied to the first drain select line DSL1, the drain select transistor is turned on (ON), and a channel can be formed in the channel layer CH of the drain select transistor. When a channel is formed in the channel layer CH, a current path 51 through which current can flow can be formed in the channel layer CH of the drain select transistor. Therefore, the channel layer CH of the memory cell and the bit line BL can be electrically connected to each other through the channel layer CH of the drain select transistor. When a precharge voltage Vpr is applied to the bit line BL and transmitted to the channel layer CH of the memory cell through the channel layer CH of the drain select transistor, the channel layer CH of the memory cell can be precharged to the positive channel voltage Vch by the precharge voltage Vpr.

[0057] Figure 6A and Figure 6B It is a diagram. Figure 4 The image shows a view of the on or off operation of a source selection transistor.

[0058] refer to Figure 6A When a turn-off voltage Voff is applied to the first source select line SSL, the source select transistor is turned off (OFF), and no channel is formed in the channel CH of the source select transistor. When no channel is formed in the channel layer CH, no current path 61 is formed in the channel CH of the source select transistor. Therefore, the channel layer CH and source line SL of the memory cell can be electrically interrupted. This electrical interruption occurs in… Figure 6AThe symbol "X" indicates this. Therefore, the channel voltage Vch of the channel layer CH of the memory cell can be applied to the channel layer CH formed on top of the source selection transistor, and the voltage applied to the source line SL can be applied to the channel layer CH formed at the bottom of the source selection transistor. Thus, when the source selection transistor is off, even if a 0V source line voltage is applied to the source line SL, the level of the channel voltage Vch applied to the channel layer CH of the memory cell does not decrease.

[0059] refer to Figure 6B When an on-state voltage Von is applied to the first source select line SSL1, the source select transistor is turned on (ON), forming a channel in the channel layer CH of the source select transistor. When a channel is formed in the channel layer CH of the source select transistor, a current path 61 can be formed within the channel layer CH of the source select transistor. Therefore, the channel layer CH of the memory cell and the source line SL can be electrically connected to each other through the channel layer CH of the source select transistor. Therefore, when a 0V source line voltage is applied to the source line SL and the source select transistor is turned on (ON), the channel voltage Vch applied to the channel layer CH of the memory cell decreases.

[0060] Figure 7 This is a diagram illustrating an operation method of a memory device according to a first embodiment of the present disclosure.

[0061] refer to Figure 7 The read operation of a memory device can include an setup phase, a read phase, and a discharge phase.

[0062] The setup phases T1 to T2 are used to increase the potential of the channel layer CH. During read operations, ground voltage or 0V can be applied to the source line SL. During setup phases T1 to T2, the shutdown voltage Voff can be applied to the selected source select line Sel_SSL and the unselected source select line Unsel_SSL, and the turn-on voltage Von can be applied to the selected drain select line Sel_DSL and the unselected drain select line Unsel_DSL. The shutdown voltage Voff is the voltage at which the transistor is turned off and can be set to 0V. The turn-on voltage Von is the voltage at which the transistor is turned on and can be set to a positive voltage higher than 0V. The pass voltage Vpass can be applied to the unselected word line Unsel_WL and the selected word line Sel_WL. The pass voltage Vpass is used to turn on unselected memory cells and can be set to a positive voltage higher than 0V.

[0063] During setup phases T1 to T2, a first precharge voltage 1Vpr can be supplied to the bit line BL. This first precharge voltage 1Vpr can be set to a positive voltage higher than the second precharge voltage 2Vpr used in read phases T2 to T3. During setup phases T1 to T2, the drain selection transistor is turned on by the turn-on voltage Von, and thus the bit line BL and the channel layer CH can be electrically connected to each other. Therefore, the voltage of the channel layer CH can be increased to a positive channel voltage by the first precharge voltage 1Vpr supplied to the bit line BL. When a high voltage such as the first precharge voltage 1Vpr is applied to the bit line BL during setup phases T1 to T2, the voltage of the channel layer CH for the selected string Sel_ST and the unselected string Unsel_ST can be further increased than when the bit line BL is precharged by the second precharge voltage 2Vpr.

[0064] The read phases T2 to T3 are the phases in which the threshold voltage of the selected memory cell is reflected in the bit line BL. At the second time T2 at the start of the read phases T2 to T3, a second precharge voltage 2Vpr, lower than the first precharge voltage 1Vpr, can be applied to the bit line BL, and a shutdown voltage Voff can be applied to the unselected drain select line Unsel_DSL and the unselected source select line Unsel_SSL. The read voltage Vrd can be applied to the selected word line Sel_WL. When the shutdown voltage Voff is applied to the unselected drain select line Unsel_DSL and the unselected source select line Unsel_SSL, the drain select transistor and the source select transistor included in the unselected string Unsel_ST are turned off, and therefore, the channel layer CH of the unselected string Unsel_ST can be floated (FT).

[0065] The read voltage Vrd is a voltage used to determine the data in a memory cell, and can be set to a voltage with various levels based on the threshold voltage distribution of the memory cell targeted by the read operation. The read voltage Vrd is applied to the selected word line Sel_WL simultaneously with the voltage Vpass.

[0066] When the turn-on voltage Von is applied to the selected drain select line Sel_DSL and the selected source select line Sel_SSL, the drain select transistor and source select transistor included in the selected string are turned on. Therefore, the channel voltage Vch of the selected string can be maintained or reduced based on the threshold voltage of the selected memory cell connected to the selected word line Sel_WL. For example, when the threshold voltage of the selected memory cell is higher than or equal to the read voltage Vrd, the selected memory cell can be identified as the programming cell PGM_Cell. When the threshold voltage of the selected memory cell is lower than the read voltage Vrd, the selected memory cell can be identified as the erase cell ER_Cell. That is, since the threshold voltage of the programming cell PGM_Cell is higher than or equal to the read voltage Vrd, the programming cell PGM_Cell is turned off, and therefore, the channel voltage Vch of the channel layer CH of the selected string Sel_ST can be maintained at the voltage pre-charged during the setup phases T1 to T2. Alternatively, since the threshold voltage of the erase unit ER_Cell is lower than the read voltage Vrd, the erase unit ER_Cell is turned on, and therefore, the channel voltage Vch of the channel layer CH of the selected string Sel_ST can become lower than the voltage pre-charged during the setup phases T1 to T2.

[0067] Discharge phases T3 to T4 are phases in which the voltages of the lines connected to the selected memory block and the channel layer CH are reset. For example, in discharge phases T3 to T4, all lines connected to the selected memory block can be discharged. The term "discharge" means that the line to which a positive voltage is applied is electrically connected to a ground terminal, thereby reducing the voltage of the line to 0V. In discharge phases T3 to T4, the voltages of the channel layer CH for the selected string Sel_ST and the unselected string Unsel_ST can be reduced due to coupling to the word line WL. When the voltage of the channel layer CH is low, the voltage of the channel layer CH may drop below 0V when the word line WL is discharged. However, in this embodiment, in the setup phases T1 to T2, the voltage of the channel layer CH is precharged to a high level by a first precharge voltage 1Vpr. Therefore, in discharge phases T3 to T4, the voltage of the channel layer CH does not drop below 0V.

[0068] During the discharge phases T3 to T4, there is no period in which the voltage of the channel layer CH increases from a negative voltage back to 0V, and therefore, the voltage of the word line will not increase further above 0V due to the voltage of the channel layer CH. This improves the reliability of the read operation.

[0069] Figure 8 This is a diagram illustrating an operation method of a memory device according to a second embodiment of the present disclosure.

[0070] refer to Figure 8 The read operation of the memory device may include an setup phase, a read phase, an equalization phase, and a discharge phase. In the second embodiment, before performing the discharge phases T3 to T4, equalization phases T2' to T3 for equivalently adjusting the voltage of the word line WL may be further performed. Each phase will be described in detail below.

[0071] The setup phases T1 to T2 are used to increase the potential of the channel layer CH. During setup phases T1 to T2, a turn-off voltage Voff can be applied to the selected source select line Sel_SSL and the unselected source select line Unsel_SSL, and a turn-on voltage Von can be applied to the selected drain select line Sel_DSL and the unselected drain select line Unsel_DSL. The turn-off voltage Voff is the voltage at which the transistor is turned off and can be set to 0V. The turn-on voltage Von is the voltage at which the transistor is turned on and can be set to a positive voltage higher than 0V. A pass voltage Vpass can be applied to the unselected word line Unsel_WL and the selected word line Sel_WL. The pass voltage Vpass is used to turn on unselected memory cells and can be set to a positive voltage higher than 0V.

[0072] During setup phases T1 to T2, a first precharge voltage 1Vpr can be supplied to the bit line BL. This first precharge voltage 1Vpr can be set to a positive voltage higher than the second precharge voltage 2Vpr used in read phases T2 to T2'. During setup phases T1 to T2, the drain selection transistor is turned on by the turn-on voltage Von, and thus the bit line BL and the channel layer CH can be electrically connected to each other. Therefore, the voltage of the channel layer CH can be increased to a positive channel voltage by the first precharge voltage 1Vpr supplied to the bit line BL. When a high voltage such as the first precharge voltage 1Vpr is applied to the bit line BL during setup phases T1 to T2, the voltage of the channel layer CH for the selected string Sel_ST and the unselected string Unsel_ST can be further increased than when the bit line BL is precharged by the second precharge voltage 2Vpr.

[0073] The read phases T2 to T2' are the phases in which the threshold voltage of the selected memory cell is reflected to bit line BL. At the second time T2 at the start of the read phases T2 to T2', a second precharge voltage 2Vpr, lower than the first precharge voltage 1Vpr, can be applied to bit line BL, and a shutdown voltage Voff can be applied to the unselected drain select line Unsel_DSL and the unselected source select line Unsel_SSL. The read voltage Vrd can be applied to the selected word line Sel_WL. When the shutdown voltage Voff is applied to the unselected drain select line Unsel_DSL and the unselected source select line Unsel_SSL, the drain select transistor and the source select transistor included in the unselected string Unsel_ST are turned off, and therefore, the channel layer CH of the unselected string Unsel_ST can be in a floating state (FT).

[0074] The read voltage Vrd is a voltage used to determine the data in a memory cell, and can be set to a voltage with various levels based on the threshold voltage distribution of the memory cell targeted by the read operation. The read voltage Vrd is applied to the selected word line Sel_WL simultaneously with the voltage Vpass.

[0075] When the turn-on voltage Von is applied to the selected drain select line Sel_DSL and the selected source select line Sel_SSL, the drain select transistor and source select transistor included in the selected string are turned on. Therefore, the channel voltage Vch of the selected string can be maintained or reduced based on the threshold voltage of the selected memory cell connected to the selected word line Sel_WL. For example, when the threshold voltage of the selected memory cell is higher than or equal to the read voltage Vrd, the selected memory cell can be identified as the programming cell PGM_Cell. When the threshold voltage of the selected memory cell is lower than the read voltage Vrd, the selected memory cell can be identified as the erase cell ER_Cell. That is, since the threshold voltage of the programming cell PGM_Cell is higher than or equal to the read voltage Vrd, the programming cell PGM_Cell is turned off, and therefore, the channel voltage Vch of the channel layer CH of the selected string Sel_ST can be maintained at the voltage pre-charged during the setup phases T1 to T2. Alternatively, since the threshold voltage of the erase unit ER_Cell is lower than the read voltage Vrd, the erase unit ER_Cell is turned on, and therefore, the channel voltage Vch of the channel layer CH of the selected string Sel_ST can become lower than the voltage pre-charged during the setup phases T1 to T2.

[0076] The equalization phases T2' to T3 are used to equally adjust the voltages of word lines WL before the discharge phases T3 to T4, and can be implemented to prevent the voltages of word lines WL from becoming different from each other during the discharge phases T3 to T4 or to prevent the voltages of some word lines WL from dropping to negative voltages. For example, when the equalization phases T2' to T3 begin, a positive voltage can be applied to the selected word line Sel_WL, making the voltage of the selected word line Sel_WL equal to the voltage applied to the unselected word line Unsel_WL. A voltage Vpass can be applied to both the selected word line Sel_WL and the unselected word line Unsel_WL. A turn-on voltage Von equal to the voltage applied to the selected drain select line Sel_DSL can be applied to the unselected drain select line Unsel_DSL.

[0077] Discharge phases T3 to T4 are phases in which the voltages of the lines connected to the selected memory block and the channel layer CH are reset. For example, in discharge phases T3 to T4, all lines connected to the selected memory block can be discharged. The term "discharge" means that the line to which a positive voltage is applied is electrically connected to a ground terminal, thereby reducing the voltage of the line to 0V. In discharge phases T3 to T4, the voltages of the channel layer CH for the selected string Sel_ST and the unselected string Unsel_ST can be reduced due to coupling to the word line WL. When the voltage of the channel layer CH is low, the voltage of the channel layer CH may drop below 0V when the word line WL is discharged. However, in this embodiment, in the setup phases T1 to T2, the voltage of the channel layer CH is precharged to a high level by a first precharge voltage 1Vpr. Therefore, in discharge phases T3 to T4, the voltage of the channel layer CH does not drop below 0V.

[0078] During the discharge phases T3 to T4, there is no period in which the voltage of the channel layer CH increases from a negative voltage back to 0V, and therefore, the voltage of the word line will not increase further above 0V due to the voltage of the channel layer CH. This improves the reliability of the read operation.

[0079] Figure 9 This is a diagram illustrating an operation method of a memory device according to a third embodiment of the present disclosure.

[0080] refer to Figure 9 The read operation of the memory device may include a first setup phase, a second setup phase, a read phase, an equalization phase, and a discharge phase. In the third embodiment, before executing the read phases T2 to T2', a first setup phase T1 to T1' and a second setup phase T1' to T2 for raising the potential of the channel layer CH may be further executed. Each phase will be described in detail below.

[0081] The first setup phase, T1 to T1', is used to increase the voltage of the word line WL. When the first setup phase, T1 to T1', begins, the turn-on voltage Von can be applied to the selected drain select line Sel_DSL, the unselected drain select line Unsel_DSL, and the selected source select line Sel_SSL, and the voltage Vpass can be applied to the selected word line Sel_WL and the unselected word line Unsel_WL. The turn-on voltage Von or the turn-off voltage Voff can be applied to the unselected source select line Unsel_SSL, and... Figure 9 The diagram illustrates an embodiment where a turn-off voltage Voff is applied. A voltage of 0V can be applied to the bit line BL and the source line SL. Therefore, during the first setup phase T1 to T1', the potential of the channel layer CH can become 0V.

[0082] When the second setup phase T1' to T2 begins, a turn-off voltage Voff can be applied to the selected source select line Sel_SSL, and a read voltage Vrd can be applied to the selected word line Sel_WL. A first precharge voltage 1Vpr can be applied to the bit line BL. The first precharge voltage 1Vpr can be set to a positive voltage higher than the second precharge voltage 2Vpr used in the read phases T2 to T2'. In the second setup phases T1' to T2, the drain select transistor is turned on by the turn-on voltage Von, and thus the bit line BL and the channel layer CH can be electrically connected to each other. Therefore, the voltage of the channel layer CH can be increased to a positive channel voltage Vch by the first precharge voltage 1Vpr supplied to the bit line BL. When a high voltage such as the first precharge voltage 1Vpr is applied to the bit line BL in the second setup phases T1' to T2, the voltage of the channel layer CH of the selected string Sel_ST and the unselected string Unsel_ST can be further increased than when the bit line BL is precharged by the second precharge voltage 2Vpr.

[0083] The read phases T2 to T2' are the phases in which the threshold voltage of the selected memory cell is reflected to bit line BL. At the second time T2 at the start of the read phases T2 to T2', a second precharge voltage 2Vpr, lower than the first precharge voltage 1Vpr, can be applied to bit line BL, and a shutdown voltage Voff can be applied to the unselected drain select line Unsel_DSL and the unselected source select line Unsel_SSL. The read voltage Vrd can be applied to the selected word line Sel_WL. When the shutdown voltage Voff is applied to the unselected drain select line Unsel_DSL and the unselected source select line Unsel_SSL, the drain select transistor and the source select transistor included in the unselected string Unsel_ST are turned off, and therefore, the channel layer CH of the unselected string Unsel_ST can be in a floating state (FT).

[0084] The read voltage Vrd is a voltage used to determine the data in a memory cell, and can be set to a voltage with various levels based on the threshold voltage distribution of the memory cell targeted by the read operation. The read voltage Vrd is applied to the selected word line Sel_WL simultaneously with the voltage Vpass.

[0085] When the turn-on voltage Von is applied to the selected drain select line Sel_DSL and the selected source select line Sel_SSL, the drain select transistor and source select transistor included in the selected string are turned on. Therefore, the channel voltage Vch of the selected string can be maintained or reduced based on the threshold voltage of the selected memory cell connected to the selected word line Sel_WL. For example, when the threshold voltage of the selected memory cell is higher than or equal to the read voltage Vrd, the selected memory cell can be identified as the programming cell PGM_Cell. When the threshold voltage of the selected memory cell is lower than the read voltage Vrd, the selected memory cell can be identified as the erase cell ER_Cell. That is, since the threshold voltage of the programming cell PGM_Cell is higher than or equal to the read voltage Vrd, the programming cell PGM_Cell is turned off, and therefore, the channel voltage Vch of the channel layer CH of the selected string Sel_ST can be maintained at the voltage pre-charged during the second setup phases T1' to T2. Alternatively, since the threshold voltage of the erase unit ER_Cell is lower than the read voltage Vrd, the erase unit ER_Cell is turned on, and therefore, the channel voltage Vch of the channel layer CH of the selected string Sel_ST can become lower than the pre-charge voltage during the second setup phase T1' to T2.

[0086] The equalization phases T2' to T3 are used to equally adjust the voltages of word lines WL before the discharge phases T3 to T4, and can be implemented to prevent the voltages of word lines WL from becoming different from each other during the discharge phases T3 to T4 or to prevent the voltages of some word lines WL from dropping to negative voltages. For example, when the equalization phases T2' to T3 begin, a positive voltage can be applied to the selected word line Sel_WL, making the voltage of the selected word line Sel_WL equal to the voltage applied to the unselected word line Unsel_WL. A voltage Vpass can be applied to both the selected word line Sel_WL and the unselected word line Unsel_WL. A turn-on voltage Von equal to the voltage applied to the selected drain select line Sel_DSL can be applied to the unselected drain select line Unsel_DSL.

[0087] Discharge phases T3 to T4 are phases in which the voltages of the lines connected to the selected memory block and the channel layer CH are reset. For example, in discharge phases T3 to T4, all lines connected to the selected memory block can be discharged. The term "discharge" means that the line to which a positive voltage is applied is electrically connected to the ground terminal, thereby reducing the voltage of the line to 0V. In discharge phases T3 to T4, the voltages of the channel layer CH for the selected string Sel_ST and the unselected string Unsel_ST can be reduced due to coupling to the word line WL. Because the voltage of the channel layer CH is precharged to a high level by the first precharge voltage 1Vpr in the second setup phases T1' to T2, the voltage of the channel layer CH does not drop below 0V in discharge phases T3 to T4.

[0088] During the discharge phases T3 to T4, there is no period in which the voltage of the channel layer CH increases from a negative voltage back to 0V, and therefore, the voltage of the word line will not increase further above 0V due to the voltage of the channel layer CH. This improves the reliability of the read operation.

[0089] Figure 10 This is a diagram illustrating an operation method of a memory device according to a fourth embodiment of the present disclosure.

[0090] refer to Figure 10 The read operation of the memory device may include a first setup phase, a second setup phase, a read phase, an equalization phase, and a discharge phase. In the fourth embodiment, a first pre-charge voltage 1Vpr may be supplied to the bit line BL during the first setup phases T1 to T1'. Each phase will be described in detail below.

[0091] The first setup phase, T1 to T1', is used to increase the voltage of the word line WL and the channel layer CH. When the first setup phase, T1 to T1', begins, a first precharge voltage 1Vpr can be applied to the bit line BL, an on-state voltage Von can be applied to the selected drain select line Sel_DSL, the unselected drain select line Unsel_DSL, the selected source select line Sel_SSL, and the unselected source select line Unsel_SSL, and a voltage Vpass can be applied to the selected word line Sel_WL and the unselected word line Unsel_WL. The first precharge voltage 1Vpr can be set to a positive voltage higher than the second precharge voltage 2Vpr used in the read phases T2-T2'. Because the source select transistor is on, the source line SL can be floated (FT) to prevent the potential of the channel layer CH from decreasing. Therefore, during the first setup phase T1-T1', the potential of the channel layer CH of the selected string Sel_ST and the unselected string Unsel_ST can be increased up to a channel voltage Vch as a positive voltage. When a high voltage such as the first precharge voltage 1Vpr is applied to the bit line BL during the first setup phase T1 to T1', the voltage of the channel layer CH of the selected string Sel_ST and the unselected string Unsel_ST can be further increased than when the bit line BL is precharged by the second precharge voltage 2Vpr.

[0092] When the second setup phase T1' to T2 begins, the read voltage Vrd can be applied to the selected word line Sel_WL. The source line SL can be kept in a floating state (FT) so that the channel voltage of the channel layer CH does not decrease.

[0093] The read phases T2 to T2' are the phases in which the threshold voltage of the selected memory cell is reflected to bit line BL. At the second time T2 at the start of the read phases T2 to T2', a second precharge voltage 2Vpr, lower than the first precharge voltage 1Vpr, can be applied to bit line BL, and a turn-off voltage Voff can be applied to the unselected drain select line Unsel_DSL and the unselected source select line Unsel_SSL. Therefore, a voltage of 0V can be applied to the source line SL from the second time T2. The read voltage Vrd can be applied to the selected word line Sel_WL. When the turn-off voltage Voff is applied to the unselected drain select line Unsel_DSL and the unselected source select line Unsel_SSL, the drain select transistor and the source select transistor included in the unselected string Unsel_ST are turned off, and therefore, the channel layer CH of the unselected string Unsel_ST can be in a floating state (FT).

[0094] The read voltage Vrd is a voltage used to determine the data in a memory cell, and can be set to a voltage with various levels based on the threshold voltage distribution of the memory cell targeted by the read operation. The read voltage Vrd is applied to the selected word line Sel_WL simultaneously with the voltage Vpass.

[0095] When the turn-on voltage Von is applied to the selected drain select line Sel_DSL and the selected source select line Sel_SSL, the drain select transistor and source select transistor included in the selected string are turned on. Therefore, the channel voltage Vch of the selected string can be maintained or reduced based on the threshold voltage of the selected memory cell connected to the selected word line Sel_WL. For example, when the threshold voltage of the selected memory cell is higher than or equal to the read voltage Vrd, the selected memory cell can be identified as the programming cell PGM_Cell. When the threshold voltage of the selected memory cell is lower than the read voltage Vrd, the selected memory cell can be identified as the erase cell ER_Cell. That is, since the threshold voltage of the programming cell PGM_Cell is higher than or equal to the read voltage Vrd, the programming cell PGM_Cell is turned off, and therefore, the channel voltage Vch of the channel layer CH of the selected string Sel_ST can be maintained at the voltage pre-charged during the second setup phases T1' to T2. Alternatively, since the threshold voltage of the erase unit ER_Cell is lower than the read voltage Vrd, the erase unit ER_Cell is turned on, and therefore, the channel voltage Vch of the channel layer CH of the selected string Sel_ST can become lower than the pre-charge voltage during the second setup phase T1' to T2.

[0096] The equalization phases T2' to T3 are used to equally adjust the voltages of word lines WL before the discharge phases T3 to T4, and can be implemented to prevent the voltages of word lines WL from becoming different from each other during the discharge phases T3 to T4 or to prevent the voltages of some word lines WL from dropping to negative voltages. For example, when the equalization phases T2' to T3 begin, a positive voltage can be applied to the selected word line Sel_WL, making the voltage of the selected word line Sel_WL equal to the voltage applied to the unselected word line Unsel_WL. A voltage Vpass can be applied to both the selected word line Sel_WL and the unselected word line Unsel_WL. A turn-on voltage Von equal to the voltage applied to the selected drain select line Sel_DSL can be applied to the unselected drain select line Unsel_DSL.

[0097] Discharge phases T3 to T4 are phases in which the voltages of the lines connected to the selected memory block and the channel layer CH are reset. For example, in discharge phases T3 to T4, all lines connected to the selected memory block can be discharged. The term "discharge" means that the line to which a positive voltage is applied is electrically connected to the ground terminal, thereby reducing the voltage of the line to 0V. In discharge phases T3 to T4, the voltages of the channel layer CH for the selected string Sel_ST and the unselected string Unsel_ST can be reduced due to coupling to the word line WL. Because the voltage of the channel layer CH is precharged to a high level by the first precharge voltage 1Vpr in the second setup phases T1' to T2, the voltage of the channel layer CH does not drop below 0V in discharge phases T3 to T4.

[0098] During the discharge phases T3 to T4, there is no period in which the voltage of the channel layer CH increases from a negative voltage back to 0V, and therefore, the voltage of the word line will not increase further above 0V due to the voltage of the channel layer CH. This improves the reliability of the read operation.

[0099] Figure 11 This is a diagram illustrating a memory card system 3000, in which a memory device according to an embodiment of the present disclosure is applied to the memory card system 3000.

[0100] refer to Figure 11 The memory card system 3000 includes a controller 3100, a memory device 3200, and a connector 3300.

[0101] Controller 3100 can be connected to memory device 3200. Controller 3100 can access memory device 3200. For example, controller 3100 can control programming, reading, or erasing operations of memory device 3200, or control background operations of memory device 3200. Controller 3100 can provide an interface between memory device 3200 and a host. Controller 3100 can drive firmware for controlling memory device 3200. For example, controller 3100 may include components such as random access memory (RAM), processing unit, host interface, memory interface, and error corrector.

[0102] Controller 3100 can communicate with external devices via connector 3300. Controller 3100 can communicate with external devices (e.g., a host) according to a specific communication protocol. Exemplarily, controller 3100 can communicate with external devices via at least one of a variety of communication protocols, such as Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI Express (PCIe), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Storage (UFS), Wi-Fi, Bluetooth, and NVMe. Exemplarily, connector 3300 can be defined by at least one of the aforementioned communication protocols.

[0103] The memory device 3200 may include memory cells and is connected to... Figure 1 The memory device 100 shown is configured similarly.

[0104] The controller 3100 and memory device 3200 can be integrated into a single semiconductor device to form a memory card. For example, the controller 3100 and memory device 3200 can form a memory card such as a personal computer (PC) memory card, a compact flash memory (CF) card, a smart media card (SM and SMC), a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro and eMMC), an SD card (SD, mini SD, micro SD and SDHC), and universal flash storage (UFS).

[0105] Figure 12 This is a diagram illustrating a solid-state drive (SSD) system 4000, in which a memory device according to an embodiment of the present disclosure is applied.

[0106] refer to Figure 12 The SSD system 4000 includes a host 4100 and an SSD 4200. The SSD 4200 exchanges signals SIG with the host 4100 through a signal connector 4001 and receives power PWR through a power connector 4002. The SSD 4200 includes a controller 4210, multiple memory devices 4221 to 422n, an auxiliary power supply 4230, and a buffer memory 4240.

[0107] The controller 4210 can control multiple storage devices 4221 to 422n in response to signals received from the host 4100. These signals can be based on the interface between the host 4100 and the SSD 4200. For example, the signal can be defined by at least one of the following interfaces: Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI Express (PCIe), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Storage (UFS), Wi-Fi, Bluetooth, and NVMe.

[0108] The plurality of memory devices 4221 to 422n may include units capable of storing data. Each of the plurality of memory devices 4221 to 422n can be connected to... Figure 1 The memory device 100 shown is configured similarly.

[0109] Auxiliary power supply 4230 can be connected to host 4100 via power connector 4002. Auxiliary power supply 4230 can receive power PWR input from host 4100 and utilize the power PWR for charging. When the power supply from host 4100 is unstable, auxiliary power supply 4230 can provide power to SSD 4200. Exemplarily, auxiliary power supply 4230 can be located inside SSD 4200 or external to SSD 4200. For example, auxiliary power supply 4230 can be located on the motherboard and provide auxiliary power to SSD 4200.

[0110] Buffer memory 4240 can operate as a buffer memory for SSD 4200. For example, buffer memory 4240 can temporarily store data received from host 4100 or data received from multiple memory devices 4221 to 422n, or temporarily store metadata (e.g., mapping tables) of memory devices 4221 to 422n. Buffer memory 4240 may include volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM, or may include non-volatile memory such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0111] According to some embodiments of this disclosure, the reliability of read operations performed in a memory device can be improved.

[0112] While this disclosure has been shown and described with reference to certain embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope of this disclosure as defined by the appended claims and their equivalents. Therefore, the scope of this disclosure should not be limited to the embodiments described above, but should be determined not only by the appended claims but also by their equivalents.

[0113] In the above embodiments, all steps may be selectively performed or some steps may be omitted. In each embodiment, the steps are not necessarily performed in the described order and may be rearranged. The embodiments disclosed in this specification and drawings are merely examples to facilitate understanding of this disclosure, and this disclosure is not limited thereto. That is, it will be apparent to those skilled in the art that various modifications can be made based on the technical scope of this disclosure.

[0114] Furthermore, embodiments of this disclosure have been described in the accompanying drawings and specification. Although specific terminology is used herein, those specific terms are only for explaining the embodiments of this disclosure. Therefore, this disclosure is not limited to the above embodiments, and many variations are possible within the spirit and scope of this disclosure. It will be apparent to those skilled in the art that various modifications can be made based on the technical scope of this disclosure in addition to the embodiments disclosed herein.

Claims

1. A memory device, comprising: A memory block comprising strings formed between bit lines and source lines; as well as Peripheral circuitry configured to perform read operations on selected memory cells, which are included in a selected string within the string. The peripheral circuitry includes a page buffer, which is configured to: During the setup phase of the read operation, the voltage of the string channel is increased by applying a first pre-charge voltage to the bit line; During the read phase of the read operation, a second precharge voltage lower than the first precharge voltage is applied to the bit line; as well as The bit line is discharged during the discharge phase of the read operation. During the setup phase, the peripheral circuitry is configured to apply a pass voltage to both the selected and unselected word lines connected to the string. During the reading phase, the peripheral circuit is configured to float the channel of the unselected string in the string.

2. The memory device of claim 1, wherein during the setup phase, the peripheral circuitry is configured to apply a voltage of 0V to the source line.

3. The memory device of claim 2, wherein during the setup phase, the peripheral circuitry is configured to turn on a drain selection transistor connected between the memory cells in the bit line and the string.

4. The memory device of claim 2, wherein during the setup phase, the peripheral circuitry is configured to turn off the source selection transistors connected between the source line and the memory cells in the string.

5. The memory device of claim 1, wherein, in order to float the channel of the unselected string, the peripheral circuitry is configured to turn off the unselected drain select transistor and the unselected source select transistor included in the unselected string.

6. The memory device of claim 1, wherein during the read phase, the peripheral circuitry is configured to apply a read voltage to a selected word line connected to the selected memory cell included in the selected string.

7. The memory device of claim 1, wherein during the setup phase, the peripheral circuitry is configured to float the source line.

8. The memory device of claim 7, wherein during the setup phase, the peripheral circuitry is configured to turn on a drain selection transistor connected between the bit line and the memory cell in the string, and to turn on a source selection transistor connected between the source line and the memory cell in the string.

9. The memory device of claim 8, wherein during the setup phase, the peripheral circuitry is configured to apply a read voltage to a selected word line among the word lines when the pass voltage is applied to the word line.

10. The memory device of claim 1, wherein prior to performing the discharge phase, the peripheral circuitry is configured to perform an equalization phase for equivalently adjusting the voltages of the word lines connected to the string.

11. The memory device of claim 1, wherein during the discharge phase, the peripheral circuitry is configured to discharge the source select line, word line, and drain select line connected to the string.

12. A method of operating a memory device, the method comprising: The channel voltage is increased by applying a first pre-charge voltage to the bit line of the channel electrically coupled to the string; When the channel voltage increases, a second precharge voltage lower than the first precharge voltage is applied to the bit line; A read voltage is applied to a selected word line among the word lines arranged between the bit line and the source line; as well as Discharge the bit lines and the word lines. In increasing the channel voltage, voltage is applied to both the selected and unselected word lines connected to the string, and During the application of the second pre-charge voltage to the bit line, the unselected drain select transistor and the unselected source select transistor connected to the unselected string are turned off.

13. The method of claim 12, wherein in increasing the channel voltage, when a voltage of 0V is applied to the source line, the drain select transistor is turned on by applying an on-state voltage to the drain select line adjacent to the bit line, and the source select transistor is turned off by applying an off-state voltage to the source select line adjacent to the source line.

14. The method of claim 12, wherein in increasing the channel voltage, when the source line is floating, the drain select transistor is turned on by applying an on-state voltage to the drain select line adjacent to the bit line, and the source select transistor is turned on by applying an on-state voltage to the source select line adjacent to the source line.

15. The method of claim 12, wherein when the read voltage is applied to the selected word line, a voltage is also applied to the unselected word line.

16. The method of claim 12, wherein an equalization phase for equivalently adjusting the voltage of the word line is further included between the application of the read voltage and the discharge.

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