A memory three-cell coupling fault detection method, a terminal device and a medium

Abstract

The application relates to a memory three-cell coupling fault detection method, a terminal device and a medium. In the method, an efficient three-cell coupling fault detection algorithm with a time complexity of 58N is provided. Compared with an existing detection algorithm, the algorithm has lower algorithm complexity and higher fault coverage, and can reduce the detection cost of an SRAM or DRAM memory.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of memory fault detection, and in particular to a memory three-cell coupling fault detection method, a terminal device and a medium. BACKGROUND

[0002] With the development of integrated circuits, chip processes are continuously reduced, the capacity and density of memories are continuously improved, and the distance between each storage cell in the memory is also reduced, which greatly increases the probability of memory failure. Therefore, how to effectively test the random access memory becomes the key. There are three main testability design techniques in the industry, namely, scan testing, boundary scan and built-in self-test (BIST). Scan testing can realize direct testing of sequential circuits by introducing scan registers and inserting scan chains, but the disadvantage is that a large number of input and output pins need to be introduced, which greatly reduces the performance of the chip. The main test object of boundary scan is the input and output pins of the circuit, which has little effect on the performance of the chip, but the test time is long. Built-in self-test is to check the manufacturing defects of the circuit through a special test circuit integrated in the chip, which occupies a very small area and has little effect on the performance of the chip, and the test time is also short. According to the different test objects, built-in self-test is divided into logic built-in self-test (LBIST) and memory built-in self-test (MBIST). There are many kinds of MBIST fault detection algorithms, among which the mainstream algorithm that takes into account the complexity and coverage is the March series algorithm based on address.

[0003] According to the fault behavior of the memory, the fault can be divided into single-cell fault and multi-cell coupling fault (CF). Among them, the single-cell fault mainly includes fixed fault (SAF), transition fault (TF) and data retention fault (DRF). Multi-cell coupling fault mainly includes double-cell coupling fault, three-cell coupling fault and adjacent vector sensitization fault (NPSF).

[0004] The existing memory fault detection algorithm can completely detect single-cell fault and double-cell coupling fault, but there are deficiencies in detection efficiency and coverage for three-cell coupling fault detection. When the process enters 40nm and below, the distance between storage cells is getting closer and closer, and the three-cell coupling fault effect will become more and more significant. The current three-cell coupling fault detection algorithm mostly has the problems of high complexity and insufficient fault coverage. SUMMARY

[0005] In order to solve the above problems, the present application provides a memory three-cell coupling fault detection method, a terminal device and a medium.

[0006] The specific scheme is as follows:

[0007] A memory three-cell coupling fault detection method, comprising the following steps:

[0008] Step one: set the storage cells of the memory to be tested to a first background data I0 through address arbitrary sequence write operation;

[0009] Step two: sequentially perform read, read, jump write and non-jump write operations on all storage cells in ascending address order;

[0010] Step three: sequentially perform read, read, jump write and non-jump write operations on all storage cells in ascending address order again;

[0011] Step four: sequentially perform read, read, jump write and non-jump write operations on all storage cells in descending address order;

[0012] Step five: sequentially perform read, read, jump write and non-jump write operations on all storage cells in descending address order again;

[0013] Step six: sequentially perform read operations on all storage cells in address arbitrary sequence;

[0014] Step seven: set the storage cells of the memory to be tested to a second data background I1 through address arbitrary sequence write operation;

[0015] Step eight: sequentially perform read, read, jump write, non-jump write, read, read, jump write, non-jump write operations on all storage cells in ascending address order;

[0016] Step nine: sequentially perform read operations on all storage cells in address arbitrary sequence;

[0017] Step ten: set the storage cells of the memory to be tested to a third data background I2 through address arbitrary sequence write operation;

[0018] Step eleven: sequentially perform read, read, jump write, non-jump write, read, read, jump write, non-jump write operations on all storage cells in ascending address order;

[0019] Step twelve: sequentially perform read operations on all storage cells in address arbitrary sequence;

[0020] Step thirteen: set the storage cells of the memory to be tested to a data background I3 through address arbitrary sequence write operation;

[0021] Step fourteen: sequentially perform read, read, jump write, non-jump write, read, read, jump write, non-jump write operations on all storage cells in ascending address order;

[0022] Step fifteen: sequentially performing read operation on all storage units in any order of addresses;

[0023] Step sixteen: setting the storage units of the storage to be tested to data background I4 through address-optional-order write operation;

[0024] Step seventeen: sequentially performing read, read, jump write, non-jump write, read, read, jump write, non-jump write operation on all storage units in ascending order of addresses;

[0025] Step eighteen: sequentially performing read operation on all storage units in any order of addresses.

[0026] A memory three-cell coupling fault detection terminal device, comprising a processor, a memory and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the method of the above-mentioned embodiment of the application when executing the computer program.

[0027] A computer readable storage medium, which stores a computer program, wherein the computer program implements the steps of the method of the above-mentioned embodiment of the application when executed by a processor.

[0028] The technical scheme can detect three-cell coupling faults in all physical arrangements and logical value distribution conditions, the fault coverage rate reaches 100%, and the time complexity is only 58N, which is lower than that of the prior art and has higher fault coverage rate, so that the detection efficiency of the memory can be improved and the detection cost can be reduced. BRIEF DESCRIPTION OF DRAWINGS

[0029] Figure 1 Fig. 1 shows six physical arrangement diagrams of three-cell coupling in the first embodiment of the application.

[0030] Figure 2 Fig. 2 shows a March ML3C algorithm test flowchart in the first embodiment of the application.

[0031] Figure 3 Fig. 3 shows five data background diagrams in the first embodiment of the application.

[0032] Figure 4 Fig. 4 shows 36 physical arrangement diagrams of three-cell coupling in the first embodiment of the application.

[0033] Figure 5 Fig. 5 shows a deduction diagram of arrangement 1 using the March ML3C algorithm in the first embodiment of the application.

[0034] Figure 6The figure shown is a derivation diagram of the permutation 36 using the March ML3C algorithm in Embodiment 1 of the present invention. Detailed Implementation

[0035] To further illustrate the various embodiments, the present invention provides accompanying drawings. These drawings are part of the disclosure of the present invention, primarily used to illustrate the embodiments, and can be used in conjunction with the relevant descriptions in the specification to explain the operating principles of the embodiments. With reference to these drawings, those skilled in the art should be able to understand other possible implementations and the advantages of the present invention.

[0036] The present invention will now be further described in conjunction with the accompanying drawings and specific embodiments.

[0037] Example 1:

[0038] Three-cell coupling faults mainly refer to coupling faults occurring in three physically adjacent memory cells within a memory array. There are six possible physical arrangements of these faults, such as... Figure 1 As shown. It is generally believed that among the three units experiencing a coupling failure, there are two attacking units and one victim unit. In a single-port random access memory, only one unit can be read from or written to at a time. Therefore, among the three coupled units, there is one dominant attacking unit and one auxiliary attacking unit, with the dominant attacking unit primarily affecting the victim unit. It is generally assumed that the coupled units do not intersect and do not produce a masking effect.

[0039] Three-unit coupled faults can be further classified into state-coupled faults (CF) based on their specific fault behaviors. st ), jump coupling fault (CF) tr Write-destroyed coupling fault (CF) wd Read-destructive coupling fault (CF) rd ), false reads disrupt coupling faults (CF) drd ), incorrect read coupling fault (CF) ir and disturbance coupling fault (CF) ds These faults can be specifically described by fault primitive (FP) symbols, as shown in Table 1. The fault primitive symbols are: da S aa S v / F / R>, where S da S represents the sensitization operation performed in the dominant attack unit. aa S represents the sensitization operation performed in the auxiliary attack unit. v ​represents a sensitization operation performed at the victim cell, F represents a fault state of the victim cell excited under the sensitization operation, R represents a result read out when a read operation is performed at the time of fault excitation, r0 represents reading 0 from the memory cell, r1 represents reading 1 from the memory cell, 0w0 represents writing 0 in the memory cell whose original logical value is 0, 0w1 represents writing 1 in the memory cell whose original logical value is 0, 1w0 represents writing 0 in the memory cell whose original logical value is 1, 1w1 represents writing 1 in the memory cell whose original logical value is 1, and represents that the logical value of the memory cell is rising, and represents that the logical value of the memory cell is falling.

[0040] Table 1

[0041]

[0042]

[0043]

[0044] A fault detection March ML3C algorithm is proposed in the embodiment, a detection sequence with a time complexity of 58N (N is the number of memory cells) is used to detect three-cell coupling faults in a random access memory, as shown in the following table. Figure 2

[0045] Figure 2 In the table, “{}” represents a complete March test, “()” represents a detection step, referred to as a March cell, which is composed of one or more read and write operations in a specific order, the superscript (1)-(18) in the upper right corner of the cell represents the serial number of the March cell, represents ascending logical addresses, represents descending logical addresses, represents arbitrary logical addresses, “R” represents performing a read operation on the memory cell, “W t ” represents performing a jump write operation on the memory cell, “W” represents performing a non-jump write operation on the memory cell, “I0”, “I1”, “I2”, “I3”, and “I4” represent five data backgrounds, as shown in the following table. Figure 3

[0046] Based on the above detection sequence, the corresponding detection steps are set as follows in the embodiment:

[0047] Step 1: all memory cells of the memory to be tested are set to 0 by an address-arbitrary-sequence write operation, i.e., set to data background I0;

[0048] Step 2: in an ascending address order, read, read, jump write, and non-jump write operations are sequentially performed on all memory cells. ​​

[0049] Step three: read, read, jump write and no jump write are performed on all memory cells in turn again in ascending address order;

[0050] Step four: read, read, jump write and no jump write are performed on all memory cells in turn in descending address order;

[0051] Step five: read, read, jump write and no jump write are performed on all memory cells in turn again in descending address order;

[0052] Step six: read is performed on all memory cells in turn in arbitrary address order;

[0053] Step seven: the memory cells of the memory under test are set to data background I1 by write operation in arbitrary address order;

[0054] Step eight: read, read, jump write, no jump write, read, read, jump write, no jump write are performed on all memory cells in turn in ascending address order;

[0055] Step nine: read is performed on all memory cells in turn in arbitrary address order;

[0056] Step ten: the memory cells of the memory under test are set to data background I2 by write operation in arbitrary address order;

[0057] Step eleven: read, read, jump write, no jump write, read, read, jump write, no jump write are performed on all memory cells in turn in ascending address order;

[0058] Step twelve: read is performed on all memory cells in turn in arbitrary address order;

[0059] Step thirteen: the memory cells of the memory under test are set to data background I3 by write operation in arbitrary address order;

[0060] Step fourteen: read, read, jump write, no jump write, read, read, jump write, no jump write are performed on all memory cells in turn in ascending address order;

[0061] Step fifteen: read is performed on all memory cells in turn in arbitrary address order;

[0062] Step sixteen: the memory cells of the memory under test are set to data background I4 by write operation in arbitrary address order;

[0063] Step seventeen: read, read, jump write, no jump write, read, read, jump write, no jump write, sequentially for all memory cells in ascending address order;

[0064] Step eighteen: read sequentially for all memory cells in arbitrary address order;

[0065] March ML3C algorithm introduces five kinds of data background, and through the specific order of read and write operations to stimulate and observe the fault, so as to realize the detection of three-unit coupling fault. The three-unit coupling fault refers to that in the single-port random access memory, three units with adjacent physical addresses can be sensitized by no more than one read and write operation, and the coupling units do not intersect, and do not produce masking effect. As shown in Figure 1 , there are six arrangements of three units with adjacent physical addresses. Considering that there is one victim unit (S v ) and two attack units in the three units, one of the attack units is the leading attack unit (S da ), and the other is the auxiliary attack unit (S aa ), according to the different distribution of victim units and attack units, there are six different distributions of victim units and attack units for each physical arrangement of three units, so as shown in Figure 4 , there are 36 arrangements in total. Each arrangement may produce 72 fault conditions as shown in Table 1, so the total number of three-unit coupling faults is 2592. The following is an example:

[0066] The process of March ML3C algorithm for arrangement 1 is shown in Figure 5 , where M0-M 18 denote the 18 steps of March ML3C algorithm. The faults that can be detected and excited by each step are shown in Table 2.

[0067] Table 2:

[0068]

[0069] Wherein, FP represents the fault primitive.

[0070] The process of March ML3C algorithm for arrangement 36 is shown in Figure 6 , where M0-M 18 denote the 18 steps of March ML3C algorithm. The faults that can be detected by each step are shown in Table 3.

[0071] Table 3:

[0072]

[0073]

[0074] From the above two examples, it can be seen that the 18 steps of the March ML3C algorithm can detect all the 72 possible faults in permutation 1 and permutation 36, and the same is true for other permutations. In the March ML3C algorithm provided in the embodiment, an arbitrary order read operation on the memory cell is introduced before each data context conversion, which ensures that the faults excited before the data context conversion can be detected. Compared with the existing partial algorithms, this ensures that the algorithm can completely cover all faults.

[0075] Table 4 is a comparison of the March ML3C algorithm provided in the embodiment with various existing algorithms. It can be seen that, in terms of fault coverage and time complexity, the March ML3C algorithm provided in the embodiment is optimal.

[0076] Table 4:

[0077]

[0078] The algorithm of the embodiment has the following improvements:

[0079] Improvement 1: Based on the framework and data context of the March SR3C algorithm, the basic detection steps composed of (R, R, W t , W) are used to reduce the complexity of the algorithm while ensuring the activation and detection of faults. Among them, the two consecutive read operations (R, R) can detect the faults activated in the previous step and the state coupling faults (FP 1-8), read disturb coupling faults (FP 25-32), pseudo read disturb coupling faults (FP 33-40) and incorrect read coupling faults (FP 41-48) in the current state if they act on the victim cell; if they act on the dominant attack cell, they can activate the disturbance coupling faults (FP 49-56) of the read operation. t The order of the two write operations W t can ensure that the operation result of Wt will not be overwritten, because W is a write operation without jump, which will not change the result after W t operation. , W If they act on the victim cell, they can activate the jump coupling faults (FP 9-16) and the write disturb coupling faults (FP 17-24); if they act on the dominant attack cell, they can activate the disturbance coupling faults (FP 57-72) of the write operation.

[0080] Improvement 2: Before each data context switching, an arbitrary order read operation is added, which ensures that the fault activated by the last read-write operation in each data context can be detected by the arbitrary order read operation. The traditional algorithm only adds this read operation after the detection step in the last data context is completed, and even some algorithms do not add such a read operation, which affects the actual algorithm coverage. The March ML3C algorithm proposed in this embodiment adds an arbitrary order read operation after the detection step in each data context is completed, which ensures that there is no activated fault that is not observed. Because if the fault is only activated and not observed by the read operation, it cannot be said that the fault has been detected.

[0081] Embodiment 2

[0082] The application further provides a memory three-cell coupling fault detection terminal device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, and the processor implements the steps in the above method embodiments of the embodiment one of the application when executing the computer program.

[0083] Further, as an executable scheme, the memory three-cell coupling fault detection terminal device can be a desktop computer, a notebook, a palm computer, a cloud server, and the like. The memory three-cell coupling fault detection terminal device can include, but is not limited to, a processor and a memory. Those skilled in the art can understand that the above-mentioned composition structure of the memory three-cell coupling fault detection terminal device is only an example of the memory three-cell coupling fault detection terminal device, and does not constitute a limitation on the memory three-cell coupling fault detection terminal device, and can include more or fewer components than the above, or combine certain components, or different components, for example, the memory three-cell coupling fault detection terminal device can also include an input and output device, a network access device, a bus, and the like, and the embodiments of the application do not limit this.

[0084] Further, as an executable solution, the processor can be a central processing unit (CPU), and can also be other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor. The processor is a control center of the memory three-unit coupling fault detection terminal device, and connects various parts of the memory three-unit coupling fault detection terminal device through various interfaces and lines.

[0085] The memory can be used to store the computer program and / or modules, and the processor realizes various functions of the memory three-unit coupling fault detection terminal device by running or executing the computer program and / or modules stored in the memory, and calling data stored in the memory. The memory can mainly include a program storage area and a data storage area. The program storage area can store an operating system and at least one application required by a function; and the data storage area can store data created according to the use of the mobile phone, etc. In addition, the memory can include a high-speed random access memory, and can also include a nonvolatile memory, for example, a hard disk, a memory, a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, at least one disk storage device, a flash memory device, or other volatile solid-state memory devices.

[0086] The application further provides a computer readable storage medium, which stores a computer program. The computer program is executed by a processor to realize the steps of the method provided in the embodiments of the application.

[0087] The module / unit of the memory three-cell coupling fault detection terminal equipment integration, if realized in the form of a software function unit and sold or used as an independent product, can be stored in a computer-readable storage medium. Based on such an understanding, all or part of the processes in the above-mentioned embodiment methods can also be completed by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium. When the computer program is executed by a processor, the steps of the above-mentioned various method embodiments can be implemented. The computer program includes computer program code, which can be in the form of source code, object code, an executable file, or some intermediate form, etc. The computer-readable medium can include any entity or device capable of carrying the computer program code, a recording medium, a U disk, a mobile hard disk, a magnetic disk, an optical disk, a computer memory, a read-only memory (ROM), a random access memory (RAM), and a software distribution medium, etc.

[0088] Although the present application has been specifically shown and described with respect to the preferred embodiments, it should be understood that the application is entitled to protection within the full scope of the appended claims, without departing from the spirit and scope of the application.

Claims

1. A memory triple-cell coupling fault detection method, characterized in that, The method comprises the following steps: Step one: set the storage units of the memory under test to a first background data I0 by address arbitrary sequence write operation; Step two: sequentially perform read, read, jump write and non-jump write operation on all storage units in ascending address order; Step three: sequentially perform read, read, jump write and non-jump write operation on all storage units in ascending address order again; Step four: sequentially perform read, read, jump write and non-jump write operation on all storage units in descending address order; Step five: sequentially perform read, read, jump write and non-jump write operation on all storage units in descending address order again; Step six: sequentially perform read operation on all storage units in address arbitrary sequence; Step seven: set the storage units of the memory under test to a second data background I1 by address arbitrary sequence write operation; Step eight: sequentially perform read, read, jump write, non-jump write, read, read, jump write, non-jump write operation on all storage units in ascending address order; Step nine: sequentially perform read operation on all storage units in address arbitrary sequence; Step ten: set the storage units of the memory under test to a third data background I2 by address arbitrary sequence write operation; Step eleven: sequentially perform read, read, jump write, non-jump write, read, read, jump write, non-jump write operation on all storage units in ascending address order; Step twelve: sequentially perform read operation on all storage units in address arbitrary sequence; Step thirteen: set the storage units of the memory under test to a data background I3 by address arbitrary sequence write operation; Step fourteen: sequentially perform read, read, jump write, non-jump write, read, read, jump write, non-jump write operation on all storage units in ascending address order; Step fifteen: sequentially perform read operation on all storage units in address arbitrary sequence; Step sixteen: set the storage units of the memory under test to a data background I4 by address arbitrary sequence write operation; Step seventeen: sequentially perform read, read, jump write, non-jump write, read, read, jump write, non-jump write operation on all storage units in ascending address order; Step eighteen: sequentially perform read operation on all storage units in address arbitrary sequence.

2. A memory triple-cell coupling fault detection terminal device, comprising: The computer program is executed by the processor to implement the steps of the method of claim 1.

3. A computer readable storage medium storing a computer program, characterized in that: The computer program is executed by the processor to implement the steps of the method of claim 1.

Images