DRAM testing methods, apparatus, computer-readable storage media and electronic devices

Abstract

This invention discloses a DRAM testing method, apparatus, computer-readable storage medium, and electronic device. The method involves performing two rounds of testing on the DRAM under test. Preset test data and its inverse are alternately written to the storage array. Based on the written data, each first preset read / write unit is traversed twice, using preset operation units as units. For each target preset operation unit encountered, adjacent preset operation units are determined. Based on the preset test data, data read / write operations are performed on the target preset operation unit and adjacent preset operation units in a preset order. The read data is compared with the corresponding written data. The final test result is obtained through the comparison results of the two rounds of testing. This method achieves proximity access to a chessboard background, covers previous test blind spots, and detects chip defects that are difficult to detect in existing technologies, improving fault coverage, enhancing the reliability of test results, and thus improving product quality.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of DRAM chip testing, and in particular to a DRAM testing method and device, a computer readable storage medium and an electronic device. BACKGROUND

[0002] Dynamic Random Access Memory (DRAM) is an indispensable component of modern computer systems, and can be applied to Double Data Rate (DDR) modules for personal computers or servers and Low Power Double Data Rate (LPDDR) chips for embedded ARM architecture.

[0003] The basic storage unit of LPDDR is a cell, and computers and embedded systems store and read / write data by writing high or low levels in the cell.

[0004] In addition, current DRAMs use burst read / write mode for efficient access rate, that is, read / write operations in a storage array are performed in units of burst length (BL), and a plurality of bit (such as 8 bits, 16 bits or 32 bits) column addresses are read / written at a time, and data composed of 0 and 1 is accessed in each burst length. For example, the address is 0 row, and the burst length is 8 bits, so 1 bit of data is written to each bit in the space from 0 row 0 column to 0 row 7 column, a total of 8 bits, the second burst length is from 0 row 8 column to 15 column, and so on. When the storage positions of a row are all written, the Memory Controller (MC) positions the address of the next row and continues the same operation.

[0005] Different access modes will have a certain impact on the state of the storage unit. Generally, ICs (Integrated Circuit) access in sequence, but in the memory failure model, some faults are more likely to be triggered using non-continuous access, such as coupling faults (CF). Therefore, for the case of sequential access, some fault types cannot be covered. SUMMARY

[0006] The technical problem to be solved by the present application is to provide a DRAM testing method, device, computer readable storage medium and electronic device, which can improve the fault coverage rate when testing DRAM.

[0007] To solve the above technical problems, one technical solution adopted by the present application is:

[0008] A DRAM testing method, comprising the steps of:

[0009] performing two rounds of testing on the DRAM to be tested to obtain a first comparison result and a second comparison result respectively;

[0010] The testing comprises:

[0011] alternately writing preset test data and the inverse of the preset test data into the memory array of the DRAM to be tested in units of preset operation units until all memory cells of the DRAM to be tested are written with data;

[0012] The data written by any preset operation unit is different from the data written by an adjacent preset operation unit adjacent to the preset operation unit;

[0013] based on the written data, performing two traversals on each first preset read-write unit of the DRAM to be tested in units of the preset operation units until all memory cells of the DRAM to be tested are traversed;

[0014] for a target preset operation unit that is traversed, determining an adjacent preset operation unit adjacent to the target preset operation unit, performing data read-write operations on the target preset operation unit and the adjacent preset operation unit in a preset order based on the preset test data, and comparing the read data with the corresponding written data;

[0015] The preset test data of the first round of testing is the inverse of the preset test data of the second round of testing;

[0016] obtaining a testing result of the DRAM to be tested according to the first comparison result and the second comparison result.

[0017] To solve the above technical problems, another technical solution adopted by the present application is:

[0018] A DRAM testing device, comprising:

[0019] a data read-write module configured to perform two rounds of testing on the DRAM to be tested to obtain a first comparison result and a second comparison result respectively;

[0020] The testing comprises:

[0021] alternately writing preset test data and the inverse of the preset test data into the memory array of the DRAM to be tested in units of preset operation units until all memory cells of the DRAM to be tested are written with data;

[0022] The data written by any preset operation unit is different from the data written by an adjacent preset operation unit adjacent to the preset operation unit;

[0023] based on the written data, each first preset read-write unit of the DRAM to be tested is traversed twice in units of the preset operation unit until all memory units of the DRAM to be tested are traversed;

[0024] For the target preset operation unit traversed, an adjacent preset operation unit adjacent to the target preset operation unit is determined, data read-write operations are performed on the target preset operation unit and the adjacent preset operation unit in a preset order based on the preset test data, and the read data is compared with the corresponding written data;

[0025] The preset test data of the first round of testing is the inverse of the preset test data of the second round of testing;

[0026] The test module is configured to obtain a test result of the DRAM to be tested according to the first comparison result and the second comparison result.

[0027] To solve the above technical problems, another technical solution adopted by the present application is:

[0028] A computer readable storage medium has a computer program stored thereon, and the computer program is executed by a processor to implement each step of the DRAM test method.

[0029] To solve the above technical problems, another technical solution adopted by the present application is:

[0030] An electronic device includes a memory, a processor, and a computer program stored on the memory and executable on the processor, and the processor executes the computer program to implement each step of the DRAM test method.

[0031] The present application has the following advantages:

[0032] By performing two rounds of testing on the DRAM to be tested, the final test result is obtained through the comparison result of the two rounds of testing, and since part of the fault uses non-continuous access, it is easier to trigger. In units of the preset operation unit, the preset test data and the inverse of the preset test data are alternately written into the memory array of the DRAM to be tested, each first preset read-write unit of the DRAM to be tested is traversed twice in units of the preset operation unit based on the written data, which can simulate a non-continuous access mode with a certain interval. For the target preset operation unit traversed, data read-write operations are performed on the target preset operation unit and the adjacent preset operation unit in a preset order based on the preset test data, which realizes the chessboard background adjacent access, covers the previous test blind area and detects the chip defects that are difficult to be found in the prior art, improves the fault coverage, enhances the reliability of the test result, and improves the product benignity. BRIEF DESCRIPTION OF DRAWINGS

[0033] Figure 1 A flow chart of a DRAM testing method according to an embodiment of the present application;

[0034] Figure 2 A structural diagram of a DRAM testing device according to an embodiment of the present application;

[0035] Figure 3 A structural diagram of an electronic device according to an embodiment of the present application;

[0036] Figure 4 A diagram of preset testing data and preset testing data inverse according to a DRAM testing method of an embodiment of the present application;

[0037] Figure 5 A flow chart of a DRAM testing method according to an embodiment of the present application;

[0038] Figure 6 (a) A diagram of first round testing background data according to a DRAM testing method of an embodiment of the present application;

[0039] Figure 6 (b) A diagram of second round testing background data according to a DRAM testing method of an embodiment of the present application;

[0040] Figure 7 (a) A diagram of first preset sequence according to a DRAM testing method of an embodiment of the present application;

[0041] Figure 7 (b) A diagram of second preset sequence according to a DRAM testing method of an embodiment of the present application;

[0042] Figure 7 (c) A diagram of third preset sequence according to a DRAM testing method of an embodiment of the present application;

[0043] Figure 7 (d) A diagram of fourth preset sequence according to a DRAM testing method of an embodiment of the present application;

[0044] Figure 8 A diagram of data reading operation according to a first preset sequence according to a DRAM testing method of an embodiment of the present application;

[0045] Figure 9 A diagram of first time traversal according to a DRAM testing method of an embodiment of the present application;

[0046] Figure 10 A diagram of second time traversal according to a DRAM testing method of an embodiment of the present application. DETAILED DESCRIPTION

[0047] To make the technical contents of the present application, the purposes and effects achieved more clear, the following will be described in detail in conjunction with the embodiments and the accompanying drawings.

[0048] Please refer to Figure 1 The embodiment of the present application provides a DRAM test method, comprising the steps of:

[0049] Two rounds of tests are performed on the DRAM to be tested, and first and second comparison results are obtained respectively;

[0050] The test comprises:

[0051] The memory array of the DRAM to be tested is alternately written with preset test data and the inverse of the preset test data in units of preset operation units until all the memory units of the DRAM to be tested are written with data;

[0052] The data written in any preset operation unit is different from the data written in the adjacent preset operation unit adjacent to it;

[0053] Each first preset read-write unit of the DRAM to be tested is traversed twice based on the written data in units of the preset operation units until all the memory units of the DRAM to be tested are traversed;

[0054] For a target preset operation unit traversed, a neighboring preset operation unit adjacent to it is determined, and data read-write operations are performed on the target preset operation unit and the neighboring preset operation unit in a preset order based on the preset test data, and the read data is compared with the corresponding written data;

[0055] The preset test data of the first round of test is the inverse of the preset test data of the second round of test;

[0056] The test result of the DRAM to be tested is obtained according to the first and second comparison results.

[0057] From the above description, the beneficial effects of the present application are that: by performing two rounds of testing on the DRAM to be tested, the final test result is obtained by comparing the results of the two rounds of testing, and since partial faults are more likely to be triggered using non-continuous access, the storage array of the DRAM to be tested is alternately written with preset test data and the inverse of the preset test data in units of preset operation units, each first preset read-write unit of the DRAM to be tested is traversed twice based on the written data in units of preset operation units, which can simulate a non-continuous access mode with a certain interval, for the target preset operation unit traversed, data read-write operations are performed on the target preset operation unit and the adjacent preset operation unit based on the preset test data in a preset order, which realizes chessboard background adjacent access, covers the previous test blind area and detects chip defects that are difficult to be found in the prior art, improves fault coverage, enhances the reliability of the test result, and thus improves product goodness.

[0058] Further, the alternately writing the preset test data and the inverse of the preset test data into the storage array of the DRAM to be tested in units of preset operation units until all storage units of the DRAM to be tested are written with data comprises:

[0059] Alternately writing the preset test data and the inverse of the preset test data into each second preset read-write unit of the storage array of the DRAM to be tested in units of preset operation units starting from the low address of the second preset read-write unit according to a preset burst length until all storage units of the DRAM to be tested are written with data.

[0060] From the above description, alternately writing the preset test data and the inverse of the preset test data into the storage array of the DRAM to be tested in units of preset operation units realizes a chessboard data background, that is, the data of any two adjacent preset operation units is different, which can cause a potential difference between the storage unit and the surrounding unit, and if the storage unit has a defect, the written data will change, making it easier to trigger partial faults in subsequent testing. Moreover, writing data into the DRAM to be tested according to the burst length can improve the data writing speed and has low time complexity, and is suitable for mass production testing.

[0061] Further, the alternately writing the preset test data and the inverse of the preset test data into the storage array of the DRAM to be tested in units of preset operation units until all storage units of the DRAM to be tested are written with data comprises:

[0062] the first preset operation unit of all the written data being the preset test data in each first preset read-write unit of the DRAM to be tested is traversed for the first time until all the first preset operation units of all the written data being the preset test data in the DRAM to be tested are traversed;

[0063] the second preset operation unit of all the written data being the inverse of the preset test data in each first preset read-write unit of the DRAM to be tested is traversed for the second time until all the second preset operation units of all the written data being the inverse of the preset test data in the DRAM to be tested are traversed.

[0064] From the above description, the first preset operation unit of all the written data being the preset test data is traversed for the first time, and the second preset operation unit of all the written data being the inverse of the preset test data is traversed for the second time, which simulates non-continuous access with a certain interval, can cover the previous test blind area and detect the chip defects that are difficult to be found in the prior art, can stimulate the multi-storage unit fault, and thus improves the fault coverage.

[0065] Further, for all the first preset operation units in each first preset read-write unit in the first traversal, the preset sequence corresponding thereto is alternately changed;

[0066] For all the second preset operation units in each first preset read-write unit in the second traversal, the preset sequence corresponding thereto is alternately changed.

[0067] Further, for the target preset operation unit traversed, the adjacent preset operation unit adjacent thereto is determined, data read-write operation is performed on the target preset operation unit and the adjacent preset operation unit based on the preset test data in the preset sequence, and the read data is compared with the corresponding written data, which includes:

[0068] For the first target preset operation unit traversed in the first traversal, the first adjacent preset operation unit adjacent thereto is determined, it is judged whether the sequence number of the first target preset operation unit in all the first preset operation units of the first preset read-write unit corresponding thereto is odd, if yes, the preset test data is written into the first adjacent preset operation unit in the first preset sequence, the data of the first target preset operation unit is read every time the preset test data is written, the read data is compared with the corresponding written data, and the inverse of the preset test data is written into the first adjacent preset operation unit currently writing the preset test data every time the inverse of the preset test data is written, the data of the first target preset operation unit is read every time the inverse of the preset test data is written, and the read data is compared with the corresponding written data;

[0069] If no, write the preset test data to the first adjacent preset operation unit according to the second preset order, read the data of the first target preset operation unit after writing the preset test data each time, compare the read data with the corresponding written data, and then write the inverse of the preset test data to the first adjacent preset operation unit currently writing the preset test data each time, read the data of the first target preset operation unit after writing the inverse of the preset test data each time, compare the read data with the corresponding written data.

[0070] For the second target preset operation unit traversed in the second traversal, determine the second adjacent preset operation unit adjacent thereto, and determine whether the serial number of the second target preset operation unit in all second preset operation units corresponding to the first preset read-write unit is even. If yes, write the inverse of the preset test data to the second adjacent preset operation unit according to the third preset order each time, read the data of the second target preset operation unit after writing the inverse of the preset test data each time, compare the read data with the corresponding written data, and then write the preset test data to the second adjacent preset operation unit currently writing the inverse of the preset test data each time, read the data of the second target preset operation unit after writing the preset test data each time, and compare the read data with the corresponding written data.

[0071] If no, write the inverse of the preset test data to the second adjacent preset operation unit according to the fourth preset order each time, read the data of the second target preset operation unit after writing the inverse of the preset test data each time, compare the read data with the corresponding written data, and then write the preset test data to the second adjacent preset operation unit currently writing the inverse of the preset test data each time, read the data of the second target preset operation unit after writing the preset test data each time, and compare the read data with the corresponding written data.

[0072] As can be seen from the above description, because there are adjacent memory cells in the memory cell, different access sequences have different possibilities of activating memory cell transition faults, for example, accessing along the s direction and then accessing along the e direction can activate the fault, but accessing along the s direction and then accessing along the w direction can not activate the fault, therefore, the data read and write operation is performed on the first preset operation unit or the second preset operation unit in different sequences, the memory cell transition fault is triggered, and because the read operation absorbs the charge and then charges, and the write operation only charges, the data is written into the adjacent preset operation unit and read from the target preset operation unit, and then the data is written into the adjacent preset operation unit and read from the target preset operation unit, the action of absorbing the charge of the read operation can cause the value stored in the relatively weak memory cell to jump, and the fault coverage is improved.

[0073] Further, the first preset read-write unit includes a row or a column.

[0074] As can be seen from the above description, the test personnel can set the first preset read-write unit as a row or a column according to needs, and the flexibility is high.

[0075] Further, the test result of the DRAM to be tested according to the first comparison result and the second comparison result includes:

[0076] If the first comparison result and the second comparison result are consistent, the test result is success, otherwise, the test result is failure.

[0077] As can be seen from the above description, the first comparison result and the second comparison result are obtained through two rounds of tests, the chip defects that are difficult to find can be detected, the fault coverage during the test is improved, and the reliability of the test is ensured.

[0078] Please refer to Figure 2 Another embodiment of the present application provides a DRAM test device, comprising:

[0079] A data read-write module is configured to perform two rounds of tests on the DRAM to be tested, and obtain a first comparison result and a second comparison result, respectively.

[0080] The test includes:

[0081] The preset test data and the inverse of the preset test data are alternately written into the memory array of the DRAM to be tested in units of preset operation units until all the memory cells of the DRAM to be tested are written with data.

[0082] The data written by any preset operation unit is different from the data written by the adjacent preset operation unit adjacent to the preset operation unit.

[0083] The data based on the writing is written into each first preset read-write unit of the DRAM to be tested in units of the preset operation unit twice until all the memory units of the DRAM to be tested are traversed.

[0084] For the target preset operation unit traversed, an adjacent preset operation unit adjacent to the target preset operation unit is determined, data read-write operations are performed on the target preset operation unit and the adjacent preset operation unit in a preset order based on the preset test data, and the read data is compared with the corresponding written data.

[0085] The preset test data of the first round of testing is the inverse of the preset test data of the second round of testing.

[0086] The test module is configured to obtain a test result of the DRAM to be tested according to the first comparison result and the second comparison result.

[0087] Another embodiment of the present application provides a computer readable storage medium having a computer program stored thereon, and the computer program is executed by a processor to implement each step of the DRAM test method.

[0088] Please refer to Figure 3 Another embodiment of the present application provides an electronic device including a memory, a processor, and a computer program stored in the memory and executable on the processor, and the processor implements each step of the DRAM test method when executing the computer program.

[0089] The above-mentioned DRAM test method, device, computer readable storage medium and electronic device can be applied to the test of any type of DRAM, such as each generation of DDR and LPDDR products, and the following will be described through a specific embodiment:

[0090] Embodiment one

[0091] Please refer to Figure 1 The DRAM test method of the embodiment includes the following steps:

[0092] S1, two rounds of testing are performed on the DRAM to be tested to obtain a first comparison result and a second comparison result, respectively.

[0093] The test includes:

[0094] S11, preset test data and the inverse of the preset test data are alternately written into the memory array of the DRAM to be tested in units of a preset operation unit until all the memory units of the DRAM to be tested are written with data.

[0095] Specifically, a low address of each second preset read-write unit of a storage array of the DRAM to be tested is alternately written with preset test data and a negative of the preset test data in a preset operation unit according to a preset burst length, until all storage units of the DRAM to be tested are written with data.

[0096] The second preset read-write unit can be flexibly set according to actual needs, for example, can be set as a column or a row.

[0097] The burst length (BL) is determined by the JEDEC standard, and can also be freely set, that is, a plurality of bits (such as 8 bits or 16 bits) are operated at a time to perform corresponding reading and writing. For example, when writing data based on a row, if the addressed address is 0 row and the burst length is 8 bits, the first 8 bits of the data to be written are written at the same time at the position of 0 row and 0 column, then the second burst length writes 9-16 bits of the data to be written, and the writing is continuously performed until the storage position of 0 row is completely written. Then, the address of the next row is repositioned, and the operation of the previous row is continued until the data is completely written. The reading operation is similar.

[0098] In this embodiment, the second preset read-write unit is a row.

[0099] The data written in any preset operation unit is different from the data written in an adjacent preset operation unit adjacent thereto.

[0100] For example, there are 10 rows and 10 columns in the storage array. The preset test data is written to the first preset operation unit from the first column of the first row, the negative of the preset test data is written to the second preset operation unit, the preset test data is written to the third preset operation unit, and so on. After writing the first row, the negative of the preset test data is written to the first preset operation unit from the first column of the second row, the preset test data is written to the second preset operation unit, the negative of the preset test data is written to the third preset operation unit, and so on, until each row of the DRAM to be tested is written with data.

[0101] S12, based on the data written, each first preset read-write unit of the DRAM to be tested is traversed twice in the preset operation unit until all storage units of the DRAM to be tested are traversed.

[0102] Specifically, all the data written in each first preset read-write unit of the DRAM to be tested is traversed for the first time in the first preset operation unit of the preset test data until all the data written in the DRAM to be tested is traversed in the first preset operation unit of the preset test data.

[0103] a second preset operation unit of all the written data of the DRAM to be tested being the inverse of the preset test data is performed until all the written data of the DRAM to be tested being the inverse of the preset test data is traversed;

[0104] The first preset read-write unit includes a row or a column. In this embodiment, the first preset read-write unit is a row.

[0105] For example, there are 3 rows and 3 columns in the storage array. The first preset operation unit in the first row that writes the preset test data is the preset operation unit in the first row and the first column and the preset operation unit in the first row and the third column. The second preset operation unit that writes the inverse of the preset test data is the preset operation unit in the first row and the second column. The first preset operation unit in the second row that writes the preset test data is the preset operation unit in the second row and the second column. The second preset operation unit that writes the inverse of the preset test data is the preset operation unit in the second row and the first column and the preset operation unit in the second row and the third column. The first preset operation unit in the third row that writes the preset test data is the preset operation unit in the third row and the first column and the preset operation unit in the third row and the third column. The second preset operation unit that writes the inverse of the preset test data is the preset operation unit in the third row and the second column.

[0106] The first preset operation unit in the first row and the first column, the first preset operation unit in the first row and the third column, the first preset operation unit in the second row and the second column, the first preset operation unit in the third row and the first column, and the first preset operation unit in the third row and the third column are traversed for the first time. The second preset operation unit in the first row and the second column, the second preset operation unit in the second row and the first column, the second preset operation unit in the second row and the third column, and the second preset operation unit in the third row and the second column are traversed for the second time.

[0107] S13, for the target preset operation unit traversed, determining an adjacent preset operation unit adjacent to the target preset operation unit, performing data read-write operation on the target preset operation unit and the adjacent preset operation unit according to a preset order based on the preset test data, and comparing the read data with the corresponding written data.

[0108] After the first round of testing is completed, a second round of testing is performed. The preset test data of the first round of testing is the inverse of the preset test data of the second round of testing.

[0109] S2, obtaining the test result of the DRAM to be tested according to the first comparison result and the second comparison result.

[0110] If the first comparison result and the second comparison result are consistent, the test result is successful. Otherwise, the test result is failed.

[0111] Embodiment Two

[0112] With reference to Figures 4-10 , the embodiment further limits how to perform data read-write operation on the target preset operation unit and the adjacent preset operation unit according to the preset order on the basis of Embodiment One, specifically:

[0113] For all the first preset operation units in each first preset read-write unit in the first traversal, the corresponding preset order is alternately changed, that is, all the first preset operation units in each first preset read-write unit in the first traversal are alternately changed to be accessed according to the first preset order and the second preset order;

[0114] For all the second preset operation units in each first preset read-write unit in the second traversal, the corresponding preset order is alternately changed, that is, all the second preset operation units in each first preset read-write unit in the second traversal are alternately changed to be accessed according to the third preset order and the fourth preset order;

[0115] Then, for the first target preset operation unit traversed in the first traversal, the first adjacent preset operation unit adjacent to the first target preset operation unit is determined, and it is judged whether the serial number of the first target preset operation unit in all the first preset operation units of the first preset read-write unit corresponding to the first target preset operation unit is odd or not. If yes, the preset test data is written into the first adjacent preset operation unit according to the first preset order, the data of the first target preset operation unit is read every time the preset test data is written, the read data is compared with the corresponding written data, and the inverse of the preset test data is written into the first adjacent preset operation unit currently writing the preset test data every time the inverse of the preset test data is written, the data of the first target preset operation unit is read every time the inverse of the preset test data is written, and the read data is compared with the corresponding written data;

[0116] If no, the preset test data is written into the first adjacent preset operation unit according to the second preset order, the data of the first target preset operation unit is read every time the preset test data is written, the read data is compared with the corresponding written data, and the inverse of the preset test data is written into the first adjacent preset operation unit currently writing the preset test data every time the inverse of the preset test data is written, the data of the first target preset operation unit is read every time the inverse of the preset test data is written, and the read data is compared with the corresponding written data;

[0117] The first preset sequence is that, taking a target preset operation unit as a center, first, adjacent preset operation units above the target preset operation unit are accessed, then, adjacent preset operation units below the target preset operation unit are accessed, next, adjacent preset operation units left of the target preset operation unit are accessed, and finally, adjacent preset operation units right of the target preset operation unit are accessed.

[0118] The second preset sequence is that, taking a target preset operation unit as a center, first, adjacent preset operation units below the target preset operation unit are accessed, then, adjacent preset operation units above the target preset operation unit are accessed, next, adjacent preset operation units right of the target preset operation unit are accessed, and finally, adjacent preset operation units left of the target preset operation unit are accessed.

[0119] If there is no adjacent preset operation unit in any direction, the access of the adjacent preset operation unit corresponding to the direction is omitted.

[0120] For example, a storage array has 10 rows and 10 columns, and it is assumed that the first target preset operation unit accessed in the first traversal is a preset operation unit in the second row and the second column, and the first adjacent preset operation units adjacent to the preset operation unit are four preset operation units in the first row and the second column, the second row and the first column, the second row and the third column, and the third row and the second column. Since the preset operation unit in the second row and the second column has a sequence number of 1 in all the first preset operation units in the second row, preset test data is first written to the preset operation unit in the first row and the second column according to the first preset sequence, data of the preset operation unit in the second row and the second column is read, the read data is compared with the corresponding written data, the inverse of the preset test data is written to the preset operation unit in the first row and the second column, and data of the preset operation unit in the second row and the second column is read, the read data is compared with the corresponding written data.

[0121] Preset test data is further written to the preset operation unit in the third row and the second column, data of the preset operation unit in the second row and the second column is read, the read data is compared with the corresponding written data, the inverse of the preset test data is written to the preset operation unit in the third row and the second column, and data of the preset operation unit in the second row and the second column is read, the read data is compared with the corresponding written data.

[0122] Next, preset test data is written to the preset operation unit in the second row and the first column, data of the preset operation unit in the second row and the second column is read, the read data is compared with the corresponding written data, the inverse of the preset test data is written to the preset operation unit in the second row and the first column, and data of the preset operation unit in the second row and the second column is read, the read data is compared with the corresponding written data.

[0123] Finally, preset test data is written to the preset operation unit in the 2nd row and the 3rd column, data of the preset operation unit in the 2nd row and the 2nd column is read, the read data is compared with the corresponding written data, the inverse of the preset test data is written to the preset operation unit in the 2nd row and the 3rd column, and data of the preset operation unit in the 2nd row and the 2nd column is read, the read data is compared with the corresponding written data;

[0124] Suppose the first target preset operation unit traversed in the first traversal is the preset operation unit in the 2nd row and the 4th column, first adjacent preset operation units adjacent to the preset operation unit in the 2nd row and the 4th column are four preset operation units in the 1st row and the 4th column, the 2nd row and the 3rd column, the 2nd row and the 5th column, and the 3rd row and the 4th column, since the preset operation unit in the 2nd row and the 4th column has a serial number of 2 among all the first preset operation units in the second row, preset test data is first written to the preset operation unit in the 3rd row and the 4th column according to the second preset sequence, data of the preset operation unit in the 2nd row and the 4th column is read, the read data is compared with the corresponding written data, the inverse of the preset test data is written to the preset operation unit in the 3rd row and the 4th column, and data of the preset operation unit in the 2nd row and the 4th column is read, the read data is compared with the corresponding written data;

[0125] Preset test data is further written to the preset operation unit in the 1st row and the 4th column, data of the preset operation unit in the 2nd row and the 4th column is read, the read data is compared with the corresponding written data, the inverse of the preset test data is written to the preset operation unit in the 1st row and the 4th column, and data of the preset operation unit in the 2nd row and the 4th column is read, the read data is compared with the corresponding written data;

[0126] Preset test data is then written to the preset operation unit in the 2nd row and the 5th column, data of the preset operation unit in the 2nd row and the 4th column is read, the read data is compared with the corresponding written data, the inverse of the preset test data is written to the preset operation unit in the 2nd row and the 5th column, and data of the preset operation unit in the 2nd row and the 4th column is read, the read data is compared with the corresponding written data;

[0127] Finally, preset test data is written to the preset operation unit in the 2nd row and the 3rd column, data of the preset operation unit in the 2nd row and the 4th column is read, the read data is compared with the corresponding written data, the inverse of the preset test data is written to the preset operation unit in the 2nd row and the 3rd column, and data of the preset operation unit in the 2nd row and the 4th column is read, the read data is compared with the corresponding written data;

[0128] Suppose the first target preset operation unit traversed in the first traversal is the preset operation unit in the first row and the first column, and the first adjacent preset operation units adjacent to the first target preset operation unit are the preset operation units in the first row and the second column and the second row and the first column. Since the preset operation unit in the first row and the first column has a serial number of 1 in all the first preset operation units in the first row, preset test data is first written to the preset operation unit in the second row and the first column according to the first preset order, data of the preset operation unit in the first row and the first column is read, the read data is compared with the corresponding written data, the inverse of the preset test data is written to the preset operation unit in the second row and the first column, data of the preset operation unit in the first row and the first column is read, and the read data is compared with the corresponding written data.

[0129] The preset test data is further written to the preset operation unit in the first row and the second column, data of the preset operation unit in the first row and the first column is read, the read data is compared with the corresponding written data, the inverse of the preset test data is written to the preset operation unit in the first row and the second column, data of the preset operation unit in the first row and the first column is read, and the read data is compared with the corresponding written data.

[0130] For the second target preset operation unit traversed in the second traversal, the second adjacent preset operation units adjacent to the second target preset operation unit are determined, it is judged whether the second target preset operation unit has an even serial number in all the second preset operation units in the first preset read-write unit corresponding to the second target preset operation unit. If yes, the inverse of the preset test data is written to the second adjacent preset operation unit according to the third preset order, data of the second target preset operation unit is read every time the inverse of the preset test data is written, the read data is compared with the corresponding written data, the preset test data is further written to the second adjacent preset operation unit currently writing the inverse of the preset test data, data of the second target preset operation unit is read every time the preset test data is written, and the read data is compared with the corresponding written data.

[0131] If no, the inverse of the preset test data is written to the second adjacent preset operation unit according to the fourth preset order, data of the second target preset operation unit is read every time the inverse of the preset test data is written, the read data is compared with the corresponding written data, the preset test data is further written to the second adjacent preset operation unit currently writing the inverse of the preset test data, data of the second target preset operation unit is read every time the preset test data is written, and the read data is compared with the corresponding written data.

[0132] The third preset sequence is that, taking a target preset operation unit as the center, first accessing a neighboring preset operation unit on the right side of the target preset operation unit, then accessing a neighboring preset operation unit on the left side of the target preset operation unit, next accessing a neighboring preset operation unit below the target preset operation unit, and finally accessing a neighboring preset operation unit above the target preset operation unit.

[0133] The fourth preset sequence is that, taking a target preset operation unit as the center, first accessing a neighboring preset operation unit on the left side of the target preset operation unit, then accessing a neighboring preset operation unit on the right side of the target preset operation unit, next accessing a neighboring preset operation unit above the target preset operation unit, and finally accessing a neighboring preset operation unit below the target preset operation unit.

[0134] For example, the storage array has 10 rows and 10 columns, and it is assumed that the second target preset operation unit in the second traversal is the preset operation unit in the second row and the third column, and the second neighboring preset operation units adjacent to the second target preset operation unit are the preset operation units in the first row and the third column, the second row and the second column, the second row and the fourth column, and the third row and the third column. Since the preset operation unit in the second row and the third column has a sequence number of 2 in all the second preset operation units in the second row, according to the third preset sequence, preset test data is first written to the preset operation unit in the second row and the fourth column, data of the preset operation unit in the second row and the third column is read, the read data is compared with the corresponding written data, the preset test data is written to the preset operation unit in the second row and the fourth column in inverse, data of the preset operation unit in the second row and the third column is read, and the read data is compared with the corresponding written data.

[0135] Next, preset test data is written to the preset operation unit in the second row and the second column, data of the preset operation unit in the second row and the third column is read, the read data is compared with the corresponding written data, the preset test data is written to the preset operation unit in the second row and the second column in inverse, data of the preset operation unit in the second row and the third column is read, and the read data is compared with the corresponding written data.

[0136] Then, preset test data is written to the preset operation unit in the third row and the third column, data of the preset operation unit in the second row and the third column is read, the read data is compared with the corresponding written data, the preset test data is written to the preset operation unit in the third row and the third column in inverse, data of the preset operation unit in the second row and the third column is read, and the read data is compared with the corresponding written data.

[0137] Finally, write the preset test data to the preset operation unit in the first row and third column, and read the data from the preset operation unit in the second row and third column. Compare the read data with the corresponding written data. Write the inverse of the preset test data to the preset operation unit in the first row and third column, and read the data from the preset operation unit in the second row and third column. Compare the read data with the corresponding written data.

[0138] Assuming the second target preset operation unit encountered in the second traversal is the preset operation unit in the 2nd row and 1st column, then the two adjacent second preset operation units are the three preset operation units in the 1st row and 1st column, the 2nd row and 2nd column, and the 3rd row and 1st column. Since the preset operation unit in the 2nd row and 1st column has the same index as all the second preset operation units in the 2nd row, the preset test data is written to the preset operation unit in the 2nd row and 2nd column according to the fourth preset order, and the data in the preset operation unit in the 2nd row and 1st column is read. The read data is compared with the corresponding written data. The inverse of the preset test data is written to the preset operation unit in the 2nd row and 2nd column, and the data in the preset operation unit in the 2nd row and 1st column is read. The read data is compared with the corresponding written data.

[0139] Then write the preset test data to the preset operation unit in the first row and first column, and read the data in the preset operation unit in the second row and first column. Compare the read data with the corresponding written data. Write the inverse of the preset test data to the preset operation unit in the first row and first column, and read the data in the preset operation unit in the second row and first column. Compare the read data with the corresponding written data.

[0140] Next, write the preset test data to the preset operation unit in the 3rd row and 1st column, and read the data from the preset operation unit in the 2nd row and 1st column. Compare the read data with the corresponding written data. Write the inverse of the preset test data to the preset operation unit in the 3rd row and 1st column, and read the data from the preset operation unit in the 2nd row and 1st column. Compare the read data with the corresponding written data.

[0141] The following is a specific implementation method to illustrate how to test DRAM:

[0142] First, such as Figure 5 As shown, the first round of testing is performed on the DRAM under test:

[0143] like Figure 4 As shown, the test data to be written is defined as D = 01010101……0101, and its inverse is / D = 10101010……1010. Assuming the preset burst length is BL = 8 bits, then D = 01010101, / D = 10101010.

[0144] S1, the positioned address is the 0th row and the 0th column, and the preset operation units corresponding to the 0th row and the 0th column start to alternately write test data D and / D from the 0th row and the 0th column, and after the 0th row is written, test data D and / D are alternately written from the 1st row and the 0th column, and so on, until the entire storage array is written with data, as shown in Figure 6 (a);

[0145] S2, a first preset operation unit with written data D in each row of the DRAM to be tested is traversed for the first time from the 0th row and the 0th column until all the first preset operation units with written data D in the DRAM to be tested are traversed, as shown in Figure 6 (a);

[0146] S3, for the first target preset operation unit A(R1, C1) traversed, the first adjacent preset operation units adjacent to A are determined, which are B(R0, C1), B(R1, C0), B(R1, C2), and B(R2, C1), as shown in Figure 6 (a);

[0147] If there is no first adjacent preset operation unit in any direction of A, the access of the first adjacent preset operation unit corresponding to the direction is omitted, for example, the first target preset operation unit is A(R0, C2), and the first adjacent preset operation units adjacent to A(R0, C2) are B(R0, C1), B(R1, C2), and B(R0, C3), as long as the three preset operation units B(R0, C1), B(R1, C2), and B(R0, C3) are accessed.

[0148] S4, as shown in Figure 7 (a), Figure 9 Since the serial number of A(R1, C1) in all the first preset operation units in the 1st row is 1, D is first written to B(R0, C1) according to the first preset order, the data of A(R1, C1) is read, the read data is compared with D, / D is written to B(R0, C1), the data of A(R1, C1) is read, and the read data is compared with D, as shown in Figure 8 (a), (b);

[0149] S5, D is written to B(R2, C1) again, the data of A(R1, C1) is read, the read data is compared with D, / D is written to B(R2, C1), the data of A(R1, C1) is read, and the read data is compared with D, as shown in Figure 8 (c), (d);

[0150] S6, then write D to B(R1, C0), read the data of A(R1, C1), compare the read data with D, write / D to B(R1, C0), read the data of A(R1, C1), compare the read data with D, as shown in Figure 8 (e), (f) shown;

[0151] S7, finally write D to B(R1, C2), read the data of A(R1, C1), compare the read data with D, write / D to B(R1, C2), read the data of A(R1, C1), compare the read data with D, as shown in Figure 8 (g), (h) shown;

[0152] S8, for the first target preset operation unit A(R1, C3) traversed, determine the first adjacent preset operation unit adjacent to A, which are B(R0, C3), B(R1, C2), B(R1, C4), B(R2, C3) respectively;

[0153] S9, as shown in Figure 7 (b), Figure 9 Since the serial number of A(R1, C3) in all first preset operation units in the first row is 2, write D to B(R2, C3) first according to the second preset order, read the data of A(R1, C3), compare the read data with D, write / D to B(R2, C3), read the data of A(R1, C3), compare the read data with D, as shown in

[0154] S10, write D to B(R0, C3) again, read the data of A(R1, C3), compare the read data with D, write / D to B(R0, C3), read the data of A(R1, C3), compare the read data with D;

[0155] S11, then write D to B(R1, C4), read the data of A(R1, C3), compare the read data with D, write / D to B(R1, C4), read the data of A(R1, C3), compare the read data with D;

[0156] S12, finally write D to B(R1, C2), read the data of A(R1, C3), compare the read data with D, write / D to B(R1, C2), read the data of A(R1, C3), compare the read data with D;

[0157] The rest of the first target preset operation unit is as shown above;

[0158] S13. After the first traversal, starting from row 0 and column 0, perform a second traversal on all second preset operation units in each row of the DRAM under test where the written data is / D, until all second preset operation units where the written data is / D in the DRAM under test have been traversed. Figure 6 As shown in (a);

[0159] S14, such as Figure 10 As shown, for the second target preset operation unit B(R1, C2) that has been traversed, the second adjacent preset operation units adjacent to B are determined as A(R1, C3), A(R1, C1), A(R0, C2), and A(R2, C2).

[0160] If there is no second adjacent preset operation unit in any direction of B, the access to the second adjacent preset operation unit corresponding to that direction is omitted. For example, if the second target preset operation unit is B(R0, C1), then the second adjacent preset operation units adjacent to B(R0, C1) are A(R0, C0), A(R1, C1), and A(R0, C2). Only the three preset operation units A(R0, C0), A(R1, C1), and A(R0, C2) need to be accessed.

[0161] S15, such as Figure 7 As shown in (c), since the sequence number of B(R1, C2) in all the second preset operation units in the first row is 2, the third preset order is followed to write / D to A(R1, C3) first, and read the data of B(R1, C2), compare the read data with / D, write D to A(R1, C3), and read the data of B(R1, C2), compare the read data with / D;

[0162] S16. Write / D to A(R1,C1) and read the data from B(R1,C2). Compare the read data with / D. Write D to A(R1,C1) and read the data from B(R1,C2). Compare the read data with / D.

[0163] S17. Next, write / D to A(R2, C2) and read the data from B(R1, C2). Compare the read data with / D. Write D to A(R2, C2) and read the data from B(R1, C2). Compare the read data with / D.

[0164] S18. Finally, write / D to A(R0, C2) and read the data from B(R1, C2). Compare the read data with / D, write D to A(R0, C2), and read the data from B(R1, C2). Compare the read data with / D.

[0165] S17、as shown in Figure 10 For the second target preset operation unit B (R1, C4) traversed, the second adjacent preset operation units adjacent to B are A (R1, C3), A (R1, C5), A (R0, C4), and A (R2, C4) respectively;

[0166] S18、as shown in Figure 7 (d), since B (R1, C4) is the third in the first row of all second preset operation units, according to the fourth preset order, / D is written to A (R1, C3) first, and the data of B (R1, C4) is read, the read data is compared with / D, D is written to A (R1, C3), and the data of B (R1, C4) is read, the read data is compared with / D;

[0167] S19, / D is written to A (R1, C5) again, and the data of B (R1, C4) is read, the read data is compared with / D, D is written to A (R1, C5), and the data of B (R1, C4) is read, the read data is compared with / D;

[0168] S20, then / D is written to A (R0, C4), and the data of B (R1, C4) is read, the read data is compared with / D, D is written to A (R0, C4), and the data of B (R1, C4) is read, the read data is compared with / D;

[0169] S21, finally / D is written to A (R2, C4), and the data of B (R1, C4) is read, the read data is compared with / D, D is written to A (R2, C4), and the data of B (R1, C4) is read, the read data is compared with / D;

[0170] The rest of the second target preset operation units are as shown above;

[0171] After the second traversal is completed, the first comparison result is obtained;

[0172] S22、as shown in Figure 6 (b), in the second round of testing, the test data / D written is defined as 01010101, and its complement D is 10101010, the above steps are performed to obtain the second comparison result;

[0173] If the first comparison result and the second comparison result are both consistent comparison results, the test result is successful; otherwise, the test result is failed.

[0174] Example three

[0175] Please refer to Figure 2 A DRAM test device, comprising:

[0176] a data read-write module, configured to perform two rounds of testing on the DRAM to be tested to obtain a first comparison result and a second comparison result respectively;

[0177] The testing comprises:

[0178] alternately writing preset test data and the inverse of the preset test data into the memory array of the DRAM to be tested in units of preset operation units until all memory cells of the DRAM to be tested are written with data;

[0179] The data written in any preset operation unit is different from the data written in an adjacent preset operation unit adjacent to the preset operation unit;

[0180] based on the written data, performing twice traversal on each first preset read-write unit of the DRAM to be tested in units of the preset operation units until all memory cells of the DRAM to be tested are traversed;

[0181] for a target preset operation unit that is traversed, determining an adjacent preset operation unit adjacent to the target preset operation unit, performing data read-write operation on the target preset operation unit and the adjacent preset operation unit in a preset order based on the preset test data, and comparing the read data with the corresponding written data;

[0182] the preset test data of the first round of testing is the inverse of the preset test data of the second round of testing;

[0183] a testing module, configured to obtain a test result of the DRAM to be tested according to the first comparison result and the second comparison result.

[0184] Embodiment Four

[0185] A computer readable storage medium having a computer program stored thereon, the computer program being executable by a processor to implement each step of the DRAM testing method in Embodiment One or Embodiment Two.

[0186] Embodiment Five

[0187] Please refer to Figure 3 An electronic device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, the processor implementing each step of the DRAM testing method in Embodiment One or Embodiment Two when executing the computer program.

[0188] In conclusion, the DRAM detection method, device, computer readable storage medium and electronic equipment provided by the application can improve the data writing speed and reduce the time complexity, and the method is convenient for mass production testing. The first preset operation unit in each first preset read-write unit of the DRAM to be tested is traversed for the first time, and the second preset operation unit in which all the written data is the inverse of the preset test data is traversed for the second time, so that the non-continuous access with a certain interval is simulated. For the first target preset operation unit traversed in the first traversal, the data read-write operation is performed on the first target preset operation unit and the first adjacent preset operation unit according to the first preset sequence and the second preset sequence based on the preset test data. For the second target preset operation unit traversed in the second traversal, the data read-write operation is performed on the second target preset operation unit and the second adjacent preset operation unit according to the third preset sequence and the fourth preset sequence based on the preset test data. The storage unit jump fault can be triggered, the chessboard background adjacent access is realized on the DRAM to be tested, the previous test blind area is covered, and the chip defects that are difficult to be found in the prior art are detected, the fault coverage is improved, the reliability of the test result is enhanced, and the product benignity is improved.

[0189] In the above-described embodiments provided in the present application, it should be understood that the disclosed method, device, computer readable storage medium and electronic equipment can be implemented in other manners. For example, the above-described device embodiments are merely schematic, and the division of the modules is merely a logical function division, and there can be another division manner in actual implementation. For example, a plurality of components or modules can be combined or integrated into another device, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the above-described components can be indirect coupling or communication connection through some interfaces, devices or components, and can be electrical, mechanical or other forms.

[0190] The components described as separate components may or may not be physically separate, and the components shown as components may or may not be physical modules, i.e., they can be located in one place or distributed on multiple network modules. Some or all of the components can be selected according to actual needs to achieve the purpose of the present embodiment.

[0191] In addition, each function module in each embodiment of the present application can be integrated in one processing module, or each component can be physically present separately, or two or more modules can be integrated in one module. The integrated module can be realized in the form of hardware or in the form of a software function module.

[0192] When the integrated module is realized in the form of a software function module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solutions of the present application or the whole or part of the technical solutions that essentially contribute to the prior art can be embodied in the form of a software product, which is stored in a storage medium and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes a U disk, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a magnetic disk or an optical disk, and various program code storage media.

[0193] It should be noted that, for each method embodiment described above, in order to simplify the description, each method embodiment is described as a combination of a series of actions, but those skilled in the art should know that the present application is not limited by the described action sequence, because according to the present application, certain steps can be performed in other order or simultaneously. Secondly, those skilled in the art should know that the embodiments described in the specification all belong to preferred embodiments, and the actions and modules involved are not necessarily essential to the present application.

[0194] In the above embodiments, the description of each embodiment has its own focus, and the parts not described in detail in a certain embodiment can be referred to the related description of other embodiments.

[0195] The above is only an embodiment of the present application, and does not limit the patent scope of the present application, and any equivalent transformation or direct or indirect application in related technical fields based on the content of the specification and drawings of the present application is also included in the patent protection scope of the present application.

Claims

1. A DRAM testing method, characterized by, The method comprises the steps of: performing two rounds of testing on the DRAM to be tested to obtain a first comparison result and a second comparison result respectively; the testing comprises: alternately writing preset test data and the inverse of the preset test data into the memory array of the DRAM to be tested in units of preset operation units until all memory cells of the DRAM to be tested are written with data; the data written in any preset operation unit is different from the data written in its adjacent preset operation unit; performing two passes on each first preset read-write unit of the DRAM to be tested in units of the preset operation units based on the written data until all memory cells of the DRAM to be tested are passed through; for a target preset operation unit that is passed through, determining an adjacent preset operation unit adjacent to the target preset operation unit, performing data read-write operations on the target preset operation unit and the adjacent preset operation unit in a preset order based on the preset test data, and comparing the read data with the corresponding written data; the preset test data of the first round of testing is the inverse of the preset test data of the second round of testing; obtaining a test result of the DRAM to be tested according to the first comparison result and the second comparison result; the alternately writing preset test data and the inverse of the preset test data into the memory array of the DRAM to be tested in units of preset operation units until all memory cells of the DRAM to be tested are written with data comprises: alternately writing preset test data and the inverse of the preset test data into each second preset read-write unit of the memory array of the DRAM to be tested in units of preset operation units starting from the low address of the second preset read-write unit in a preset burst length until all memory cells of the DRAM to be tested are written with data, the second preset read-write unit being a row; the performing two passes on each first preset read-write unit of the DRAM to be tested in units of the preset operation units based on the written data until all memory cells of the DRAM to be tested are passed through comprises: performing a first pass on all first preset operation units in each first preset read-write unit of the DRAM to be tested whose written data is the preset test data until all written data of the DRAM to be tested is the first preset operation unit whose written data is the preset test data; performing a second pass on all second preset operation units in each first preset read-write unit of the DRAM to be tested whose written data is the inverse of the preset test data until all written data of the DRAM to be tested is the second preset operation unit whose written data is the inverse of the preset test data.

2. The DRAM testing method of claim 1, wherein, for all first preset operation units in each first preset read-write unit in the first pass, the corresponding preset order alternates; for all second preset operation units in each first preset read-write unit in the second pass, the corresponding preset order alternates.

3. The DRAM testing method of claim 2, wherein, The target preset operation unit to be traversed is determined, and adjacent preset operation units adjacent to the target preset operation unit are determined. Data read-write operations are performed on the target preset operation unit and the adjacent preset operation units in a preset order based on the preset test data. The read data is compared with the corresponding written data, which includes: For the first target preset operation unit traversed in the first traversal, the first adjacent preset operation unit adjacent to the first target preset operation unit is determined. It is judged whether the sequence number of the first target preset operation unit in all first preset operation units corresponding to the first preset read-write unit is odd. If yes, the preset test data is written to the first adjacent preset operation unit in a first preset order. After each writing of the preset test data, the data of the first target preset operation unit is read, and the read data is compared with the corresponding written data. The inverse of the preset test data is written to the first adjacent preset operation unit currently writing the preset test data. After each writing of the inverse of the preset test data, the data of the first target preset operation unit is read, and the read data is compared with the corresponding written data. If no, the preset test data is written to the first adjacent preset operation unit in a second preset order. After each writing of the preset test data, the data of the first target preset operation unit is read, and the read data is compared with the corresponding written data. The inverse of the preset test data is written to the first adjacent preset operation unit currently writing the preset test data. After each writing of the inverse of the preset test data, the data of the first target preset operation unit is read, and the read data is compared with the corresponding written data. For the second target preset operation unit traversed in the second traversal, the second adjacent preset operation unit adjacent to the second target preset operation unit is determined. It is judged whether the sequence number of the second target preset operation unit in all second preset operation units corresponding to the first preset read-write unit is even. If yes, the inverse of the preset test data is written to the second adjacent preset operation unit in a third preset order. After each writing of the inverse of the preset test data, the data of the second target preset operation unit is read, and the read data is compared with the corresponding written data. The preset test data is written to the second adjacent preset operation unit currently writing the inverse of the preset test data. After each writing of the preset test data, the data of the second target preset operation unit is read, and the read data is compared with the corresponding written data. If no, the inverse of the preset test data is written to the second adjacent preset operation unit in a fourth preset order. After each writing of the inverse of the preset test data, the data of the second target preset operation unit is read, and the read data is compared with the corresponding written data. The preset test data is written to the second adjacent preset operation unit currently writing the inverse of the preset test data. After each writing of the preset test data, the data of the second target preset operation unit is read, and the read data is compared with the corresponding written data. If not, the inverse of the preset test data is written to the second adjacent preset operation unit according to a fourth preset order, the data of the second target preset operation unit is read every time the inverse of the preset test data is written, the read data is compared with the corresponding written data, and the preset test data is written to the second adjacent preset operation unit currently writing the inverse of the preset test data. The data of the second target preset operation unit is read every time the preset test data is written, and the read data is compared with the corresponding written data.

4. The DRAM testing method of any one of claims 1 to 3, wherein, The first preset read-write unit includes a row or a column.

5. The DRAM testing method of any one of claims 1 to 3, wherein, The test result of the DRAM to be tested according to the first comparison result and the second comparison result includes: If the first comparison result and the second comparison result are consistent, the test result is success; otherwise, the test result is failure.

6. A DRAM testing apparatus, characterized by comprising: Including: The data read-write module is configured to perform two rounds of tests on the DRAM to be tested to obtain a first comparison result and a second comparison result, respectively. The test includes: The preset test data and the inverse of the preset test data are alternately written to the storage array of the DRAM to be tested in units of preset operation units until all storage units of the DRAM to be tested are written with data; The data written by any preset operation unit is different from the data written by its adjacent preset operation unit; Each first preset read-write unit of the DRAM to be tested is traversed twice based on the written data in units of the preset operation units until all storage units of the DRAM to be tested are traversed; For a target preset operation unit that is traversed, an adjacent preset operation unit adjacent to the target preset operation unit is determined, data read-write operations are performed on the target preset operation unit and the adjacent preset operation unit based on the preset test data according to a preset order, and the read data is compared with the corresponding written data; The preset test data of the first round of tests is the inverse of the preset test data of the second round of tests; The test module is configured to obtain a test result of the DRAM to be tested according to the first comparison result and the second comparison result. The preset test data and the inverse of the preset test data are alternately written to the storage array of the DRAM to be tested in units of preset operation units until all storage units of the DRAM to be tested are written with data, including: The preset test data and the inverse of the preset test data are alternately written to the low address of each second preset read-write unit of the storage array of the DRAM to be tested in units of preset operation units according to a preset burst length until all storage units of the DRAM to be tested are written with data, and the second preset read-write unit is a row. The preset test data and the inverse of the preset test data are alternately written to the low address of each second preset read-write unit of the storage array of the DRAM to be tested in units of preset operation units according to a preset burst length until all storage units of the DRAM to be tested are written with data, and the second preset read-write unit is a row. performing a first iteration on each first preset operation unit of all written data in each first preset read-write unit of the DRAM to be tested until all written data in each first preset operation unit of the DRAM to be tested is iterated; performing a second iteration on each second preset operation unit of all written data in each first preset read-write unit of the DRAM to be tested until all written data in each second preset operation unit of the DRAM to be tested is iterated.

7. A computer readable storage medium having stored thereon a computer program, characterized in that, The computer program is executed by a processor to implement each step of the DRAM testing method according to any one of claims 1 to 5.

8. An electronic device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that, The processor executes the computer program to implement each step of the DRAM testing method according to any one of claims 1 to 5.

Images