DRAM testing methods, apparatus, readable storage media and electronic devices

Abstract

This invention discloses a DRAM testing method, apparatus, readable storage medium, and electronic device. The method involves performing two rounds of testing on the DRAM under test. For each target preset operation bit encountered, data read / write operations are performed on the target preset operation bit and its adjacent preset operation bits according to a preset order based on preset test data. The read data is compared with the corresponding written data, and the final test result is obtained through the comparison results of the two rounds of testing. Since coupling faults can only be triggered under specific conditions, such as a significant potential difference between adjacent memory cells, data writing and reading are performed on the target preset operation bit and its adjacent preset operation bits to simulate this situation. This covers previous test blind spots and detects chip defects that are difficult to detect in existing technologies. It triggers multiple memory cell faults such as bridging faults and coupling faults, improving fault coverage, enhancing the reliability of test results, and thus improving product yield.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of DRAM chip testing, and in particular to a DRAM testing method and device, a readable storage medium and an electronic device. BACKGROUND

[0002] Dynamic Random Access Memory (DRAM) is an indispensable component of modern computer systems, which can be applied to Double Data Rate (DDR) modules for personal computers or servers and Low Power Double Data Rate (LPDDR) chips for embedded ARM architecture.

[0003] The basic storage unit of LPDDR is a cell, and computers and embedded systems store and read / write data by writing high or low levels in the cell.

[0004] In addition, current DRAMs use burst read / write mode for efficient access rate, that is, read / write operations in a storage array are performed in units of burst length (BL), and a plurality of bit (such as 8 or 16 bits) column addresses are read / written at a time, and data composed of 0 and 1 is accessed in each burst length. For example, the addressed address is 0 row, and the burst length is 8 bits, so 1 bit of data is written to each bit in the space from 0 row 0 column to 0 row 7 column, a total of 8 bits, the second burst length is from 0 row 8 column to 15 column, and so on. When the storage positions of a row are all written, the Memory Controller (MC) positions the address of the next row and continues the same operation.

[0005] Due to the characteristics of the internal structure of DRAM, the storage unit used to store information will continue to leak electricity, and the data therein will be lost when it reaches a certain level, so it is necessary to re-write the current data to the storage unit before the data is lost, that is, refresh (REF). If the DRAM is working normally, the data will not change after refreshing, and if there is a defect or in extreme conditions, the data will change after refreshing.

[0006] Meanwhile, the process of the manufacturing process affects the storage unit to cause data storage failure when reading and writing. The storage failure is divided into single cell and multi-cell failure. Single cell failure mainly includes stuck at fault (SF) and transition fault (TF). For the detection of the two faults, 1 is generally written to the unit to be tested, then 0 is written, and then 0 is read out. Correspondingly, 0 is written, then 1 is written, and then 1 is read out to detect. Typical multi-cell faults include bridging fault (BF) and coupling fault (CF). For the two faults, the traditional detection method is to write and read the storage unit in the address space in ascending order, and then write and read in descending order to detect whether there is data error.

[0007] Coupling fault is relatively easy to trigger under special circumstances. One of the circumstances is that a certain cell is at a high level, but the cells around it are all at a low level, or a certain cell is at a low level, but the cells around it are all at a high level. This large amplitude potential difference is easy to trigger the storage error of the fault cell. There is no specific testing method for this fault condition. SUMMARY

[0008] The technical problem to be solved by the present application is to provide a DRAM test method, device, readable storage medium and electronic equipment, which can improve the coverage rate of fault when testing DRAM.

[0009] To solve the above technical problems, a technical solution adopted by the present application is:

[0010] A DRAM test method, comprising the steps of:

[0011] Two rounds of testing are performed on the DRAM to be tested, and first and second comparison results are obtained respectively;

[0012] The test comprises:

[0013] The preset test data is written to the DRAM to be tested until all the storage units of the DRAM to be tested are written with data;

[0014] The DRAM to be tested is traversed in units of preset operation bits until all the preset operation bits of the DRAM to be tested are traversed;

[0015] For the target preset operation bit traversed, data read and write operation is performed on the target preset operation bit and the adjacent preset operation bit adjacent to the target preset operation bit in a preset order based on the preset test data, and the read data is compared with the corresponding written data.

[0016] The preset operation bits of the first round of tests are different from those of the second round of tests;

[0017] The test result of the DRAM to be tested is obtained according to the first comparison result and the second comparison result.

[0018] To solve the above technical problems, another technical solution adopted by the present application is:

[0019] A DRAM testing device comprises:

[0020] A data read-write module is configured to perform two rounds of tests on the DRAM to be tested, and obtain a first comparison result and a second comparison result, respectively.

[0021] The test comprises:

[0022] The preset test data is written into the DRAM to be tested until all the memory cells of the DRAM to be tested are written with data.

[0023] The DRAM to be tested is traversed in units of preset operation bits until all the preset operation bits of the DRAM to be tested are traversed.

[0024] For a target preset operation bit that is traversed, data read-write operations are performed on the target preset operation bit and adjacent preset operation bits adjacent to the target preset operation bit in a preset order based on the preset test data, and the read data is compared with the corresponding written data.

[0025] The preset operation bits of the first round of tests are different from those of the second round of tests;

[0026] A test module is configured to obtain a test result of the DRAM to be tested according to the first comparison result and the second comparison result.

[0027] To solve the above technical problems, another technical solution adopted by the present application is:

[0028] A computer readable storage medium has a computer program stored thereon, and the computer program is executed by a processor to implement each step of the DRAM testing method.

[0029] To solve the above technical problems, another technical solution adopted by the present application is:

[0030] An electronic device comprises a memory, a processor, and a computer program stored on the memory and executable on the processor, and the processor implements each step of the DRAM testing method when executing the computer program.

[0031] The beneficial effect of the present application is that: through two rounds of testing on the DRAM to be tested, for the target preset operation bit traversed, data read-write operations are performed on the target preset operation bit and the adjacent preset operation bit adjacent to the target preset operation bit in a preset order based on preset test data, the read data is compared with the corresponding written data, the final test result is obtained through the comparison result of the two rounds of testing, since the coupling fault can be triggered only in a specific case, such as a large potential difference between adjacent storage units, data writing and reading on the target preset operation bit and the adjacent preset operation bit can simulate the specific case, cover the previous test blind area and detect the chip defects that are difficult to be found in the prior art, so that the multi-storage unit faults such as bridge fault and coupling fault are triggered, the fault coverage is improved, the reliability of the test result is enhanced, and the product yield is improved. BRIEF DESCRIPTION OF DRAWINGS

[0032] Figure 1 A step flow chart of a DRAM test method according to an embodiment of the present application;

[0033] Figure 2 A structural schematic diagram of a DRAM test device according to an embodiment of the present application;

[0034] Figure 3 A structural schematic diagram of an electronic device according to an embodiment of the present application;

[0035] Figure 4 A schematic diagram of preset test data and the inverse of the preset test data in a DRAM test method according to an embodiment of the present application;

[0036] Figure 5 A schematic diagram of a storage array of a DRAM to be tested in which preset test data D is written in a DRAM test method according to an embodiment of the present application;

[0037] Figure 6 A schematic diagram of a DRAM test method according to an embodiment of the present application, in which the inverse of the preset test data D is written on the target row, the data written is read on the adjacent row and compared with D;

[0038] Figure 7 A schematic diagram of a DRAM test method according to an embodiment of the present application, in which the data written is read on the target row and compared with the inverse of D, the inverse of the preset test data D is written on the adjacent row;

[0039] Figure 8 A schematic diagram of a DRAM test method according to an embodiment of the present application, in which the preset test data D is written on the target row, the data written is read on the adjacent row and compared with D;

[0040] Figure 9A diagram for reading and writing data of a target row in the DRAM test method of the embodiment of the present application and comparing with D, and writing preset test data D of adjacent rows;

[0041] Figure 10 A diagram for writing inverse of preset test data D of a target column in the DRAM test method of the embodiment of the present application, reading and writing data of adjacent columns and comparing with D;

[0042] Figure 11 A diagram for reading and writing data of a target column in the DRAM test method of the embodiment of the present application and comparing with inverse of preset test data D, and writing inverse of preset test data D of adjacent columns;

[0043] Figure 12 A diagram for writing preset test data D of a target column in the DRAM test method of the embodiment of the present application, reading and writing data of adjacent columns and comparing with inverse of preset test data D;

[0044] Figure 13 A diagram for reading and writing data of a target column in the DRAM test method of the embodiment of the present application and comparing with D, and writing preset test data D of adjacent columns. DETAILED DESCRIPTION

[0045] To make the technical contents, purposes and effects of the present application clear, the following will be described in combination with embodiments and the accompanying drawings.

[0046] Please refer to Figure 1 The embodiment of the present application provides a DRAM test method, comprising the steps of:

[0047] Two rounds of tests are performed on the DRAM to be tested, and first and second comparison results are obtained respectively;

[0048] The test comprises:

[0049] Preset test data is written into the DRAM to be tested until all memory cells of the DRAM to be tested are written with data;

[0050] The DRAM to be tested is traversed in units of preset operation bits until all preset operation bits of the DRAM to be tested are traversed;

[0051] For a target preset operation bit traversed, data read-write operation is performed on the target preset operation bit and adjacent preset operation bits adjacent to the target preset operation bit in a preset order based on the preset test data, and the read data is compared with the corresponding written data;

[0052] The preset operation bits of the first round of test and the second round of test are different;

[0053] obtaining a test result of the DRAM to be tested according to the first comparison result and the second comparison result.

[0054] From the above description, the beneficial effects of the present application are that: through two rounds of testing of the DRAM to be tested, for the target preset operation bit traversed, data read-write operations are performed on the target preset operation bit and the adjacent preset operation bit adjacent to the target preset operation bit according to a preset order based on preset test data, the read data is compared with the corresponding written data, the final test result is obtained through the comparison results of the two rounds of testing, since the coupling fault can be triggered only in a specific case, such as a large potential difference between adjacent storage units, data writing and reading to the target preset operation bit and the adjacent preset operation bit can simulate the specific case, cover the previous test blind area and detect the chip defects that are difficult to be found in the prior art, so that the multi-storage unit faults such as bridge fault and coupling fault are triggered, the fault coverage is improved, the reliability of the test result is enhanced, and the product yield is improved.

[0055] Further, the writing of the preset test data into the DRAM to be tested until all the storage units of the DRAM to be tested are written with data comprises:

[0056] The preset test data is written from the low address of each first preset read-write unit of the DRAM to be tested in units of preset burst length until all the storage units of the DRAM to be tested are written with data.

[0057] From the above description, by writing the preset test data into the DRAM to be tested in units of burst length, the data writing speed can be improved, and the time complexity is low, which is suitable for mass production testing.

[0058] Further, the data read-write operations on the target preset operation bit and the adjacent preset operation bit adjacent to the target preset operation bit according to a preset order based on the preset test data comprises:

[0059] The data read-write operations on the target preset operation bit and the target preset operation bit and the previous preset operation bit and the next preset operation bit according to a preset order based on the preset test data, if the previous preset operation bit or the next preset operation bit of the target preset operation bit does not exist, the data read-write operation of the previous preset operation bit or the next preset operation bit is omitted.

[0060] As described above, data read and write operations are performed on the target preset operation bit and the preset operation bit before and after the target preset operation bit in a preset order, resulting in a large potential difference between the target preset operation bit and the adjacent preset operation bit. This simulates a specific situation that is easy to trigger coupling faults, which can cover the previous test blind zone and make it easier to trigger faults in multiple memory cells, thereby improving the fault coverage.

[0061] Further, the step of performing data read / write operations on the target preset operation bit and adjacent preset operation bits adjacent to the target preset operation bit in a preset order based on the preset test data includes:

[0062] Write the inverse of the preset test data to the target preset operation bit, and read the data of the adjacent preset operation bit adjacent to the target preset operation bit, and compare the read data with the corresponding written data;

[0063] Write the inverse of the preset test data to the adjacent preset operation bit, and read the data of the target preset operation bit, and compare the read data with the corresponding written data;

[0064] Write the preset test data to the target preset operation bit, and read the data of the adjacent preset operation bit, and compare the read data with the corresponding written data;

[0065] Write the preset test data to the adjacent preset operation bit, and read the data of the target preset operation bit, and compare the read data with the corresponding written data.

[0066] As described above, by writing the inverse of the preset test data to the target preset operation bit and the adjacent preset operation bit, then reading the written data, then writing the preset test data again, and then reading the written data again, a single storage unit can be activated, improving fault coverage and ensuring the reliability and accuracy of the test.

[0067] Furthermore, the preset operation bits include rows or columns.

[0068] As described above, testers can set preset operation positions to rows or columns as needed, offering high flexibility.

[0069] Further, the data read / write operation to the adjacent preset operation bit adjacent to the target preset operation bit includes:

[0070] First, perform data read / write operations on the previous preset operation bit of the target preset operation bit, and then perform data read / write operations on the next preset operation bit of the target preset operation bit.

[0071] Alternatively, data read / write operations can be performed on the next preset operation bit of the target preset operation bit first, and then data read / write operations can be performed on the previous preset operation bit of the target preset operation bit.

[0072] Alternatively, data read / write operations may be performed simultaneously on the preceding and following preset operation bits of the target preset operation bit.

[0073] As described above, when performing data read / write operations on adjacent preset operation bits, the preceding preset operation bit can be read / written first, followed by the following preset operation bit; or the following preset operation bit can be read / written first, followed by the preceding preset operation bit; or the preceding and following preset operation bits can be read / written simultaneously. This allows testers to choose the order of masked access, providing high flexibility.

[0074] Further, obtaining the test result of the DRAM to be tested based on the first comparison result and the second comparison result includes:

[0075] If both the first comparison result and the second comparison result are consistent, the test result is successful; otherwise, the test result is unsuccessful.

[0076] As can be seen from the above description, by obtaining the first comparison result and the second comparison result through two rounds of testing, it is possible to detect chip defects that are difficult to find, improve the fault coverage during testing, and ensure the reliability of testing.

[0077] Please refer to Figure 2 Another embodiment of the present invention provides a DRAM testing apparatus, comprising:

[0078] The data read / write module is used to perform two rounds of testing on the DRAM under test, and obtain the first comparison result and the second comparison result respectively.

[0079] The tests include:

[0080] Preset test data is written to the DRAM to be tested until all memory cells of the DRAM to be tested have been written with data;

[0081] The DRAM to be tested is traversed in units of preset operation bits until all preset operation bits of the DRAM to be tested have been traversed.

[0082] For the target preset operation bit that is traversed, data read and write operations are performed on the target preset operation bit and the adjacent preset operation bits adjacent to the target preset operation bit in a preset order based on the preset test data, and the read data is compared with the corresponding written data.

[0083] The preset operation positions are different in the first round of testing and the second round of testing;

[0084] The testing module is used to obtain the test results of the DRAM to be tested based on the first comparison result and the second comparison result.

[0085] Another embodiment of the present invention provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the various steps in the above-described DRAM testing method.

[0086] like Figure 3 As shown, another embodiment of the present invention provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements the various steps in the above-described DRAM testing method.

[0087] The DRAM testing method, apparatus, computer-readable storage medium, and electronic device described above are applicable to the testing of any type of DRAM, such as DDR and LPDDR generations of products. Specific embodiments are described below:

[0088] Example 1

[0089] Please refer to Figure 1 This embodiment of a DRAM testing method includes the following steps:

[0090] S1. Perform two rounds of testing on the DRAM to be tested, and obtain the first comparison result and the second comparison result respectively;

[0091] The test includes:

[0092] S11. Write preset test data to the DRAM to be tested until all memory cells of the DRAM to be tested have been written with data;

[0093] Specifically, the preset test data is written from the low address of each first preset read / write unit of the DRAM under test in units of a preset burst length until all memory units of the DRAM under test are written with data.

[0094] The first preset read / write unit can be flexibly configured according to actual needs, such as being set as a column or a row;

[0095] The burst length (BL) is defined by the JEDEC standard, but it can also be set arbitrarily. This means that multiple bits (e.g., 8 bits or 16 bits) are used for reading and writing at the same time. For example, when writing data based on rows, if the address is row 0 and the burst length is 8 bits, the first 8 bits of the data to be written are written simultaneously starting at the position of row 0, column 0. Then, the second burst length is used to write bits 9-16 of the data to be written, and so on until the storage location of row 0 is completely written. Then, the address of the next row is repositioned and the operation of the previous row is continued until the data is written to the entire disk. Reading data is a similar operation.

[0096] In this embodiment, the first preset unit is a row, such as... Figure 5 As shown;

[0097] For example, start writing preset test data from the first column of the first row. After writing the first row, start writing preset test data from the first column of the second row, and so on, until data is written to each row of the DRAM to be tested.

[0098] S12. Traverse the DRAM to be tested in units of preset operation bits until all preset operation bits of the DRAM to be tested have been traversed.

[0099] For the target preset operation bit that is traversed, data read and write operations are performed on the target preset operation bit and the adjacent preset operation bits adjacent to the target preset operation bit in a preset order based on the preset test data, and the read data is compared with the corresponding written data.

[0100] The preset operation bits include rows or columns;

[0101] Specifically, based on the preset test data, data read and write operations are performed on the target preset operation bit and the previous and next preset operation bits of the target preset operation bit in a preset order. If there is no previous or next preset operation bit of the target preset operation bit, the data read and write operation of the previous or next preset operation bit is omitted.

[0102] The data read / write operation to the adjacent preset operation bit adjacent to the target preset operation bit includes:

[0103] First, perform data read / write operations on the previous preset operation bit of the target preset operation bit, and then perform data read / write operations on the next preset operation bit of the target preset operation bit.

[0104] Alternatively, data read / write operations can be performed on the next preset operation bit of the target preset operation bit first, and then data read / write operations can be performed on the previous preset operation bit of the target preset operation bit.

[0105] Alternatively, data read / write operations may be performed simultaneously on the preceding and following preset operation bits of the target preset operation bit.

[0106] In this embodiment, data read and write operations are performed simultaneously on the previous preset operation bit and the next preset operation bit of the target preset operation bit.

[0107] For example, for the target row that has been traversed, assuming that the target row has a previous row and a next row, then based on the preset test data, the data read and write operations are performed on the previous row and the next row of the target row simultaneously in units of preset burst length.

[0108] Alternatively, for the target column that is traversed, assuming that the target column has a preceding column and a following column, then based on the preset test data, the preceding column and the following column of the target column are read and written simultaneously in units of preset burst length.

[0109] For example, if the target row is the first row, then only the row after it exists, and the data read / write operations of the row before the target row are omitted; if the target row is the last row, then only the row before it exists, and the data read / write operations of the row after the target row are omitted; if the target row is any row other than the first or last row, then both the row before and the row after it exist, and the data read / write operations of the row before and the row after the target row are performed simultaneously based on the preset test data and in units of preset burst length.

[0110] Alternatively, if the target column is the first column, then only the column following it exists, and the data read / write operations of the column preceding the target column are omitted; if the target column is the last column, then only the column preceding it exists, and the data read / write operations of the column following the target column are omitted; if the target column is any column other than the first or last column, then both the column preceding and following it exist, and data read / write operations of both the column preceding and following the target column are performed simultaneously based on preset test data and in units of preset burst length.

[0111] Specifically, the step of performing data read / write operations on the target preset operation bit and adjacent preset operation bits adjacent to the target preset operation bit in a preset order based on the preset test data includes:

[0112] S121. Write the inverse of the preset test data to the target preset operation bit, and read the data of the adjacent preset operation bit adjacent to the target preset operation bit, and compare the read data with the corresponding written data.

[0113] For example, write the inverse of the preset test data to the target line in units of preset burst length, and at the same time read the data of the line before and after the target line, and compare the read data with the corresponding written data;

[0114] Alternatively, write the inverse of the preset test data to the target column in units of preset burst length, and simultaneously read the data in the column before and after the target column, and compare the read data with the corresponding written data;

[0115] S122. Write the inverse of the preset test data to the adjacent preset operation bit, and read the data of the target preset operation bit, and compare the read data with the corresponding written data;

[0116] For example, write the inverse of the preset test data to the line before and after the target line simultaneously in units of preset burst length, and read the data of the target line, and compare the read data with the corresponding written data.

[0117] Alternatively, write the inverse of the preset test data to the column before and the column after the target column simultaneously in units of preset burst length, and read the data of the target column, comparing the read data with the corresponding written data;

[0118] S123. Write the preset test data to the target preset operation bit, and read the data of the adjacent preset operation bit, and compare the read data with the corresponding written data;

[0119] For example, write preset test data to the target line in units of preset burst length, and at the same time read the data of the line before and after the target line, and compare the read data with the corresponding written data.

[0120] Alternatively, write preset test data to the target column in units of preset burst length, and simultaneously read the data in the column before and after the target column, and compare the read data with the corresponding written data;

[0121] S124. Write the preset test data to the adjacent preset operation bit, and read the data of the target preset operation bit, and compare the read data with the corresponding written data;

[0122] For example, write preset test data to the line before and after the target line simultaneously in units of preset burst length, and read the data of the target line, then compare the read data with the corresponding written data.

[0123] Alternatively, write preset test data to the column before and the column after the target column simultaneously in units of preset burst length, and read the data of the target column, comparing the read data with the corresponding written data;

[0124] After the first round of testing is completed, the second round of testing is conducted. The preset operation positions for the first round of testing are different from those for the second round of testing.

[0125] S2. Obtain the test results of the DRAM to be tested based on the first comparison result and the second comparison result;

[0126] If both the first comparison result and the second comparison result are consistent, the test result is successful; otherwise, the test result is unsuccessful.

[0127] In this embodiment, specific references are made. Figures 4-13 R i For row operations, where 0 ≤ i < RowMax, RowMax is the maximum row size of the storage array, C j For column operation bits, where 0 ≤ j < ColMax, and ColMax is the maximum column value of the storage array;

[0128] First, the DRAM under test is subjected to the first round of testing, with the preset operation bit set to row:

[0129] like Figure 4 As shown, the test data to be written is defined as D = 01010101……0101, and its inverse is / D = 10101010……1010. Assuming the preset burst length is BL = 8 bits, then D = 01010101, / D = 10101010.

[0130] First, the address is located at row 0, column 0. Starting from the storage cell corresponding to row 0, column 0, write test data D according to BL. After writing row 0, start writing test data D again from row 1, column 0, and so on, until the entire storage array is filled with data. Figure 5 As shown;

[0131] Secondly, traversing the storage array row by row, starting from row R0, until all rows of the entire storage array have been traversed, for each target row R... i Press BL to target line R i Write to / D and read from R simultaneously. i-1 Line and R i+1 The data in the row is compared with D to check for errors, such as... Figure 6 As shown;

[0132] Next, press BL and simultaneously move to R. i-1 Line and R i+1 Write line / D and read target line R. i The data is compared with / D to check for errors, such as... Figure 7 As shown;

[0133] Then, press BL to navigate to the target line R. i Write to D and simultaneously read from R. i-1 Line and R i+1The data in the row is compared with / D to check for errors, such as... Figure 8 As shown;

[0134] Next, press BL and simultaneously move to R. i-1 Line and R i+1 Write line D and read target line R. i The data is compared with D to check for errors, such as... Figure 9 As shown;

[0135] If there is no target row R i R i-1 row or R i+1 If the line is empty, then R is omitted. i-1 row or R i+1 Data read and write operations on rows, for example, row R0 is the target row R. i Then the target row R i R does not exist i-1 Okay, only R exists i+1 If the line is empty, then R is omitted. i-1 Data read and write operations on R i+1 The row performs data read and write operations;

[0136] Obtain the first comparison result;

[0137] In the second round of testing, the preset operation bit is column:

[0138] First, the address is located at row 0, column 0. Starting from the storage cell corresponding to row 0, column 0, write test data D according to BL. After writing row 0, start writing test data D from row 1, column 0, and so on, until the entire storage array is written with data.

[0139] Secondly, traversing the storage array column by column, starting from column C0, until all columns of the entire storage array have been traversed, for the target column C... j , press BL to target column C j Write to / D and read from C simultaneously. j-1 Column and C j+1 The data in the column is compared with the data in D to check for errors, such as... Figure 10 As shown;

[0140] Next, press BL and simultaneously move to C. j-1 Column and C j+1 Write column / D and read target column C. j The data is compared with / D to check for errors, such as... Figure 11 As shown;

[0141] Then, press BL to navigate to target column C. jWrite to D and simultaneously read from C. j-1 Column and C j+1 The data in the column is compared with / D to check for errors, such as... Figure 12 As shown;

[0142] Next, press BL and simultaneously move to C. j-1 Column and C j+1 Write column D and read target column C. j The data is compared with D to check for errors, such as... Figure 13 As shown;

[0143] If the target column C does not exist j C j-1 Column or C j+1 If column C is omitted, then C is omitted. j-1 Column or C j+1 Read and write data to a column, for example, column C0 is the target column C. j Then the target column C j C does not exist j-1 Column, only C exists j+1 If column C is omitted, then C is omitted. j-1 Column data read and write operations, for C j+1 The column performs data read and write operations;

[0144] A second comparison result was obtained;

[0145] If both the first and second comparison results are consistent, the test is successful; otherwise, the test fails.

[0146] Example 2

[0147] This embodiment further defines how to perform data read and write operations on the target preset operation bit and adjacent preset operation bits adjacent to the target preset operation bit in a preset order based on the preset test data. Specifically:

[0148] Write the inverse of the preset test data to the target preset operation bit, and read the data of the adjacent preset operation bit adjacent to the target preset operation bit, and compare the read data with the corresponding written data;

[0149] For example, write the inverse of the preset test data to the target line in units of preset burst length, and at the same time read the data of the line before and after the target line, and compare the read data with the corresponding written data;

[0150] Alternatively, write the inverse of the preset test data to the target column in units of preset burst length, and simultaneously read the data in the column before and after the target column, and compare the read data with the corresponding written data;

[0151] Write the inverse of the preset test data to the adjacent preset operation bit, and read the data of the target preset operation bit, and compare the read data with the corresponding written data;

[0152] For example, write the inverse of the preset test data to the line before and after the target line simultaneously in units of preset burst length, and read the data of the target line, and compare the read data with the corresponding written data.

[0153] Alternatively, write the inverse of the preset test data to the column before and the column after the target column simultaneously in units of preset burst length, and read the data of the target column, comparing the read data with the corresponding written data;

[0154] Write the preset test data to the target preset operation bit, and read the data of the adjacent preset operation bit, and compare the read data with the corresponding written data;

[0155] For example, write preset test data to the target line in units of preset burst length, and at the same time read the data of the line before and after the target line, and compare the read data with the corresponding written data.

[0156] Alternatively, write preset test data to the target column in units of preset burst length, and simultaneously read the data in the column before and after the target column, and compare the read data with the corresponding written data;

[0157] Write the preset test data to the adjacent preset operation bit, and read the data of the target preset operation bit, and compare the read data with the corresponding written data;

[0158] For example, write preset test data to the line before and after the target line simultaneously in units of preset burst length, and read the data of the target line, then compare the read data with the corresponding written data.

[0159] Alternatively, write preset test data to the column before and the column after the target column simultaneously in units of preset burst length, and read the data of the target column, comparing the read data with the corresponding written data;

[0160] In another alternative implementation, the preset operation bit for the first round of testing can be set to column, and the preset operation bit for the second round of testing can be set to row.

[0161] Example 3

[0162] The difference between this embodiment three and embodiment one is that the first preset unit is a column, and based on the preset test data, the data read and write operation is first performed on the preset operation bit before the target preset operation bit, and then the data read and write operation is performed on the preset operation bit after the target preset operation bit.

[0163] Specifically, the address is column 0, row 0. Starting from the storage cell corresponding to column 0, row 0, write test data D according to BL. That is, write test data D from column 0, row 0 to column 12, row 0. After writing, start writing test data D from column 0, row 1. After writing all rows from column 0 to column 7, continue writing all rows from column 8 to column 13 in row order, and so on, until the entire storage array is written with data.

[0164] Secondly, traversing the storage array row by row, starting from row R0, until all rows of the entire storage array have been traversed, for each target row R... i Press BL to target line R i Write to / D, first read R i-1 Read the data from the row, then read R. i+1 The data in the row is compared with D to check for errors.

[0165] Next, press BL to move to R. i-1 Write the line to / D, then to R i+1 Write line / D and read target line R. i The data is compared with / D to verify for errors.

[0166] Then, press BL to navigate to the target line R. i Write to D, then read R first. i-1 Read the data from the row, then read R. i+1 The data in the row is compared with / D to check for errors;

[0167] Next, press BL to move to R. i-1 Write the line to D, then to R i+1 Write line D and read target line R. i The data is compared with D to verify for errors.

[0168] Obtain the first comparison result;

[0169] In the second round of testing, the preset operation bit is column:

[0170] First, the address is located at column 0, row 0. Starting from the storage cell corresponding to column 0, row 0, write test data D according to BL. That is, write test data D from column 0, row 0 to column 7, row 0. After writing, start writing test data D from column 0, row 1. After writing all rows from column 0 to column 7, continue writing all rows from column 8 to column 13 in row order, and so on, until the entire storage array is written with data.

[0171] Secondly, traversing the storage array column by column, starting from column C0, until all columns of the entire storage array have been traversed, for the target column C... j , press BL to target column C j Write to / D, first read from C j-1 The data in the column is then read from C. j+1 The data in column D is compared with the data read to check for errors.

[0172] Next, press BL to navigate to C. j-1 Write the column to / D, then to C. j+1 Write column / D and read target column C. j The data is compared with / D to verify for errors.

[0173] Then, press BL to navigate to target column C. j Write to D, then read C first. j-1 The data in the column is then read from C. j+1 The data in the column is compared with / D to check for errors.

[0174] Next, press BL to navigate to C. j-1 Write the column to D, then to C. j+1 Write column D and read target column C. j The data is compared with D to verify for errors.

[0175] A second comparison result was obtained;

[0176] If both the first and second comparison results are consistent, the test is successful; otherwise, the test fails.

[0177] Example 4

[0178] Please refer to Figure 2 A DRAM testing apparatus, comprising:

[0179] The data read / write module is used to perform two rounds of testing on the DRAM under test, and obtain the first comparison result and the second comparison result respectively.

[0180] The test includes:

[0181] Preset test data is written to the DRAM to be tested until all memory cells of the DRAM to be tested have been written with data;

[0182] The DRAM to be tested is traversed in units of preset operation bits until all preset operation bits of the DRAM to be tested have been traversed.

[0183] For the target preset operation bit that is traversed, data read and write operations are performed on the target preset operation bit and the adjacent preset operation bits adjacent to the target preset operation bit in a preset order based on the preset test data, and the read data is compared with the corresponding written data.

[0184] The preset operation positions are different in the first round of testing and the second round of testing;

[0185] The testing module is used to obtain the test results of the DRAM to be tested based on the first comparison result and the second comparison result.

[0186] Example 5

[0187] A computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, can implement the various steps of the DRAM testing method in Embodiment 1 or Embodiment 3.

[0188] Example 6

[0189] Please refer to Figure 3 An electronic device includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements the various steps of the DRAM testing method in Embodiment 1 or Embodiment 3.

[0190] In summary, the DRAM testing method, apparatus, readable storage medium, and electronic device provided by this invention perform two rounds of testing on the DRAM to be tested. During the writing of preset test data to the DRAM and the data read / write operations on the target preset operation bit and adjacent preset operation bits, writing is performed in units of a preset burst length, which improves the data writing speed and reduces time complexity, facilitating mass production testing. By writing the inverse of the preset test data to the target preset operation bit and adjacent preset operation bits, then reading the written data, and repeating this process, a single memory cell can be activated. Data read / write operations are performed on the preceding and following preset operation bits of the target preset operation bit, resulting in a large span between the target preset operation bit and adjacent preset operation bits. The potential difference makes it easier to trigger multi-memory cell faults. When performing read / write operations on adjacent preset operation bits, the preceding preset operation bit can be read / written first, followed by the following preset operation bit; or the following preset operation bit can be read / written first, followed by the preceding preset operation bit; or the preceding and following preset operation bits can be read / written simultaneously. This allows testers to choose the order of row and column masking access, offering high flexibility. By implementing row and column masking access on the DRAM under test, previous test blind spots can be covered, and chip defects that are difficult to detect in existing technologies can be detected. This triggers multi-memory cell faults such as bridging faults and coupling faults, improving fault coverage, enhancing the reliability of test results, and thus improving product quality.

[0191] In the embodiments provided in this application, it should be understood that the disclosed methods, apparatuses, computer-readable storage media, and electronic devices can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative. For instance, the division of modules is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple components or modules may be combined or integrated into another device, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices, components, or modules may be electrical, mechanical, or other forms.

[0192] The components described as separate parts may or may not be physically separate. The components shown as components may or may not be physical modules; that is, they may be located in one place or distributed across multiple network modules. Some or all of the components can be selected to achieve the purpose of this embodiment according to actual needs.

[0193] Furthermore, the functional modules in the various embodiments of the present invention can be integrated into one processing module, or each component can exist physically separately, or two or more modules can be integrated into one module. The integrated modules described above can be implemented in hardware or as software functional modules.

[0194] If the integrated module is implemented as a software functional module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0195] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that the present invention is not limited to the described order of actions, because according to the present invention, some steps can be performed in other orders or simultaneously. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions and modules involved are not necessarily essential to the present invention.

[0196] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0197] The above description is merely an embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent modifications made based on the content of the present invention specification and drawings, or direct or indirect applications in related technical fields, are similarly included within the patent protection scope of the present invention.

Claims

1. A DRAM testing method, characterized by, The method comprises the steps of: performing two rounds of testing on the DRAM to be tested to obtain a first comparison result and a second comparison result respectively; the testing comprises: writing preset test data to the DRAM to be tested until all memory cells of the DRAM to be tested are written with data; traversing the DRAM to be tested in preset operation bit units until all preset operation bits of the DRAM to be tested are traversed, the preset operation bits including rows or columns; for a target preset operation bit traversed, performing data read-write operations on the target preset operation bit and adjacent preset operation bits adjacent to the target preset operation bit in a preset order based on the preset test data, and comparing the read data with the corresponding written data; the preset operation bits of the first round of testing are different from those of the second round of testing; obtaining a test result of the DRAM to be tested according to the first comparison result and the second comparison result; the data read-write operations on the target preset operation bit and the adjacent preset operation bits adjacent to the target preset operation bit in the preset order based on the preset test data comprise: performing data read-write operations on the target preset operation bit and the previous and next preset operation bits of the target preset operation bit in a preset order based on the preset test data, and omitting the data read-write operations of the previous or next preset operation bit if the previous or next preset operation bit of the target preset operation bit does not exist.

2. The DRAM testing method of claim 1, wherein, the writing of the preset test data to the DRAM to be tested until all memory cells of the DRAM to be tested are written with data comprises: writing the preset test data from a low address of each first preset read-write unit of the DRAM to be tested in a preset burst length unit until all memory cells of the DRAM to be tested are written with data.

3. The method of claim 1, wherein, the data read-write operations on the target preset operation bit and the adjacent preset operation bits adjacent to the target preset operation bit in the preset order based on the preset test data comprise: writing the inverse of the preset test data to the target preset operation bit, reading data of the adjacent preset operation bit adjacent to the target preset operation bit, and comparing the read data with the corresponding written data; writing the inverse of the preset test data to the adjacent preset operation bit, reading data of the target preset operation bit, and comparing the read data with the corresponding written data; writing the preset test data to the target preset operation bit, reading data of the adjacent preset operation bit, and comparing the read data with the corresponding written data; writing the preset test data to the adjacent preset operation bit, reading data of the target preset operation bit, and comparing the read data with the corresponding written data.

4. The DRAM testing method of claim 1, wherein, the data read-write operations on the adjacent preset operation bits adjacent to the target preset operation bit comprise: first performing data read-write operations on the previous preset operation bit of the target preset operation bit, and then performing data read-write operations on the next preset operation bit of the target preset operation bit; Or, the data read-write operation is performed on the previous preset operation bit of the target preset operation bit after the data read-write operation is performed on the subsequent preset operation bit of the target preset operation bit. Or, the data read-write operation is performed on the previous preset operation bit and the subsequent preset operation bit of the target preset operation bit simultaneously.

5. The DRAM testing method of any one of claims 1 to 3, wherein, The test result of the DRAM to be tested is obtained according to the first comparison result and the second comparison result, and the test result includes: If the first comparison result and the second comparison result are consistent, the test result is success; otherwise, the test result is failure.

6. A DRAM testing apparatus, characterized by comprising: The test includes: The data read-write module is configured to perform two rounds of tests on the DRAM to be tested to obtain the first comparison result and the second comparison result respectively. The test includes: The preset test data is written into the DRAM to be tested until all the memory cells of the DRAM to be tested are written with data. The DRAM to be tested is traversed in units of preset operation bits until all the preset operation bits of the DRAM to be tested are traversed, and the preset operation bits include rows or columns. For the target preset operation bit traversed, data read-write operation is performed on the target preset operation bit and the adjacent preset operation bit adjacent to the target preset operation bit in a preset order based on the preset test data, and the read data is compared with the corresponding written data. The preset operation bits of the first round of test and the second round of test are different. The test module is configured to obtain the test result of the DRAM to be tested according to the first comparison result and the second comparison result. The data read-write operation includes: The data read-write operation is performed on the target preset operation bit and the previous preset operation bit and the subsequent preset operation bit of the target preset operation bit in a preset order based on the preset test data, and if the previous preset operation bit or the subsequent preset operation bit of the target preset operation bit does not exist, the data read-write operation of the previous preset operation bit or the subsequent preset operation bit is omitted.

7. A computer readable storage medium having stored thereon a computer program, characterized in that, The computer program is executed by the processor to realize each step in the DRAM test method according to any one of claims 1 to 5.

8. An electronic device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that, The processor executes the computer program to realize each step in the DRAM test method according to any one of claims 1 to 5.

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