Display panel and display device

Abstract

Embodiments of the present application provide a display panel and a display device. The display area of the display panel includes a center area and an edge area surrounding at least one side of the center area, the display panel includes a plurality of first light emitting units and a plurality of first pixel driving circuits located in the edge area, each of the first pixel driving circuits is electrically connected to a corresponding first light emitting unit and includes a first unit and a common transistor which are electrically connected to each other; wherein the first units of at least two first pixel driving circuits are electrically connected to the same common transistor.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel and a display device. BACKGROUND

[0002] With the development of multimedia, display devices become more and more important. Accordingly, the requirements for various types of display devices are increasingly high, especially in the field of smart phones, and in the future, extremely narrow frame display is the development requirement direction at present and in the future. Especially for high-resolution screens, the pixel size has reached the limit, and it is urgent to develop new compression technology to reduce the frame. SUMMARY

[0003] The embodiments of the present application provide a display panel and a display module, which can improve the technical problem of large frame of high-resolution display panel.

[0004] The embodiments of the present application provide a display panel, a display area of the display panel includes a center area and an edge area around at least one side of the center area, the display panel includes a plurality of first light emitting units located in the edge area, and a plurality of first pixel driving circuits located in the edge area, each first pixel driving circuit is electrically connected to the corresponding first light emitting unit, and includes a first unit and a common transistor which are electrically connected to each other; wherein the first units of at least two first pixel driving circuits are electrically connected to the same common transistor.

[0005] In some embodiments, the display panel further includes a plurality of second light emitting units and a plurality of second pixel driving circuits located in the center area, each second pixel driving circuit is electrically connected to the corresponding second light emitting unit, and includes a second unit and a second transistor which are electrically connected to each other and one-to-one corresponding, the circuit structure of the second unit is the same as that of the first unit, and the circuit structure of the second transistor is the same as that of the common transistor.

[0006] In some embodiments, the display panel includes a first active layer, the first active layer includes a common active pattern of the common transistor; a common source area of the common active pattern is electrically connected to a signal line, and a common drain area of the common active pattern is electrically connected to at least two first units.

[0007] In some embodiments, each first unit includes a driving transistor, the signal line includes a first reset signal line; the common source area of the common transistor is electrically connected to the first reset signal line, and the common drain area of the common transistor is electrically connected to the gate of the driving transistor of at least two first units.

[0008] In some embodiments, the common active pattern of the common transistor further comprises a common channel region; the common source region and the common drain region of the common transistor are located on two sides of the common channel region along a first direction, the common drain region comprises two first sub-regions located on two sides of the common channel region along a second direction intersecting the first direction, and the two first sub-regions are electrically connected to the gate of the driving transistor of the two first units respectively.

[0009] In some embodiments, each of the first units further comprises a compensation transistor, and the first active layer further comprises a compensation active pattern of the compensation transistor; a compensation channel region and a compensation source region of the compensation active pattern are connected to a side of the first sub-region of the corresponding common transistor away from the common channel region of the common transistor and extend along the first direction, the compensation channel region is located between the first sub-region and the compensation source region, the compensation source region is electrically connected to the source of the driving transistor, and the first sub-region is multiplexed as a compensation drain region of the compensation active pattern.

[0010] In some embodiments, a width of the first sub-region along the first direction is greater than a width of the common channel region along the second direction.

[0011] In some embodiments, the first reset signal line comprises a first part and a second part arranged at intervals, the source region of the common transistor is electrically connected between the first part and the second part through a bridge, and the bridge is arranged at a different layer from the first part and the second part.

[0012] In some embodiments, the first units of the two first pixel driving circuits are symmetrical about a center line of the common channel region of the common transistor along the first direction.

[0013] Embodiments of the present application also provide a display device comprising the display panel as described above and a housing mounting the display panel.

[0014] In the display panel and display device provided by the embodiments of the present application, by designing two or more pixel driving circuits located in the edge region of the display region to share a common thin film transistor and a signal line, the size of the pixel unit can be compressed, which is not limited by the limit of screen resolution and process capability, and the narrow frame effect of a high-resolution display panel can be achieved. BRIEF DESCRIPTION OF DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments description will be briefly introduced. Obviously, the drawings in the following description only represent some of the embodiments of the present application, and all of the other drawings can be obtained by those skilled in the art without any creative effort based on these drawings.

[0016] Figure 1 is a plane schematic diagram of a display panel provided by the embodiments of the present application;

[0017] Figure 2 is Figure 1 is a cross-sectional structural schematic diagram of the display panel in

[0018] Figure 3 is Figure 1 is a circuit schematic diagram of a first pixel driving circuit of the display panel in

[0019] Figure 4 is Figure 1 is a circuit schematic diagram of a second pixel driving circuit of the display panel in

[0020] Figure 5 is Figure 1 is a plane structural schematic diagram of the display panel in DETAILED DESCRIPTION

[0021] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments only represent some of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without any creative effort belong to the scope of protection of the present application. In addition, it should be understood that the specific embodiments described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, the orientation words such as "upper" and "lower" generally refer to the upper and lower in the actual use or working state of the device, and specifically refer to the direction of the drawing surface in the drawings. The "inner" and "outer" refer to the outline of the device.

[0022] As Figure 1As shown, an embodiment of the present application provides a display panel 1000. The display panel 1000 can be an organic light-emitting diode (OLED) display panel, a micro light-emitting diode (Micro LED) display panel, or a minature light-emitting diode (Mini LED) display panel. Exemplarily, the display panel 1000 is an OLED display panel.

[0023] The display panel 1000 includes a display area DA and a non-display area NDA. The display area DA can be an area for disposing sub-pixels for displaying images, and includes a center area CDA and a peripheral area PDA surrounding at least one side of the center area CDA. The non-display area NDA can be an area for disposing a driving unit such as a gate driving circuit for providing driving signals to pixel driving circuits of sub-pixels, and for disposing some traces for providing signals to the driving unit. Within the non-display area NDA, generally no sub-pixels for displaying are disposed. The non-display area NDA can be disposed at least one side of the display area DA to at least partially surround the display area DA.

[0024] Referring to Figure 2 , the display panel 1000 includes a substrate 1, a pixel driving circuit layer 2 on the substrate 1, a pixel definition layer 3 on the pixel driving circuit layer 2, and a light-emitting device layer 4 on the pixel driving circuit layer 2.

[0025] The substrate 1 is used to carry the film layers disposed thereon. The substrate 1 can include a single-layer insulating material such as glass, quartz, and polymer resin, or a multi-layer insulating material such as double-layer polymer resin. The substrate 1 can be a rigid substrate, or a flexible substrate.

[0026] The pixel driving circuit layer 2 is used to drive the light-emitting device layer 4 to emit light. The pixel driving circuit layer 2 includes, in sequence, a polycrystalline semiconductor layer ACT1 (i.e., a second active layer), a first insulating layer GI1, a first conductive layer GE1, a second insulating layer GI2, a second conductive layer GE2, a first interlayer dielectric layer ILD1, an oxide semiconductor layer ACT2 (i.e., a first active layer), a third insulating layer GI3, a third conductive layer GE3, a second interlayer dielectric layer ILD2, a fourth conductive layer SD1, a first planarization layer PLN1, a fifth conductive layer SD2, and a second planarization layer PLN2. These semiconductor layers, conductive layers, and intermediate film layers collectively form a plurality of pixel driving circuits PDC and a plurality of signal lines SGL.

[0027] The pixel definition layer 3 is provided with a plurality of pixel definition openings for exposing the first electrode layer 41 of the light emitting device layer 4 and accommodating the light emitting layer of the light emitting device layer 4.

[0028] The light emitting device layer 4 comprises a first electrode layer 41, a light emitting layer and a second electrode layer, the light emitting layer being electrically connected between the first electrode layer 41 and the second electrode layer. The first electrode layer 41 is electrically connected to the plurality of pixel driving circuits PDC through the fifth conductive layer SD2.

[0029] Please refer to Figure 1 , Figure 3 and Figure 4 , the plurality of pixel driving circuits PDC comprises a plurality of first pixel driving circuits PDC1 and a plurality of second pixel driving circuits PDC2, the plurality of first pixel driving circuits PDC1 are electrically connected to a plurality of first light emitting units EL1 of the light emitting layer for driving, and the plurality of second pixel driving circuits PDC2 are electrically connected to a plurality of first light emitting units EL2 of the light emitting layer for driving. Each of the first pixel driving circuit PDC1 and the corresponding first light emitting unit EL1 is located in the edge area PDA, the first pixel driving circuit PDC1 comprises a first unit U1 and a common transistor STFT which are electrically connected to each other, and the first units U1 of at least two first pixel driving circuits PDC1 are electrically connected to the same common transistor STFT. Each of the second pixel driving circuit PDC2 and the corresponding first light emitting unit EL2 is located in the center area CDA, the second pixel driving circuit PDC2 comprises a second unit U2 and a second transistor OTFT which are electrically connected to each other and one-to-one corresponding. Wherein, the circuit structure of the second unit U2 is the same as that of the first unit U1, and the circuit structure of the second transistor OTFT is the same as that of the common transistor STFT.

[0030] Please refer to Figure 3 , since the circuit structures of the first pixel driving circuit PDC1 and the second pixel driving circuit PDC2 are the same, the structure of the first pixel driving circuit PDC1 will be introduced as an example. The first unit U1 of each of the first pixel driving circuit PDC1 comprises a driving transistor T1, a data transistor T2, a compensation transistor T3, light emitting control transistors T5 and T6, an anode reset transistor T7, and a storage capacitor Cst. The common transistor STFT is a gate reset transistor T4.

[0031] The plurality of signal lines SGL include a high power voltage line ELVDD, a low power voltage line ELVSS, a data line Data, a first scan line PSCAN, a second scan line NSCAN, a third scan line NSCAN_1, an emission control signal line EM, and reset signal lines VI1 and VI2. The high power voltage line ELVDD is located in the fifth conductive layer SD2. The low power voltage line ELVSS is in the same layer as the cathode of the light emitting device layer 4. The data line Data and the reset signal line VI1 are located in the fourth conductive layer SD1. The second scan line NSCAN, the third scan line NSCAN_1, and the reset signal line VI2 are located in the second conductive layer GE2. The first scan line PSCAN and the emission control signal line EM are located in the first conductive layer GE1.

[0032] The source of the drive transistor T1 is electrically connected to the drain of the emission control transistor T5 and the drain of the data transistor T2, the drain of the drive transistor T1 is electrically connected to the source of the emission control transistor T6 and the source of the compensation transistor T3, and the gate of the drive transistor T1 is electrically connected to the drain of the compensation transistor T3 and the drain of the gate reset transistor T4.

[0033] The source of the data transistor T2 is electrically connected to the data line Data, and the gate of the data transistor T2 is electrically connected to the first scan line PSCAN.

[0034] The gate of the compensation transistor T3 is electrically connected to the second scan line NSCAN.

[0035] The source of the gate reset transistor T4 is electrically connected to the reset signal line VI2, and the gate of the gate reset transistor T4 is electrically connected to the third scan line NSCAN_1.

[0036] The source of the emission control transistor T5 is electrically connected to the high power voltage line ELVDD, and the gate of the emission control transistor T5 is electrically connected to the emission control signal line EM.

[0037] The drain of the emission control transistor T6 is electrically connected to the low power voltage line ELVSS through the first light emitting unit EL1, and the gate of the emission control transistor T6 is electrically connected to the emission control signal line EM.

[0038] The source of the anode reset transistor T7 is electrically connected to the reset signal line VI1, the drain of the anode reset transistor T7 is electrically connected to the anode of the first light emitting unit EL1, and the gate of the anode reset transistor T7 is electrically connected to the first scan line PSCAN.

[0039] The storage capacitor Cst is electrically connected between the high power voltage line ELVDD and the gate of the driving transistor T1.

[0040] Please refer to Figure 2 and Figure 5 The oxide semiconductor layer ACT2 includes a metal oxide material, such as indium gallium zinc oxide (IGZO). The oxide semiconductor layer ACT2 includes a compensation active pattern of the compensation transistor T3 and a common active pattern of the gate reset transistor T4. The polysilicon semiconductor layer ACT1 (i.e., the second active layer) includes active patterns of the rest of the transistors.

[0041] The common source region S1 and the common drain region D1 of the common active pattern are located on both sides of the common channel region C1 of the common active pattern along a first direction (the up-down direction in the figure). Moreover, the first unit U1 of the two first pixel driving circuits PDC1 is symmetric about the center line of the common channel region C1 of the common transistor STFT along the first direction. The common source region S1 is electrically connected to the reset signal line VI2 (i.e., the first reset signal line). The common drain region D1 includes two first sub-regions SUB located on both sides of the common channel region C1 along a second direction (the left-right direction in the figure) intersecting the first direction, and the two first sub-regions SUB are respectively electrically connected to the gate of the driving transistor T1 of the two first units U1, so that the common drain region D1 is electrically connected to the gate of the driving transistor T1 of at least two first units U1. Considering the spatial layout, the two first sub-regions SUB are designed to be arranged along the second direction, and since the first sub-region SUB needs to be electrically connected to the gate of the driving transistor T1, the width of the first sub-region SUB along the first direction is designed to be greater than the width of the common channel region C1 along the second direction. Figure 5 Considering the spatial layout, the compensation channel region C2 and the compensation source region S2 of the compensation active pattern are designed to be connected to the side of the first sub-region SUB of the corresponding gate reset transistor T4 away from the common channel region C1 of the gate reset transistor T4 and extend along the first direction, the compensation channel region C2 is located between the first sub-region SUB and the compensation source region S2, the compensation source region S2 is electrically connected to the source of the driving transistor T1, and the first sub-region SUB is multiplexed as a compensation drain region of the compensation active pattern.

[0042]

[0043] ​The reset signal line VI2 includes a first part PT1 and a second part PT2 arranged at intervals, and the common source region S1 of the common transistor STFT is electrically connected between the first part PT1 and the second part PT2 through a bridge BG. The bridge BG is arranged at a layer different from the first part PT1 and the second part PT2.

[0044] In the embodiment, by designing two or more pixel driving circuits PDC located in the edge region PDA of the display region DA to share the thin film transistor and the signal line, the size of the pixel unit can be compressed, which is not limited by the limit of screen resolution and process capability, and narrow frame can be achieved.

[0045] In other embodiments, the anode reset transistor T7 and the reset signal line VI1 can also be shared by similar principles.

[0046] In other embodiments, the thin film transistors of the pixel driving circuit PDC can all be low-temperature polysilicon thin film transistors.

[0047] The embodiment of the present application also provides a display device including the display panel 1000 and a housing for mounting the display panel 1000. Exemplarily, the display device can be a mobile terminal such as a smart phone, a tablet computer, can be a fixed terminal such as a television, a desktop television, or can be a wearable device such as smart glasses, a VR / AR device.

[0048] The above describes the embodiments of the present application in detail, and the principles and implementation modes of the present application are described by applying specific examples; the above embodiment descriptions are only used to help understand the method of the present application and its core idea; meanwhile, for those skilled in the art, according to the idea of the present application, the specific implementation mode and application range can be changed, and the above description should not be understood as limiting the present application.

Claims

1. A display panel, characterized by, The display area of the display panel includes a center area and an edge area surrounding at least one side of the center area, and the display panel comprises: a plurality of first light emitting units and a plurality of first pixel driving circuits located in the edge area, each first pixel driving circuit is electrically connected to a corresponding first light emitting unit and comprises a first unit and a common transistor which are electrically connected to each other; each first unit comprises a compensation transistor; wherein the first units of at least two first pixel driving circuits are electrically connected to the same common transistor; the display panel comprises a first active layer, the first active layer comprises a common active pattern of the common transistor and compensation active patterns of two compensation transistors; a common source region and a common drain region of the common transistor are located on both sides of a common channel region of the common transistor along a first direction, the common drain region comprises two first sub-regions located on both sides of the common channel region along a second direction intersecting the first direction, and the two first sub-regions are electrically connected to the two first units respectively; and the first sub-regions are multiplexed as a compensation drain region of the compensation active pattern.

2. The display panel of claim 1, wherein, Further comprising a plurality of second light emitting units and a plurality of second pixel driving circuits located in the center area, each second pixel driving circuit is electrically connected to a corresponding second light emitting unit and comprises a second unit and a second transistor which are electrically connected to each other and one-to-one corresponding, the circuit structure of the second unit is the same as that of the first unit, and the circuit structure of the second transistor is the same as that of the common transistor.

3. The display panel of claim 1, wherein, The common source region of the common active pattern is electrically connected to a signal line.

4. The display panel of claim 3, wherein, Each first unit comprises a driving transistor, the signal line comprises a first reset signal line; the common source region of the common transistor is electrically connected to the first reset signal line, and the common drain region of the common transistor is electrically connected to the gate of the driving transistor of at least two first units.

5. The display panel of claim 4, wherein, The two first sub-regions are electrically connected to the gates of the driving transistors of the two first units respectively.

6. The display panel of claim 5, wherein, The compensation channel region and the compensation source region of the compensation active pattern are connected to the side of the first sub-region of the corresponding common transistor away from the common channel region of the common transistor and extend along the first direction, the compensation channel region is located between the first sub-region and the compensation source region, and the compensation source region is electrically connected to the source of the driving transistor.

7. The display panel of claim 1, wherein, The width of the first sub-region along the first direction is greater than the width of the common channel region along the second direction.

8. The display panel of claim 5, wherein, The first reset signal line comprises a first part and a second part arranged at intervals, the common source region of the common transistor is electrically connected between the first part and the second part through a bridge part, and the bridge part is arranged in a layer different from the first part and the second part.

9. The display panel of claim 1, wherein, The first units of the two first pixel driving circuits are symmetric about the center line of the common channel region of the common transistor along the first direction.

10. A display device, characterized by comprising: The display panel comprises a display panel as claimed in any one of claims 1-9 and a housing mounting the display panel.

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