Display panel and display device

Abstract

This invention discloses a display panel and a display device. The display panel includes a first display area and a second display area, wherein the light transmittance of the first display area is greater than that of the second display area; a substrate; a first pixel driving circuit located in the second display area and disposed on one side of the substrate; a first sub-pixel located in the first display area and disposed on the side of the first pixel driving circuit away from the substrate, and electrically connected to the first pixel driving circuit through electrode traces; a capacitance compensation unit located in the first display area and disposed on the side of the first sub-pixel adjacent to the substrate; at least a portion of the orthographic projection of the capacitance compensation unit onto the substrate is covered by the orthographic projection of the first sub-pixel onto the substrate. The technical solution provided by the embodiments of this invention improves the display uniformity of the display panel.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] With the development of display technology, people's requirements for display technology are also getting higher and higher. The structure of the pixel driving circuit of the display panel is becoming more and more complex, which causes display differences in different areas of the transparent display area, resulting in uneven display in the transparent display area and affecting the display effect of the display panel. Summary of the Invention

[0003] The present invention provides a display panel and a display device to solve the problem of uneven display in the transparent display area due to display differences in different areas.

[0004] According to one aspect of the present invention, a display panel is provided, comprising: a first display area and a second display area, wherein the light transmittance of the first display area is greater than the light transmittance of the second display area;

[0005] substrate,

[0006] The first pixel driving circuit, located in the second display area, is disposed on one side of the substrate;

[0007] The first sub-pixel located in the first display area is disposed on the side of the first pixel driving circuit away from the substrate and is electrically connected to the first pixel driving circuit through electrode traces;

[0008] The capacitance compensation unit located in the first display area is disposed on the side of the first sub-pixel adjacent to the substrate;

[0009] At least a portion of the capacitance compensation unit's orthogonal projection onto the substrate is covered by the orthogonal projection of the first sub-pixel onto the substrate.

[0010] Optionally, the display panel may also include:

[0011] The first wiring layer is disposed on the side of the first sub-pixel adjacent to the substrate;

[0012] The second wiring layer is disposed on the side of the first wiring layer away from the substrate;

[0013] Electrode traces, including:

[0014] A first trace that is at least partially located in a first trace layer and a second trace that is at least partially located in a second trace layer, wherein the length of the second trace is less than the length of the first trace;

[0015] A capacitor compensation unit is provided corresponding to the first sub-pixel connected to the second trace.

[0016] Optionally, the first sub-pixel includes a first electrode and a light-emitting device; the first electrode is disposed on the side of the light-emitting device adjacent to the substrate, and the first electrode is connected to an electrode trace; the display panel further includes:

[0017] Multiple power cords

[0018] A first metal layer is disposed on the side of the first wiring layer adjacent to the substrate;

[0019] A second metal layer is disposed between the first metal layer and the first trace layer;

[0020] The capacitor compensation unit includes:

[0021] Multiple first compensation blocks, each first compensation block is located in a first metal layer and is connected to a power line;

[0022] Multiple second compensation blocks are located in the second metal layer and are connected to the first electrode.

[0023] The orthographic projection of the first compensation block onto the substrate and the orthographic projection of the second compensation block onto the substrate at least partially overlap.

[0024] Optionally, the orthographic projection of the first electrode connected to the second trace on the substrate at least partially covers the orthographic projection of the first compensation block on the substrate, and at least partially covers the orthographic projection of the second compensation block on the substrate.

[0025] Preferably, the orthographic projection of the first sub-pixel connected to the second trace on the substrate completely covers the orthographic projection of the first compensation block on the substrate, and completely covers the orthographic projection of the second compensation block on the substrate.

[0026] Optionally, the display panel may also include:

[0027] A third metal layer is disposed between the first trace layer and the second metal layer;

[0028] The capacitor compensation unit also includes:

[0029] Multiple third compensation blocks are located in the third metal layer and are connected to the power line.

[0030] The orthographic projection of the first electrode of at least a portion of the first sub-pixel connected to the second trace on the substrate at least partially covers the orthographic projection of the third compensation block on the substrate.

[0031] Optionally, the capacitor compensation unit may also include:

[0032] Multiple fourth compensation blocks are located on the first routing layer; the fourth compensation blocks are connected to the power lines.

[0033] The orthographic projection of the first electrode of the first sub-pixel onto the substrate at least partially overlaps with the orthographic projection of the fourth compensation block onto the substrate.

[0034] Optionally, the width of the second trace is greater than the width of the first trace;

[0035] The width of the second trace located in the first display area is greater than the width of the second trace located in the second display area.

[0036] Optional electrode traces may also include:

[0037] The third routing line has a length between the length of the first routing line and the length of the second routing line.

[0038] The first routing line is located on the first routing layer;

[0039] In the second display area, the second trace is at least partially located in the second trace layer; in the first display area, the second trace is at least partially located in the first trace layer.

[0040] In the second display area, the third trace is at least partially located in the second metal layer; in the first display area, the third trace is at least partially located in the first trace layer.

[0041] The electrode traces located in the first trace layer are connected to the first electrode of the first sub-pixel through vias.

[0042] Optionally, the display panel may also include:

[0043] A first insulating layer is disposed between a first metal layer and a second metal layer;

[0044] A second insulating layer is disposed between the third metal layer and the first trace layer;

[0045] A third insulating layer is disposed between the first wiring layer and the second wiring layer;

[0046] The thickness of the first insulating layer is less than the thickness of the second insulating layer, and less than the thickness of the third insulating layer;

[0047] Preferably, the dielectric constant of the first insulating layer is greater than that of the second insulating layer; the dielectric constant of the second insulating layer is the same as that of the third insulating layer.

[0048] According to another aspect of the present invention, a display device is provided, comprising: a display panel as described in any of the preceding items.

[0049] The technical solution of this invention involves setting a first pixel driving circuit in the second display area on one side of the substrate; and setting a first sub-pixel in the first display area on the side away from the substrate from the first pixel driving circuit, with the first sub-pixel electrically connected to the first pixel driving circuit via electrode traces. The first sub-pixel is located in the first display area, while the first pixel driving circuit for driving the first sub-pixel is located in the second display area. This allows for a larger number of first sub-pixels, eliminating the need for a low-transmittance first pixel driving circuit in the first display area and improving its transmittance. Furthermore, by setting a capacitance compensation unit in the first display area on the side of the substrate adjacent to the first sub-pixel, at least a portion of the capacitance compensation unit's projection onto the substrate is covered by the projection of the first sub-pixel onto the substrate. This allows capacitance compensation for the first sub-pixel in the first display area, ensuring that the coupling capacitance of the electrode traces of each first sub-pixel in the first display area is as consistent as possible. This improves the signal uniformity transmitted on the electrode traces, enhances the display uniformity of the first display area, and ultimately improves the display effect of the display panel.

[0050] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0051] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0052] Figure 1 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention;

[0053] Figure 2 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention;

[0054] Figure 3 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention;

[0055] Figure 4 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention;

[0056] Figure 5 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention;

[0057] Figure 6This is a schematic diagram of another display panel structure provided in an embodiment of the present invention;

[0058] Figure 7 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention;

[0059] Figure 8 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention;

[0060] Figure 9 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention. Detailed Implementation

[0061] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0062] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0063] As mentioned in the background section, the increasingly complex structure of pixel driving circuits in display panels leads to display differences in different areas of the transparent display area, resulting in uneven display and affecting the display effect of the display panel. The inventors discovered that to improve the light transmittance of the transparent display area, the pixel driving circuits of each sub-pixel in the transparent display area need to be located in the main display area. However, because the distance from the pixel driving circuits connected to each sub-pixel in the transparent display area to the transparent display area varies, the parasitic capacitance of the electrode traces of each sub-pixel in the transparent display area differs significantly, affecting the display uniformity of the transparent display area and consequently impacting the display effect of the display panel.

[0064] Figure 1 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention. Figure 2 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention. Figure 3 This is a schematic diagram of the structure of another display panel provided in an embodiment of the present invention. (Combined with...) Figures 1 to 3 The display panel 100 provided in this embodiment of the invention includes a first display area 10 and a second display area 20, wherein the light transmittance of the first display area 10 is greater than that of the second display area 20; a substrate 1; a first pixel driving circuit 2 located in the second display area 20 disposed on one side of the substrate 1; a first sub-pixel 3 located in the first display area 10 disposed on the side of the first pixel driving circuit 2 away from the substrate 1, and electrically connected to the first pixel driving circuit 2 through an electrode trace 4; a capacitance compensation unit 5 located in the first display area 10 disposed on the side of the first sub-pixel 3 adjacent to the substrate 1; at least a portion of the orthographic projection of the capacitance compensation unit 5 on the substrate 1 is covered by the orthographic projection of the first sub-pixel 3 on the substrate 1.

[0065] Specifically, the first display area 10 can be a transparent display area or a transitional display area, and the second display area 20 can be a main screen area or a transitional area. The first sub-pixel 3 of the first display area 10 is electrically connected to the first pixel driving circuit 2 located in the second display area 20 through electrode traces 4. The first sub-pixel 3 is driven by the first pixel driving circuit 2 located in the second display area 20. The first display area 10 does not have a first pixel driving circuit 2, so that the first display area 10 has high light transmittance, which is convenient for setting optical sensing devices such as optical sensors and camera devices that have high light transmittance requirements.

[0066] The first pixel driving circuit 2 is disposed on one side of the substrate 1, the first sub-pixel 3 is disposed on the side of the first pixel driving circuit 2 away from the substrate 1, and the capacitance compensation unit 5 is disposed on the side of the first sub-pixel 3 adjacent to the substrate 1. At least part of the orthographic projection of the capacitance compensation unit 5 onto the substrate 1 is covered by the orthographic projection of the first sub-pixel 3 onto the substrate 1, so that the capacitance compensation unit 5 can be at least partially covered by the first sub-pixel 3, thereby improving the light transmittance of the first display area 10.

[0067] The capacitance compensation unit 5 is disposed in the first display area 10. By setting at least part of the orthographic projection of the capacitance compensation unit 5 on the substrate 1 to be covered by the orthographic projection of the first sub-pixel 3 on the substrate 1, the first sub-pixel 3 and the capacitance compensation unit 5 can have at least part of the area facing each other. This can better adjust the capacitance of the first sub-pixel 3 that at least partially overlaps with the capacitance compensation unit 5, improve the display uniformity of each first sub-pixel 3 in the first display area 10, and thus improve the display effect of the display panel 100.

[0068] The technical solution provided in this embodiment involves setting a first pixel driving circuit 2 located in the second display area 20 on one side of the substrate 1; and setting a first sub-pixel 3 located in the first display area 10 on the side of the first pixel driving circuit 2 away from the substrate 1. The first sub-pixel 3 is electrically connected to the first pixel driving circuit 2 through an electrode trace 4. The first sub-pixel 3 is located in the first display area 10, and the first pixel driving circuit 2 used to drive the first sub-pixel 3 is located in the second display area 20. This allows for a larger number of first sub-pixels 3, eliminating the need for a first pixel driving circuit 2 with low light transmittance in the first display area 10, thus improving the light transmittance of the first display area 10. On the other hand, by setting the capacitance compensation unit 5 located in the first display area 10 on the side of the first sub-pixel 3 adjacent to the substrate 1, at least part of the orthographic projection of the capacitance compensation unit 5 on the substrate 1 is covered by the orthographic projection of the first sub-pixel 3 on the substrate 1. This allows the capacitance compensation unit 5 to perform capacitance compensation on the first sub-pixel 3 located in the first display area 10, making the coupling capacitance of the electrode traces 4 of each first sub-pixel 3 in the first display area 10 as consistent as possible, improving the uniformity of the signal transmitted on the electrode traces 4, improving the display uniformity of the first display area 10, and thus improving the display effect of the display panel 100.

[0069] Optionally, based on the above embodiments, see also... Figure 2 and Figure 3 The display panel 100 may also include a second sub-pixel 30 located in the second display area 20. The second sub-pixel 30 is driven by a second pixel driving circuit 40 located in the second display area 20. The arrangement of the first sub-pixel 30 and the second sub-pixel 30 may be the same.

[0070] It should be noted that this embodiment only illustrates the arrangement of the first sub-pixel 3 and the second sub-pixel 30 by way of example, and is not intended to limit the present invention. In other embodiments, the arrangement of the first sub-pixel 3 and the second sub-pixel 30 can be RGB arrangement, RGBG arrangement, pentile arrangement (diamond arrangement), RGBW arrangement, RGB Delta arrangement, RGB S-Strip arrangement, and other arrangement methods.

[0071] The shape of the first display area 10 can be square, circular, or racetrack-shaped, etc., and there is no limitation here. In one optional application scenario, the display panel 100 can be a full-screen display, and at least part of the first display area 10 is surrounded by the second display area 20.

[0072] Optional, Figure 4 This is a schematic diagram of another display panel provided in an embodiment of the present invention. Figure 5 This is a schematic diagram of another display panel provided in an embodiment of the present invention. Based on the above embodiments, and combined with… Figure 2 , Figure 4 and Figure 5 The display panel 100 provided in this embodiment of the invention may further include: a first wiring layer 6 disposed on the side of the first sub-pixel 3 adjacent to the substrate 1; a second wiring layer 7 disposed on the side of the first wiring layer 6 away from the substrate 1; an electrode wiring 4 including a first wiring 41 at least partially located in the first wiring layer 6 and a second wiring 42 at least partially located in the second wiring layer 7, wherein the length of the second wiring 42 is less than the length of the first wiring 41; and a capacitor compensation unit 5 is correspondingly disposed on the first sub-pixel 3 connected to the second wiring 42.

[0073] Specifically, the first wiring layer 6 and the second wiring layer 7 are used to set the electrode wirings 4. A portion of the first wiring 41 is located in the first wiring layer 6, and a portion of the second wiring 42 is located in the second wiring layer 7. Since the second wiring 42 is connected to the electrode of the first sub-pixel 3, the length of the second wiring 42 is relatively small. Because the length of the second wiring 42 is less than the length of the first wiring 41, the coupling capacitance between the second wiring 42 and the data lines and power lines of the display panel 100 is smaller than that of the first wiring 41. A capacitance compensation unit 5 is provided corresponding to the first sub-pixel 3 connected to the second wiring 42, which increases the capacitance of the first sub-pixel 3 connected to the second wiring 42 and reduces the capacitance difference between the electrode wirings 4 of the first sub-pixel 3 connected to the first wiring 41 and the electrode wirings 4 of the first sub-pixel 3 connected to the second wiring 42. This results in better display uniformity of each first sub-pixel 3 in the first display area 10, further improving the display effect of the display panel 100.

[0074] Optionally, based on the above embodiments, see also... Figure 5 The first sub-pixel 3 provided in this embodiment of the invention includes a first electrode 31 and a light-emitting device D1; the first electrode 31 is disposed on the side of the light-emitting device D1 adjacent to the substrate 1, and the first electrode 31 is connected to the electrode trace 4. The display panel 100 also includes multiple power lines (not shown in the figure); a first metal layer M1, which is disposed on the side of the first trace layer 6 adjacent to the substrate 1; and a second metal layer M2, which is disposed between the first metal layer M1 and the first trace layer 6. The capacitance compensation unit 5 includes multiple first compensation blocks 51, which are located on the first metal layer M1 and connected to the power lines; and multiple second compensation blocks 52, which are located on the second metal layer M2 and connected to the first electrode 31; the orthographic projection of the first compensation block 51 on the substrate 1 and the orthographic projection of the second compensation block 52 on the substrate 1 at least partially overlap.

[0075] Specifically, the first metal layer M1 can be disposed on one side of the substrate 1, and the gate of the driving transistor of the first pixel driving circuit 2 can be disposed on the first metal layer M1. The second metal layer M2 is disposed on the side of the first metal layer M1 away from the substrate 1, and the second metal layer M2 can be the first electrode plate of the capacitor of the first pixel driving circuit 2. The first compensation block 51 is disposed on the first metal layer M1 and connected to the power line. The second compensation block 52 is disposed on the second metal layer M2 and connected to the first electrode 31. The orthographic projection of the first compensation block 51 on the substrate 1 and the orthographic projection of the second compensation block 52 on the substrate 1 at least partially overlap, so that a coupling capacitance is formed between the first compensation block 51 and the second compensation block 52, which increases the capacitance of the first electrode 31 of the first sub-pixel 3 connected to the second compensation block 52, improves the display uniformity of the first display area 10 of the display panel 100, and further improves the display effect of the display panel 100.

[0076] One possible application scenario, see below. Figure 5 The first compensation block 51 can be connected to the power line through the traces of the first trace layer 6, and the second compensation block 52 can be connected to the first electrode 31 of the first sub-pixel 3 through the via and the traces of the second trace layer 7, so that the first compensation block 51 is connected to the voltage of the power supply, and the second compensation block 52 is connected to the voltage of the first electrode 31, thereby forming a coupling capacitor between the first compensation block 51 and the second compensation block 52.

[0077] Optionally, based on the above embodiments, see also... Figure 5 The display panel 100 provided in this embodiment of the invention has a first electrode 31 connected to the second trace 42 whose orthogonal projection on the substrate 1 at least partially covers the orthogonal projection of the first compensation block 51 on the substrate 1, and at least partially covers the orthogonal projection of the second compensation block 52 on the substrate 1.

[0078] Specifically, this arrangement further increases the facing area of ​​the first compensation block 51 and the second compensation block 52 of the capacitance compensation unit 5, increases the capacitance of the capacitance compensation unit 5, and thus increases the capacitance of the first sub-pixel 3 connected to the capacitance compensation unit 5, improving the display uniformity of the first display area 10. On the other hand, the orthographic projection of the first electrode 31 connected to the second trace 42 on the substrate 1 at least partially covers the orthographic projection of the first compensation block 51 on the substrate 1, and at least partially covers the orthographic projection of the second compensation block 52 on the substrate 1, reducing the occlusion of the first compensation block 51 and the second compensation block 52 on the first display area 10, and improving the light transmittance of the first display area 10.

[0079] Preferably, the orthographic projection of the first sub-pixel 3 connected to the second trace 42 on the substrate 1 completely covers the orthographic projection of the first compensation block 51 on the substrate 1, and completely covers the orthographic projection of the second compensation block 52 on the substrate 1.

[0080] Specifically, this arrangement further increases the facing area of ​​the first compensation block 51 and the second compensation block 52 of the capacitance compensation unit 5, resulting in a larger capacitance of the capacitance compensation unit 5. This, in turn, increases the capacitance of the first sub-pixel 3 connected to the capacitance compensation unit 5, further improving the display uniformity of the first display area 10. On the other hand, by ensuring that the orthographic projection of the first electrode 31 connected to the second trace 42 on the substrate 1 completely covers the orthographic projection of the first compensation block 51 on the substrate 1, and also completely covers the orthographic projection of the second compensation block 52 on the substrate 1, the obstruction of the first display area 10 by the first compensation block 51 and the second compensation block 52 can be effectively avoided, further improving the light transmittance of the first display area 10.

[0081] Optional, Figure 6 This is a schematic diagram of another display panel provided in an embodiment of the present invention. Based on the above embodiments, see... Figure 6 The display panel 100 provided in this embodiment of the invention may further include: a third metal layer M3, the third metal layer M3 being disposed between the first wiring layer 6 and the second metal layer M2; the capacitance compensation unit 5 may further include: a plurality of third compensation blocks 53, the third compensation blocks 53 being located in the third metal layer M3 and connected to the power line; the orthographic projection of the first electrode 31 of at least a portion of the first sub-pixels 3 connected to the second wiring 42 on the substrate 1 at least partially covers the orthographic projection of the third compensation blocks 53 on the substrate 1.

[0082] Specifically, the third metal layer M3 is disposed between the first trace layer 6 and the second metal layer M2. The third metal layer M3 may have a second electrode plate of the capacitor of the first pixel driving circuit 2. The third compensation block 53 of the capacitor compensation unit 5 is disposed on the third metal layer M3. Since the third compensation block 53 is disposed in the first display area 10 and is connected to the power line VDD, the potential of the third compensation block 53 is the voltage of the power supply. The orthographic projection of the first electrode 31 of at least a portion of the first sub-pixels 3 connected to the second trace 42 on the substrate 1 at least partially covers the orthographic projection of the third compensation block 53 on the substrate 1, so that the first electrode 31 and the third compensation block 53 have at least a partially facing area, forming a coupling capacitor. This increases the capacitance of the first electrode 31 of the first sub-pixels 3 connected to the second trace 42, further reduces the difference in capacitance of the first electrode 31 of each first sub-pixel 3 located in the first display area 10, further improves the display uniformity of the first display area 10, and thus improves the display effect of the display panel 100.

[0083] Optional, Figure 7 This is a schematic diagram of another display panel provided in an embodiment of the present invention. Based on the above embodiments, see... Figure 7The capacitance compensation unit 5 of the display panel 100 provided in this embodiment of the invention may further include: a plurality of fourth compensation blocks 54, the fourth compensation blocks 54 being located in the first wiring layer 6; the fourth compensation blocks 54 being connected to the power line VDD; and the orthographic projection of the first electrode 31 of the first sub-pixel 3 onto the substrate 1 and the orthographic projection of the fourth compensation blocks 54 onto the substrate 1 at least partially overlapping.

[0084] Specifically, the fourth compensation block 54 is located in the first trace layer 6. The material of the fourth compensation block 54 can be a transparent conductive material, such as ITO (indium tin oxide). The fourth compensation block 54 is connected to the power line, so that the potential of the fourth compensation block 54 is the voltage of the power supply. The orthographic projection of the first electrode 31 of the first sub-pixel 3 on the substrate 1 and the orthographic projection of the fourth compensation block 54 on the substrate 1 are at least partially overlapped, so that the first electrode 31 of the first sub-pixel 3 and the fourth compensation block 54 have at least a partially facing area, which further increases the capacitance of the first electrode 31 of the first sub-pixel 3 and further improves the display effect of the display panel 100.

[0085] Optionally, based on the above embodiments, see also... Figure 4 In this embodiment of the invention, the width of the second trace 42 of the display panel 100 is greater than the width of the first trace 41; the width of the second trace 42 located in the first display area 10 is greater than the width of the second trace 42 located in the second display area 20.

[0086] Specifically, this configuration allows the shorter second trace 42 to be wider, increasing the area of ​​the second trace 42 and thus increasing the overlap area between the second trace 42 and power lines VDD, data lines, etc., thereby increasing the parasitic capacitance of the second trace 42, further reducing the capacitance difference of each first sub-pixel 3 in the first display area 10, and further improving the display effect of the display panel 100.

[0087] The width of the second trace 42 located in the first display area 10 is set to be greater than the width of the second trace 42 located in the second display area 20, thereby increasing the facing area between the second trace 42 in the first display area 10 and the capacitor compensation unit 5, further increasing the capacitance of the first electrode 31 of the first sub-pixel 3 connected to the second trace 42, and further improving the display effect of the display panel 100.

[0088] Optional, Figure 8 This is a schematic diagram of another display panel provided in an embodiment of the present invention. Based on the above embodiments, and combined with… Figure 4 and Figure 8The electrode trace 4 may further include: a third trace 43, the length of which is between the length of the first trace 41 and the length of the second trace 42; the first trace 41 is located in the first trace layer 6; in the second display area 20, the second trace 42 is at least partially located in the second trace layer 7, and in the first display area 10, the second trace 42 is at least partially located in the first trace layer 6; in the second display area 20, the third trace 43 is at least partially located in the second metal layer M2, and in the first display area 10, the third trace 43 is at least partially located in the first trace layer 6; the electrode trace 4 located in the first trace layer 6 is connected to the first electrode 31 of the first sub-pixel 3 through a via.

[0089] Specifically, since the third trace 43 is located in the second metal layer M2, the third trace 43 can be an opaque metal trace. The capacitance formed by the third trace 43 and the power line VDD, data line, etc., is relatively large. The length of the third trace 43 is set between the length of the first trace 41 and the length of the second trace 42, so that the capacitance of the first electrode 31 of the first sub-pixel 3 connected to the third trace 43 is as consistent as possible with the capacitance of the first electrode 31 of the first sub-pixel 3 connected to the first trace 41, further improving the display uniformity of the first display area 10.

[0090] Since the first display area 10 requires high light transmittance, the third trace 43 and the second trace 42 located in the first display area 10 are both routed through the first trace layer 6. In the first display area 10, the electrode traces 4 located in the first trace layer 6 are connected to the first electrode 31 of the first sub-pixel 3 through vias. This arrangement further improves the light transmittance of the first display area 10.

[0091] Optionally, based on the above embodiments, see also... Figure 8 The display panel 100 may further include: a first insulating layer 101 disposed between a first metal layer M1 and a second metal layer M2; a second insulating layer 102 disposed between a third metal layer M3 and a first wiring layer 6; and a third insulating layer 103 disposed between the first wiring layer 6 and a second wiring layer 7. The thickness of the first insulating layer 101 is less than the thickness of the second insulating layer 102 and less than the thickness of the third insulating layer 103.

[0092] Specifically, the first insulating layer 101 can be an inorganic insulating layer, while the second insulating layer 102 and the third insulating layer 103 can be organic insulating layers. This arrangement results in a relatively thin first insulating layer 101 between the first metal layer M1 and the second metal layer M2, leading to a larger coupling capacitance between the first compensation block 51 and the second compensation block 52, and a larger coupling capacitance per unit area between them. This reduces the space occupied by the first compensation block 51 and the second compensation block 52 in the first display area 10, which has high light transmittance. This not only compensates for the capacitance of the first sub-pixel 3 but also ensures the light transmittance of the first display area 10, further improving the display effect and user experience of the display panel 100.

[0093] In one optional configuration, the thickness of the first insulating layer 101 may include 0.133 μm, and the thicknesses of the second insulating layer 102 and the third insulating layer 103 are both between 1.65 μm and 2.1 μm. The thicknesses of the second insulating layer 102 and the third insulating layer 103 may be set to be the same or different as needed, and no limitation is made here.

[0094] Preferably, the dielectric constant of the first insulating layer 101 is greater than that of the second insulating layer 102; the dielectric constant of the second insulating layer 102 is the same as that of the third insulating layer 103.

[0095] Specifically, the capacitance value is related to the facing area between the capacitor plates and the dielectric constant. A higher dielectric constant of the first insulating layer 101 results in a larger coupling capacitance per unit area between the first compensation block 51 and the second compensation block 52, further increasing the compensation capacitance between them. Setting the dielectric constant of the second insulating layer 102 to be the same as that of the third insulating layer 103 facilitates manufacturing and reduces production costs.

[0096] It should be noted that different capacitance compensation units 5 can be set according to the capacitance size of each first sub-pixel 3 in the first display area 10.

[0097] When the capacitance of the first electrode 31 of the first sub-pixel 3 is particularly small, a particularly large compensation capacitor is required. A particularly large capacitor can be formed by using the first compensation block 51 and the second compensation block 52.

[0098] When the capacitance of the first electrode 31 of the first sub-pixel 3 is small, a larger compensation capacitor is required. This can be achieved by using the third compensation block 53 and the fourth compensation block 54, together with the first electrode 31, to form a larger capacitor. The third compensation block 53 is connected to the first electrode 31, and the fourth compensation block 54 is connected to the power line. This creates coupling capacitors between the fourth compensation block 54 and the third compensation block 53, as well as between the fourth compensation block 54 and the first electrode 31, resulting in a larger capacitance for the first electrode 31 of the first sub-pixel 3.

[0099] When the capacitance of the first electrode 31 of the first sub-pixel 3 is slightly small, a smaller compensation capacitor is required. A fourth compensation block 54 can be used to form a smaller compensation capacitor with the first electrode 31. This arrangement can make the capacitance between each first sub-pixel 3 in the first display area 10 as consistent as possible, further reducing the difference in capacitance between each first sub-pixel 3, further improving the display uniformity of the first display area 10, and improving the display effect of the display panel 100.

[0100] It should be noted that, in order to improve the flatness of the first display area 10, a virtual compensation unit can be set at the corresponding position of the first sub-pixel where no capacitor compensation unit is set. The virtual compensation unit is not connected to a voltage signal, which facilitates the flatness of the first display area and further improves the user experience.

[0101] Figure 9 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention. See also: Figure 9 This invention provides a display device 200, including the display panel 100 described in any of the above embodiments, and possesses the beneficial effects of the display panel 100 described in any of the above embodiments, which will not be repeated here. The display device 200 provided in this invention can include terminals such as mobile phones, tablet computers, and wearable devices.

[0102] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0103] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A display panel, characterized in that, include: A first display area and a second display area, wherein the light transmittance of the first display area is greater than that of the second display area; substrate, The first pixel driving circuit located in the second display area is disposed on one side of the substrate; The first sub-pixel located in the first display area is disposed on the side of the first pixel driving circuit away from the substrate, and is electrically connected to the first pixel driving circuit through electrode traces; The capacitance compensation unit located in the first display area is disposed on the side of the first sub-pixel adjacent to the substrate; At least a portion of the capacitance compensation unit's orthographic projection onto the substrate is covered by the orthographic projection of the first sub-pixel onto the substrate; The display panel further includes: The first wiring layer is disposed on the side of the first sub-pixel adjacent to the substrate; The second wiring layer is disposed on the side of the first wiring layer away from the substrate; The electrode traces include: A first trace that is at least partially located in the first trace layer and a second trace that is at least partially located in the second trace layer, wherein the length of the second trace is less than the length of the first trace; The first sub-pixel connected to the second trace is provided with the capacitor compensation unit.

2. The display panel according to claim 1, characterized in that, The first sub-pixel includes a first electrode and a light-emitting device; the first electrode is disposed on the side of the light-emitting device adjacent to the substrate, and the first electrode is connected to the electrode trace; the display panel further includes: Multiple power cords A first metal layer is disposed on the side of the first wiring layer adjacent to the substrate; A second metal layer is disposed between the first metal layer and the first trace layer; The capacitance compensation unit includes: Multiple first compensation blocks, each first compensation block being located in the first metal layer and connected to a power line; Multiple second compensation blocks are located in the second metal layer and are connected to the first electrode. The orthographic projection of the first compensation block on the substrate and the orthographic projection of the second compensation block on the substrate at least partially overlap.

3. The display panel according to claim 2, characterized in that, The orthographic projection of the first electrode connected to the second trace on the substrate at least partially covers the orthographic projection of the first compensation block on the substrate, and at least partially covers the orthographic projection of the second compensation block on the substrate.

4. The display panel according to claim 3, characterized in that, The orthographic projection of the first sub-pixel connected to the second trace on the substrate completely covers the orthographic projection of the first compensation block on the substrate, and completely covers the orthographic projection of the second compensation block on the substrate.

5. The display panel according to claim 2, characterized in that, The display panel further includes: A third metal layer is disposed between the first trace layer and the second metal layer; The capacitor compensation unit further includes: Multiple third compensation blocks are located in the third metal layer and are connected to the power line; The orthographic projection of the first electrode of at least a portion of the first sub-pixel connected to the second trace on the substrate at least partially covers the orthographic projection of the third compensation block on the substrate.

6. The display panel according to claim 3, characterized in that, The capacitor compensation unit further includes: Multiple fourth compensation blocks are located on the first trace layer; the fourth compensation blocks are connected to the power lines. The orthographic projection of the first electrode of the first sub-pixel onto the substrate at least partially overlaps with the orthographic projection of the fourth compensation block onto the substrate.

7. The display panel according to claim 2, characterized in that, The width of the second trace is greater than the width of the first trace; The width of the second trace located in the first display area is greater than the width of the second trace located in the second display area.

8. The display panel according to claim 3, characterized in that, The electrode traces also include: The length of the third trace is between the length of the first trace and the length of the second trace; The first trace is located in the first trace layer; Within the second display area, the second trace is at least partially located in the second trace layer; within the first display area, the second trace is at least partially located in the first trace layer. Within the second display area, the third trace is at least partially located in the second metal layer; within the first display area, the third trace is at least partially located in the first trace layer. The electrode trace located in the first trace layer is connected to the first electrode of the first sub-pixel through a via.

9. The display panel according to claim 5, characterized in that, The display panel further includes: A first insulating layer is disposed between the first metal layer and the second metal layer; A second insulating layer is disposed between the third metal layer and the first trace layer; A third insulating layer is disposed between the first trace layer and the second trace layer; The thickness of the first insulating layer is less than the thickness of the second insulating layer and less than the thickness of the third insulating layer.

10. The display panel according to claim 9, characterized in that, The dielectric constant of the first insulating layer is greater than that of the second insulating layer; the dielectric constant of the second insulating layer is the same as that of the third insulating layer.

11. A display device, characterized in that, include: The display panel according to any one of claims 1-10.

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