An Improved ES-SCL Decoding Method for Polar Codes
By constructing the error set and setting parity bits in the polarization code, the ES-SCL decoding method of the polarization code is improved, the error correction performance under medium and short code length is improved and the decoding complexity is reduced.
Patent Information
- Application Number
- CN202211140736.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-09-20
- Publication Date
- 2025-08-08
- Estimated Expiration
- 2042-09-20
AI Technical Summary
The existing polarized code has poor block error rate performance under medium and short code length, and the existing parity code cascade polarized code scheme does not fully consider the channel characteristics of the polarized code, resulting in insufficient error correction capabilities.
Construct the error set, set the parity bit according to the channel characteristics of the polarization code. When decoding the parity bit, the decoder estimates the bit value through the check function, does not perform path splitting and pruning, and performs serial cancellation list decoding at other locations, and selects the path that passes the CRC check as the final output.
This improves the situation of missing correct paths during polarization coding, increases the difference in decoding paths, improves error correction performance, and reduces the decoding complexity.
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Figure CN115473537B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of channel coding technology and relates to an improved polar code ES-SCL (Successive Cancellation List based on the Error Set, ES-SCL) decoding method for channel coding. This method, based on the principles of Error Set (ES) construction, parity check (PC) codes, and a polar code serial cancellation list (SCL) decoding algorithm, improves the insufficient error correction performance of polar codes for short and medium code lengths. Background Art
[0002] Polar codes, proposed by Arikan, are the first type of codeword proven to achieve the channel capacity of a binary input memoryless symmetric channel and are a key technology for next-generation mobile communication systems. Polar codes have been successfully incorporated into the 5G standard as the coding scheme for control channels in 5G enhanced mobile broadband scenarios and are a current research hotspot in the field of channel coding. In addition to their achievable channel capacity, polar codes offer the distinct advantage of eliminating an error floor under serial cancellation decoding algorithms. However, when code length is limited and channel polarization is incomplete, the actual SC decoding algorithm exhibits significantly lower block error rate (BLER) performance than Turbo and LDPC codes.
[0003] Researchers have therefore proposed the Successive Cancellation List (SCL) decoding algorithm, which can retain multiple decoding paths, and the CA-SCL (CRC Aid SCL) decoding algorithm, which uses a CRC-Polar code cascaded with a cyclic redundancy check (CRC) code. At the end of decoding, the CA-SCL decoding algorithm selects the path with the smallest path metric (PM) from among the paths that pass the CRC check as the decoding output, improving the decoding performance of the SCL. Using the CA-SCL decoder, polar codes can achieve better BLER performance than existing LDPC codes of the same code length and code rate.
[0004] Since the CRC code is generally added at the end of the information sequence, it is impossible to detect errors that occur during the decoding process. Therefore, some scholars have proposed a scheme of cascading parity check (PC) codes to promptly correct errors that occur during the decoding process, thereby further improving the error correction capability of the polar code. The key to the parity check code cascade polar code scheme lies in the selection of the PC code position and the determination of the check function of the PC bit. Some scholars have proposed a parity check code assisted serial cancellation list (PC-SCL) decoding algorithm, which calculates the error probability P of each channel through Gaussian approximation. e , select P e The largest non-frozen bit is used as the position of the PC code, and each PC code only checks part of P e In addition, some scholars have proposed a parity check aided partial successive cancellation list (PC-PSCL) decoding algorithm based on parity check code cascaded polar code. Although this algorithm also calculates the error probability P of each channel through Gaussian approximation, e , but chooses P in some split bits e The smallest position is the position of the PC code, and each PC code also checks part P e Larger information bits. Since the above two parity-check code concatenated polar code schemes only rely on Gaussian approximation to select the position of the PC code and do not fully consider the channel characteristics of the polar code, they do not achieve significant performance improvement compared to the CA-SCL decoding algorithm. To address this problem, the present invention constructs an error set by analyzing the characteristics of the polarization channel in the polar code, and sets the PC bits according to the elements in the error set, thereby proposing an improved ES-SCL (Successive Cancellation List based on Error Set, ES-SCL) decoding method with a lower block error rate. Summary of the Invention
[0005] In light of this, the present invention aims to provide an improved ES-SCL decoding method for polar codes. This method first constructs an error set based on the channel characteristics of the polar code. During polar code encoding, PC bits are set based on the elements in the error set, while information bits and frozen bits are placed in the remaining positions. When decoding the PC bits, the decoder applies a check function to each path to obtain a bit estimate for the PC bits. Path splitting and pruning are not performed, and SCL decoding is performed on the remaining positions.
[0006] In order to achieve the above object, the present invention provides the following technical solutions:
[0007] First, the polar code length N, the number of information bits k, the number of parity check code bits m, and the number of CRC code bits r to be designed are selected. The reliability metric value of each channel is calculated using the Gaussian approximation method and sorted from high to low to obtain the split channel position index value sequence. The best k+m+r channels among the N polarized channels are selected to transmit the non-frozen bit set A, and the remaining Nkmr channels are used to transmit the frozen bit set A. c .
[0008] Then through A and A c Determine the rate-1 (R1) nodes and single-parity-check (SPC) nodes. The R1 node is a sub-polarization code block containing only information bits, and the SPC node is a sub-polarization code block in which all bits except the first bit are information bits. Then, sort the R1 and SPC nodes in descending order by node length. If two nodes have the same length, sort the node with the lower channel number first. Finally, add the first non-frozen bits of the sorted R1 and SPC nodes to the error set ES.
[0009] Then select the positions of k PC codes and calculate the value of each PC bit to complete the PC code encoding and obtain the encoded sequence at this time Again Perform CRC encoding to obtain Finally As the non-frozen bit set in the polar code, polar code encoding is performed to obtain the codeword
[0010] At the receiving end, a corresponding decoding method is used. Specifically, when the decoder decodes to the PC bit, each decoding path uses its own decoding result to calculate a decoding estimate for the PC bit using a check function. The PM is then updated based on the LLR at that point. When the decoder decodes other positions, it performs SCL decoding. After decoding, the path with the lowest PM among the paths that pass the CRC check is selected as the decoder output.
[0011] Finally, in the same simulation environment, a simulation comparison and analysis is performed between an improved ES-SCL decoding method for polar codes proposed in this patent and other similar decoding methods.
[0012] The beneficial effects of the present invention are:
[0013] An improved ES-SCL decoding method for polar codes is proposed. This method first constructs an error set based on the channel characteristics of polar codes. During polar code encoding, parity check bits (PC bits) are set based on the elements in the error set, while information bits and frozen bits are placed in the remaining positions. When decoding the PC bits, the decoder uses a check function to obtain a bit estimate for each PC bit, without performing path splitting or pruning. SCL decoding is performed on the remaining positions. This method has the following advantages: 1. It mitigates the loss of correct paths during SCL decoding; 2. It increases the codeword variance between decoding paths during the decoding process, enabling better discrimination between correct and incorrect paths. BRIEF DESCRIPTION OF THE DRAWINGS
[0014] In order to make the purpose, technical solutions and beneficial effects of the present invention more clear, the present invention provides the following drawings for illustration:
[0015] Figure 1 It is the technical roadmap of the method of the present invention;
[0016] Figure 2 Schematic diagram of a binary tree with a polar code length of 16;
[0017] Figure 3 Figure 2 compares the block error rate performance of five polar code decoding methods when the code length N = 512.
[0018] Figure 4 Figure 2 compares the block error rate performance of five polar code decoding methods when the code length N = 256.
[0019] Figure 5 is the average number of decoding rankings for different decoding methods. DETAILED DESCRIPTION
[0020] The preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
[0021] (1) Combined with attachment Figure 1 The specific implementation method of an improved ES-SCL decoding method in polar code is as follows:
[0022] In the polar code encoding stage, the code length N, the number of information bits k, the number of parity check bits m, and the number of CRC bits r of the polar code to be designed are first selected. The reliability metric value of each channel is calculated using the Gaussian approximation method and sorted from high to low to obtain the split channel position index value sequence. The best k+m+r channels among the N polarized channels are selected to transmit the non-frozen bit set A, and the remaining Nkmr channels are used to transmit the frozen bit set A. c , then through A and A cDetermine the R1 node and the SPC node. The R1 node is a sub-polar code block containing only information bits, and the SPC node is a sub-polar code block in which all bits except the first bit are information bits. Then, sort the R1 and SPC nodes in descending order by node length. If two nodes have the same length, sort the node with the lower channel number first. Finally, add the first non-frozen bits of the sorted R1 and SPC nodes to the error set ES.
[0023] Then select k PC code positions and calculate the value of each PC bit as shown in formula (1) to complete the PC code encoding and obtain the encoded sequence at this time Again Perform CRC encoding to obtain Finally As the non-frozen bit set in the polar code, polar code encoding is performed to obtain the codeword
[0024]
[0025] Among them S i Represents the set of information bits between the i-1th PC bit and the i-th PC bit.
[0026] At the receiving end, the value of the received signal is first converted into a logarithm likelihood ratio (LLR), as shown in formula (2).
[0027]
[0028] In formula (2), y i represents the received signal value of each bit, σ 2 represents the variance of the channel noise. Then each path obtains the decision LLR of each bit by performing the corresponding f and g operations.
[0029] L≈sign(L1)sign(L2)min{|L1||L2|} (3)
[0030] L=(1-2U1)L1+L2 (4)
[0031] Formula (3) represents the f operation which is easy to implement in hardware, and formula (4) represents the g operation, where L represents the LLR output by the operation, L1 and L2 represent the LLR input to the operation, and U1 represents the decoded estimated value of the previous bit input to the operation.
[0032] When the decoder decodes the PC bit, each decoding path calculates the decoding estimate of the PC bit according to its own decoding result through the check function shown in formula (1), and updates the PM according to the LLR at this time as shown in formula (5). When the decoder decodes other positions, it performs SCL decoding and selects the path with the smallest PM from the paths that pass the CRC check after decoding as the output result of the decoder.
[0033]
[0034] in represents the path metric value of the lth decoding path after decoding the i-th bit, represents the decoding estimate of the i-th bit in the l-th decoding path, represents the LLR of the decoding decision of the i-th bit in the l-th decoding path.
[0035] (2) Combined with attachment Figure 2 Explain the construction of error set:
[0036] Polar codes can be viewed as consisting of multiple sub-polar code blocks. In the figure, white leaf nodes represent frozen bits, black leaf nodes represent information bits, and gray nodes represent sub-blocks that contain both frozen bits and information bits. The sub-block {A, B, C, D, E} containing only information bits is called an R1 node, and the sub-block {F} containing only the first bit as a frozen bit and all other bits as information bits is called an SPC node. c Determine the R1 and SPC nodes in the polar code. Then, sort the lengths of the R1 and SPC nodes in descending order. If two nodes have the same length, put the node with the lower channel number first. Finally, add the first non-frozen bits of the sorted R1 and SPC nodes to the error set ES.
[0037] (3) Combined with attachment Figure 3 ,4,5 demonstrate the superiority of the proposed decoding method, as follows:
[0038] The CA-SCL decoding algorithm is the scheme proposed in the literature [1] "Niu Kai, Chen Kai. CRC-Aided Decoding of Polar Codes[J]. IEEE Communications Letters, 2012, 16(10): 1668-1671."
[0039] The PSS-SS-SCL decoding algorithm is the solution proposed in the literature [2] "Gao chenyu, Liu Rongke, Dai Bin, et al. Path Splitting Selecting Strategy-Aided Successive Cancellation List Algorithm for Polar Codes[J]. IEEE Communications Letters, 2019, 23(3): 422-425."
[0040] The PC-PSCL decoding algorithm is a scheme proposed in the literature [3] "A low-complexity decoding algorithm based on parity-check code cascaded polar code [J]. Journal of Electronics and Information Technology, 2022, 44(02): 637-645."
[0041] Since the PC-PSCL decoding algorithm in document [3] and the PSS-SS-SCL decoding algorithm in document [2] only perform path splitting on some non-frozen bits during decoding, the search set in document [2] is used to perform partial bit splitting decoding based on the ES-SCL decoding method proposed in the present invention, that is, the decoder only performs path splitting when decoding elements in the key set, and the ES-SCL decoding method of partial splitting decoding (abbreviated as PS-ES-SCL) is compared and analyzed with the PC-PSCL decoding algorithm in document [3] and the PSS-SS-SCL decoding algorithm in document [2]. Analysis of the SCL decoding process shows that when the number of decoding paths is greater than the maximum number of decoding lists L, the PMs need to be sorted, and L paths with smaller PMs need to be retained. Since the number of paths grows exponentially, sorting is required when decoding the (1+log2L)th non-frozen bit, and the sorting work is almost the most complex part of decoding each bit. Therefore, the present invention describes the decoding complexity of each method by counting the average number of sorting times for each decoding method. Figure 3 The code length N = 512, the code rate (k is the number of information bits transmitted), the block error rate simulation results of each algorithm, Figure 4 The code length N = 256, the code rate The block error rate simulation results for each algorithm are shown in Figure 2. All other simulation parameters are set identically, namely, the maximum number of decoding lists, L, is 8. The CA-SCL and PSS-SS-SCL decoding algorithms use a 16-bit CRC checksum. The PC-PSCL, ES-SCL, and partially split ES-SCL decoding algorithms all use an 8-bit PC code and an 8-bit CRC checksum. All algorithms use BPSK modulation, and the channel uses an additive white Gaussian noise channel. Figure 5 The average number of sorting times per decoding for each method with different code lengths was counted.
[0042] Depend on Figure 3 and Figure 4 It can be seen that the block error rate of the ES-SCL decoding method proposed in the present invention is lower than that of other decoding algorithms. -5 When N=512, the ES-SCL decoding method has a gain of about 0.15dB compared with the CA-SCL decoding algorithm. -5 , when N=256, the ES-SCL decoding method has a gain of about 0.3dB compared with the CA-SCL decoding algorithm. Figure 5 It can be seen that the decoding complexity of the ES-SCL decoding method proposed in this paper is almost the same as that of the CA-SCL decoding algorithm. Since the calculation of the PC bit value only involves a modulo-2 addition operation, it has little effect on the overall decoding complexity. Compared with the CA-SCL decoding algorithm, the ES-SCL decoding method only adds one error set construction step with an average time complexity of O(N+tlog2t) (N is the polar code length, and t represents the total number of R1 nodes and SPC nodes). Figure 3-5 It can also be seen that the block error rate of the PS-ES-SCL decoding method is almost the same as that of the PC-PSCL decoding algorithm in reference [3], but the number of required sorting times is reduced by 50%, resulting in lower decoding complexity. In addition, the PS-ES-SCL decoding method has a lower block error rate than the PSS-SS-SCL decoding algorithm in reference [2] when the number of sorting times is similar, further demonstrating the advantage of the present invention in improving the error correction performance of polar codes.
Claims
1. An improved ES-SCL (Successive Cancellation List based on the Error Set) decoding method for polar codes, characterized by: To address the insufficient error correction performance of polar codes with short or medium code lengths, an error set (ES) is first constructed based on the channel characteristics of polar codes. During polar code encoding, parity check (PC) bits are set based on the elements in the error set, while information bits and frozen bits are placed in the remaining positions. When decoding the PC bits, the decoder uses a check function to obtain a bit estimate of the PC bits for each path without performing path splitting or pruning. Serial Cancellation List (SCL) decoding is performed on the remaining positions. The method specifically includes the following steps: Step 1: Select the polar code length N, the number of information bits k, the number of parity check bits m, and the number of cyclic redundancy check (CRC) bits r to be designed. Use the Gaussian approximation method to calculate the reliability measurement parameter of each split channel. Then sort all split channels from high to low according to channel reliability to obtain the sorted split channel position index value sequence. Step 2: Select the first k+m+r split channels with the largest reliability, that is, The split channels corresponding to the first k+m+r index values are used to transmit the non-frozen bit set A, and the remaining Nkmr split channels are used to transmit the frozen bit set A (usually set to 0). c ; Step 3: Through the non-frozen bit set A, the frozen bit set A c Determine the rate-1 (R1) nodes and single-parity-check (SPC) nodes. The R1 node is a sub-polarization code block containing only information bits, and the SPC node is a sub-polarization code block in which all bits except the first bit are information bits. Then, sort the R1 and SPC nodes in descending order by node length. If two nodes have the same length, sort the node with the lower channel number first. Finally, add the first non-frozen bits of the sorted R1 and SPC nodes to the error set ES. Step 4: Select the first k elements in the constructed error set ES as the location to place the PC code, and then Segment and add m-bit parity check code to get the segmented sequence Step 5: Sequence Perform CRC encoding, Add r bits of CRC check code at the end to check all the previous bits to get the sequence Step 6: Sequence Polar code encoding is performed, and the sequence As a non-frozen bit, it is input into the polar code encoder for polar code encoding to obtain the polar code encoded codeword Then Incoming channel for transmission; Step 7: Decoding. During decoding, the receiver first converts the received signal into a log-likelihood ratio (LLR). It then calculates the decision LLR for each bit. If the current bit is a PC bit, each decoding path uses a check function to calculate the decoding estimate of the PC bit based on its own decoding result, and updates the path metric (PM) value based on the current LLR. When the decoder decodes other positions, it performs SCL decoding. After decoding, the path with the smallest PM is selected from the paths that pass the CRC check as the decoder output result.