Display devices

Abstract

The present invention discloses a display device. The display device includes: a first pixel configured to be located in a first pixel region and configured to be connected to a first scan line; a first scan stage circuit configured to be located in a first peripheral region disposed outside the first pixel region and configured to supply a first scan signal to the first scan line; a second pixel configured to be located in a second pixel region and configured to be connected to a second scan line; and a second scan stage circuit configured to be located in a second peripheral region disposed outside the second pixel region and configured to supply a second scan signal to the second scan line. The gap between adjacent second scan stage circuits is larger than the gap between adjacent first scan stage circuits.

Description

[0001] This application is a divisional application of the patent application with application number 201710816355.1 and title “DISPLAY DEVICE” filed on September 12, 2017.

[0002] Related applications

[0003] This application claims priority to and the benefit of Korean Patent Application No. 10-2016-0117555, filed on September 12, 2016, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0004] An exemplary embodiment according to the present disclosure relates to a display device. Background Art

[0005] With the development of information technology, the importance of display devices for providing an interface between users and information has become prominent. Various types of display devices including liquid crystal display devices, organic light emitting display devices, etc. have been widely used.

[0006] The display device includes a plurality of pixels and a driver for driving the pixels.

[0007] The driver may be embedded in the display device, in which case a dead space may be formed in the display device. Summary of the Invention

[0008] Exemplary embodiments of the present disclosure are to provide a display device capable of effectively utilizing a dead angle.

[0009] Furthermore, exemplary embodiments of the present disclosure are to provide a display apparatus having improved uniformity.

[0010] A display device according to an exemplary embodiment of the present disclosure includes: a first pixel, configured to be located in a first pixel area and configured to be connected to a first scan line; a first scan level circuit, configured to be located in a first peripheral area disposed outside the first pixel area and configured to supply a first scan signal to the first scan line; a second pixel, configured to be located in a second pixel area and configured to be connected to a second scan line; and a second scan level circuit, configured to be located in a second peripheral area disposed outside the second pixel area and configured to supply a second scan signal to the second scan line, wherein a gap between adjacent second scan level circuits is larger than a gap between adjacent first scan level circuits.

[0011] In some exemplary embodiments, the second pixel region may have a width smaller than that of the first pixel region.

[0012] In some exemplary embodiments, gaps between adjacent second scan stage circuits may be set differently from each other according to positions.

[0013] In some exemplary embodiments, the display device may further include: a dummy scanning stage circuit configured to be located between adjacent second scanning stage circuits.

[0014] In some exemplary embodiments, the number of dummy scan stage circuits may be set differently according to locations.

[0015] In some exemplary embodiments, the second scan stage circuit may include: a first pair of adjacent second scan stage circuits and a second pair of adjacent second scan stage circuits, and a gap between the second pair of adjacent second scan stage circuits may be larger than a gap between the first pair of adjacent second scan stage circuits.

[0016] In some exemplary embodiments, the display device may further include: at least one first dummy scan level circuit, arranged between a first pair of adjacent second scan level circuits; and a second dummy scan level circuit, arranged between a second pair of adjacent second scan level circuits, wherein the number of the second dummy scan level circuits may be greater than the number of the first dummy scan level circuits.

[0017] In some exemplary embodiments, the second pair of adjacent second scan stage circuits may be farther from the first peripheral area than the first pair of adjacent second scan stage circuits.

[0018] In some exemplary embodiments, the first pixel area may include a first sub-pixel area and a second sub-pixel area, the first peripheral area may include a first sub-peripheral area located outside the first sub-pixel area and a second sub-peripheral area located outside the second sub-pixel area, and the gap between a pair of adjacent first scanning level circuits located in the second sub-peripheral area may be larger than the gap between a pair of adjacent first scanning level circuits located in the first sub-peripheral area.

[0019] In some exemplary embodiments, the first sub-pixel region may be located between the second pixel region and the second sub-pixel region, and the first sub-peripheral region may be located between the second peripheral region and the second sub-peripheral region.

[0020] In some exemplary embodiments, the first scan stage circuit may be electrically connected to the first scan line through a first scan wiring, the second scan stage circuit may be electrically connected to the second scan line through a second scan wiring, and the length of the second scan wiring may be greater than that of the first scan wiring.

[0021] In some exemplary embodiments, the display device may further include: a third pixel configured to be located in a third pixel area and configured to be connected to a third scan line; and a third scan level circuit configured to be located in a third peripheral area disposed outside the third pixel area and configured to supply a third scan signal to the third scan line.

[0022] In some exemplary embodiments, the third pixel region may have a width smaller than that of the first pixel region and may be located at a position separated from the second pixel region.

[0023] In some exemplary embodiments, a gap between adjacent third scanning stage circuits may be larger than a gap between adjacent first scanning stage circuits.

[0024] In some exemplary embodiments, gaps between adjacent third scan stage circuits may be set differently from each other according to positions.

[0025] In some exemplary embodiments, the display device may further include: a dummy scanning stage circuit configured to be located between adjacent third scanning stage circuits.

[0026] In some exemplary embodiments, the number of dummy scan stage circuits may be set differently according to locations.

[0027] In some exemplary embodiments, the first scan level circuit may be electrically connected to the first scan line via a first scan wiring, the second scan level circuit may be electrically connected to the second scan line via a second scan wiring, the third scan level circuit may be electrically connected to the third scan line via a third scan wiring, and the lengths of the second scan wiring and the third scan wiring may be greater than the length of the first scan wiring.

[0028] In some exemplary embodiments, the display device may further include: a first emission level circuit, configured to be located in the first peripheral area and configured to supply a first emission control signal to the first pixel through a first emission control line; and a second emission level circuit, configured to be located in the second peripheral area and configured to supply a second emission control signal to the second pixel through a second emission control line.

[0029] In some exemplary embodiments, a gap between adjacent second emitter stage circuits may be larger than a gap between adjacent first emitter stage circuits.

[0030] In some exemplary embodiments, the gap between adjacent second transmitter stage circuits may be set differently depending on the location.

[0031] In some exemplary embodiments, the display device may further include: a dummy emitter stage circuit configured to be located between adjacent second emitter stage circuits.

[0032] In some exemplary embodiments, the number of dummy transmitter stage circuits may be set differently depending on the location.

[0033] According to exemplary embodiments of the present disclosure, a display device capable of effectively utilizing a dead angle can be provided.

[0034] Furthermore, according to another exemplary embodiment of the present disclosure, a display device having improved uniformity may be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 is a diagram illustrating a pixel area of ​​a display device according to an embodiment of the present disclosure.

[0036] Figure 2 is a diagram illustrating a display device according to an embodiment of the present disclosure.

[0037] Figure 3 is a more detailed diagram of a display device according to one embodiment of the present disclosure.

[0038] Figure 4 yes Figure 3 A more detailed diagram of the scan driver and transmit driver is shown.

[0039] Figure 5 1 is a diagram illustrating a layout structure of a scanning stage circuit and an emission stage circuit according to an embodiment of the present disclosure.

[0040] Figure 6A and Figure 6B is a diagram illustrating a layout structure of a second scanning stage circuit and a second emission stage circuit according to various embodiments of the present disclosure.

[0041] Figure 7 is a diagram illustrating a second scan driver and a second emission driver according to another embodiment of the present disclosure.

[0042] Figure 8 is a diagram illustrating a layout structure of a dummy stage circuit according to one embodiment of the present disclosure.

[0043] Figure 9A and Figure 9B is a diagram illustrating a layout structure of a dummy stage circuit according to various embodiments of the present disclosure.

[0044] Figure 10 1 is a diagram illustrating a layout structure of a first scanning stage circuit and a first emission stage circuit according to an embodiment of the present disclosure.

[0045] Figure 11 is a diagram illustrating a scanning stage circuit according to one embodiment of the present disclosure.

[0046] Figure 12 It shows Figure 11 The waveform diagram of the driving method of the scanning stage circuit shown.

[0047] Figure 13 is a diagram illustrating a transmitter stage circuit according to one embodiment of the present disclosure.

[0048] Figure 14 It shows Figure 13 The waveform diagram of the driving method of the emitter stage circuit is shown.

[0049] Figure 15 is a diagram illustrating a pixel according to one embodiment of the present disclosure.

[0050] Figure 16 is a diagram illustrating a pixel area of ​​a display device according to another embodiment of the present disclosure.

[0051] Figure 17 is a diagram illustrating a display device according to another embodiment of the present disclosure.

[0052] Figure 18 is a more detailed diagram of a display device according to another embodiment of the present disclosure.

[0053] Figure 19 yes Figure 18 A more detailed diagram of the third scan driver and the third emission driver is shown.

[0054] Figure 20 is a diagram illustrating a layout structure of a third scanning stage circuit and a third emission stage circuit according to one embodiment of the present disclosure.

[0055] Figure 21 is a diagram illustrating a layout structure of a dummy stage circuit according to one embodiment of the present disclosure. DETAILED DESCRIPTION

[0056] The specific contents of this embodiment are described with reference to the specification and drawings.

[0057] In view of the accompanying drawings and the embodiments to be described in detail, the advantages and features of the present disclosure and their implementation methods will become more apparent. However, the present disclosure is not limited to the embodiments to be described below and can be implemented in various forms that may be different from each other. In the case described below as one unit being connected to another unit, the connection includes not only a direct connection but also an electrical connection through a certain element. In addition, in order to make the description of the present disclosure clear, parts not related to the present disclosure are omitted in the accompanying drawings, and the same symbols or figure marks are attached to similar configuration elements throughout the specification.

[0058] Hereinafter, a display device according to an embodiment of the present disclosure will be described with reference to the embodiment of the present disclosure and related drawings.

[0059] Figure 1 is a diagram illustrating a pixel area of ​​a display device according to an embodiment of the present disclosure.

[0060] like Figure 1 As shown, the display device 10 according to one embodiment of the present disclosure may include pixel areas AA1 and AA2 and peripheral areas NA1 and NA2.

[0061] The pixel areas AA1 and AA2 may include a plurality of pixels PXL1 and PXL2 to display a predetermined image. Therefore, the pixel areas AA1 and AA2 may be referred to as display areas.

[0062] The peripheral areas NA1 and NA2 may include configuration elements (eg, drivers and wires) for driving the pixels PXL1 and PXL2 . The peripheral areas NA1 and NA2 may not include the pixels PXL1 and PXL2 , and thus, the peripheral areas NA1 and NA2 may be referred to as non-display areas.

[0063] For example, the peripheral areas NA1 and NA2 may be located outside the pixel areas AA1 and AA2 and may have a shape surrounding at least a portion of the pixel areas AA1 and AA2.

[0064] The pixel areas AA1 and AA2 may include a first pixel area AA1 and a second pixel area AA2 .

[0065] The second pixel area AA2 may be located at one side of the first pixel area AA1 and may have a smaller area than the first pixel area AA1.

[0066] For example, the width W2 of the second pixel area AA2 may be set to be smaller than the width W1 of the first pixel area AA1 , and the length L2 of the second pixel area AA2 may be set to be smaller than the length L1 of the first pixel area AA1 .

[0067] The peripheral areas NA1 and NA2 may include a first peripheral area NA1 and a second peripheral area NA2.

[0068] The first peripheral area NA1 may be located at a periphery of the first pixel area AA1 and may have a shape surrounding at least a portion of the first pixel area AA1.

[0069] The width of the first peripheral area NA1 may be set to be substantially uniform along the periphery surrounding the first pixel area AA1 . The width of the first peripheral area NA1 is not limited thereto and may be set differently depending on the location.

[0070] The second peripheral area NA2 may be located at the periphery of the second pixel area AA2 and may have a shape surrounding at least a portion of the second pixel area AA2.

[0071] The width of the second peripheral area NA2 may be set to be substantially uniform along the periphery surrounding the second pixel area AA2 . The width of the second peripheral area NA2 is not limited thereto and may be set differently depending on the location.

[0072] The pixels PXL1 and PXL2 may include a first pixel PXL1 and a second pixel PXL2 .

[0073] For example, the first pixel PXL1 may be located in the first pixel area AA1 , and the second pixel PXL2 may be located in the second pixel area AA2 .

[0074] The pixels PXL1 and PXL2 may emit light at a predetermined brightness according to control of a driver, and may include one or more light emitting elements (eg, organic light emitting diodes) for emitting light.

[0075] Pixel areas AA1 and AA2 and peripheral areas NA1 and NA2 may be defined on the substrate 100 of the display unit 10 .

[0076] The substrate 100 may be formed in various forms capable of setting the pixel areas AA1 and AA2 and the peripheral areas NA1 and NA2 .

[0077] For example, the substrate 100 may include a base substrate 101 having a planar shape and an auxiliary plate 102 protruding from one end portion of the base substrate 101 to extend to one side.

[0078] According to one embodiment, the auxiliary plate 102 may have an area smaller than that of the base substrate 101. For example, the width of the auxiliary plate 102 may be set smaller than that of the base substrate 101, and the length of the auxiliary plate 102 may be set smaller than that of the base substrate 101.

[0079] The auxiliary plate 102 may have a shape that is the same as or similar to that of the second pixel area AA2 , but is not limited thereto and may have a shape that is different from that of the second pixel area AA2 .

[0080] The substrate 100 may be made of an insulating material such as glass, resin, etc. In addition, the substrate 100 may be made of a flexible material so as to be bent or folded, and may have a single-layer structure or a multi-layer structure.

[0081] For example, the substrate 100 may include at least one of polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose triacetate, and cellulose acetate propionate.

[0082] The material constituting the substrate 100 can be variously changed, and may be composed of fiberglass reinforced plastic (FRP) or the like.

[0083] The first pixel area AA1 and the second pixel area AA2 may have various shapes. For example, each of the first pixel area AA1 and the second pixel area AA2 may have a shape such as a polygonal shape, a ring shape, or the like.

[0084] Figure 1 A case where each of the first pixel area AA1 and the second pixel area AA2 has a quadrangle is exemplarily shown.

[0085] According to one embodiment, at least a portion of the first pixel area AA1 may have a curved shape.

[0086] For example, a corner portion of the first pixel area AA1 may have a curved shape having a predetermined curvature.

[0087] In this case, the first peripheral area NA1 may include at least a portion having a curved shape so as to correspond to the curved shape of the first pixel area AA1.

[0088] According to the shape variation of the first pixel area AA1 , the number of first pixels PXL1 located in one line (row or column) may vary according to positions.

[0089] In addition, at least a portion of the second pixel area AA2 may have a curved shape. For example, a corner of the second pixel area AA2 may have a curved shape having a predetermined curvature.

[0090] In this case, the second peripheral area NA2 may include at least a portion having a curved shape so as to correspond to the curved shape of the second pixel area AA2.

[0091] According to the shape variation of the second pixel area AA2 , the number of second pixels PXL2 located in one line (row or column) may be changed according to positions.

[0092] Figure 2 is a diagram illustrating a display device according to an embodiment of the present disclosure.

[0093] like Figure 2As shown, the display unit 10 may include a substrate 100 , a first pixel PXL1 , a second pixel PXL2 , a first scan driver 210 , a second scan driver 220 , a first emission driver 310 , and a second emission driver 320 .

[0094] The first pixel PXL1 may be located in the first pixel area AA1 and may be connected to the first scan line S1 , the first emission control line E1 , and the first data line D1 , respectively.

[0095] The first scan driver 210 may supply a first scan signal to the first pixel PXL1 through the first scan line S1 .

[0096] For example, the first scan driver 210 may sequentially supply the first scan signal to the first scan lines S1 .

[0097] The first scan driver 210 may be located in the first peripheral area NA1 .

[0098] For example, the first scan driver 210 may be located at one side of the first pixel area AA1 (eg, as shown in FIG. 2 ). Figure 2 In the first peripheral area NA1 (left side shown).

[0099] The first scan wiring R1 may be connected between the first scan driver 210 and the first scan line S1 .

[0100] Accordingly, the first scan driver 210 may be electrically connected to the first scan line S1 located in the first pixel area AA1 through the first scan wiring R1 .

[0101] The first emission driver 310 may supply a first emission control signal to the first pixel PXL1 through the first emission control line E1 .

[0102] For example, the first emission driver 310 may sequentially supply the first emission control signals to the first emission control lines E1 .

[0103] The first emission driver 310 may be located in the first peripheral area NA1 .

[0104] For example, the first emission driver 310 may be located at one side of the first pixel area AA1 (eg, as shown in FIG. 1 ). Figure 2 In the first peripheral area NA1 (left side shown).

[0105] Figure 2 The first emission driver 310 is shown as being located outside the first scan driver 210. However, in another embodiment, the first emission driver 310 may be located inside the first scan driver 210.

[0106] The third emission wiring R3 may be connected between the first emission driver 310 and the first emission control line E1 .

[0107] Accordingly, the first emission driver 310 may be electrically connected to the first emission control line E1 located in the first pixel area AA1 through the third emission wiring R3 .

[0108] Meanwhile, if the first pixel PXL1 has a structure that does not require the first emission control signal, the first emission driver 310 , the third emission wiring R3 , and the first emission control line E1 may be omitted.

[0109] The second pixel PXL2 may be located in the second pixel area AA2 and may be connected to the second scan line S2 , the second emission control line E2 , and the second data line D2 .

[0110] The second scan driver 220 may supply a second scan signal to the second pixel PXL2 through the second scan line S2 .

[0111] For example, the second scan driver 220 may sequentially supply the second scan signal to the second scan lines S2 .

[0112] The second scan driver 220 may be located in the second peripheral area NA2 .

[0113] For example, the second scan driver 220 may be located at one side of the second pixel area AA2 (eg, Figure 2 In the second peripheral area NA2 (on the left side).

[0114] The second scan wiring R2 may be connected between the second scan driver 220 and the second scan line S2 .

[0115] Accordingly, the second scan driver 220 may be electrically connected to the second scan line S2 located in the second pixel area AA2 through the second scan wiring R2.

[0116] The second emission driver 320 may supply a second emission control signal to the second pixel PXL2 through the second emission control line E2 .

[0117] For example, the second emission driver 320 may sequentially supply the second emission control signals to the second emission control lines E2.

[0118] The second emission driver 320 may be located in the second peripheral area NA2 .

[0119] For example, the second emission driver 320 may be located at one side of the second pixel area AA2 (eg, as shown in FIG. 1 ). Figure 2 In the second peripheral area NA2 (on the left side shown).

[0120] Figure 2 The second emission driver 320 is shown as being located outside the second scan driver 220. However, in another embodiment, the second emission driver 320 may be located inside the second scan driver 220.

[0121] The fourth emission wiring R4 may be connected between the second emission driver 320 and the second emission control line E2.

[0122] Accordingly, the second emission driver 320 may be electrically connected to the second emission control line E2 located in the second pixel area AA2 through the fourth emission wiring R4.

[0123] Meanwhile, if the second pixel PXL2 has a structure that does not require the second emission control signal, the second emission driver 320 , the fourth emission wiring R4 , and the second emission control line E2 may be omitted.

[0124] Since the second pixel area AA2 has an area smaller than that of the first pixel area AA1 , the lengths of the second scan line S2 and the second emission control line E2 may be smaller than those of the first scan line S1 and the first emission control line E1 .

[0125] In addition, the number of second pixels PXL2 connected to the second scan line S2 may be less than the number of first pixels PXL1 connected to the first scan line S1, and the number of second pixels PXL2 connected to the second emission control line E2 may be less than the number of first pixels PXL1 connected to the first emission control line E1.

[0126] The emission control signal may be used to control the emission time of the pixels PXL1 and PXL2. According to one embodiment, the emission control signal may be set to have a width greater than that of the scan signal.

[0127] For example, the emission control signal may be set to a gate-off voltage (e.g., a high-level voltage) so that the transistors included in the pixels PXL1 and PXL2 may be turned off, and the scan signal may be set to a gate-on voltage (e.g., a low-level voltage) so that the transistors included in the pixels PXL1 and PXL2 may be turned on.

[0128] The data driver 400 may supply data signals to the pixels PXL1 and PXL2 through the data lines D1 and D2. For example, the second data line D2 may be connected to a portion of the first data line D1.

[0129] The data driver 400 may be located in the first peripheral area NA1, and specifically, may be disposed at a position not overlapping the first scan driver 210. For example, the data driver 400 may be located in the first peripheral area NA1 disposed at a lower side of the first pixel area AA1.

[0130] The data driver 400 may be provided in various types such as chip on glass, chip on plastic, tape carrier package, chip on film, and the like.

[0131] For example, the data driver 400 may be directly mounted on the substrate 100 or may be connected to the substrate 100 through other elements (eg, a flexible printed circuit board).

[0132] At the same time, although Figure 2 Although not shown in the figures, the display unit 10 may further include a timing controller that supplies predetermined signals to the scan drivers 210 and 220 , the emission drivers 310 and 320 , and the data driver 400 .

[0133] Figure 3 is a more detailed diagram of a display device according to one embodiment of the present disclosure.

[0134] The first scan driver 210 may supply the first scan signal to the first pixel PXL1 through the first scan wirings R11 to R1 k and the first scan lines S11 to S1 k.

[0135] The first scan wirings R11 to R1k may be connected between the output terminals of the first scan driver 210 and the first scan lines S11 to S1k.

[0136] For example, the first scan wirings R11 to R1k and the first scan lines S11 to S1k may be located at different layers from each other, and in this case, may be connected to each other through a contact hole (not shown).

[0137] The first emission driver 310 may supply the first emission control signal to the first pixel PXL1 through the first emission wirings R31 to R3 k and the first emission control lines E11 to E1 k.

[0138] The first emission wirings R31 to R3k may be connected between the output terminal of the first emission driver 310 and the first emission control lines E11 to E1k.

[0139] For example, the first emission wirings R31 to R3 k and the first emission control lines E11 to E1 k may be located at different layers from each other, and in this case, may be connected to each other through contact holes (not shown).

[0140] The first scan driver 210 and the first emission driver 310 may operate in response to a first scan control signal SCS1 and a first emission control signal ECS1 , respectively.

[0141] The data driver 400 may supply data signals to the first pixels PXL1 through the first data lines D11 to D1o.

[0142] The first pixel PXL1 may be connected to a first pixel power source ELVDD and a second pixel power source ELVSS. If necessary, the first pixel PXL1 may be further connected to an initialization power source Vint.

[0143] When the first scan signal is supplied to the first scan lines S11 to S1k, the first pixel PXL1 can receive the data signal from the first data lines D11 to D1o, and the first pixel PXL1 receiving the data signal can control the current flowing from the first pixel power source ELVDD to the second pixel power source ELVSS through the organic light emitting diode (not shown).

[0144] In addition, the number of first pixels PXL1 located in one line (row or column) may vary depending on the location.

[0145] The second scan driver 220 may supply the second scan signal to the second pixel PXL2 through the second scan wirings R21 to R2 j and the second scan lines S21 to S2 j.

[0146] The second scan wirings R21 to R2j may be connected between the output terminals of the second scan driver 220 and the second scan lines S21 to S2j.

[0147] For example, the second scan wirings R21 to R2j and the second scan lines S21 to S2j may be located at different layers from each other, and in this case, may be connected to each other through a contact hole (not shown).

[0148] The second emission driver 320 may supply the second emission control signal to the second pixel PXL2 through the second emission wirings R41 to R4j and the second emission control lines E21 to E2j.

[0149] The second emission path wirings R41 to R4j may be connected between the output terminals of the second emission driver 320 and the second emission control lines E21 to E2j.

[0150] For example, the second emission wirings R41 to R4j and the second emission control lines E21 to E2j may be located at different layers from each other, and in this case, may be connected to each other through a contact hole (not shown).

[0151] The second scan driver 220 and the second emission driver 320 may operate in response to the second scan control signal SCS2 and the second emission control signal ECS2, respectively.

[0152] The data driver 400 may supply data signals to the second pixels PXL2 through the second data lines D21 to D2p.

[0153] For example, the second data lines D21 to D2p may be connected to a partial subset of the first data lines, and in this embodiment, may be connected to the first data lines D11 to D1m-1.

[0154] In addition, the second pixel PXL2 may be connected to the first pixel power source ELVDD and the second pixel power source ELVSS. If necessary, the second pixel PXL2 may be further connected to an initialization power source Vint.

[0155] When the second scan signal is supplied to the second scan lines S21 to S2j, the second pixel PXL2 can receive the data signal from the second data line D21 to D2p, and the second pixel PXL2 receiving the data signal can control the current flowing from the first pixel power supply ELVDD to the second pixel power supply ELVSS through the organic light emitting diode (not shown).

[0156] In addition, the number of second pixels PXL2 located in one line (row or column) may be changed according to positions.

[0157] The data driver 400 may operate in response to the data control signal DCS.

[0158] Since the second pixel area AA2 has an area smaller than that of the first pixel area AA1, the number of second pixels PXL2 can be less than the number of first pixels PXL1, and the length and number of the second scan lines S21 to S2j and the second emission control lines E21 to E2j can be set to be less than the length and number of the first scan lines S11 to S1k and the first emission control lines E11 to E1k, respectively.

[0159] The number of second pixels PXL2 connected to any one of the second scan lines S21 to S2j may be less than the number of first pixels PXL1 connected to any one of the first scan lines S11 to S1k.

[0160] In addition, the number of second pixels PXL2 connected to any one of the second emission control lines E21 to E2j may be less than the number of first pixels PXL1 connected to any one of the first emission control lines E11 to E1k.

[0161] The timing controller 270 may control the first scan driver 210 , the second scan driver 220 , the data driver 400 , the first emission driver 310 , and the second emission driver 320 .

[0162] The timing controller 270 may supply first and second scan control signals SCS1 and SCS2 to the first and second scan drivers 210 and 220 , respectively, and may supply first and second emission control signals ECS1 and ECS2 to the first and second emission drivers 310 and 320 , respectively.

[0163] Each of the scan control signals SCS1 and SCS2 and the emission control signals ECS1 and ECS2 may include at least one clock signal and a start pulse.

[0164] The start pulse can control the timing of the first scan signal or the first emission control signal. The clock signal can be used to shift the start pulse.

[0165] According to one embodiment, the timing controller 270 may supply the data control signal DCS to the data driver 400 .

[0166] The data control signal DCS may include a source start pulse and at least one clock signal. The source start pulse may be used to control a sampling start time point of data, and the clock signal may be used to control a sampling operation.

[0167] Figure 4 yes Figure 3 A more detailed diagram of the scan driver and transmit driver is shown.

[0168] The first scan driver 210 may include a plurality of first scan stage circuits SST11 to SST1 k .

[0169] Each of the first scan stage circuits SST11 to SST1 k may be connected to a corresponding terminal of the first scan wirings R11 to R1 k and may supply a first scan signal to the first scan lines S11 to S1 k.

[0170] The first scanning stage circuits SST11 to SST1k may operate in response to clock signals CLK1 and CLK2 supplied from the timing controller 270. According to one embodiment, the first scanning stage circuits SST11 to SST1k may be implemented by the same circuit.

[0171] The first scan stage circuits SST11 to SST1 k may receive an output signal (ie, a scan signal) of a previous scan stage circuit or a first start pulse SSP1 .

[0172] For example, the first circuit SST11 in the first scan stage circuit may receive the first start pulse SSP1, and the other circuits SST12 to SST1 k in the first scan stage circuit may receive the output signal of the previous scan stage circuit.

[0173] In another embodiment, the first circuit SST11 of the first scan stage circuits of the first scan driver 210 may use a signal output from the last scan stage circuit SST2 j of the second scan driver 220 as a start pulse.

[0174] The first scan stage circuits SST11 to SST1 k may receive a first driving power source VDD1 and a second driving power source VSS1 , respectively.

[0175] Here, the first driving power source VDD1 may be set to a gate-off voltage, such as a high-level voltage, and the second driving power source VSS1 may be set to a gate-on voltage, such as a low-level voltage.

[0176] The second scan driver 220 may include a plurality of second scan stage circuits SST21 to SST2 j.

[0177] Each of the second scan stage circuits SST21 to SST2 j may be connected to a corresponding terminal of the second scan wirings R21 to R2 j and may supply a second scan signal to the second scan lines S21 to S2 j.

[0178] The second scan stage circuits SST21 to SST2j may operate in response to clock signals CLK1 and CLK2 supplied from the timing controller 270. According to one embodiment, the second scan stage circuits SST21 to SST2j may be implemented by the same circuit.

[0179] The second scan stage circuits SST21 to SST2 j may receive an output signal (ie, a scan signal) of a previous scan stage circuit or a second start pulse SSP2 .

[0180] For example, the first circuit SST21 in the second scan stage circuit may receive the second start pulse SSP2 , and the other circuits SST22 to SST2 j in the second scan stage circuit may receive the output signal of the previous scan stage circuit.

[0181] According to one embodiment, the last scan stage circuit SST2 j of the second scan driver 220 may supply an output signal to the first first scan stage circuit SST11 of the first scan driver 210 .

[0182] The second scan stage circuits SST21 to SST2 j may receive the first driving power source VDD1 and the second driving power source VSS1 , respectively.

[0183] The first and second clock lines 241 and 242 may be connected to the first and second scan drivers 210 and 220 .

[0184] According to one embodiment, the first and second clock lines 241 and 242 may be connected to the timing controller 270 and may transfer the first and second clock signals CLK1 and CLK2 supplied from the timing controller 270 to the first and second scan drivers 210 and 220 .

[0185] The first and second clock lines 241 and 242 may be disposed in the first and second peripheral areas NA1 and NA2 .

[0186] The first clock signal CLK1 and the second clock signal CLK2 may have different phases from each other. For example, the second clock signal CLK2 may have a phase difference of 180 degrees relative to the first clock signal CLK1.

[0187] Figure 4 A case is shown where the first scan driver 210 and the second scan driver 220 share the same clock lines 241 and 242 , but the present disclosure is not limited thereto, and the first scan driver 210 and the second scan driver 220 may be connected to clock lines separate from each other, respectively.

[0188] also, Figure 4 The scan drivers 210 and 220 are shown as using two clock signals CLK1 and CLK2 , respectively, but the number of clock signals used by the scan drivers 210 and 220 may vary depending on the structure of the scan stage circuit.

[0189] The first emission driver 310 may include a plurality of first emission stage circuits (referred to as, first emission stages for short) EST11 to EST1k.

[0190] Each of the first emission stage circuits EST11 to EST1k may be connected to a corresponding terminal of the first emission wirings R31 to R3k and may supply a first emission control signal to the first emission control lines E11 to E1k.

[0191] The first transmitter stage circuits EST11 to EST1k may operate in response to clock signals CLK3 and CLK4 supplied from the timing controller 270. According to one embodiment, the first transmitter stage circuits EST11 to EST1k may be implemented by the same circuit.

[0192] The first transmitter stage circuits EST11 to EST1k may receive an output signal (ie, an emission control signal) of a previous transmitter stage circuit or a third start pulse SSP3.

[0193] For example, the first circuit EST11 in the first transmitting stage circuit may receive the third start pulse SSP3, and the other circuits EST12 to EST1k in the first transmitting stage circuit may receive the output signal of the previous transmitting stage circuit.

[0194] In another embodiment, the first circuit EST11 among the first emission stage circuits of the first emission driver 310 may use a signal output from the last emission stage circuit EST2 j of the second emission driver 320 as a start pulse.

[0195] The first transmitter stage circuits EST11 to EST1k may receive a third driving power source VDD2 and a fourth driving power source VSS2, respectively.

[0196] Here, the third driving power source VDD2 may be set to a gate-off voltage, such as a high-level voltage, and the fourth driving power source VSS2 may be set to a gate-on voltage, such as a low-level voltage.

[0197] According to one embodiment, the third driving power source VDD2 may have the same voltage as the first driving power source VDD1 , and the fourth driving power source VSS2 may have the same voltage as the second driving power source VSS1 .

[0198] The second emission driver 320 may include a plurality of second emission stage circuits (hereinafter referred to as second emission stages) EST21 to EST2j.

[0199] Each of the second emission stage circuits EST21 to EST2j may be connected to a corresponding terminal of the second emission wirings R41 to R4j and may supply a second emission control signal to the second emission control lines E21 to E2j.

[0200] The second transmitting stage circuits EST21 to EST2j may operate in response to clock signals CLK3 and CLK4 supplied from the timing controller 270. According to one embodiment, the second transmitting stage circuits EST21 to EST2j may be implemented by the same circuit.

[0201] The second transmit stage circuits EST21 to EST2j may receive an output signal (ie, an emission control signal) of a previous transmit stage circuit or a fourth start pulse SSP4.

[0202] For example, the first circuit EST21 in the second transmitting stage circuit may receive the fourth start pulse SSP4, and the other circuits EST22 to EST2j in the second transmitting stage circuit may receive the output signal of the previous transmitting stage circuit.

[0203] According to one embodiment, the last emitter stage circuit EST2 j of the second emission driver 320 may supply an output signal to the first first emission stage circuit EST11 of the first emission driver 310 .

[0204] The second transmitter stage circuits EST21 to EST2j may receive the third driving power source VDD2 and the fourth driving power source VSS2, respectively.

[0205] The third clock line 243 and the fourth clock line 244 may be connected to the first emission driver 310 and the second emission driver 320 .

[0206] According to one embodiment, the third and fourth clock lines 243 and 244 may be connected to the timing controller 270 and may transmit the third and fourth clock signals CLK3 and CLK4 supplied from the timing controller 270 to the first and second emission drivers 310 and 320 .

[0207] The third clock line 243 and the fourth clock line 244 may be disposed in the first peripheral area NA1 and the second peripheral area NA2 .

[0208] The third clock signal CLK3 and the fourth clock signal CLK4 may have different phases from each other. For example, the third clock signal CLK3 may have a phase difference of 180 degrees with respect to the fourth clock signal CLK4.

[0209] Figure 4 A case is shown where the first emission driver 310 and the second emission driver 320 share the same clock lines 243 and 244 , but the present disclosure is not limited thereto, and the first emission driver 310 and the second emission driver 320 may be connected to clock lines separate from each other, respectively.

[0210] also, Figure 4 The emission drivers 310 and 320 are shown as using two clock signals CLK3 and CLK4, respectively, but the number of clock signals used by the emission drivers 310 and 320 may vary depending on the structure of the emission stage circuit.

[0211] Figure 5 1 is a diagram illustrating a layout structure of a scanning stage circuit and an emission stage circuit according to an embodiment of the present disclosure.

[0212] Specifically, Figure 5 Part of the first scanning level circuits SST11 to SST16 and part of the first emission level circuits EST11 to EST16 arranged in the first peripheral area NA1, and part of the second scanning level circuits SST21 to SST210 and part of the second emission level circuits EST21 to EST210 arranged in the second peripheral area NA2 are shown by way of example.

[0213] like Figure 5 As shown in FIG. 1 , the corners of the second peripheral area NA2 may have a curved shape. Figure 5As shown, a region in the second peripheral area NA2 where the second scanning stage circuits SST21 to SST210 and the second transmitting stage circuits EST21 to EST210 are disposed may have a curved shape having a predetermined curvature.

[0214] The corners of the second pixel area AA2 may also have a curved shape corresponding to the curved shape of the second peripheral area NA2 .

[0215] In order to make the corners of the second pixel area AA2 have a curved shape, the farther the pixel row in the second pixel area AA2 is from the first pixel area AA1 , the fewer pixels PXL2 the row may include.

[0216] The farther the pixel rows arranged in the second pixel area AA2 are from the first pixel area AA1, the smaller the length of the rows. The length does not need to be reduced at the same ratio, and the number of second pixels PXL2 included in each pixel row may be changed differently depending on the curvature of the curve forming the corner of the second pixel area AA2.

[0217] The first peripheral area NA1 may have a straight line shape, and in this case, the first pixel area AA1 may have a quadrangular shape.

[0218] All pixel rows in the first pixel area AA1 may include the same number of first pixels PXL1 .

[0219] Unlike the first peripheral area NA1, the second peripheral area NA2 has a curved shape. Therefore, the layout structure of the second scanning level circuit SST21 to SST210 and the second emission level circuit EST21 to EST210 in the second peripheral area NA2 can be set to be different from the layout structure of the first scanning level circuit SST11 to SST16 and the first emission level circuit EST11 to EST16 in the first peripheral area NA1, so as to effectively use the second peripheral area NA2 which may be a dead angle.

[0220] For example, the gap P2 between the adjacent second scan stage circuits SST21 to SST210 may be set to be larger than the gap P1 between the adjacent first scan stage circuits SST11 to SST16 .

[0221] The gap P1 between adjacent first scan stage circuits SST11 to SST16 may be set to be constant.

[0222] In addition, the gaps P2 between the adjacent second scan stage circuits SST21 to SST210 may be set differently from each other according to positions.

[0223] For example, the gap P2a between the pair of second scanning stage circuits SST23 and SST24 may be set to be different from the gap P2b between the pair of second scanning stage circuits SST21 and SST22.

[0224] Specifically, the gap P2b between the pair of second scanning stage circuits SST21 and SST22 may be set to be larger than the gap P2a between the pair of second scanning stage circuits SST23 and SST24.

[0225] In this example, the pair of second scan stage circuits SST21 and SST22 may be located farther from the first peripheral area NA1 than the pair of second scan stage circuits SST23 and SST24 .

[0226] In other words, the farther the gap P2 between the adjacent second scan stage circuits SST21 to SST210 is from the first peripheral area NA1 , the larger the gap P2 may become.

[0227] In addition, the second scan stage circuits SST21 to SST210 may have a predetermined slope compared to the first scan stage circuits SST11 to SST16. For example, the slope may become larger as the second scan stage circuits SST21 to SST210 are farther from the first peripheral area NA1.

[0228] Meanwhile, the second transmission stages EST21 to EST210 may be provided in a substantially similar manner to the second scanning stage circuits SST21 to SST210.

[0229] For example, the gap P4 between the adjacent second transmitting stage circuits EST21 to EST210 may be set to be larger than the gap P3 between the adjacent first transmitting stage circuits EST11 to EST16.

[0230] For example, the gap P3 between adjacent first transmitter stage circuits EST11 to EST16 may be constant.

[0231] In addition, the gaps P4 between the adjacent second transmitting stages EST21 to EST210 may be set differently from each other according to positions.

[0232] For example, the gap P4a between the pair of second transmitting stages EST23 and EST24 may be set to be different from the gap P4b between the pair of second transmitting stages EST21 and EST22.

[0233] Specifically, the gap P4b between the pair of second transmitting stages EST21 and EST22 may be set to be larger than the gap P4a between the pair of second transmitting stages EST23 and EST24.

[0234] In this example, the pair of second transmitting stages EST21 and EST22 may be located farther from the first peripheral area NA1 than the pair of second transmitting stages EST23 and EST24.

[0235] In other words, the farther the gap P4 between the adjacent second emission stages EST21 to EST210 is from the first peripheral area NA1 , the larger the gap P4 may become.

[0236] The second transmitter stage circuits EST21 to EST210 may have a predetermined slope compared to the first transmitter stage circuits EST11 to EST16. For example, the farther the second transmitter stage circuits EST21 to EST210 are from the first peripheral area NA1, the greater the slope may become.

[0237] The first scan stage circuits SST11 to SST16 may be electrically connected to the first scan lines S11 to S16 through the first scan wirings R11 to R16, and the second scan stage circuits SST21 to SST210 may be electrically connected to the second scan lines S21 to S210 through the second scan wirings R21 to R210.

[0238] In this case, since the corner portion of the second pixel area AA2 is set to have a curved shape, the lengths of the second scan wirings R21 to R210 may be set to be greater than those of the first scan wirings R11 to R16 .

[0239] According to one embodiment, connection points between the first scan wirings R11 to R16 and the first scan lines S11 to S16 may be located within the first pixel area AA1, and connection points between the second scan wirings R21 to R210 and the second scan lines S21 to S210 may be located within the second pixel area AA2.

[0240] In addition, the first emitter circuits EST11 to EST16 may be electrically connected to the first emission control lines E11 to E16 through the first emission wirings R31 to R36, and the second emitter circuits EST21 to EST210 may be electrically connected to the second emission control lines E21 to E210 through the second emission wirings R41 to R410.

[0241] In this case, since the corner portion of the second pixel area AA2 is set to have a curved shape, the length of the second emission wirings R41 to R410 may be set to be greater than the length of the first emission wirings R31 to R36.

[0242] According to one embodiment, connection points between the first emission wirings R31 to R36 and the first emission control lines E11 to E16 may be located within the first pixel area AA1, and connection points between the second emission wirings R41 to R410 and the second emission control lines E21 to E210 may be located within the second pixel area AA2.

[0243] Figure 6A and Figure 6B is a diagram illustrating a layout structure of a second scanning stage circuit and a second emission stage circuit according to various embodiments of the present disclosure.

[0244] Specifically, for convenience, Figure 6A and 6B Second scanning stage circuits SST21 to SST210 and second transmitting stages EST21 to EST210 provided in the second peripheral area NA2 are shown.

[0245] like Figure 6A As shown, the gaps P21 , P22 , and P23 between the adjacent second scan stage circuits SST21 to SST210 may be set differently from each other by the groups SG1 , SG2 , and SG3 .

[0246] For example, the second scan level circuits SST27 to SST210 included in the first group SG1 can be set with a first gap P21 between them, the second scan level circuits SST24 to SST26 included in the second group SG2 can be set with a second gap P22 between them, and the second scan level circuits SST21 to SST23 included in the third group SG3 can be set with a third gap P23 between them.

[0247] In this case, the first gap P21 , the second gap P22 , and the third gap P23 may be set differently from each other.

[0248] For example, the first gap P21 , the second gap P22 , and the third gap P23 may have larger values ​​in ascending order.

[0249] Furthermore, the gaps P41 , P42 , and P43 between the adjacent second emission stages EST21 to EST210 may be set differently from one another by the groups EG1 , EG2 , and EG3 .

[0250] For example, the second emitter stage circuits EST27 to EST210 included in the first group EG1 can be set with a first gap P41 between them, the second emitter stage circuits EST24 to EST26 included in the second group EG2 can be set with a second gap P42 between them, and the second emitter stage circuits EST21 to EST23 included in the third group EG3 can be set with a third gap P43 between them.

[0251] In this case, the first gap P41 , the second gap P42 , and the third gap P43 may be set differently from each other.

[0252] For example, the first gap P41 , the second gap P42 , and the third gap P43 may have larger values ​​in ascending order.

[0253] like Figure 6B As shown, the gap P2 between adjacent second scan stage circuits SST21 to SST210 may gradually increase.

[0254] For example, the gap P2 between the adjacent second scanning stage circuits SST21 to SST210 is away from one side (for example, Figure 6B The closer to the upper side shown), the larger the gap P2 can become.

[0255] According to this, the gaps P2 adjacent to each other can be set differently from each other.

[0256] In addition, the gap P4 between adjacent second transmitting stages EST21 to EST210 may gradually increase.

[0257] For example, the gap P4 between the adjacent second transmitting stage circuits EST21 to EST210 is away from one side (for example, Figure 6B The closer to the upper side shown), the larger the gap P4 can become.

[0258] According to this, the gaps P4 adjacent to each other can be set differently from each other.

[0259] Figure 7 is a diagram illustrating a second scan driver and a second emission driver according to another embodiment of the present disclosure.

[0260] like Figure 7 As shown, the second scan driver 220' may further include one or more dummy scan stage circuits DSST.

[0261] Since the dummy scan stage circuit DSST is located between the second scan stage circuits SST21 to SST2 j , the critical dimension (CD) uniformity of the second scan driver 220 ′ can be increased.

[0262] For example, the dummy scanning stage circuit DSST may be located between the second scanning stage circuits SST21 to SST2 j , and the number of the dummy scanning stage circuits DSST may be differently set according to the location.

[0263] The dummy scan stage circuit DSST may have the same circuit structure as the second scan stage circuits SST21 to SST2 j , but is not connected to the clock lines 241 and 242 , thereby not performing an output operation of a scan signal.

[0264] Meanwhile, the second emission driver 320 ′ may further include one or more dummy emission stage circuits DEST.

[0265] The dummy emitter circuit DEST is located between the second emitter circuits EST21 to EST2j, and can increase the CD uniformity of the second emission driver 320'.

[0266] For example, the dummy emitter stage circuit DEST may be located between the second emitter stage circuits EST21 to EST2 j , and the number of the dummy emitter stage circuits DEST may be differently set according to the location.

[0267] The dummy transmitter stage circuit DEST may have the same circuit structure as the second transmitter stage circuits EST21 to EST2 j , but is not connected to the clock lines 243 and 244 , thereby not performing an output operation of an emission control signal.

[0268] Figure 8 is a diagram illustrating a layout structure of a dummy stage circuit according to one embodiment of the present disclosure.

[0269] Specifically, Figure 8 Shown in Figure 5 In the circuit shown, the shapes of the dummy stage circuits DSST and DEST are set.

[0270] like Figure 8 As shown, the dummy scan stage circuit DSST may be provided in the second peripheral area NA2 and may be located between the second scan stage circuits SST21 to SST210 .

[0271] Figure 8 A case is shown where the dummy scan stage circuit DSST is partially located between the second scan stage circuits SST21 to SST25 .

[0272] The number of dummy scan stage circuits DSST may be changed depending on the location.

[0273] For example, the number of dummy scanning stage circuits DSST located between a pair of second scanning stage circuits SST23 and SST24 may be different from the number of dummy scanning stage circuits DSST located between a pair of second scanning stage circuits SST21 and SST22 .

[0274] Specifically, the number of dummy scanning stage circuits DSST located between the pair of second scanning stage circuits SST21 and SST22 may be set to be greater than the number of dummy scanning stage circuits DSST located between the pair of second scanning stage circuits SST23 and SST24 .

[0275] In this example, the pair of second scan stage circuits SST21 and SST22 may be located farther from the first peripheral area NA1 than the pair of second scan stage circuits SST23 and SST24 .

[0276] Meanwhile, the dummy emitter circuit DEST may be provided in the second peripheral area NA2 and may be located between adjacent second emitter stages EST21 to EST210 .

[0277] Figure 8 A case is shown where the dummy transmitter stage circuit DEST is partially located between the second transmitter stages EST21 to EST25.

[0278] The number of dummy transmitter stage circuits DEST may be changed depending on the location.

[0279] For example, the number of dummy transmitter stage circuits DEST located between the pair of second transmitter stage circuits EST23 and EST24 may be different from the number of dummy transmitter stage circuits DEST located between the pair of second transmitter stage circuits EST21 and EST22.

[0280] Specifically, the number of dummy transmitter-stage circuits DEST located between the pair of second transmitter-stage circuits EST21 and EST22 may be set to be greater than the number of dummy transmitter-stage circuits DEST located between the pair of second transmitter-stage circuits EST23 and EST24.

[0281] In this example, the pair of second transmitter stage circuits EST21 and EST22 may be located farther from the first peripheral area NA1 than the pair of second transmitter stage circuits EST23 and EST24 .

[0282] Meanwhile, although not shown separately, the dummy scanning stage circuit DSST and the dummy transmitting stage circuit DEST may be provided in the embodiment of FIG. Figure 6A and 6B In the illustrated embodiment, various additional arrangements are provided.

[0283] Figure 9A and Figure 9B is a diagram illustrating a layout structure of a dummy stage circuit according to various embodiments of the present disclosure.

[0284] Specifically, for convenience, Figure 9A and Figure 9BThe second scanning stage circuits SST21 to SST210 , the dummy scanning stage circuit DSST, the second transmitting stages EST21 to EST210 , and the dummy transmitting stage circuit DEST provided in the second peripheral area NA2 are shown.

[0285] like Figure 9A As shown, the second scanning stage circuits SST21 to SST210 and the dummy scanning stage circuit DSST may be located outside the second transmitting stages EST21 to EST210 and the dummy transmitting stage circuit DEST.

[0286] For example, with Figure 8 In comparison, the positions of the second scanning stage circuits SST21 to SST210 may be replaced with those of the second transmitting stages EST21 to EST210 , and the position of the dummy scanning stage circuit DSST may be replaced with that of the dummy transmitting stage circuit DEST.

[0287] According to this layout structure, the second emission stages EST21 to EST210 and the dummy emission stage circuit DEST may be located closer to the second pixel area AA2 than the second scan stage circuits SST21 to SST210 and the dummy scan stage circuit DSST.

[0288] like Figure 9B As shown, the second scanning stage circuits SST21 to SST210 and the second transmitting stages EST21 to EST210 may be placed along the same line.

[0289] For example, in Figure 9A The second scanning stage circuits SST21 to SST210 and the second transmitting stages EST21 to EST210 are disposed on different lines, but the second scanning stage circuits SST21 to SST210 and the second transmitting stages EST21 to EST210 may be disposed on the same line.

[0290] In this case, the second scan stage circuits SST21 to SST210 may be inserted between the second transmission stages EST21 to EST210.

[0291] In addition, the dummy scan stage circuit DSST and the dummy emission stage circuit DEST may be provided in various types between the second scan stage circuits SST21 to SST210 and the second emission stages EST21 to EST210.

[0292] Figure 10 1 is a diagram illustrating a layout structure of a first scanning stage circuit and a first emission stage circuit according to an embodiment of the present disclosure.

[0293] like Figure 10As shown, the first pixel area AA1 may include a first sub-pixel area SAA1 and a second sub-pixel area SAA2 .

[0294] In addition, the first peripheral area NA1 may include a first sub-peripheral area SNA1 and a second sub-peripheral area SNA2 .

[0295] The first sub peripheral area SNA1 may be located outside the first sub pixel area SAA1, and the second sub peripheral area SNA2 may be located outside the second sub pixel area SAA2.

[0296] For example, the first sub-pixel area SAA1 may be located between the second pixel area AA2 (not shown) and the second sub-pixel area SAA2 , and the first sub-peripheral area SNA1 may be located between the second peripheral area NA2 (not shown) and the second sub-peripheral area SNA2 .

[0297] Corners of the second sub peripheral area SNA2 may have a curved shape. For example, the second sub peripheral area SNA2 may include a portion of the first scanning stage circuits SSTli+4 to SSTli+10 and a portion of the first transmitting stage circuits ESTli+4 to ESTli+10.

[0298] Corners of the second sub-pixel area SAA2 corresponding to corners of the second sub-peripheral area SNA2 may also have a curved shape.

[0299] In order to make the corners of the second sub-pixel area SAA2 have a curved shape, the farther the pixel rows in the second sub-pixel area SAA2 are from the first sub-pixel area SAA1 , the fewer the number of pixels PXL1 may be set.

[0300] The farther the pixel rows arranged in the second sub-pixel area SAA2 are from the first sub-pixel area SAA1, the smaller the length of the rows. The lengths of the rows do not need to be reduced at the same ratio, and the number of pixels PXL1 included in each pixel row may vary depending on the curvature of the curve forming the corner of the second sub-pixel area SAA2.

[0301] The first sub peripheral area SNA1 may have a straight line shape, and in this case, the first sub pixel area SAA1 has a quadrangular shape.

[0302] According to this layout structure, all pixel rows in the first sub-pixel area SAA1 may include the same number of pixels PXL1 .

[0303] For example, the first sub peripheral area SNA1 may include a portion of the first scanning stage circuits SSTli to SSTli+3 and a portion of the first transmitting stage circuits ESTli to ESTli+3.

[0304] Unlike the first sub peripheral area SNA1 , the second sub peripheral area SNA2 has a curved shape, and thus, a layout structure of a stage circuit may be set differently from the first sub peripheral area SNA1 .

[0305] For example, the gap P5 between the adjacent first scanning stage circuits SST1i+4 to SST1i+10 may be set to be larger than the gap P6 between the adjacent first scanning stage circuits SST1i to SST1i+3.

[0306] For example, the gap P6 between adjacent first scan stage circuits SST1 to SST1+3 located in the first sub-peripheral area SNA1 may be set to be constant.

[0307] In addition, the gaps P5 between the adjacent first scan stage circuits SST1i+4 to SST1i+10 located in the second sub peripheral area SNA2 may be set differently from each other according to positions.

[0308] The gap P5 between the adjacent first scanning stage circuits SST1i+4 to SST1i+10 located in the second sub peripheral area SNA2 may be limited according to the presence of the data line D. In this case, the gap P5 between the adjacent first scanning stage circuits SST1i+4 to SST1i+10 located in the second sub peripheral area SNA2 may be set to be less than Figure 5 and Figure 6B A gap P2 is shown between adjacent second scan stage circuits SST21 to SST210.

[0309] However, the present disclosure is not limited thereto, and the gap P5 between the adjacent first scan stage circuits SST1i+4 to SST1i+10 located in the second sub-peripheral area SNA2 may be set to be equal to or greater than Figure 5 and Figure 6B A gap P2 is shown between adjacent second scan stage circuits SST21 to SST210.

[0310] Furthermore, according to one embodiment, one or more dummy scan stage circuits DSST may also be located between adjacent first scan stage circuits SST1i+4 to SST1i+10 disposed in the second sub-peripheral area SNA2.

[0311] Meanwhile, a gap P7 between adjacent first transmitting stage circuits ESTli+4 to ESTli+10 in the second sub peripheral area SNA2 may be set larger than a gap P8 between adjacent first transmitting stage circuits ESTli to ESTli+3 in the first sub peripheral area SNA1.

[0312] For example, the gap P8 between adjacent first transmitter stage circuits EST11 to EST11+3 located in the first sub-peripheral area SNA1 may be set to be constant.

[0313] In addition, the gaps P7 between the adjacent first transmitting stage circuits EST1i+4 to EST1i+10 located in the second sub peripheral area SNA2 may be set differently from each other according to positions.

[0314] The gap P7 between the adjacent first transmitting stage circuits EST11+4 to EST11+10 located in the second sub peripheral area SNA2 may be limited only by the presence of the data line D. In this case, the gap P7 between the adjacent first transmitting stage circuits EST11+4 to EST11+10 located in the second sub peripheral area SNA2 may be set to be less than Figure 5 and Figure 6B A gap P4 is shown between adjacent second transmitting stages EST21 to EST210.

[0315] However, the present disclosure is not limited thereto, and the gap P7 between the adjacent first transmitting stage circuits EST1i+4 to EST1i+10 located in the second sub-peripheral area SNA2 may be set to be equal to or greater than Figure 5 and Figure 6B A gap P4 is shown between adjacent second transmitting stages EST21 to EST210.

[0316] In addition, according to one embodiment, one or more dummy transmitter stage circuits DEST may be further provided between adjacent first transmitter stage circuits ESTli+4 to ESTli+10 in the second sub-peripheral area SNA2.

[0317] Figure 11 is a diagram illustrating a scanning stage circuit according to one embodiment of the present disclosure.

[0318] For convenience, Figure 11 Scan stage circuits SST11 and SST12 of the first scan driver 210 are shown.

[0319] like Figure 11 As shown, the first first scan stage circuit SST11 may include a first driving circuit 1210 , a second driving circuit 1220 and an output unit 1230 .

[0320] The output unit 1230 may control a voltage supplied to the output terminal 1006 in response to voltages of the first node N1 and the second node N2. The output unit 1230 may include a fifth transistor M5 and a sixth transistor M6.

[0321] The fifth transistor M5 may be connected between the fourth input terminal 1004 to which the first driving power source VDD1 is input and the output terminal 1006, and a gate electrode of the fifth transistor M5 may be connected to the first node N1. The fifth transistor M5 may control the connection between the fourth input terminal 1004 and the output terminal 1006 in response to a voltage applied to the first node N1.

[0322] The sixth transistor M6 may be connected between the output terminal 1006 and the third input terminal 1003, and a gate electrode of the sixth transistor M6 may be connected to the second node N2. The sixth transistor M6 may control the connection between the output terminal 1006 and the third input terminal 1003 in response to a voltage applied to the second node N2.

[0323] The output unit 1230 may be driven to function as a buffer. In addition, the fifth transistor M5 and / or the sixth transistor M6 may be composed of a plurality of transistors connected in parallel to each other.

[0324] The first driving circuit 1210 may control a voltage of the third node N3 in response to signals supplied to the first to third input terminals 1001 to 1003 .

[0325] The first driving circuit 1210 may include second to fourth transistors M2 to M4 .

[0326] The second transistor M2 may be connected between the first input terminal 1001 and the third node N3, and a gate electrode of the second transistor M2 may be connected to the second input terminal 1002. The second transistor M2 may control the connection between the first input terminal 1001 and the third node N3 in response to a signal supplied to the second input terminal 1002.

[0327] The third transistor M3 and the fourth transistor M4 may be connected in series between the third node N3 and the fourth input terminal 1004. The third transistor M3 may be connected between the fourth transistor M4 and the third node N3, and a gate electrode of the third transistor M3 may be connected to the third input terminal 1003. The third transistor M3 may control connection between the fourth transistor M4 and the third node N3 in response to a signal supplied to the third input terminal 1003.

[0328] The fourth transistor M4 may be connected between the third transistor M3 and the fourth input terminal 1004, and a gate electrode of the fourth transistor M4 may be connected to the first node N1. The fourth transistor M4 may control the connection between the third transistor M3 and the fourth input terminal 1004 in response to the voltage of the first node N1.

[0329] The second driving circuit 1220 may control the voltage of the first node N1 in response to the voltages of the second input terminal 1002 and the third node N3. The second driving circuit 1220 may include a first transistor M1, a seventh transistor M7, an eighth transistor M8, a first capacitor C1, and a second capacitor C2.

[0330] The second capacitor C1 may be connected between the second node N2 and the output terminal 1006. The first capacitor C1 may be charged with a voltage corresponding to turning on and off.

[0331] The second capacitor C2 may be connected between the first node N1 and the fourth input terminal 1004. The second capacitor C2 may be charged with a voltage applied to the first node N1.

[0332] The seventh transistor M7 may be connected between the first node N1 and the second input terminal 1002, and a gate electrode of the seventh transistor M7 may be connected to the third node N3. The seventh transistor M7 may control the connection between the first node N1 and the second input terminal 1002 in response to a voltage of the third node N3.

[0333] The eighth transistor M8 may be connected between the first node N1 and the fifth input terminal 1005 to which the second driving power source VSS1 is supplied, and a gate electrode of the eighth transistor M8 may be connected to the second input terminal 1002. The eighth transistor M8 may control the connection between the first node N1 and the fifth input terminal 1005 in response to a signal of the second input terminal 1002.

[0334] The first transistor M1 may be connected between the third node N3 and the second node N2, and the gate electrode of the first transistor M1 may be connected to the fifth input terminal 1005. The first transistor M1 may provide a connection between the third node N3 and the second node N2 while maintaining a conductive state. In addition, the first transistor M1 may control the magnitude of the reduction in the voltage of the third node N3 in response to the voltage of the second node N2. In other words, although the voltage of the second node N2 may be reduced to a voltage lower than the voltage of the second driving power supply VSS1, the voltage of the third node N3 may not be reduced to a voltage lower than the voltage obtained by subtracting the threshold voltage of the first transistor M1 from the second driving power supply VSS1. This will be described below.

[0335] The second scanning stage circuit SST12 and the other scanning stage circuits SST13 to SST1 k may have the same configuration as the first scanning stage circuit SST11 .

[0336] The second input terminal 1002 of the j-th (j is an odd or even number) first scanning stage circuit SST1j can receive the first clock signal CLK1, and the third input terminal 1003 can receive the second clock signal CLK2. The second input terminal 1002 of the (j+1)-th first scanning stage circuit SST1j+1 can receive the second clock signal CLK2, and the third input terminal 1003 can receive the first clock signal CLK1.

[0337] The first clock signal CLK1 and the second clock signal CLK2 may have the same period, but may have phases that do not overlap with each other. As an example, when a period in which a scan signal is supplied to one first scan line S1 is referred to as one horizontal period of 1H, each of the clock signals CLK1 and CLK2 may have a period of 2H and may be supplied in different horizontal periods.

[0338] Figure 11 The stage circuits included in the first scan driver 210 are shown, but the stage circuits included in the second scan driver 220 in addition to the first scan driver 210 may also have the same circuit configuration.

[0339] Furthermore, the above-described dummy scanning stage circuit DSST may have the same circuit configuration except that the input terminals 1001 to 1005 and the output terminal 1006 are not connected to the dummy scanning stage circuit DSST.

[0340] Figure 12 It shows Figure 11 For convenience, Figure 12 The operation using the first first scanning stage circuit SST11 is shown.

[0341] like Figure 12 As shown, each of the first clock signal CLK1 and the second clock signal CLK2 can have a period of two horizontal periods of 2H and can be supplied in different horizontal periods. In other words, the second clock signal CLK2 can be set to a signal shifted from the first clock signal CLK1 by half a period (i.e., one horizontal period of 1H). In addition, the first start pulse SSP1 supplied to the first input terminal 1001 is synchronized with the clock signal (i.e., the first clock signal CLK1) supplied to the second input terminal 1002.

[0342] When the first start pulse SSP1 is supplied, the first input terminal 1001 may be set to have a voltage of the second driving power supply VSS1, and when the first start pulse SSP1 is not supplied, the first input terminal 1001 may be set to have a voltage of the first driving power supply VDD1. In addition, when the clock signals CLK1 and CLK2 are supplied to the second input terminal 1002 and the third input terminal 1003, the second input terminal 1002 and the third input terminal 1003 may be set to have a voltage of the second driving power supply VSS1, and when the clock signals CLK1 and CLK2 are not supplied, the second input terminal 1002 and the third input terminal 1003 may be set to have a voltage of the first driving power supply VDD1.

[0343] The operation is described in detail below: First, a first start pulse SSP1 is supplied to be synchronized with the first clock signal CLK1.

[0344] When the first clock signal CLK1 is supplied, the second transistor M2 and the eighth transistor M8 can be turned on. When the second transistor M2 is turned on, the first input terminal 1001 can be connected to the third node N3. Here, the first transistor M1 can be set to be continuously turned on, thereby maintaining the electrical connection between the second node N2 and the third node N3.

[0345] When the first input terminal 1001 is electrically connected to the third node N3, the third node N3 and the second node N2 may be set to a voltage having a low level by the first start pulse SSP1 supplied to the first input terminal 1001. When the third node N3 and the second node N2 are set to a voltage having a low level, the sixth transistor M6 and the seventh transistor M7 may be turned on.

[0346] When the sixth transistor M6 is turned on, the third input terminal 1003 can be electrically connected to the output terminal 1006. Here, the third input terminal 1003 is set to have a high-level voltage (i.e., the second clock signal CLK2 is not supplied), thereby also outputting a high-level voltage to the output terminal 1006. When the seventh transistor M7 is turned on, the second input terminal 1002 can be electrically connected to the first node N1. Then, the voltage of the first clock signal CLK1 (i.e., the low-level voltage supplied to the second input terminal 1002) can be supplied to the first node N1.

[0347] When the first clock signal CLK1 is supplied, the eighth transistor M8 may be turned on. When the eighth transistor M8 is turned on, the voltage of the second driving power supply VSS1 may be supplied to the first node N1. Here, the voltage of the second driving power supply VSS1 may be set to the same voltage as the first clock signal CLK1, and thus the first node N1 may stably maintain a low voltage.

[0348] When the first node N1 is set to have a low voltage, the fourth transistor M4 and the fifth transistor M5 can be turned on. When the fourth transistor M4 is turned on, the fourth input terminal 1004 can be electrically connected to the third transistor M3. Here, the third transistor M3 is set to an off state, so even though the fourth transistor M4 is turned on, the third node N3 can also stably maintain a low voltage.

[0349] When the fifth transistor M5 is turned on, the voltage of the first driving power supply VDD1 can be supplied to the output terminal 1006. Here, the voltage of the first driving power supply VDD1 can be set to the high voltage level supplied to the third input terminal 1003, thereby stably maintaining the high voltage level of the output terminal 1006.

[0350] Afterwards, the supply of the first start pulse SSP1 and the first clock signal CLK1 may be stopped. When the supply of the first clock signal CLK1 is stopped, the second transistor M2 and the eighth transistor M8 may be turned off. At the same time, the sixth transistor M6 and the seventh transistor M7 may remain in an on state in response to the voltage stored in the first capacitor C1. That is, the second node N2 and the third node N3 may be maintained at a low voltage level by the voltage stored in the first capacitor C1.

[0351] When the sixth transistor M6 remains in an on state, the electrical connection between the output terminal 1006 and the third input terminal 1003 can be maintained. When the seventh transistor M7 remains in an on state, the electrical connection between the first node N1 and the second input terminal 1002 can be maintained. Here, when the supply of the first clock signal CLK1 stops, the voltage of the second input terminal 1002 can be set to a high level voltage, thereby also setting the first node N1 to a high level voltage. When a high level voltage is supplied to the first node N1, the fourth transistor M4 and the fifth transistor M5 can be turned off.

[0352] Thereafter, the second clock signal CLK2 may be supplied to the third input terminal 1003. Since the sixth transistor M6 is set to an on state, the second clock signal CLK2 supplied to the third input terminal 1003 may be supplied to the output terminal 1006. In this case, the output terminal 1006 may output the second clock signal CLK2 to the first scan line as a scan signal.

[0353] Meanwhile, when the second clock signal CLK2 is supplied to the output terminal 1006 , the voltage of the second node N2 may drop below the voltage of the second driving power supply VSS1 due to coupling of the first capacitor C1 , thereby stably maintaining the sixth transistor M6 in the on state.

[0354] Meanwhile, although the voltage of the second node N2 decreases, the third node N3 may be maintained at a voltage approximately equal to the second driving power source VSS1 (eg, a voltage obtained by subtracting the threshold voltage of the first transistor M1 from the second driving power source VSS1) by the first transistor M1.

[0355] After the scan signal is output to the first line S11 of the first scan line, the supply of the second clock signal CLK2 may be stopped. When the supply of the second clock signal CLK2 is stopped, the output terminal 1006 may output a high-level voltage. In addition, the voltage of the second node N2 may increase to a voltage similar to the second driving power supply VSS1 in response to the high-level voltage of the output terminal 1006.

[0356] Afterwards, the first clock signal CLK1 may be supplied. When the first clock signal CLK1 is supplied, the second transistor M2 and the eighth transistor M8 may be turned on. When the second transistor M2 is turned on, the first input terminal 1001 may be electrically connected to the third node N3. The first start pulse SSP1 may not be supplied to the first input terminal 1001, and the first input terminal 1001 may be set to a high-level voltage. Therefore, when the first transistor M1 is turned on, a high-level voltage may be supplied to the third node N3 and the second node N2, thereby turning off the sixth transistor M6 and the seventh transistor M7.

[0357] When the eighth transistor M8 is turned on, the second driving power source VSS1 may be supplied to the first node N1, thereby turning on the fourth transistor M4 and the fifth transistor M5. When the fifth transistor M5 is turned on, the voltage of the first driving power source VDD1 may be supplied to the output terminal 1006. Thereafter, the fourth transistor M4 and the fifth transistor M5 may remain in the on state in response to the voltage stored in the second capacitor C2, thereby allowing the output terminal 1006 to stably receive the voltage of the first driving power source VDD1.

[0358] In addition, when the second clock signal CLK2 is supplied, the third transistor M3 can be turned on. Since the fourth transistor M4 is set to the on state, the voltage of the first driving power supply VDD1 can be supplied to the third node N3 and the second node N2. In this case, the sixth transistor M6 and the seventh transistor M7 can be stably maintained in the off state.

[0359] The second scanning stage circuit SST12 can receive the output signal (i.e., the scanning signal) of the first scanning stage circuit SST11 so as to synchronize with the second clock signal CLK2. In this case, the second scanning stage circuit SST12 can output the scanning signal to the second line S12 of the first scanning line so as to synchronize with the first clock signal CLK1. The scanning stage circuit SST according to the present disclosure can repeat the above-mentioned process, thereby sequentially outputting the scanning signal to the scanning lines.

[0360] Meanwhile, the first transistor M1 limits the reduction of the voltage of the third node N3 regardless of the voltage of the second node N2 , thereby reducing manufacturing costs and improving the reliability of the driving signal.

[0361] Figure 13 is a diagram illustrating a transmitter stage circuit according to one embodiment of the present disclosure.

[0362] For convenience, Figure 13 A first first emitter stage circuit EST11 and a second first emitter stage circuit EST12 of the first emission driver 310 are shown.

[0363] like Figure 13 As shown, the first first transmitter stage circuit EST11 may include a first driving circuit 2100 , a second driving circuit 2200 , a third driving circuit 2300 and an output unit 2400 .

[0364] The first driving circuit 2100 may control voltages of the 22nd node N22 and the 21st node N21 in response to signals supplied to the first input terminal 2001 and the second input terminal 2002. The first driving circuit 2100 may include eleventh to thirteenth transistors M11 to M13.

[0365] The eleventh transistor M11 may be connected between the first input terminal 2001 and the twenty-first node N21, and a gate electrode of the eleventh transistor M11 may be connected to the second input terminal 2002. When the third clock signal CLK3 is supplied to the second input terminal 2002, the eleventh transistor M11 may be turned on.

[0366] The twelfth transistor M12 may be connected between the second input terminal 2002 and the 22nd node N22, and a gate electrode of the twelfth transistor M12 may be connected to the 21st node N21. The twelfth transistor M12 may be turned off in response to a voltage of the 21st node N21.

[0367] The thirteenth transistor M13 may be connected between the twenty-second node N22 and the fifth input terminal 2005 for receiving the fourth driving power source VSS2, and a gate electrode of the thirteenth transistor M13 may be connected to the second input terminal 2002. When the third clock signal CLK3 is supplied to the second input terminal 2002, the thirteenth transistor M13 may be turned on.

[0368] The second driving circuit 2200 may control the voltages of the 21st and 23rd nodes N21 and N23 in response to the signal supplied to the third input terminal 2003 and the voltage of the 22nd node N22. The second driving circuit 2200 may include 14th to 17th transistors M14 to M17, an 11th capacitor C11, and a 12th capacitor C12.

[0369] The fourteenth transistor M14 may be connected between the fifteenth transistor M15 and the twenty-first node N21, and a gate electrode of the fourteenth transistor M14 may be connected to the third input terminal 2003. When the fourth clock signal CLK4 is supplied to the third input terminal 2003, the fourteenth transistor M14 may be turned on.

[0370] The fifteenth transistor M15 may be connected between the fourteenth transistor M14 and the fourth input terminal 2004 for receiving the third driving power VDD2, and a gate electrode of the fifteenth transistor M15 may be connected to the twenty-second node N22. The fifteenth transistor M15 may be turned on or off in response to the voltage of the twenty-second node N22.

[0371] The sixteenth transistor M16 is connected between the first electrode of the seventeenth transistor M17 and the third input terminal 2003, and a gate electrode of the sixteenth transistor M16 is connected to the twenty-second node N22. The sixteenth transistor M16 is turned on or off in response to a voltage of the twenty-second node N22.

[0372] The seventeenth transistor M17 may be connected between the first electrode of the sixteenth transistor M16 and the twenty-third node N23, and a gate electrode of the seventeenth transistor M17 may be connected to the third input terminal 2003. When the fourth clock signal CLK4 is supplied to the third input terminal 2003, the seventeenth transistor M17 may be turned on.

[0373] The eleventh capacitor C11 may be connected between the twenty-first node N21 and the third input terminal 2003 .

[0374] The twelfth capacitor C12 may be connected between the twenty-second node N22 and the seventeenth transistor M17.

[0375] The third driving circuit 2300 may control the voltage of the 23rd node N23 in response to the voltage of the 21st node N21. The third driving circuit 2300 may include an 18th transistor M18 and a 13th capacitor C13.

[0376] The eighteenth transistor M18 is connected between the twenty-third node N23 and the fourth input terminal 2004 for receiving the third driving power source VDD2, and has a gate electrode connected to the twenty-first node N21. The eighteenth transistor M18 is turned on or off in response to the voltage of the twenty-first node N21.

[0377] The thirteenth capacitor C13 may be connected between the twenty-third node N23 and the fourth input terminal 2004 for receiving the third driving power source VDD2 .

[0378] The output unit 2400 may control a voltage supplied to the output terminal 2006 in response to voltages of the 21st node N21 and the 23rd node N23. The output unit 2400 may include a 19th transistor M19 and a 20th transistor M20.

[0379] The nineteenth transistor M19 may be connected between the output terminal 2006 and the fourth input terminal 2004 for receiving the third driving power source VDD2, and a gate electrode of the nineteenth transistor M19 may be connected to the twenty-third node N23. The nineteenth transistor M19 may be turned on or off in response to the voltage of the twenty-third node N23.

[0380] The twentieth transistor M20 may be connected between the output terminal 2006 and the fifth input terminal 2005 for receiving the fourth driving power source VSS2, and the gate electrode of the twentieth transistor M20 may be connected to the twenty-first node N21. The twentieth transistor M20 may be turned on or off in response to the voltage of the twenty-first node N21. The output unit 2400 may be driven to function as a buffer.

[0381] In addition, the nineteenth transistor M19 and the twentieth transistor M20 may be configured by a plurality of transistors connected in parallel to each other.

[0382] The second first transmitting stage circuit EST12 and the other transmitting stage circuits EST13 to EST1k may have the same configuration as the first first transmitting stage circuit EST11.

[0383] The second input terminal 2002 of the j-th first transmitter stage circuit EST1j may receive the third clock signal CLK3, and the third input terminal 2003 may receive the fourth clock signal CLK4. The second input terminal 2002 of the (j+1)-th first transmitter stage circuit EST1j+1 may receive the fourth clock signal CLK4, and the third input terminal 2003 may receive the third clock signal CLK3.

[0384] The third clock signal CLK3 and the fourth clock signal CLK4 may have the same period but have phases that do not overlap with each other. As an example, each of the clock signals CLK3 and CLK4 may have a period of 2H and may be supplied in different horizontal periods.

[0385] Figure 13 The stage circuit included in the first emission driver 310 is shown, but the stage circuit included in the second emission driver 320 in addition to the first emission driver 310 may also have the same circuit configuration.

[0386] Furthermore, the above-described dummy emitter circuit DEST may have the same circuit configuration except that the input terminals 2001 to 2005 and the output terminal 2006 are not connected to the dummy emitter circuit DEST.

[0387] Figure 14 It shows Figure 13 For the sake of convenience, Figure 14 The operation using the first first transmitting stage circuit EST11 is shown.

[0388] like Figure 14 As shown, each of the third clock signal CLK3 and the fourth clock signal CLK4 may have a period of two horizontal periods (2H) and may be supplied in different horizontal periods. In other words, the fourth clock signal CLK4 may be set to a signal shifted from the third clock signal CLK3 by half a period (i.e., one horizontal period (1H)).

[0389] When the second start pulse SSP2 is supplied, the first input terminal 2001 can be set to have a voltage of the third driving power supply VDD2, and when the second start pulse SSP2 is not supplied, the first input terminal 2001 can be set to have a voltage of the fourth driving power supply VSS2. In addition, when the clock signals CLK3 and CLK4 are supplied to the second input terminal 2002 and the third input terminal 2003, the second input terminal 2002 and the third input terminal 2003 can be set to have a voltage of the fourth driving power supply VSS2, and when the clock signals CLK3 and CLK4 are not supplied, the second input terminal 2002 and the third input terminal 2003 can be set to have a voltage of the third driving power supply VDD2.

[0390] The second start pulse SSP2 supplied to the first input terminal 2001 may be synchronized with the clock signal (i.e., the third clock signal CLK3) supplied to the second input terminal 2002. Furthermore, the second start pulse SSP2 may be set to have a width greater than that of the third clock signal CLK3. For example, the second start pulse SSP2 may be supplied during a horizontal period of 4H.

[0391] The operation is described in detail below. First, the third clock signal CLK3 may be supplied to the second input terminal 2002 at a first time t1. When the third clock signal CLK3 is supplied to the second input terminal 2002, the eleventh transistor M11 and the thirteenth transistor M13 may be turned on.

[0392] When the eleventh transistor M11 is turned on, the first input terminal 2001 may be electrically connected to the 21st node N21. Since the second start pulse SSP2 may not be supplied to the first input terminal 2001, a low level voltage may be supplied to the 21st node N21.

[0393] When a voltage of a low level is supplied to the 21st node N21 , the twelfth transistor M12 , the eighteenth transistor M18 , and the twentieth transistor M20 may be turned on.

[0394] When the eighteenth transistor M18 is turned on, the third driving power VDD2 may be supplied to the twenty-third node N23 , and thus, the nineteenth transistor M19 may be turned off.

[0395] Meanwhile, the thirteenth capacitor C13 may be charged with a voltage corresponding to the third driving power source VDD2 , and thus, the first transistor M19 may be maintained in a turn-off state after the first time t1 .

[0396] When the twentieth transistor M20 is turned on, the voltage of the fourth driving power source VSS2 may be supplied to the output terminal 2006. Therefore, the emission control signal may not be supplied to the first line E11 of the first emission control line at the first time t1.

[0397] When the twelfth transistor M12 is turned on, the third clock signal CLK3 can be supplied to the twenty-second node N22. In addition, when the thirteenth transistor M13 is turned on, the voltage of the fourth driving power supply VSS2 can be supplied to the twenty-second node N22. Here, the third clock signal CLK3 can be set to the voltage of the fourth driving power supply VSS2, thereby stably setting the twenty-second node N22 to have the voltage of the fourth driving power supply VSS2. At the same time, when the voltage of the twenty-second node N22 is set to the fourth driving power supply VSS2, the seventeenth transistor M17 can be set to a cut-off state. Therefore, regardless of the voltage of the twenty-second node N22, the twenty-third node N23 can be maintained at the voltage of the third driving power supply VDD2.

[0398] At the second time t2, the third clock signal CLK3 may be stopped from being supplied to the second input terminal 2002. When the third clock signal CLK3 is stopped, the eleventh transistor M11 and the thirteenth transistor M13 may be turned off. At this time, the voltage of the twenty-first node N21 may be maintained at a low level by the eleventh capacitor C11, thereby maintaining the twelfth transistor M12, the eighteenth transistor M18, and the twentieth transistor M20 in an on state.

[0399] When the twelfth transistor M12 is turned on, the second input terminal 2002 may be electrically connected to the 22nd node N22. At this time, the 22nd node N22 may be set to have a high level voltage.

[0400] When the eighteenth transistor M18 is turned on, the voltage of the third driving power source VDD2 may be supplied to the twenty-third node N23 , so that the nineteenth transistor M19 may be maintained in a turned-off state.

[0401] When the twentieth transistor M20 is turned on, the voltage of the fourth driving power source VSS2 may be supplied to the output terminal 2006 .

[0402] The fourth clock signal CLK4 may be supplied to the third input terminal 2003 at the third time t3. When the fourth clock signal CLK4 is supplied to the third input terminal 2003, the fourteenth transistor M14 and the seventeenth transistor M17 may be turned on.

[0403] When the seventeenth transistor M17 is turned on, the twelfth capacitor C12 can be electrically connected to the twenty-third node N23. At this time, the twenty-third node N23 can be maintained at the voltage of the third driving power supply VDD2. In addition, when the fourteenth transistor M14 is turned on, the fifteenth transistor M15 can be set to a cut-off state. Thus, even though the fourteenth transistor M14 is turned on, the voltage of the twenty-first node N21 can also not change.

[0404] When the fourth clock signal CLK4 is supplied to the third input terminal 2003, the voltage of the 21st node N21 can be reduced to a voltage lower than the voltage of the fourth driving power supply VSS2 due to the coupling of the 11th capacitor C11. When the voltage of the 21st node N21 is reduced to a voltage lower than the voltage of the fourth driving power supply VSS2, the driving characteristics of the 18th transistor M18 and the 20th transistor M20 can be improved. The lower the voltage received by the PMOS transistor, the better the driving characteristics of the PMOS transistor.

[0405] The second start pulse SSP2 may be supplied to the first input terminal 2001 at a fourth time t4 , and the third clock signal CLK3 may be supplied to the second input terminal 2002 .

[0406] When the third clock signal CLK3 is supplied to the second input terminal 2002, the eleventh transistor M11 and the thirteenth transistor M13 may be turned on. When the eleventh transistor M11 is turned on, the first input terminal 2001 may be electrically connected to the twenty-first node N21. Since the second start pulse SSP2 is supplied to the first input terminal 2001, a high-level voltage may be supplied to the twenty-first node N21. When the high-level voltage is supplied to the twenty-first node N21, the twelfth transistor M12, the eighteenth transistor M18, and the twentieth transistor M20 may be turned off.

[0407] When the thirteenth transistor M13 is turned on, the voltage of the fourth driving power source VSS2 can be supplied to the twenty-second node N22. Since the fourteenth transistor M14 is set to the off state, the twenty-first node N21 can be maintained at a high voltage. In addition, since the seventeenth transistor M17 is set to the off state, the voltage of the twenty-third node N23 can be maintained at a high voltage via the thirteenth capacitor C13. Therefore, the nineteenth transistor M19 can be maintained in the off state.

[0408] The fourth clock signal CLK4 may be supplied to the third input terminal 2003 at the fifth time t5. When the fourth clock signal CLK4 is supplied to the third input terminal 2003, the fourteenth transistor M14 and the seventeenth transistor M17 may be turned on. In addition, since the twenty-second node N22 is set to have the voltage of the fourth driving power supply VSS2, the fifteenth transistor M15 and the sixteenth transistor M16 may be turned on.

[0409] When the sixteenth transistor M16 and the seventeenth transistor M17 are turned on, the fourth clock signal CLK4 may be supplied to the twenty-third node N23. When the fourth clock signal CLK4 is supplied to the twenty-third node N23, the nineteenth transistor M19 may be turned on. When the nineteenth transistor M19 is turned on, the voltage of the third driving power supply VDD2 may be supplied to the output terminal 2006. The voltage of the third driving power supply VDD2 supplied to the output terminal 2006 may be supplied to the first line E11 of the first emission control line as an emission control signal.

[0410] At the same time, when the voltage of the fourth clock signal CLK4 is supplied to the twenty-third node N23, due to the coupling of the twelfth capacitor C12, the voltage of the twenty-second node N22 can be reduced to a voltage lower than the voltage of the fourth driving power supply VSS2, thereby improving the driving characteristics of the transistor connected to the twenty-second node N22.

[0411] When the fourteenth transistor M14 and the fifteenth transistor M15 are turned on, the voltage of the third driving power supply VDD2 can be supplied to the twenty-first node N21. Since the voltage of the third driving power supply VDD2 can be supplied to the twenty-first node N21, the twentieth transistor M20 can be kept in the off state. Therefore, the voltage of the third driving power supply VDD2 can be supplied to the first line E11 of the first emission control line.

[0412] The third clock signal CLK3 may be supplied to the second input terminal 2002 at a sixth time t6. When the third clock signal CLK3 is supplied to the second input terminal 2002, the eleventh transistor M11 and the thirteenth transistor M13 may be turned on.

[0413] When the eleventh transistor M11 is turned on, the twenty-first node N21 may be electrically connected to the first input terminal 2001, whereby the twenty-first node N21 may be set to a low voltage. When the twenty-first node N21 is set to a low voltage, the eighteenth transistor M18 and the twentieth transistor M20 may be turned on.

[0414] When the eighteenth transistor M18 is turned on, the voltage of the third driving power supply VDD2 can be supplied to the twenty-third node N23, thereby turning off the nineteenth transistor M19. If the twentieth transistor M20 is turned on, the voltage of the fourth driving power supply VSS2 can be supplied to the output terminal 2006. The voltage of the fourth driving power supply VSS2 supplied to the output terminal 2006 can be supplied to the first line E11 of the first emission control line, thereby stopping the supply of the emission control signal.

[0415] The transmitting stage circuit EST according to the present disclosure may repeat the above-described process, whereby the emission control signals may be sequentially output to the emission control lines.

[0416] Figure 15 is a diagram illustrating a pixel according to one embodiment of the present disclosure.

[0417] For convenience, Figure 15 A first pixel PXL1 connected to an mth data line Dm and an i-th line Sli of the first scan line is shown.

[0418] like Figure 15 As shown, the first pixel PXL1 may include an organic light emitting diode OLED, first to seventh transistors T1 to T7 , and a storage capacitor Cst.

[0419] The anode of the organic light emitting diode OLED may be connected to the first transistor T1 through the sixth transistor T6, and the cathode of the organic light emitting diode OLED may be connected to the second pixel power source ELVSS. The organic light emitting diode OLED may emit light at a predetermined brightness in response to current supplied from the first transistor T1.

[0420] The first pixel power source ELVDD may be set to a voltage higher than the second pixel power source ELVSS so that current flows through the organic light emitting diode OLED.

[0421] The seventh transistor T7 may be connected between an initialization power supply Vint and an anode of the organic light emitting diode OLED. Furthermore, a gate electrode of the seventh transistor T7 may be connected to the (i+1)th line Sli+1 of the first scan line. When a scan signal is supplied to the (i+1)th line Sli+1 of the first scan line, the seventh transistor T7 may be turned on, thereby supplying a voltage of the initialization power supply Vint to the anode of the organic light emitting diode OLED. Here, the initialization power supply Vint may be set to a voltage lower than a voltage of the data signal.

[0422] The sixth transistor T6 may be connected between the first transistor T1 and the organic light emitting diode OLED. Furthermore, a gate electrode of the sixth transistor T6 may be connected to the i-th line Eli of the first emission control line. The sixth transistor T6 may be turned off when an emission control signal is supplied to the i-th line Eli of the first emission control line, and may be turned on otherwise.

[0423] The fifth transistor T5 may be connected between the first pixel power source ELVDD and the first transistor T1. Furthermore, a gate electrode of the fifth transistor T5 may be connected to the i-th line Eli of the first emission control line. The fifth transistor T5 may be turned off when an emission control signal is supplied to the i-th line Eli of the first emission control line, and may be turned on otherwise.

[0424] A first electrode of the first transistor T1 (i.e., the driving transistor) may be connected to the first pixel power source ELVDD via the fifth transistor T5, and a second electrode of the first transistor T1 may be connected to the anode of the organic light emitting diode OLED via the sixth transistor T6. Furthermore, a gate electrode of the first transistor T1 may be connected to a tenth node N10. The first transistor T1 may control a current flowing from the first pixel power source ELVDD through the organic light emitting diode OLED to the second pixel power source ELVSS in response to a voltage at the tenth node N10.

[0425] The third transistor T3 may be connected between the second electrode of the first transistor T1 and the tenth node N10. Furthermore, a gate electrode of the third transistor T3 may be connected to the i-th line S1i of the first scan line. When a scan signal is supplied to the i-th line S1i of the first scan line, the third transistor T3 may be turned on, thereby electrically connecting the second electrode of the first transistor T1 to the tenth node N10. Therefore, when the third transistor T3 is turned on, the first transistor T1 may be connected in a diode-like manner.

[0426] The fourth transistor T4 may be connected between the tenth node N10 and the initialization power supply Vint. Furthermore, a gate electrode of the fourth transistor T4 may be connected to the (i-1)th line Sli-1 of the first scan line. When a scan signal is supplied to the (i-1)th line Sli-1 of the first scan line, the fourth transistor T4 may be turned on, thereby supplying the initialization power supply Vint to the tenth node N10.

[0427] The second transistor T2 may be connected between the mth data line Dm and the first electrode of the first transistor T1. Furthermore, a gate electrode of the second transistor T2 may be connected to the i-th line Sli of the first scan line. When a scan signal is supplied to the i-th line Sli of the first scan line, the second transistor T2 may be turned on, thereby electrically connecting the first electrode of the first transistor T1 to the mth data line Dm.

[0428] The storage capacitor Cst may be connected between the first pixel power source ELVDD and the tenth node N10. The storage capacitor Cst may store a voltage corresponding to the data signal and a threshold voltage of the first transistor T1.

[0429] According to one embodiment, the second pixel PXL2 may be implemented by the same circuit as the first pixel PXL1. Therefore, a detailed description of the second pixel PXL2 will be omitted.

[0430] also, Figure 15 The pixel structure shown is merely an example of using scan lines and emission control lines, and the pixels PXL1 and PXL2 according to the present disclosure are not limited to this pixel structure. The pixel may have a circuit structure capable of supplying current to the organic light emitting diode OLED, and may be selected as any of various known structures.

[0431] In the present disclosure, the organic light emitting diode (OLED) can generate light of various colors including red, green, and blue in response to current supplied from a driving transistor, but the present disclosure is not limited thereto. For example, the organic light emitting diode (OLED) can generate white light in response to current supplied from a driving transistor. In this case, a color image can be generated by using a separate color filter, etc.

[0432] In addition, for convenience, in the present disclosure, a transistor is described by using a P-channel (P-type) transistor, but the present disclosure is not limited thereto. In other words, the transistor may be formed by an N-channel (N-type) transistor.

[0433] In addition, the gate-off voltage and the gate-on voltage of the transistor may be set to voltages of different levels depending on the type of the transistor.

[0434] For example, in the case of a P-channel transistor, the gate cutoff voltage and the gate on voltage can be set to a high level voltage and a low level voltage, respectively, and in the case of an N-channel transistor, the gate cutoff voltage and the gate on voltage can be set to a low level voltage and a high level voltage, respectively.

[0435] Figure 16 is a diagram illustrating a pixel area of ​​a display device according to another embodiment of the present disclosure.

[0436] Will refer to Figure 16 To mainly describe the above embodiments (for example, Figure 1 ) different parts, and will not be described again with respect to the parts overlapping with the above embodiment. Accordingly, the following will mainly describe the third pixel area AA3 and the third pixel PXL3.

[0437] like Figure 16As shown, the display device 10 ′ may include pixel areas AA1 , AA2 , and AA3 , peripheral areas NA1 , NA2 , and NA3 , and pixels PXL1 , PXL2 , and PXL3 .

[0438] The second pixel area AA2 and the third pixel area AA3 may be located at one side of the first pixel area AA1. The second pixel area AA2 and the third pixel area AA3 may be located at positions separated from each other.

[0439] The first pixel area AA1 may have a wider area than the second and third pixel areas AA2 and AA3 .

[0440] For example, the width W1 of the first pixel area AA1 may be set greater than the widths W2 and W3 of the other pixel areas AA2 and AA3 , and the length L1 of the first pixel area AA1 may be set greater than the lengths L2 and L3 of the other pixel areas AA2 and AA3 .

[0441] In addition, each of the second pixel area AA2 and the third pixel area AA3 may have an area smaller than the first pixel area AA1 and may have the same area as or different areas from each other.

[0442] For example, the width W2 of the second pixel area AA2 may be set to be the same as or different from the width W3 of the third pixel area AA3 , and the length L2 of the second pixel area AA2 may be set to be the same as or different from the length L3 of the third pixel area AA3 .

[0443] The third peripheral area NA3 may be located outside the third pixel area AA3 and may have a shape surrounding at least a portion of the third pixel area AA3.

[0444] The width of the third peripheral area NA3 may be set to be substantially uniform along the periphery around the third pixel area AA3. However, the present disclosure is not limited thereto, and the width of the third peripheral area NA3 may be set differently depending on the location.

[0445] The second peripheral area NA2 and the third peripheral area NA3 may be connected to each other or may not be connected to each other according to the shape of the substrate 100 .

[0446] The widths of the peripheral areas NA1, NA2, and NA3 may be set to be generally the same. However, the present disclosure is not limited thereto, and the widths of the peripheral areas NA1, NA2, and NA3 may be set differently depending on the location.

[0447] The pixels PXL1 , PXL2 , and PXL3 may include a first pixel PXL1 , a second pixel PXL2 , and a third pixel PXL3 .

[0448] For example, the first pixel PXL1 may be located in the first pixel area AA1 , the second pixel PXL2 may be located in the second pixel area AA2 , and the third pixel PXL3 may be located in the third pixel area AA3 .

[0449] The pixels PXL1 , PXL2 , and PXL3 may emit light at predetermined brightness according to control of a driver located in the peripheral areas NA1 , NA2 , and NA3 , and each of the pixels may include a light emitting element (eg, an organic light emitting diode).

[0450] The substrate 100 may be formed in various forms in which the pixel areas AA1 , AA2 , and AA3 and the peripheral areas NA1 , NA2 , and NA3 may be set.

[0451] For example, the substrate 100 may include a base substrate 101 , and first and second auxiliary plates 102 and 103 protruding and extending at one side from one end portion of the base substrate 101 .

[0452] According to one embodiment, the first auxiliary plate 102 and the second auxiliary plate 103 may be formed as one body with the base substrate 101 , and the recess 104 may be located between the first auxiliary plate 102 and the second auxiliary plate 103 .

[0453] The recess 104 may be formed by removing a portion of the substrate 100 , whereby the first auxiliary plate 102 and the second auxiliary plate 103 may be separated from each other.

[0454] The first auxiliary plate 102 and the second auxiliary plate 103 may have an area smaller than that of the base substrate 101 , and may have the same area or areas different from each other.

[0455] The first auxiliary plate 102 and the second auxiliary plate 103 may be formed in various shapes in which the pixel areas AA2 and AA3 and the peripheral areas NA2 and NA3 may be set.

[0456] In this case, the above-mentioned first pixel area AA1 and the first peripheral area NA1 can be defined in the base substrate 101, and the above-mentioned second pixel area AA2 and the second peripheral area NA2 can be defined in the first auxiliary plate 102, and the above-mentioned third pixel area AA3 and the third peripheral area NA3 can be defined in the second auxiliary plate 103.

[0457] The base substrate 101 may also have various shapes. For example, the base substrate 101 may have a polygonal shape, a ring shape, etc. In addition, at least a portion of the base substrate 101 may have a curved shape.

[0458] For example, the base substrate 101 may have Figure 16The corners of the base substrate 101 may be deformed into a slope or a curve.

[0459] The base substrate 101 may have a shape that is the same as or similar to the first pixel area AA1 , but is not limited thereto and may have a shape that is different from the first pixel area AA1 .

[0460] The first auxiliary plate 102 and the second auxiliary plate 103 may also have various shapes.

[0461] For example, the first auxiliary plate 102 and the second auxiliary plate 103 may have a shape such as a polygonal shape or a ring shape. In addition, at least a portion of the first auxiliary plate 102 and the second auxiliary plate 103 may have a curved shape.

[0462] The recess 104 may have various shapes. For example, the recess 104 may have a shape such as a polygonal shape or a ring shape. In addition, at least a portion of the recess 104 may have a curved shape.

[0463] The third pixel area AA3 may have various shapes. For example, the third pixel area AA3 may have a shape such as a polygonal shape or a ring shape.

[0464] In addition, at least a portion of the third pixel area AA3 may have a curved shape.

[0465] For example, a corner portion of the third pixel area AA3 may have a curved shape having a predetermined curvature.

[0466] In this case, at least a portion of the third peripheral area NA3 may have a curved shape corresponding to the third pixel area AA3.

[0467] According to the deformation of the third pixel area AA3 , the number of third pixels PXL3 located in one line (row or column) may be changed according to positions.

[0468] Figure 17 is a diagram illustrating a display device according to another embodiment of the present disclosure.

[0469] Will refer to Figure 16 To mainly describe the above embodiments (for example, Figure 2 ) different parts, and will not be described again with respect to the parts overlapping with the above embodiment. Accordingly, the following will mainly describe the third pixel PXL3, the third scan driver 230 and the third emission driver 330.

[0470] like Figure 17As shown, the display device 10 ′ may include a substrate 100 , first pixels PXL1 , second pixels PXL2 , third pixels PXL3 , a first scan driver 210 , a second scan driver 220 , a third scan driver 230 , a first emission driver 310 , a second emission driver 320 , and a third emission driver 330 .

[0471] The third pixel PXL3 may be located in the third pixel area AA3 and may be connected to the third scan line S3, the third emission control line E3, and the third data line D3, respectively.

[0472] The third scan driver 230 may supply a third scan signal to the third pixel PXL3 through the third scan line S3 .

[0473] For example, the third scan driver 230 may sequentially supply the third scan signal to the third scan lines S3 .

[0474] The third scan driver 230 may be located in the third peripheral area NA3 .

[0475] For example, the third scan driver 230 may be located at one side of the third pixel area AA3 (eg, as shown in FIG. 2 ). Figure 17 In the third peripheral area NA3 (on the right side as shown).

[0476] The third scan wiring R5 may be connected between the third scan driver 230 and the third scan line S3 .

[0477] The third scan driver 230 may be electrically connected to the third scan line S3 located in the third pixel area AA3 through the third scan wiring R5 .

[0478] The third emission driver 330 may supply a third emission control signal to the third pixel PXL3 through the third emission control line E3 .

[0479] For example, the third emission driver 330 may sequentially supply the third emission control signal to the third emission control line E3.

[0480] The third emission driver 330 may be located in the third peripheral area NA3 .

[0481] For example, the third emission driver 330 may be located at one side of the third pixel area AA3 (eg, as shown in FIG. 1 ). Figure 17 In the third peripheral area NA3 (on the right side as shown).

[0482] Figure 17 The third emission driver 330 is shown positioned outside the third scan driver 230 , but in another embodiment, the third emission driver 330 may be positioned inside the third scan driver 230 .

[0483] The third emission wiring R6 may be connected between the third emission driver 330 and the third emission line E3 .

[0484] The third emission driver 330 may be electrically connected to the third emission control line E3 located in the third pixel area AA3 through the third emission wiring R6 .

[0485] If the third pixel PXL3 has a structure that does not require the third emission control signal, the third emission driver 330 , the third emission wiring R6 , and the third emission control line E3 may be omitted.

[0486] Since the third pixel area AA3 has an area smaller than the first pixel area AA1 , the lengths of the third scan line S3 and the third emission control line E3 may be smaller than those of the first scan line S1 and the first emission control line E1 .

[0487] In addition, the number of third pixels PXL3 connected to a third scan line S3 may be less than the number of first pixels PXL1 connected to a first scan line S1, and the number of third pixels PXL3 connected to a third emission control line E3 may be less than the number of first pixels PXL1 connected to a first emission control line E1.

[0488] The data driver 400 may supply data signals to the pixels PXL1, PXL2, and PXL3 through the data lines D1, D2, and D3. For example, the second data line D2 may be connected to a portion of the first data line D1, and the third data line D3 may be connected to another portion of the first data line D1.

[0489] Figure 18 is a more detailed diagram of a display device according to another embodiment of the present disclosure.

[0490] Will refer to Figure 18 To mainly describe the above embodiments (for example, Figure 3 ) different parts, and the parts overlapping with the above embodiment will not be described again. Accordingly, the following will mainly describe the third scan driver 230 and the third emission driver 330.

[0491] The third scan driver 230 may supply the third scan signal to the third pixel PXL3 through the third scan wirings R51 to R5h and the third scan lines S31 to S3h.

[0492] The third scan wirings R51 to R5h may be connected between the output terminals of the third scan driver 230 and the third scan lines S31 to S3h.

[0493] For example, the third scan wirings R51 to R5h and the third scan lines S31 to S3h may be located at different layers from each other, and in this case, may be connected to each other through a contact hole (not shown).

[0494] The third scan driver 230 may operate in response to the third scan control signal SCS3 .

[0495] The third emission driver 330 may supply the third emission control signal to the third pixel PXL3 through the third emission wirings R61 to R6h and the third emission control lines E31 to E3h.

[0496] The third emission wirings R61 to R6h may be connected between the output terminal of the third emission driver 330 and the third emission control lines E31 to E3h.

[0497] For example, the third emission wirings R61 to R6h and the third emission control lines E31 to E3h may be located at different layers from each other, and in this case, may be connected to each other through a contact hole (not shown).

[0498] The third emission driver 330 may operate in response to the third emission control signal ECS3.

[0499] The data driver 400 may supply data signals to the third pixels PXL3 through the third data lines D31 to D3q.

[0500] The third pixel PXL3 may be connected to the first pixel power source ELVDD and the second pixel power source ELVSS. If necessary, the third pixel PXL3 may be additionally connected to an initialization power source Vint.

[0501] When the third scan signal is supplied to the third scan lines S31 to S3h, the third pixel PXL3 can receive the data signal from the third data line D31 to D3q, and the third pixel PXL3 receiving the data signal can control the current flowing from the first pixel power source ELVDD to the second pixel power source ELVSS through the organic light emitting diode (not shown).

[0502] The number of third pixels PXL3 located in one line (row or column) may vary depending on the location.

[0503] For example, the third data lines D31 to D3q may be connected to a portion of the first data lines D1n+1 to D1o.

[0504] In addition, the second data lines D21 to D2p may be connected to a portion of the first data lines D11 to D1m-1.

[0505] Since the third pixel area AA3 has an area smaller than the first pixel area AA1, the number of third pixels PXL3 can be less than the number of first pixels PXL1, and the lengths of the third scan lines S31 to S3h and the third emission control lines E31 to E3h can be less than the lengths of the first scan lines S11 to S1k and the first emission control lines E11 to E1k.

[0506] The number of third pixels PXL3 connected to any one of the third scan lines S31 to S3 h may be less than the number of first pixels PXL1 connected to any one of the first scan lines S11 to S1 k .

[0507] In addition, the number of third pixels PXL3 connected to any one of the third emission control lines E31 to E3h may be less than the number of first pixels PXL1 connected to any one of the first emission control lines E11 to E1k.

[0508] The timing controller 270 may supply the third scan control signal SCS3 and the third emission control signal ECS3 to the third scan driver 230 and the third emission driver 330 , respectively, so as to control the third scan driver 230 and the third emission control driver 330 .

[0509] Each of the third scan control signal SCS3 and the third emission control signal ECS3 may include at least one clock signal and at least one start pulse.

[0510] Figure 19 yes Figure 18 A more detailed diagram of the third scan driver and the third emission driver is shown.

[0511] like Figure 19 As shown, the third scan driver 230 may include a plurality of third scan stage circuits SST31 to SST3h.

[0512] Each of the third scan stage circuits SST31 to SST3h may be connected to a corresponding terminal of the third scan wirings R51 to R5h, thereby supplying a third scan signal to the third scan lines S31 to S3h.

[0513] The third scan stage circuits SST31 to SST3h may operate in response to clock signals CLK5 and CLK6 supplied from the timing controller 270. According to one embodiment, the third scan stage circuits SST31 to SST3h may be implemented by the same circuit.

[0514] The third scan stage circuits SST31 to SST3h may receive an output signal of a previous scan stage circuit or a fifth start pulse SSP5.

[0515] For example, the first circuit SST31 of the third scan stage circuits may receive the fifth start pulse SSP5, and the other third scan stage circuits SST32 to SST3h may receive output signals of previous scan stage circuits.

[0516] Each of the third scan stage circuits SST31 to SST3 h may receive a first driving power source VDD1 and a second driving power source VSS1 .

[0517] The fifth clock line 245 and the sixth clock line 246 may be connected to the third scan driver 230 .

[0518] The fifth and sixth clock lines 245 and 246 may be connected to the timing controller 270 , thereby transferring the fifth and sixth clock signals CLK5 and CLK6 supplied from the timing controller 270 to the third scan driver 230 .

[0519] According to one embodiment, the fifth clock line 245 and the sixth clock line 246 may be provided in the first peripheral area NA1 and the third peripheral area NA3 .

[0520] The fifth clock signal CLK5 and the sixth clock signal CLK6 may have different phases from each other. For example, the sixth clock signal CLK6 may have a phase difference of 180 degrees relative to the fifth clock signal CLK5.

[0521] Figure 19 The third scan driver 230 is shown using two clock signals CLK5 and CLK6, and the number of clock signals used by the third scan driver 230 may vary according to the structure of the scan stage circuit.

[0522] The third scanning stage circuits SST31 to SST3 h may have the same circuit structure as the first scanning stage circuits SST11 to SST1 k and the second scanning stage circuits SST21 to SST2 j described above.

[0523] The third emission driver 330 may include a plurality of third emission stage circuits EST31 to EST3h.

[0524] Each of the third emitter stage circuits EST31 to EST3h may be connected to a corresponding terminal of the third emission wirings R61 to R6h, thereby supplying a third emission control signal to the third emission control lines E31 to E3h.

[0525] The third transmitter stage circuits EST31 to EST3h may operate in response to clock signals CLK7 and CLK8 supplied from the timing controller 270. According to one embodiment, the third transmitter stage circuits EST31 to EST3h may be implemented by the same circuit.

[0526] The third transmitter stage circuits EST31 to EST3h may receive an output signal (ie, an emission control signal) of a previous transmitter stage circuit or a sixth start pulse SSP6.

[0527] For example, the first circuit EST31 of the third emitter stage circuits may receive the sixth start pulse SSP6, and the other third emitter stage circuits EST32 to EST3h may receive output signals of previous emitter stage circuits.

[0528] Each of the third transmitter stage circuits EST31 to EST3 h may receive the third driving power VDD2 and the fourth driving power VSS2 .

[0529] The seventh clock line 247 and the eighth clock line 248 may be connected to the third emission driver 330 .

[0530] In addition, the seventh and eighth clock lines 247 and 248 may be connected to the timing controller 270 , thereby transferring the seventh and eighth clock signals CLK7 and CLK8 supplied from the timing controller 270 to the third emission driver 330 .

[0531] According to one embodiment, the seventh clock line 247 and the eighth clock line 248 may be provided in the first peripheral area NA1 and the third peripheral area NA3 .

[0532] The seventh clock signal CLK7 and the eighth clock signal CLK8 may have different phases from each other. For example, the eighth clock signal CLK8 may have a phase difference of 180 degrees relative to the seventh clock signal CLK7.

[0533] Figure 19 The third emission driver 330 is shown using two clock signals CLK7 and CLK8 , and the number of clock signals used by the third emission driver 330 may vary according to the structure of the emission stage circuit.

[0534] The third transmitter stage circuits EST31 to EST3h may have the same circuit structure as the first transmitter stage circuits EST11 to EST1k and the second transmitter stage circuits EST21 to EST2j described above.

[0535] Figure 20 is a diagram illustrating a layout structure of a third scanning stage circuit and a third emission stage circuit according to one embodiment of the present disclosure.

[0536] Specifically, Figure 20 The third scanning stage circuits SST31 to SST310 and the third transmitting stage circuits EST31 to EST310 provided in the third peripheral area NA3 are exemplarily shown.

[0537] like Figure 20 As shown in FIG. 1 , the corners of the third peripheral area NA3 may have a curved shape. Figure 20 As shown, a region of the third peripheral area NA3 where the third scanning stage circuits SST31 to SST310 and the third transmitting stage circuits EST31 to EST310 are disposed may have a curved shape having a predetermined curvature.

[0538] The corners of the third pixel area AA3 corresponding to the curved shape of the third peripheral area NA3 may also have a curved shape.

[0539] In order to make the corner of the third pixel area AA3 have a curved shape, the farther the pixel row in the third pixel area AA3 is from the first pixel area AA1 , the fewer pixels PXL3 the row may include.

[0540] The farther the pixel row arranged in the third pixel area AA3 is from the first pixel area AA1, the smaller the length of the row. The length does not need to be reduced at the same ratio, and the number of third pixels PXL3 included in each pixel row can be changed differently according to the curvature of the curve forming the corner of AA3.

[0541] The third scanning stage circuits SST31 to SST310 and the third transmitting stage circuits EST31 to EST310 may be connected to Figure 5 The second scanning stage circuits SST21 to SST210 are shown to be arranged in the same shape as the second transmitting stages EST21 to EST210.

[0542] For example, the gap P9 between the adjacent third scanning stage circuits SST31 to SST310 may be set to be larger than the gap P1 between the adjacent first scanning stage circuits SST11 to SST16 .

[0543] In addition, the gaps P9 between the adjacent third scan stage circuits SST31 to SST310 may be set differently from each other according to positions.

[0544] For example, the gap P9a between the pair of third scanning stage circuits SST33 and SST34 may be set to be different from the gap P9b between the pair of third scanning stage circuits SST31 and SST32.

[0545] Specifically, the gap P9b between the pair of third scanning stage circuits SST31 and SST32 may be set to be larger than the gap P9a between the pair of third scanning stage circuits SST33 and SST34.

[0546] The pair of third scan stage circuits SST31 and SST32 may be located farther from the first peripheral area NA1 than the pair of third scan stage circuits SST33 and SST34 .

[0547] In other words, the farther the gap P9 between the adjacent third scan stage circuits SST31 to SST310 is from the first peripheral area NA1 , the larger the gap P9 may become.

[0548] In addition, the third scan stage circuits SST31 to SST310 may have a predetermined slope compared to the first scan stage circuits SST11 to SST16. For example, the slope may become larger as the third scan stage circuits SST31 to SST310 are farther from the first peripheral area NA1.

[0549] The third transmission stages EST31 to EST310 may be provided in a substantially similar manner to the third scanning stage circuits SST31 to SST310 .

[0550] For example, the gap P10 between the adjacent third transmitter stages EST31 to EST310 may be set to be larger than the gap P3 between the adjacent first transmitter stage circuits EST11 to EST16.

[0551] In addition, the gaps P10 between the adjacent third emission stages EST31 to EST310 may be set differently from each other according to positions.

[0552] For example, the gap P10a between the pair of third transmitting stages EST33 and EST34 may be set to be different from the gap P10b between the pair of third transmitting stages EST31 and EST32.

[0553] Specifically, the gap P10b between the pair of third transmitting stages EST31 and EST32 may be set to be larger than the gap P10a between the pair of third transmitting stages EST33 and EST34.

[0554] The pair of third transmitting stages EST31 and EST32 may be located farther from the first peripheral area NA1 than the pair of third transmitting stages EST33 and EST34.

[0555] In other words, the farther the gap P10 between the adjacent third emission stages EST31 to EST310 is from the first peripheral area NA1 , the larger the gap P10 may become.

[0556] In addition, the third transmitter stage circuits EST31 to EST310 may have a predetermined slope compared to the first transmitter stage circuits EST11 to EST16. For example, the farther the third transmitter stage circuits EST31 to EST310 are from the first peripheral area NA1, the greater the slope may become.

[0557] The third scan stage circuits SST31 to SST310 may be electrically connected to the third scan lines S31 to S310 through third scan wirings R51 to R510 .

[0558] In this case, since the corner portion of the third pixel area AA3 is set to have a curved shape, the lengths of the third scan wirings R51 to R510 may be set to be greater than those of the first scan wirings R11 to R16.

[0559] According to one embodiment, connection points between the third scan wirings R51 to R510 and the third scan lines S31 to S310 may be located within the third pixel area AA3 .

[0560] The third emitter stage circuits EST31 to EST310 may be electrically connected to the third emission control lines E31 to E310 through third emission wirings R61 to R610 .

[0561] In this case, since the corner portion of the third pixel area AA3 is set to have a curved shape, the length of the third emission wirings R61 to R610 may be set to be greater than that of the first emission wirings R31 to R36.

[0562] According to one embodiment, connection points between the third emission wirings R61 to R610 and the first emission control lines E31 to E310 may be located within the third pixel area AA3 .

[0563] In addition, although not shown separately, the third scanning stage circuits SST31 to SST310 and the third emission stage circuits EST31 to EST310 may be connected to the Figure 6A and Figure 6B are arranged in a substantially similar manner as shown.

[0564] Figure 21 is a diagram illustrating a layout structure of a dummy stage circuit according to one embodiment of the present disclosure.

[0565] Specifically, Figure 21 shows the dummy stage circuit DSST and DEST set in Figure 20 The shape of the embodiment shown.

[0566] like Figure 21 As shown, the third scan driver 230 may further include a dummy scan stage circuit DSST located in the third peripheral area NA3.

[0567] For example, the dummy scanning stage circuit DSST may be located between the third scanning stage circuits SST31 to SST310 , and the number of the dummy scanning stage circuits DSST may be set differently from each other according to the locations.

[0568] For example, the number of dummy scanning stage circuits DSST located between a pair of third scanning stage circuits SST33 and SST34 may be different from the number of dummy scanning stage circuits DSST located between a pair of third scanning stage circuits SST31 and SST32 .

[0569] Specifically, the number of dummy scanning stage circuits DSST located between a pair of third scanning stage circuits SST31 and SST32 may be set to be greater than the number of dummy scanning stage circuits DSST located between a pair of third scanning stage circuits SST33 and SST34 .

[0570] The pair of third scan stage circuits SST31 and SST32 may be located farther from the first peripheral area NA1 than the pair of third scan stage circuits SST33 and SST34 .

[0571] The dummy scan stage circuit DSST may have the same circuit structure as the third scan stage circuits SST31 to SST310 , but may not be connected to the clock lines 245 and 246 , and thus, may not perform an output operation of a scan signal.

[0572] In addition, the third emission driver 330 may further include a dummy emission stage circuit DEST located in the third peripheral area NA3 .

[0573] For example, the dummy transmitter stage circuit DEST may be located between the third transmitter stage circuits EST31 to EST310 , and the number of the dummy transmitter stage circuits DEST may be differently set according to the location.

[0574] For example, the number of dummy emitter stage circuits DEST located between a pair of third emitter stage circuits EST33 and EST34 may be different from the number of dummy emitter stage circuits DEST located between a pair of third emitter stage circuits EST31 and EST32.

[0575] Specifically, the number of dummy emitter stage circuits DEST located between the first pair of third emitter stage circuits EST31 and EST32 may be set to be greater than the number of dummy emitter stage circuits DEST located between the pair of third emitter stage circuits EST33 and EST34.

[0576] The pair of third transmitter stage circuits EST31 and EST32 may be located farther from the first peripheral area NA1 than the pair of third transmitter stage circuits EST33 and EST34 .

[0577] The dummy transmitter stage circuit DEST may have the same circuit structure as the third transmitter stage circuits EST31 to EST310 , but may not be connected to the clock lines 247 and 248 , and thus may not perform an output operation of an emission control signal.

[0578] Meanwhile, although not shown separately, the third scanning stage circuits SST31 to SST310, the third emission stage circuits EST31 to EST310, and the dummy emission stage circuit DEST may be configured as shown in FIG. Figure 9A and Figure 9B Basically set up in a similar way.

[0579] Those skilled in the art of the present disclosure will be able to understand that the present disclosure can be implemented in other specific forms without changing the technical spirit or basic characteristics. Therefore, it should be understood that the above embodiments are only exemplary and not restrictive. The scope of the present disclosure is defined by the scope of the described claims (rather than the above description). In addition, it should be understood that the entire change or modification derived from the meaning and scope of the claims and equivalent concepts are included within the scope of the present disclosure.

Claims

1. A display device, comprising: a first pixel configured to be located in a first pixel region and configured to be connected to a first scan line; a first scanning stage circuit configured to be located in a first peripheral region disposed outside the first pixel region and configured to supply a first scanning signal to the first scanning line; a second pixel configured to be located in a second pixel region and configured to be connected to a second scan line; a second scanning stage circuit configured to be located in a second peripheral region provided outside the second pixel region and configured to supply a second scanning signal to the second scanning line; and The dummy scanning stage circuit is configured to be located between adjacent second scanning stage circuits, wherein the gap between adjacent second scanning stage circuits is larger than the gap between adjacent first scanning stage circuits, and The second scanning stage circuit is arranged along a curve with a predetermined curvature.

2. The display device according to claim 1, wherein The second pixel region has a width smaller than that of the first pixel region.

3. The display device according to claim 1, wherein The gaps between the adjacent second scanning stage circuits are set differently from each other depending on positions.

4. The display device according to claim 3, wherein The number of the dummy scanning stage circuits is set differently depending on the location.

5. The display device according to claim 1, wherein The second scanning stage circuit includes a first pair of adjacent second scanning stage circuits and a second pair of adjacent second scanning stage circuits, and The gap between the second pair of adjacent second scanning stage circuits is larger than the gap between the first pair of adjacent second scanning stage circuits.

6. The display device according to claim 5, wherein the dummy scanning stage circuit comprises: at least one first dummy scanning stage circuit, disposed between the first pair of adjacent second scanning stage circuits; as well as a second dummy scanning stage circuit disposed between the second pair of adjacent second scanning stage circuits, and The number of the second dummy scanning stage circuits is greater than the number of the at least one first dummy scanning stage circuit.

7. The display device according to claim 5, wherein The second pair of adjacent second scanning stage circuits is farther away from the first peripheral area than the first pair of adjacent second scanning stage circuits.

8. The display device according to claim 1, The first pixel region includes a first sub-pixel region and a second sub-pixel region. The first peripheral region includes a first sub-peripheral region located outside the first sub-pixel region and a second sub-peripheral region located outside the second sub-pixel region, and The gap between a pair of adjacent first scanning stage circuits in the second sub-peripheral region is larger than the gap between a pair of adjacent first scanning stage circuits in the first sub-peripheral region.

9. The display device according to claim 8, The first sub-pixel region is located between the second pixel region and the second sub-pixel region, and The first sub-peripheral region is located between the second peripheral region and the second sub-peripheral region.

10. The display device according to claim 1, wherein the first scanning stage circuit is electrically connected to the first scanning line via a first scanning wiring, wherein the second scanning stage circuit is electrically connected to the second scanning line via a second scanning wiring, The length of the second scanning wiring is greater than the length of the first scanning wiring.

11. The display device according to claim 1 , further comprising: a third pixel configured to be located in a third pixel region and configured to be connected to a third scan line; as well as The third scanning stage circuit is configured to be located in a third peripheral region provided outside the third pixel region and configured to supply a third scanning signal to the third scanning line.

12. The display device according to claim 11, wherein The third pixel region has a width smaller than that of the first pixel region and is located apart from the second pixel region.

13. The display device according to claim 11, wherein The gap between adjacent third scanning stage circuits is larger than the gap between adjacent first scanning stage circuits.

14. The display device according to claim 11, wherein The gaps between adjacent third scanning stage circuits are set differently from each other depending on the positions.

15. The display device according to claim 14, further comprising: A dummy scanning stage circuit is configured to be located between the adjacent third scanning stage circuits.

16. The display device according to claim 15, wherein The number of the dummy scanning stage circuits arranged to be located between the adjacent third scanning stage circuits is set differently depending on the position.

17. The display device according to claim 11, wherein the first scanning stage circuit is electrically connected to the first scanning line via a first scanning wiring, wherein the second scanning stage circuit is electrically connected to the second scanning line via a second scanning wiring, wherein the third scanning stage circuit is electrically connected to the third scanning line via a third scanning wiring, The lengths of the second scanning wiring and the third scanning wiring are greater than the length of the first scanning wiring.

18. The display device according to claim 1, further comprising: a first emission stage circuit configured to be located in the first peripheral region and configured to supply a first emission control signal to the first pixel through a first emission control line; as well as The second emission stage circuit is configured to be located in the second peripheral region and configured to supply a second emission control signal to the second pixel through a second emission control line.

19. The display device according to claim 18, wherein The gap between adjacent second emitter stage circuits is larger than the gap between adjacent first emitter stage circuits.

20. The display device according to claim 19, wherein The gap between the adjacent second transmitter stage circuits is set differently depending on positions.

21. The display device according to claim 18, further comprising: The dummy transmitter stage circuit is configured to be located between adjacent second transmitter stage circuits.

22. The display device according to claim 21, wherein The number of the dummy transmitter stage circuits is set differently depending on the location.

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