Memory Structure and Memory Layout

Abstract

An embodiment of the present application provides a memory structure and a memory layout, including: a storage array, and each storage array includes a plurality of storage cells; a read / write conversion circuit, arranged between two adjacent storage arrays in a first direction, the read / write conversion circuit is arranged in a second direction and has a symmetry axis in the second direction, and is used to write external data into the storage cells or read the data of the storage cells; a sense amplifier circuit, symmetrically arranged between two adjacent storage arrays according to the symmetry axis, and coupled to the storage cells of adjacent storage arrays; a bias contact structure, arranged in the gap between the read / write conversion circuits, and is used to set the bias voltage of the well region where the bias contact structure is located; wherein, in the first direction, the distance between the sense amplifier circuit adjacent to the bias contact structure and the read / write conversion circuit is equal to the distance from the bias contact structure; to balance the body bias voltages of the MOS transistors in different sense amplifiers arranged between the storage arrays.

Description

Technical Field

[0001] This application relates to the field of semiconductor memory structure design, and particularly to a memory structure and a memory layout. Background Art

[0002] A dynamic random access memory (DRAM) completes the data writing operation of the memory by storing charges in the capacitors of the memory cells, and completes the data reading operation of the memory by reading the charges in the capacitors of the memory cells.

[0003] In a DRAM, the memory cells are connected to a bit line BL and a complementary bit line BLB. During the data reading operation, a sense amplifier is used to read the voltages of the bit line BL and the complementary bit line BLB, and amplify the voltage difference between the bit line BL and the complementary bit line BLB.

[0004] However, the applicant has found that in the related art, the bias voltage supply points are located on both sides of the read / write conversion circuit, and the distance between adjacent bias voltage supply points is large. For the MOS transistor structures of different sense amplifiers arranged between the memory cells, the MOS transistors in the middle region are farther away from the bias voltage supply points, resulting in a large error in the body bias voltage of the MOS transistors in the middle region compared with the body bias voltage of the MOS transistors at the edge, thereby affecting the overall amplification ability of the sense amplifier; in addition, the body bias voltages of the read / write conversion circuits at different positions may also be different, thereby reducing the DRAM performance. Summary of the Invention

[0005] Embodiments of this application provide a memory structure and a memory layout to balance the body bias voltages of the MOS transistors in different sense amplifiers arranged between memory arrays.

[0006] To solve the above technical problems, embodiments of this application provide a memory structure, including: a memory array, and each memory array includes a plurality of memory cells; a read / write conversion circuit, arranged between two adjacent memory arrays in a first direction, the read / write conversion circuits are arranged in a second direction and have a symmetry axis in the second direction, and are used to write external data into the memory cells or read the data of the memory cells, the first direction and the second direction are perpendicular to each other; a sense amplifier circuit, symmetrically arranged between two adjacent memory arrays according to the symmetry axis and coupled to the memory cells of the adjacent memory arrays, and is used to sense the memory cell voltage and output a logic 1 or 0 corresponding to the memory cell voltage; a bias contact structure, arranged in the gap between the read / write conversion circuits, and is used to set the bias voltage of the well region where the bias contact structure is located; wherein, in the first direction, the distance between the sense amplifier circuit adjacent to the bias contact structure and the read / write conversion circuit is equal to the distance from the bias contact structure.

[0007] Compared with the related art, the bias contact structure is disposed in the gap between the read / write conversion circuits, thereby reducing the distance between the bias contact structure and the MOS transistors in different sense amplifier circuits, and thus avoiding the deviation of the body bias voltage of the MOS transistors in the sense amplifier circuit structure in the middle region compared with the body bias voltage of the MOS transistors in the edge region, so as to balance the body bias voltages of the MOS transistors in different sense amplifiers disposed between the memory arrays; the substrate bias voltage is provided by the bias contact structures at different positions to reduce the substrate body resistance of the MOS transistors and reduce the latch-up risk of the MOS transistors. In addition, the distances between the sense amplifier circuit adjacent to the bias contact structure and the read / write conversion circuit and the bias contact structure are equal, so as to ensure that the environments of the corresponding MOS transistors in the different sense amplifier circuits disposed on both sides of the read / write conversion circuit are the same, to balance the device characteristics of the corresponding MOS transistors in different sense amplifiers, and further improve the stability of the DRAM.

[0008] In addition, in the second direction, the distances between adjacent bias contact structures are equal.

[0009] In addition, the MOS transistor structure in the read / write conversion circuit includes: a first active region disposed in the well region of the semiconductor substrate and extending in the second direction; a gate structure spaced apart from the first active region and extending in the first direction, and the extending direction is the same as the extending direction of the gate structure of the MOS transistor in the sense amplifier circuit; a gate extension structure disposed at the edge of the gate structure on the first active region and extending in the second direction, and the gate extension structure and the gate structure enclose an annular gate structure; in the first direction, the distances between the gate structure of the MOS transistor in the sense amplifier circuit adjacent to the gate extension structure and the gate extension structure are equal; a conductive contact structure disposed on the first active region in the gap between two adjacent gate structures, and the height of the top surface of the conductive contact structure is higher than the height of the top surface of the gate structure.

[0010] In addition, the bias contact structure includes: a doped region disposed in the well region, the ion type doped in the doped region being the same as the ion type doped in the well region, and the ion concentration doped in the doped region being greater than the ion concentration doped in the well region; a second active region disposed in the doped region; an isolation region disposed around the edge of the second active region; a first equalization structure disposed at intervals on the second active region, and the length of the first equalization structure in the second direction being less than the length of the first equalization structure in the first direction; a second equalization structure disposed on the second active region and the isolation region, extending in the second direction, and located at the edge of the first equalization structure and enclosing a ring-shaped equalization structure with the first equalization structure; in the first direction, the length of the outer side surface of the ring-shaped equalization structure being the same as the length of the outer side surface of the ring-shaped gate structure; a bias contact structure disposed on the second active region in the gap between two adjacent first equalization structures, and the height of the top surface of the bias contact structure being higher than the height of the top surface of the first equalization structure.

[0011] In addition, the distance between the active region in the sense amplifier circuit adjacent to the bias contact structure and the first active region is equal to the distance between the active region in the sense amplifier circuit adjacent to the bias contact structure and the second active region; the distance between the gate structure in the sense amplifier circuit adjacent to the bias contact structure and the gate extension structure is equal to the distance between the gate structure in the sense amplifier circuit adjacent to the bias contact structure and the second equalization structure. By ensuring that the distance between the active region in the sense amplifier circuit adjacent to the bias contact structure and the first active region is equal to the distance between the active region in the sense amplifier circuit adjacent to the bias contact structure and the second active region, it is ensured that the bias contact structure disposed in the gap of the read / write conversion circuit does not change the environment of the active region of the MOS transistor in the sense amplifier circuit; by ensuring that the distance between the gate structure in the sense amplifier circuit adjacent to the bias contact structure and the gate extension structure is equal to the distance between the gate structure in the sense amplifier circuit adjacent to the bias contact structure and the second equalization structure, it is ensured that the bias contact structure disposed in the gap of the read / write conversion circuit does not change the environment of the gate structure of the MOS transistor in the sense amplifier circuit, so as to ensure that after adding the new bias contact structure, the environment of the MOS transistors in the sense amplifier circuits disposed on both sides of the read / write conversion circuit remains consistent.

[0012] In addition, the intervals between the adjacent and spaced-apart first equalization structures are the same.

[0013] In addition, the length of the second equalization structure in the first direction is the same as the length of the first equalization structure in the second direction.

[0014] In addition, the material of the first equalization structure is the same as the material of the second equalization structure, and the height of the top surface of the first equalization structure is the same as the height of the top surface of the second equalization structure, and the thickness of the first equalization structure is the same as the thickness of the second equalization structure. By ensuring that the materials, thicknesses, and heights of the first equalization structure and the second equalization structure are the same, the first equalization structure and the second equalization structure can be formed in the same process step.

[0015] In addition, the materials of the first balancing structure, the second balancing structure, and the gate structure are the same. By ensuring that the materials of the first balancing structure, the second balancing structure, and the gate structure are the same, the first balancing structure, the second balancing structure, and the gate structure can be formed in the same process step.

[0016] In addition, the bias contact structure fills the annular balancing structure.

[0017] In addition, in the first direction, the length of the bias contact structure is greater than the length of the first balancing structure, and a part of the bias contact structure is also located on the top surface of the second balancing structure and is in contact with the second balancing structure.

[0018] In addition, the materials of the bias contact structure and the conductive contact structure are the same. By ensuring that the materials of the bias contact structure and the conductive contact structure are the same, the bias contact structure and the conductive contact structure can be formed in the same process step.

[0019] In addition, the sense amplifier circuit includes: a first NMOS region circuit coupled to the memory cells in adjacent memory arrays; a second NMOS region circuit coupled to the memory cells in adjacent memory arrays; a first PMOS region circuit coupled to the memory cells in one of the adjacent memory arrays; and a second PMOS region circuit coupled to the memory cells in adjacent memory arrays.

[0020] In addition, the memory structure further includes: a balancing circuit symmetrically disposed between two adjacent memory arrays according to the symmetry axis and electrically connected to the sense amplifier circuit for balancing the voltages of the lines coupling the sense amplifier circuit to the memory cells; and an input / output circuit symmetrically disposed between two adjacent memory arrays according to the symmetry axis and electrically connected to the memory cells of the adjacent memory arrays for selecting the memory cells in the memory arrays.

[0021] An embodiment of the present application further provides a memory layout, including: a memory array layout; a read / write conversion circuit layout disposed between two adjacent memory array layouts in the first direction, the read / write conversion circuit layout being arranged in the second direction and having a symmetry axis in the second direction, the first direction and the second direction being perpendicular; a sense amplifier circuit layout symmetrically disposed between two adjacent memory array layouts based on the symmetry axis; a bias contact structure layout disposed in the gap between the read / write conversion circuit layouts; in the first direction, the distance between the sense amplifier circuit layout adjacent to the bias contact structure layout and the read / write conversion circuit layout is equal to the distance between the sense amplifier circuit layout and the bias contact structure layout.

[0022] In addition, in the second direction, the distances between adjacent bias contact structure layouts in the read / write conversion circuit layout are equal.

[0023] In addition, a first active pattern is disposed in the well region of the semiconductor substrate and extends in a second direction; a gate pattern is disposed at intervals on the first active pattern and extends in a first direction, and the extending direction is the same as that of the gate pattern of the MOS transistor in the sense amplifier circuit layout; a gate extension pattern is disposed at the edge of the gate pattern on the first active pattern and extends in the second direction, and the gate extension pattern and the gate pattern enclose a first closed loop; in the first direction, the distance between the gate pattern in the sense amplifier circuit layout adjacent to the gate extension pattern and the gate extension pattern is equal; a conductive contact pattern is disposed on the first active pattern in the gap between two adjacent gate patterns.

[0024] In addition, the bias contact structure layout includes: a doping pattern disposed in the well region; a second active pattern disposed in the doping pattern and extending in the second direction; an isolation pattern disposed around the edge of the second active pattern; a first equalization pattern disposed at intervals on the second active pattern, and the length of the first equalization pattern in the second direction is less than the length of the first equalization pattern in the first direction; a second equalization pattern disposed on the second active pattern and the isolation pattern, extending in the second direction, and located at the edge of the first equalization pattern and enclosing a second closed loop with the first equalization pattern; in the first direction, the length of the outer side surface of the first closed loop is the same as the length of the outer side surface of the second closed loop; a bias contact pattern is disposed on the second active pattern in the gap between two adjacent first equalization patterns.

[0025] In addition, the distance between the active pattern in the sense amplifier circuit layout adjacent to the bias contact structure layout and the first active pattern is equal to the distance between the active pattern in the sense amplifier circuit layout adjacent to the bias contact structure layout and the second active pattern; the distance between the gate pattern in the sense amplifier circuit layout adjacent to the bias contact structure layout and the gate extension pattern is equal to the distance between the gate pattern in the sense amplifier circuit layout adjacent to the bias contact structure layout and the second equalization pattern.

[0026] In addition, the intervals between adjacent and spaced-apart first equalization layouts are the same.

[0027] In addition, the length of the second equalization pattern in the first direction is the same as the length of the first equalization pattern in the second direction.

[0028] In addition, in the first direction, the length of the bias contact pattern is greater than the length of the first equalization pattern, and a part of the bias contact pattern is also located on the top surface of the second equalization pattern and is in contact with the second equalization pattern.

[0029] In addition, the sense amplifier circuit layout includes: a first NMOS region layout, a second NMOS layout, a first PMOS region layout, and a second PMOS region layout.

[0030] In addition, the memory layout further includes: an equalization circuit layout, which is disposed between two adjacent memory array layouts based on the axis of symmetry; an input / output circuit layout, which is disposed between two adjacent memory array layouts based on the axis of symmetry.

[0031] Compared with the related art, by ensuring that the distances between the active patterns in the adjacent sense amplifier circuit layout and the first active pattern and the second active pattern are equal, it is ensured that the bias contact structure layout disposed in the gap of the read / write conversion circuit layout does not change the environment of the active patterns in the different sense amplifier circuit layouts on both sides; by ensuring that the distances between the gate patterns in the adjacent sense amplifier circuit layout and the gate extension pattern and the second equalization pattern are equal, it is ensured that the bias contact structure layout disposed in the gap of the read / write conversion circuit layout does not change the environment of the gate patterns in the different sense amplifier circuit layouts on both sides. Description of the Drawings

[0032] Figure 1 is a schematic structural diagram of the memory;

[0033] Figure 2 is a schematic structural diagram of the memory structure provided by an embodiment of the present application;

[0034] Figure 3 is a schematic structural diagram of the read / write conversion circuit provided by an embodiment of the present application;

[0035] Figure 4 is a schematic structural diagram of the bias contact structure provided by an embodiment of the present application;

[0036] Figure 5 is a schematic cross-sectional structural diagram of the bias contact structure provided by an embodiment of the present application;

[0037] Figure 6 is a schematic combined structural diagram of the read / write conversion circuit and the bias contact structure provided by an embodiment of the present application;

[0038] Figure 7 is a schematic layout diagram of the memory structure provided by an embodiment of the present application;

[0039] Figure 8 is a schematic structural diagram of the memory layout provided by another embodiment of the present application;

[0040] Figure 9 is a schematic layout diagram of the memory layout provided by another embodiment of the present application. Detailed Embodiments

[0041] Reference Figure 1, in the structure of the memory, each memory array 101 contains multiple memory cells 111. The memory cell 111 has a 1T1C (1 transistor 1 capacitance) structure composed of a unit transistor and a unit capacitor. The read / write conversion circuit 200, the sense amplifier circuit 300, the equalization circuit 400, and the input / output circuit 500 are arranged between adjacent memory arrays.

[0042] Among them, one terminal of the source / drain of the unit transistor is connected to the unit capacitor, and the other terminal is connected to the bit line BL / complementary bit line BLB. The word line WL is connected to the gate of the unit transistor, and is used to select and turn on the gate of the corresponding unit transistor, so that the unit capacitor is connected to the bit line BL / complementary bit line BLB, thereby realizing writing the electrical signal in the bit line BL / complementary bit line BLB into the unit capacitor, or realizing reading the electrical signal in the unit capacitor to the bit line BL / complementary bit line BLB.

[0043] The equalization circuit 400 is connected to the bit line BL and the complementary bit line BLB, and is used to equalize the voltage between the bit line BL and the complementary bit line BLB during the pre-charge stage.

[0044] The input / output circuit 500 includes: an input / output transistor. One terminal of the source / drain of the input / output transistor is connected to the bit line BL / complementary bit line BLB, and the other terminal is connected to the local data line Local I / O. The gate is used to receive a selection signal, and according to the selection signal, select and turn on the corresponding bit line BL / complementary bit line BLB of the selection signal, so that the bit line BL / complementary bit line BLB is connected to the local data line Local I / O, thereby realizing data transfer between the bit line BL / complementary bit line BLB and the local data line Local I / O.

[0045] The local data line Local I / O is connected to the global data line Global I / O through the read / write conversion circuit 200, thereby realizing transferring external data or data in the local sense amplifier (placed in the read / write conversion circuit 200) to the local data line Local I / O, or outputting the data in the local data line Local I / O to the global data line Global I / O.

[0046] The sense amplifier circuit 300 is connected between the bit line BL and the complementary bit line BLB. When the electrical signal in the unit capacitor is read to the bit line BL / complementary bit line BLB, due to the charge sharing between the unit capacitor and the bit line BL / complementary bit line BLB, the voltage of the bit line BL / complementary bit line BLB increases or decreases by a voltage change amount △V from the pre-charge voltage. The sense amplifier circuit 300 is used to read and amplify the voltage change amount △V between the bit line BL and the complementary bit line BLB in response to the first control signal PCS and the second control signal NCS.

[0047] Among them, the bias voltage supply points are located on the opposite sides of the read / write conversion circuit 200 in the length direction, and the distance between adjacent bias voltage supply points is large. For the MOS transistor structures of different sense amplifiers arranged between the memory cells 111, the MOS transistors located in the middle region are farther away from the bias voltage supply points, resulting in a large error in the body bias voltage of the MOS transistors in the middle region compared to the body bias voltage of the MOS transistors at the edge, thus affecting the overall amplification ability of the sense amplifier. In addition, the required bias voltages of the read / write conversion circuits at different positions may also be different, further reducing the DRAM performance.

[0048] To solve the above problems, embodiments of the present application provide a memory structure and a memory layout, including: a memory array, and each memory array includes a plurality of memory cells; a read / write conversion circuit, arranged between two adjacent memory arrays in a first direction, the read / write conversion circuit is arranged in a second direction and has a symmetry axis in the second direction, for writing external data into the memory cells or reading the data of the memory cells, the first direction and the second direction are perpendicular to each other; a sense amplifier circuit, symmetrically arranged between two adjacent memory arrays according to the symmetry axis and coupled to the memory cells of the adjacent memory arrays, for sensing the memory cell voltage and outputting a logic 1 or 0 corresponding to the memory cell voltage; a bias contact structure, arranged in the gap between the read / write conversion circuits, for setting the bias voltage of the well region where the bias contact structure is located; wherein, in the first direction, the distance between the sense amplifier circuit adjacent to the bias contact structure and the read / write conversion circuit is equal to the distance from the bias contact structure.

[0049] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the following will elaborate on each embodiment of the present application with reference to the accompanying drawings. However, those of ordinary skill in the art can understand that in each embodiment of the present application, many technical details are presented for the convenience of readers to better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions required to be protected by the present application can still be implemented. The following division of each embodiment is for convenience of description and should not constitute any limitation to the specific implementation manner of the present application. Each embodiment can be combined with each other and cross-referenced on the premise of no contradiction.

[0050] Figure 2 It is a schematic structural diagram of the memory structure provided by this embodiment. Figure 3 It is a schematic structural diagram of the read / write conversion circuit provided by this embodiment. Figure 4 It is a schematic structural diagram of the bias contact structure provided by this embodiment. Figure 5 It is a schematic cross-sectional structure diagram of the bias contact structure provided by this embodiment. Figure 6Schematic diagram of the combined structure of the read / write conversion circuit and the bias contact structure provided in this embodiment Figure 7 Schematic diagram of the layout of the memory structure provided in this embodiment; The memory structure provided in this embodiment will be further described in detail below with reference to the accompanying drawings, specifically as follows:

[0051] Refer to Figure 2 , the memory structure includes:

[0052] A memory array 101, and each memory array 101 includes a plurality of memory cells 111 (refer to Figure 1 );

[0053] A read / write conversion circuit 200 is provided between two adjacent memory arrays 101 in the first direction X. The read / write conversion circuits 200 are arranged in the second direction Y and have a symmetry axis AA1 in the second direction, and are used to write external data into the memory cells 111 (refer to Figure 1 ), or read the data of the memory cells 111; wherein, the first direction X and the second direction Y are perpendicular to each other. It should be noted that in this embodiment, "external data" includes but is not limited to data in the global data line Global I / O (refer to Figure 1 ) and the local sense amplifier (refer to Figure 1 , placed in the read / write conversion circuit 200).

[0054] A sense amplifier circuit 300 is symmetrically arranged between two adjacent memory arrays 101 according to the symmetry axis AA1 and couples the memory cells 111 of the adjacent memory arrays 101 (refer to Figure 1 ), and is used to sense the voltage of the memory cells 111 (refer to Figure 1 ) and output a logic 1 or logic 0 corresponding to the memory cells 111 (refer to Figure 1 ).

[0055] It should be noted that in the gap between adjacent memory arrays 101, the structures of the read / write conversion circuits 200 and the sense amplifier circuits 300 are arranged in the second direction Y, that is, in the second direction Y, there are a plurality of read / write conversion circuits 200 and sense amplifier circuits 300 arranged.

[0056] The bias contact structure 600 is disposed in the gap between the read / write conversion circuits 200 and is used to set the bias voltage of the well region where the bias contact structure 600 is located. The bias contact structure 600 is disposed in the gap between the read / write conversion circuits 200, thereby reducing the distance between the bias contact structure 600 and the MOS transistors in different sense amplifier circuits 300, and thus avoiding the deviation of the body bias voltage of the MOS transistors in the sense amplifier circuit structure in the middle region compared with the body bias voltage of the MOS transistors at the edge, so as to balance the body bias voltages of the MOS transistors in different sense amplifiers disposed between the memory arrays 101; the substrate bias is provided by the bias contact structures 600 at different positions to reduce the body resistance of the substrate of the MOS transistor and reduce the latch-up risk of the MOS transistor.

[0057] It should be noted that, in this embodiment, the MOS transistors in the read / write conversion circuit 200 are all of NMOS structure, and the NMOS in the bias contact structure 600, the read / write conversion circuit 200, and the sense amplifier circuit 300 are disposed in the same well region; in other embodiments, the MOS transistors in the read / write conversion circuit may also be of PMOS structure, and correspondingly, the PMOS in the bias contact structure, the read / write conversion circuit, and the sense amplifier circuit are disposed in the same well region.

[0058] In the first direction X, the distance s1 between the sense amplifier circuit 300 adjacent to the bias contact structure 600 and the read / write conversion circuit 200 is equal to the distance s2 from the bias contact structure 600; by setting s1 = s2, to ensure that the environments of the MOS transistors in the different sense amplifier circuits 300 disposed on both sides of the read / write conversion circuit 200 are the same, to balance the device characteristics of the MOS transistors in different sense amplifiers, and further improve the stability of the DRAM.

[0059] In this embodiment, in the second direction Y, the distances d2 between adjacent bias contact structures 600 are equal; in other embodiments, the distances between the bias contact structures may also be set differently according to the MOS transistor structure in the sense amplifier circuit.

[0060] This embodiment specifically describes the MOS transistors in the read / write conversion circuit 200 as N-type MOS transistors, which does not constitute a limitation to this embodiment. In other embodiments, the MOS transistors in the read / write conversion circuit may be P-type MOS transistors.

[0061] Specifically, referring to Figure 3 , the MOS transistor structure in the read / write conversion circuit 200 includes:

[0062] A first active region 202 is disposed in the well region 201 of the semiconductor substrate and extends in the second direction Y.

[0063] The gate structure 203 is disposed at intervals on the first active region 202, extends in the first direction X, and the extending direction is the same as that of the MOS transistor gate structure in the sense amplifier circuit 300.

[0064] The gate structure 203 of the read / write conversion circuit 200 extends in the first direction, and the read / write conversion circuit 200 has a symmetry axis AA1 in the second direction Y. By setting the extending direction of the MOS transistor gate structure 203 in the read / write conversion circuit 200 to be the same as that of the MOS transistor gate structure in the sense amplifier circuit 300, it is further ensured that the distances between the gate structures of the corresponding MOS transistors in the sense amplifier circuits 300 on both sides of the read / write conversion circuit 200 and the gate structure 203 of the MOS transistors in the read / write conversion circuit 200 are equal, thereby balancing the device characteristics of the sense amplifiers on both sides of the read / write conversion circuit 200, and further improving the stability of the DRAM.

[0065] The gate extension structure 204 is disposed at the edge of the gate structure 203 on the first active region 202 and extends in the second direction Y. The gate extension structure 204 and the gate structure 203 enclose an annular gate structure 206. In the first direction X, the distance d0 (reference Figure 6 ) between the gate structure of the MOS transistor in the sense amplifier circuit 300 adjacent to the gate extension structure 204 and the gate extension structure 204 is equal; by forming the gate extension structure 204 at the edge of the gate structure 203, the gate extension structure 204 and the gate structure 203 together form an annular gate structure 206, and the gate extension structure 204 extends in the second direction Y, that is, the gate extension structure 204 is arranged in parallel with the adjacent sense amplifier circuit 300, ensuring that the distances between the gate structures of the MOS transistors in the sense amplifier circuit 300 at any adjacent position and the gate extension structure 204 are equal.

[0066] In this embodiment, the material of the gate extension structure 204 is the same as that of the gate structure 203, the height of the top surface of the gate extension structure 204 is the same as that of the top surface of the gate structure 203, and the thickness of the gate extension structure 204 is the same as that of the gate structure 203; by ensuring that the materials, thicknesses, and heights of the gate extension structure 204 and the gate structure 203 are the same, the gate extension structure 204 and the gate structure 203 can be formed in the same process step.

[0067] The conductive contact structure 205 is disposed on the first active region 202 in the gap between two adjacent gate structures 203. The height of the top surface of the conductive contact structure 205 is higher than that of the top surface of the gate structure 203. The first active regions 202 on both sides of the gate structure 203 serve as the source and drain of the MOS transistor respectively. One end of the conductive contact structure 205 is electrically connected to the first active regions 202 on both sides of the gate structure 203, and the other end is used to export the signals of the first active region 202.

[0068] In this embodiment, the conductive contact structure 205 and the gate extension structure 204 are insulated from each other.

[0069] In one example, the conductive contact structure 205 extends in the first direction X, and there is no contact between the conductive contact structure 205 and the annular gate structure 206. By separately disposing the conductive contact structure 205 and the annular gate structure 206, the conductive contact structure 205 and the gate extension structure 204 are insulated from each other.

[0070] In another example, the read / write conversion circuit 200 further includes: an isolation structure located on the inner circumferential sidewall of the annular gate structure 206, and the conductive contact structure 205 fills the remaining gap of the annular gate structure 206, so that the conductive contact structure 205 and the gate extension structure 204 are insulated from each other through the isolation structure.

[0071] Specifically, referring to Figure 4 and Figure 5 , Figure 5 is Figure 4 the cross-sectional schematic diagram along the BB1 direction in

[0072] The doped region 220 is disposed in the well region 201; the ion type doped in the doped region 220 is the same as that doped in the well region 201, and the ion concentration doped in the doped region 220 is greater than that doped in the well region 201.

[0073] The second active region 212 is disposed in the doped region 220.

[0074] The isolation region 230 (refer to Figure 5 ) surrounds and is disposed at the edge of the second active region 212.

[0075] The first balancing structure 213 is spaced apart and disposed on the second active region 212, and the length of the first balancing structure 213 in the second direction Y is less than the length of the first balancing structure 213 in the first direction X.

[0076] The second balancing structure 214 is disposed on the second active region 212 and the isolation region 230 (refer to Figure 5) extends in the second direction Y, is located at the edge of the first balancing structure 213, and forms an annular balancing structure 216 with the first balancing structure 213.

[0077] In this embodiment, in the first direction X, the length s4 of the outer side surface of the annular balancing structure 216 (refer to Figure 4 ) is the same as the length s3 of the outer side surface of the annular gate structure 206 (refer to Figure 3 ).

[0078] In one example, the length of the first balancing structure 213 in the first direction X is dx, the length dz of the second balancing structure 214 in the first direction X is the same as the length dy of the first balancing structure 213 in the second direction Y, and dx is greater than dy.

[0079] In one example, the material of the first balancing structure 213 is the same as that of the second balancing structure 213, the height of the top surface of the first balancing structure 213 is the same as the height of the top surface of the second balancing structure 214, and the thickness of the first balancing structure 213 is the same as the thickness of the second balancing structure 213; by ensuring that the materials, thicknesses, and heights of the first balancing structure 213 and the second balancing structure 214 are the same, the first balancing structure 213 and the second balancing structure 214 can be formed in the same process step.

[0080] Furthermore, in one example, the materials of the first balancing structure 213 and the second balancing structure 214 are the same as the material of the gate structure 203. By ensuring that the materials of the first balancing structure 213 and the second balancing structure 214 are the same as the material of the gate structure 203, the annular gate structure 206 and the annular balancing structure 216 can be formed in the same process step.

[0081] The bias contact structure 215 is disposed on the second active region 212 in the gap between two adjacent first balancing structures 213, and the height of the top surface of the bias contact structure 215 is higher than the height of the top surface of the first balancing structure 213.

[0082] Specifically, in the first direction X, the length of the bias contact structure 215 is greater than the length of the first balancing structure 213, and a part of the bias contact structure 215 is also located on the top surface of the second balancing structure 214 and is in contact with the second balancing structure. By setting the bias contact structure 215 to be in contact with the second balancing structure 214, that is, the bias contact structure 215 is also indirectly in contact with the first balancing structure 213, that is, the bias contact structure 215 is also used to balance the voltage of the annular balancing structure 216 and prevent the annular balancing structure 216 from being in a floating state.

[0083] In one example, the materials of the bias contact structure 215 and the conductive contact structure 205 are the same, such that the bias contact structure 215 and the conductive contact structure 205 can be formed in the same process step.

[0084] Reference Figure 6 , the extending direction of the gate structure of the MOS transistor in the sense amplifier circuit 300 is the same as that of the gate structure of the MOS transistor in the read / write conversion circuit 200; the sense amplifier circuit 300 is arranged based on the symmetry axis AA1 of the read / write conversion circuit 200, that is, the MOS transistors in different sense amplifier circuits 300 are arranged based on the symmetry axis AA1 of the read / write conversion circuit 200, so as to ensure that the environments of the corresponding MOS transistors in the sense amplifier circuits 300 arranged on both sides of the read / write conversion circuit 200 are the same; it should be noted that in this embodiment, "environment" being the same means that the characteristics such as the size, distance, and arrangement manner of the semiconductor structures composed of the same surrounding materials are the same.

[0085] For the MOS transistor structure in the read / write conversion circuit 200, in the first direction X, the distance between the active region of the MOS transistor in the sense amplifier circuit 300 adjacent to the MOS transistor structure in the read / write conversion circuit 200 and the first active region 202 is equal.

[0086] Specifically, the distance between the first active region 202 and the active regions in the sense amplifier circuits 300 on both sides is d1, and the distance from any edge position of the first active region 202 to the active regions in the sense amplifier circuits 300 on both sides is equal; the distance between the gate extension structure 204 and the gate structures in the sense amplifier circuits 300 on both sides is d0, and the distance from any edge position of the gate extension structure 204 to the gate structures in the sense amplifier circuits 300 on both sides is equal, so as to ensure that the environments of the gate structures of different MOS transistors in the sense amplifier circuits arranged on both sides of the read / write conversion circuit 200 are the same; in addition, the interval d5 between the adjacent and spaced gate structures 203 is the same.

[0087] For the bias contact structure 600, in the first direction X, the distance between the active region of the MOS transistor in the sense amplifier circuit 300 adjacent to the bias contact structure 600 and the second active region 212 is equal.

[0088] Specifically, the distance between the second active region 212 and the active regions in the sense amplifier circuits 300 on both sides is d4, and the distance from any edge position of the second active region 212 to the active regions in the sense amplifier circuits 300 on both sides is equal.

[0089] Further, in the sense amplifier circuit 300 adjacent to the bias contact structure 600, the distance d1 between the active region and the first active region 202 is equal to the distance d4 from the second active region 212, that is, d1 = d4; by ensuring that the distance d4 between the active region in the adjacent sense amplifier circuit 300 and the second active region 212 is equal to the distance d1 from the first active region 202, it is ensured that the bias contact structure 600 disposed in the gap of the read / write conversion circuit 200 does not change the environment of the active region in the sense amplifier circuit 300.

[0090] The distance between the second equalization structure 214 and the gate structures in the sense amplifier circuits 300 on both sides is d3, and any edge of the second equalization structure 214 is located at an equal distance from the gate structures in the sense amplifier circuits 300 on both sides, so as to ensure that the environments of the gate structures of different MOS transistors in the sense amplifier circuits 300 on both sides of the bias contact structure 600 are consistent; in addition, the intervals d6 between the adjacent and spaced first equalization structures 213 are the same.

[0091] Further, in the sense amplifier circuit 300 adjacent to the bias contact structure 600, the distance d0 between the gate structure and the gate extension structure 204 is equal to the distance d3 from the second equalization structure 214, that is, d0 = d3; by ensuring that the distance between the gate structure in the adjacent sense amplifier circuit 300 and the gate extension structure 204 is equal to the distance from the second equalization structure 214, it is ensured that the bias contact structure 600 disposed in the gap of the read / write conversion circuit 200 does not change the environment of the gate structure in the sense amplifier circuit 300.

[0092] Reference Figure 7 , in this embodiment, the sense amplifier circuit 300 includes:

[0093] The first NMOS region 310 circuit is coupled to the memory cells 111 in the adjacent memory array 101 (reference Figure 1 ), the second NMOS region 320 circuit is coupled to the memory cells 111 in the adjacent memory array 101 (reference Figure 1 ), the first PMOS region 301 circuit is coupled to the memory cells 111 in the adjacent memory array 101 (reference Figure 1 ), and the second PMOS region 302 circuit is coupled to the memory cells 111 in the adjacent memory array 101 (reference Figure 1); wherein, the first NMOS region 310 circuits in the sense amplifier circuits 300 on both sides of the read / write conversion circuit 200 are symmetrically arranged according to the axis of symmetry AA1, the second NMOS region 320 circuits in the sense amplifier circuits 300 on both sides of the read / write conversion circuit 200 are symmetrically arranged according to the axis of symmetry AA1, the first PMOS region 301 circuits in the sense amplifier circuits 300 on both sides of the read / write conversion circuit 200 are symmetrically arranged according to the axis of symmetry AA1, and the second PMOS region 302 circuits in the sense amplifier circuits 300 on both sides of the read / write conversion circuit 200 are symmetrically arranged according to the axis of symmetry AA1.

[0094] Continue to refer to Figure 7 , the sense amplifier circuit 300 further includes: an equalization circuit 400, which is symmetrically arranged between two adjacent memory arrays 101 according to the axis of symmetry AA1 and is electrically connected to the sense amplifier circuit 300 for equalizing the voltages of the lines coupling the sense amplifier circuit 300 to the memory cells 111 (refer to Figure 1 ); an input / output circuit 500, which is symmetrically arranged between two adjacent memory arrays 101 according to the axis of symmetry AA1 and is electrically connected to the memory cells 111 of the adjacent memory arrays 101 for selecting the memory cells 111 in the memory array 101. When the memory performs a write operation, the data on the local data line Local I / O is transmitted to the bit line BL and then written into the memory cell 111; when the memory performs a read operation, the data on the bit line BL is transmitted to the local data line Local I / O and then the memory is read out.

[0095] Regarding the arrangement of the sense amplifier circuit 300, the equalization circuit 400, the input / output circuit 500, and the read / write conversion circuit 200, the read / write conversion circuit 200 is arranged in the middle of the gap between two adjacent memory arrays 101, and the read / write conversion circuit 200 has an axis of symmetry AA1. The first NMOS region 310 circuits, the second NMOS region 320 circuits, the first PMOS region 301 circuits, the second PMOS region 302 circuits, the equalization circuit 400, and the input / output circuit 500 in the sense amplifier circuits arranged on both sides of the read / write conversion circuit 200 are symmetrically arranged on both sides of the read / write conversion circuit 200 based on the axis of symmetry AA1, respectively.

[0096] Specifically, in one arrangement, refer to Figure 7In the arrangement shown in P1 and P2, the first NMOS region 310 circuit, the second NMOS region 320 circuit, the first PMOS region 301 circuit, and the second PMOS region 302 circuit are alternately arranged on one side of the read / write conversion circuit 200. The equalization circuit 400 and the input / output circuit 500 can be located at any position between the first NMOS region 310 circuit, the second NMOS region 320 circuit, the first PMOS region 301 circuit, and the second PMOS region 302 circuit. The equalization circuit 400 on the same side serves as the equalization circuit 400 of a sense amplifier circuit 300 (reference Figure 1 ).

[0097] In one arrangement, referring to Figure 7 the arrangement shown in P3 and P4, the first NMOS region 310 circuit and the second NMOS region 320 circuit are located between the first PMOS region 301 circuit and the second PMOS region 302 circuit, or the first PMOS region 301 circuit and the second PMOS region 302 circuit are located between the first NMOS region 310 circuit and the second NMOS region 320 circuit. The equalization circuit 400 and the input / output circuit 500 can be located at any position between the first NMOS region 310 circuit, the second NMOS region 320 circuit, the first PMOS region 301 circuit, and the second PMOS region 302 circuit. The equalization circuit 400 on the same side serves as the equalization circuit 400 of a sense amplifier circuit 300 (reference Figure 1 ).

[0098] It should be noted that in the arrangement shown in Figure 7 , only the layout diagram of the sense amplifier circuit 300 on one side of the read / write conversion circuit 200 is given. The sense amplifier circuit on the other side of the read / write conversion circuit 200 is symmetrically arranged based on the symmetry axis AA1 with the layout of the shown sense amplifier circuit 300.

[0099] Compared with the related art, the bias contact structure is disposed in the gap between the read / write conversion circuits, thereby reducing the distance between the bias contact structure and the MOS transistors in different sense amplifier circuits, and avoiding the deviation of the body bias voltage of the MOS transistors in the sense amplifier circuit structure in the middle region compared with the body bias voltage of the MOS transistors at the edge, so as to balance the body bias voltage of the MOS transistors in different sense amplifiers disposed between the memory arrays; the substrate bias is provided by the bias contact structures at different positions to reduce the body resistance of the substrate of the MOS transistors and reduce the latch-up risk of the MOS transistors. In addition, the distance between the sense amplifier circuit adjacent to the bias contact structure and the read / write conversion circuit is equal to the distance between the sense amplifier circuit and the bias contact structure, so as to ensure that the environments of the corresponding MOS transistors in the different sense amplifier circuits disposed on both sides of the read / write conversion circuit are the same, balance the device characteristics of the corresponding MOS transistors in different sense amplifiers, and further improve the stability of the DRAM.

[0100] Another embodiment of the present application further provides a memory layout, including: a memory array layout; a read / write conversion circuit layout disposed between two adjacent memory array layouts in the first direction, the read / write conversion circuit layout is arranged in the second direction and has a symmetry axis in the second direction, the first direction and the second direction are perpendicular; a sense amplifier circuit layout symmetrically disposed between two adjacent memory array layouts based on the symmetry axis; a bias contact structure layout disposed in the gap between the read / write conversion circuit layouts; in the first direction, the distance between the sense amplifier circuit layout adjacent to the bias contact structure layout and the read / write conversion circuit layout is equal to the distance between the sense amplifier circuit layout and the bias contact structure layout.

[0101] Figure 8 is a schematic structural diagram of the memory layout provided in this embodiment, Figure 9 is a schematic layout diagram of the memory layout provided in this embodiment. The memory layout provided in this embodiment will be further described in detail below with reference to the accompanying drawings, specifically as follows:

[0102] Refer to Figure 8 , the memory layout, including:

[0103] a memory array layout 601 extending in the second direction Y, and the memory array layout 601 is used to form a memory array 101 (refer to Figure 1 ).

[0104] a read / write conversion circuit layout 700 disposed between two adjacent memory array layouts 601 in the first direction X, the read / write conversion circuit layout 700 is arranged in the second direction Y and has a symmetry axis AA1 in the second direction Y, the first direction X and the second direction Y are perpendicular, and the read / write conversion circuit layout 700 is used to form a read / write conversion circuit 200 (refer to Figure 1 ).

[0105] The layout 800 of the sense amplifier circuit is symmetrically arranged between two adjacent memory array layouts 601 based on the axis of symmetry AA1. Among them, the extending direction of the gate pattern 802 in the sense amplifier circuit layout 800 is the same as that of the gate pattern 702 in the read / write conversion circuit layout 700.

[0106] It should be noted that only a partial schematic diagram of the sense amplifier circuit layout 800 is given in the figure, which is a partial MOS layout adjacent to the read / write conversion circuit layout 700. Those skilled in the art understand that the sense amplifier circuit layout 800 also includes other structures, enabling the memory formed by the memory layout to operate normally.

[0107] The layout 900 of the bias contact structure is arranged in the gap between the read / write conversion circuit layouts 700 for forming the bias contact structure 200 (refer to Figure 2 ).

[0108] It should be noted that in the second direction Y, only a schematic diagram of one bias contact structure layout 900 and the read / write conversion circuit layout 700 is shown in this embodiment. In the second direction Y, there are also multiple read / write conversion circuit layouts 700 and bias contact structure layouts 900, as well as the sense amplifier circuit layouts 800 located on both sides of the read / write conversion circuit layouts 700 and the bias contact structure layouts 900 respectively.

[0109] In the first direction X, the distance between the sense amplifier circuit layout 800 adjacent to the bias contact structure layout 900 and the read / write conversion circuit layout 700 is equal to the distance between the sense amplifier circuit layout 800 and the bias contact structure layout 900.

[0110] Refer to Figure 9 , in this embodiment, the distance l2 between adjacent bias contact structure layouts 900 is equal.

[0111] It should be noted that Figure 8 the structures of the equalization circuit layout and the input / output circuit layout are not shown. Based on the above description of the embodiments, those skilled in the art should understand that in this embodiment, the memory layout also includes: an equalization circuit layout, which is arranged between two adjacent memory array layouts 601 based on the axis of symmetry AA1 for forming the equalization circuit 400 (refer to Figure 1 ), and an input / output circuit layout, which is arranged between two adjacent memory array layouts 601 based on the axis of symmetry AA1 for forming the input / output circuit 500 (refer to Figure 1 ).

[0112] Specifically, the read / write conversion circuit layout 700 includes:

[0113] The first active pattern 701 is disposed in the well region of the semiconductor substrate and extends in the second direction Y for forming the first active region 202 (refer to Figure 3 ).

[0114] The gate pattern 702 is spaced apart from the first active pattern 701 and extends in the first direction X, and the extending direction is the same as that of the gate pattern 802 of the MOS transistor in the sense amplifier circuit layout 800, for forming the gate structure 203 (refer to Figure 3 ).

[0115] The gate extension pattern 704 is disposed at the edge of the gate pattern 702 on the first active pattern 601 and extends in the second direction. The gate extension pattern 704 and the gate pattern 703 enclose the first closed loop 705. In the first direction, the distance between the gate pattern 802 in the sense amplifier circuit layout 800 adjacent to the gate extension pattern 704 and the gate extension pattern 704 is equal.

[0116] The conductive contact pattern 703 is disposed on the first active pattern 701 in the gap between two adjacent gate patterns 702 for forming the conductive contact structure 205 (refer to Figure 3 ).

[0117] In this embodiment, the conductive contact pattern 703 and the gate extension pattern 704 are also insulated from each other.

[0118] In one example, refer to Figure 7 , the conductive contact pattern 703 extends in the first direction X, and the conductive contact pattern 703 does not contact the closed loop 705. By separately disposing the conductive contact pattern 703 and the closed loop 705, the conductive contact pattern 703 and the gate extension pattern 704 are insulated from each other.

[0119] In another example, the read / write conversion circuit pattern further includes an isolation pattern located on the inner sidewall of the ring of the closed loop, and the conductive contact pattern fills the remaining gap of the closed loop, so that the conductive contact pattern 703 and the gate extension pattern 704 are insulated from each other through the isolation pattern.

[0120] The bias contact structure layout 900 includes:

[0121] The doping pattern is disposed in the well region for forming the doped region 220 (refer to Figure 4 ).

[0122] The second active pattern 711 is disposed in the doping pattern and extends in the second direction Y for forming the second active region 212 (refer to Figure 4 ).

[0123] An isolation pattern (not shown) is disposed around the edge of the second active pattern 711 for forming an isolation layer 230 (refer to Figure 5 ).

[0124] The first equalization pattern 712 is spaced on the second active pattern 711, and the length of the first equalization pattern 717 in the second direction Y is less than the length of the first equalization pattern 712 in the first direction X for forming a first equalization structure 213 (refer to Figure 4 ).

[0125] The second equalization pattern 714 is disposed on the second active pattern 711 and the isolation pattern (not shown), extends in the second direction Y, and is located at the edge of the first equalization pattern 712 for forming a second equalization structure 214 (refer to Figure 4 ), and encloses a second closed loop 715 with the first equalization pattern 712; in the first direction X, the length of the outer side surface of the first closed loop 705 is the same as the length of the outer side surface of the second closed loop 715.

[0126] In one example, the length of the second equalization pattern 714 in the first direction X is the same as the length of the first equalization pattern 712 in the second direction Y.

[0127] The bias contact pattern 713 is disposed on the second active pattern 711 in the gap between two adjacent first equalization patterns 712.

[0128] In one example, in the first direction X, the length of the bias contact pattern 713 is greater than the length of the first equalization pattern 711, and the bias contact pattern 713 is further located on the top surface of the second equalization pattern 714 and is in contact with the second equalization pattern.

[0129] For the read / write conversion circuit layout 700, in the first direction X, the distance between the active pattern 801 in the sense amplifier circuit layout 800 adjacent to the read / write conversion circuit layout 700 and the first active pattern 701 is equal.

[0130] Specifically, the distance between the first active pattern 701 and the active pattern 801 in the sense amplifier circuit layouts 800 on both sides is d1, and the distance from any edge position of the first active pattern 701 to the active pattern 801 in the sense amplifier circuit layouts 800 on both sides is equal; the distance between the gate extension pattern 704 and the gate pattern 801 in the sense amplifier circuit layouts 800 on both sides is d0, and the distance from any edge position of the gate extension pattern 704 to the gate pattern 801 in the sense amplifier circuit layouts 800 on both sides is equal to ensure the same environment for the gate patterns 801 of different MOS transistors in the sense amplifier circuit layouts 800 on both sides of the read / write conversion circuit layout 700; in addition, the intervals between adjacent and spaced gate patterns 702 are the same.

[0131] For the layout 900 of the bias contact structure, in the first direction X, the distances between the active pattern 801 in the sense amplifier circuit layout 800 adjacent to the layout 900 of the bias contact structure and the second active pattern 711 are equal.

[0132] Specifically, the distance between the second active pattern 711 and the active pattern 801 in the sense amplifier circuit layout 800 on both sides is d4, and the distances from any edge position of the second active pattern 711 to the active pattern 801 in the sense amplifier circuit layout 800 on both sides are equal.

[0133] Furthermore, the distance d1 between the active pattern 801 in the sense amplifier circuit layout 800 adjacent to the layout 900 of the bias contact structure and the first active pattern 701 is equal to the distance d4 from the active pattern 801 to the second active pattern 711, that is, d1 = d4; by ensuring that the distance d4 between the active pattern 801 in the adjacent sense amplifier circuit layout 800 and the second active pattern 711 is equal to the distance d1 from the active pattern 801 to the first active pattern 701, it is ensured that the layout 900 of the bias contact structure arranged in the gap of the read / write conversion circuit layout 700 does not change the environment of the active pattern 801 in the sense amplifier circuit layout 800.

[0134] The distance between the second equalization pattern 714 and the gate pattern 802 in the sense amplifier circuit layout 800 on both sides is d3, and the distances from any edge of the second equalization pattern 714 to the gate pattern 802 in the sense amplifier circuit layout 800 on both sides are equal, so as to ensure that the environments of the gate patterns 802 of different MOS transistors in the sense amplifier circuit layout 800 on both sides of the read / write conversion circuit layout 700 are consistent; in addition, the intervals between the adjacent and spaced first equalization patterns 712 are the same.

[0135] Furthermore, the distance d0 between the gate pattern 802 in the sense amplifier circuit layout 800 adjacent to the layout 900 of the bias contact structure and the gate extension pattern 704 is equal to the distance d3 from the gate pattern 802 to the second equalization pattern 714, that is, d0 = d3; by ensuring that the distances between the gate pattern 802 in the adjacent sense amplifier circuit layout 800 on both sides and the gate extension pattern 704 are equal to the distances from the gate pattern 802 to the second equalization pattern 714, it is ensured that the layout 900 of the bias contact structure arranged in the gap of the read / write conversion circuit layout 700 does not change the environment of the gate pattern 802 in the sense amplifier circuit layout 800 on both sides.

[0136] In addition, in this embodiment, the sense amplifier circuit layout 800 includes: the first NMOS region layout, the second NMOS region layout, the first PMOS region layout, and the second PMOS region layout; it should be noted that Figure 9The layout schematic diagram does not show the schematic diagrams of the above-mentioned first NMOS region layout, second NMOS region layout, first PMOS region layout, and second PMOS region layout. Those skilled in the art can refer to Figure 7 for the layout schematic; wherein, the first NMOS region layout and the second NMOS region layout are arranged between two adjacent memory array layouts 601 according to the symmetry axis AA1, and the first PMOS region layout and the second PMOS region layout are arranged between two adjacent memory array layouts 601 according to the symmetry axis AA1; wherein, the first NMOS region layout is used to form the first NMOS region 310 circuit (refer to Figure 7 ), the second NMOS region layout is used to form the second NMOS region 320 circuit (refer to Figure 7 ), the first PMOS region layout is used to form the first PMOS region 301 circuit (refer to Figure 7 ), the second PMOS region layout is used to form the second PMOS region 302 circuit (refer to Figure 7 ), so as to realize a storage structure as shown in Figure 7 .

[0137] Compared with the related art, by ensuring that the distances between the active patterns in the layout of the adjacent sense amplifier circuit and the first active pattern and the second active pattern are equal, it is ensured that the layout of the bias contact structure arranged in the gap of the read / write conversion circuit layout does not change the environment of the active patterns in the layout of the different sense amplifier circuits on both sides; by ensuring that the distances between the gate patterns in the layout of the adjacent sense amplifier circuit and the gate extension pattern and the second equalization pattern are equal, it is ensured that the layout of the bias contact structure arranged in the gap of the read / write conversion circuit layout does not change the environment of the gate patterns in the layout of the different sense amplifier circuits on both sides.

[0138] Since the above embodiments correspond to this embodiment, this embodiment can be implemented in cooperation with the above embodiments. The relevant technical details mentioned in the above embodiments are still valid in this embodiment, and the technical effects achievable in the above embodiments can also be achieved in this embodiment. To avoid repetition, they will not be elaborated here. Correspondingly, the relevant technical details mentioned in this embodiment can also be applied to the above embodiments.

[0139] Those of ordinary skill in the art can understand that the above embodiments are specific embodiments for implementing the present application, and in practical applications, various changes can be made in form and details without departing from the spirit and scope of the present application.

Claims

1. A memory structure, characterized in that, Comprising: A storage array, and each of the storage arrays includes a plurality of storage cells; A read / write conversion circuit, disposed between two adjacent storage arrays in a first direction, the read / write conversion circuit being arranged in a second direction and having a symmetry axis in the second direction, for writing external data into the storage cells or reading out the data of the storage cells, the first direction and the second direction being perpendicular to each other; A sense amplifier circuit, symmetrically disposed between two adjacent storage arrays according to the symmetry axis and coupling the storage cells of the adjacent storage arrays, for sensing the voltage of the storage cells and outputting a logic 1 or 0 corresponding to the voltage of the storage cells; A bias contact structure, disposed in the gap between the read / write conversion circuits, for setting the bias voltage of the well region where the bias contact structure is located; Wherein, in the first direction, the distance between the sense amplifier circuit adjacent to the bias contact structure and the read / write conversion circuit is equal to the distance between the sense amplifier circuit and the bias contact structure.

2. The memory structure according to claim 1, wherein In the second direction, the distances between adjacent bias contact structures are equal.

3. The memory structure according to claim 1, wherein The MOS transistor structure in the read / write conversion circuit includes: A first active region, disposed in the well region of the semiconductor substrate and extending in the second direction; A gate structure, spaced apart from the first active region and extending in the first direction, and the extending direction is the same as the extending direction of the MOS transistor gate structure in the sense amplifier circuit; A gate extension structure, disposed at the edge of the gate structure on the first active region and extending in the second direction, the gate extension structure and the gate structure enclosing an annular gate structure; In the first direction, the distance between the gate structure of the MOS transistor in the sense amplifier circuit adjacent to the gate extension structure and the gate extension structure is equal; A conductive contact structure, disposed on the first active region in the gap between two adjacent gate structures, and the height of the top surface of the conductive contact structure is higher than the height of the top surface of the gate structure.

4. The memory structure according to claim 3, wherein The bias contact structure includes: A doped region, disposed in the well region, the ion type doped in the doped region is the same as the ion type doped in the well region, and the ion concentration doped in the doped region is greater than the ion concentration doped in the well region; A second active region, disposed in the doped region; An isolation region, disposed around the edge of the second active region; A first equalization structure, spaced apart from the second active region, and the length of the first equalization structure in the second direction is less than the length of the first equalization structure in the first direction; A second equalization structure, disposed on the second active region and the isolation region, extending in the second direction, and located at the edge of the first equalization structure and enclosing an annular equalization structure with the first equalization structure; In the first direction, the length of the outer side surface of the annular equalization structure is the same as the length of the outer side surface of the annular gate structure; A bias contact structure is disposed on a second active region in a gap between two adjacent first equalization structures, and the height of the top surface of the bias contact structure is higher than the height of the top surface of the first equalization structure.

5. The memory structure according to claim 4, characterized in that, It includes: In the sense amplifier circuit adjacent to the bias contact structure, the distance between the active region and the first active region is equal to the distance between the active region and the second active region; In the sense amplifier circuit adjacent to the bias contact structure, the distance between the gate structure and the gate extension structure is equal to the distance between the gate structure and the second equalization structure.

6. The memory structure according to claim 4, wherein The intervals between the adjacent and spaced-apart first equalization structures are the same.

7. The memory structure according to claim 4, wherein The length of the second equalization structure in the first direction is the same as the length of the first equalization structure in the second direction.

8. The memory structure according to claim 4, wherein The material of the first equalization structure is the same as that of the second equalization structure, and the height of the top surface of the first equalization structure is the same as the height of the top surface of the second equalization structure, and the thickness of the first equalization structure is the same as the thickness of the second equalization structure.

9. The memory structure according to claim 4 or 8, characterized in that, The material of the first equalization structure, the material of the second equalization structure are the same as the material of the gate structure.

10. The memory structure according to claim 4, characterized in that, The bias contact structure fills the annular equalization structure.

11. The memory structure according to claim 4, wherein In the first direction, the length of the bias contact structure is greater than the length of the first equalization structure, and a part of the bias contact structure is also located on the top surface of the second equalization structure and is in contact with the second equalization structure.

12. The memory structure according to claim 4, wherein The material of the bias contact structure is the same as that of the conductive contact structure.

13. The memory structure according to claim 1, characterized in that, The sense amplifier circuit includes: A first NMOS region circuit coupled to the memory cells in the adjacent memory array; A second NMOS region circuit coupled to the memory cells in the adjacent memory array; A first PMOS region circuit coupled to the memory cells in the adjacent memory array; A second PMOS region circuit coupled to the memory cells in the adjacent memory array.

14. The memory structure according to claim 1, wherein It further includes: An equalization circuit symmetrically disposed between two adjacent memory arrays according to the symmetry axis and electrically connected to the sense amplifier circuit for equalizing the voltage of the lines through which the sense amplifier circuit couples the memory cells; An input / output circuit symmetrically disposed between two adjacent memory arrays according to the symmetry axis and electrically connected to the memory cells of the adjacent memory arrays for selecting the memory cells in the memory array.

15. A memory layout, characterized in that, It includes: A memory array layout; A read / write conversion circuit layout disposed between two adjacent memory array layouts in the first direction, the read / write conversion circuit layout is arranged in the second direction and has a symmetry axis in the second direction, and the first direction and the second direction are perpendicular; A sense amplifier circuit layout symmetrically disposed between two adjacent memory array layouts based on the symmetry axis; A bias contact structure layout disposed in the gap between the read / write conversion circuit layouts; In the first direction, the distance between the sense amplifier circuit layout adjacent to the bias contact structure layout and the read / write conversion circuit layout is equal to the distance between the sense amplifier circuit layout and the bias contact structure layout.

16. The memory layout according to claim 15, wherein In the second direction, the distances between adjacent bias contact structure layouts are equal.

17. The memory layout according to claim 15, wherein The read / write conversion circuit layout includes: A first active pattern, disposed in the well region of the semiconductor substrate and extending in the second direction; A gate pattern, spaced apart and disposed on the first active pattern, extending in the first direction, and having the same extension direction as the gate pattern of the MOS transistor in the sense amplifier circuit layout; A gate extension pattern, disposed at the edge of the gate pattern on the first active pattern and extending in the second direction, the gate extension pattern and the gate pattern enclosing a first closed loop; In the first direction, the distances between the gate patterns in the sense amplifier circuit layout adjacent to the gate extension pattern and the gate extension pattern are equal; A conductive contact pattern, disposed on the first active pattern in the gap between two adjacent gate patterns.

18. The memory layout according to claim 17, wherein The bias contact structure layout includes: A doping pattern, disposed in the well region; A second active pattern, disposed in the doping pattern and extending in the second direction; An isolation pattern, disposed around the edge of the second active pattern; A first equalization pattern, spaced apart and disposed on the second active pattern, and the length of the first equalization pattern in the second direction is less than the length of the first equalization pattern in the first direction; A second equalization pattern, disposed on the second active pattern and the isolation pattern, extending in the second direction, located at the edge of the first equalization pattern, and enclosing a second closed loop with the first equalization pattern; In the first direction, the length of the outer side surface of the first closed loop is the same as the length of the outer side surface of the second closed loop; A bias contact pattern, disposed on the second active pattern in the gap between two adjacent first equalization patterns.

19. The memory layout according to claim 18, wherein Includes: The distances between the active pattern in the sense amplifier circuit layout adjacent to the bias contact structure layout and the first active pattern and the second active pattern are equal; The distances between the gate pattern in the sense amplifier circuit layout adjacent to the bias contact structure layout and the gate extension pattern and the second equalization pattern are equal.

20. The memory layout according to claim 18, wherein The intervals between adjacent and spaced-apart first equalization patterns are the same.

21. The memory layout according to claim 18, characterized in that, The length of the second equalization pattern in the first direction is the same as the length of the first equalization pattern in the second direction.

22. The memory layout according to claim 18, wherein, In the first direction, the length of the bias contact pattern is greater than the length of the first equalization pattern, and a part of the bias contact pattern is also located on the top surface of the second equalization pattern and is in contact with the second equalization pattern.

23. The memory layout according to claim 15, wherein The sense amplifier circuit layout includes: a first NMOS region layout, a second NMOS layout, a first PMOS region layout, and a second PMOS region layout.

24. The memory layout according to claim 15, wherein Further includes: An equalization circuit layout, disposed between two adjacent memory array layouts based on the axis of symmetry; An input / output circuit layout, disposed between two adjacent memory array layouts based on the axis of symmetry.

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