Nanometer structure field effect transistor device and method of forming the same

Abstract

The present application provides nanostructure field effect transistor devices and methods of forming the same. A method of forming a semiconductor device includes forming a fin structure protruding above a substrate, wherein the fin structure includes a fin and a layer stack above the fin, the layer stack including alternating layers of a first semiconductor material and a second semiconductor material; forming a first dummy gate structure and a second dummy gate structure above the fin structure; forming an opening in the fin structure between the first dummy gate structure and the second dummy gate structure; converting an upper layer of the fin exposed to a bottom of the opening to a seed layer by performing an implantation process; selectively depositing a dielectric layer above the seed layer at the bottom of the opening; and selectively growing a source / drain material on opposing sidewalls of the second semiconductor material exposed by the opening.

Description

Technical Field

[0001] This disclosure generally relates to the field of semiconductor technology, and more specifically to nanostructured field-effect transistor devices and methods for forming the same. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by the following steps: depositing an insulating or dielectric material layer, a conductive material layer, and a semiconductor material layer on a semiconductor substrate, and using photolithography to pattern the various material layers to form circuit elements and assemblies thereon.

[0003] The semiconductor industry continuously increases the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by constantly reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, other problems arise that need to be addressed. Summary of the Invention

[0004] In one aspect of this application, a method of forming a semiconductor device is provided, the method comprising: forming a fin structure protruding above a substrate, wherein the fin structure includes a fin and a layer stack above the fin, the layer stack including alternating layers of a first semiconductor material and a second semiconductor material; forming a first dummy gate structure and a second dummy gate structure above the fin structure; forming an opening in the fin structure between the first dummy gate structure and the second dummy gate structure; converting an upper layer of the fin exposed at the bottom of the opening into a seed layer by performing an implantation process; selectively depositing a dielectric layer above the seed layer at the bottom of the opening; and selectively growing source / drain materials on opposite sidewalls of the second semiconductor material exposed by the opening.

[0005] In another aspect of this application, a method for forming a semiconductor device is provided, the method comprising: forming a fin structure over a substrate, the fin structure including a fin and a layer stack above the fin, the layer stack including alternating layers of a first semiconductor material and a second semiconductor material; forming a dummy gate structure over the fin structure; forming an opening in the fin structure adjacent to the dummy gate structure, wherein the sidewalls of the opening expose a first end of the first semiconductor material and a second end of the second semiconductor material, and wherein the bottom of the opening exposes an upper surface of the fin; replacing the first end of the first semiconductor material with an internal spacer; and forming a source / drain region in the opening, comprising: selectively depositing a dielectric layer above the upper surface of the fin; and selectively growing source / drain material on the second end of the second semiconductor material using an epitaxial growth process, wherein the source / drain material is spaced apart from the dielectric layer after the epitaxial growth process.

[0006] According to another aspect of this application, a semiconductor device is provided, comprising: a fin protruding above a substrate; a first gate structure located above the fin; a second gate structure located above the fin; a source / drain region located above the fin between the first gate structure and the second gate structure, wherein an air gap exists between the source / drain region and the fin; and a first channel layer below the first gate structure and a second channel layer below the second gate structure, wherein the source / drain region extends continuously from the first channel layer to the second channel layer. Attached Figure Description

[0007] The various aspects of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, according to industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily enlarged or reduced.

[0008] Figure 1 An example of a nanostructured field-effect transistor (NSFET) device according to some embodiments is shown in a three-dimensional view.

[0009] Figure 2 , Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figures 5A-5C , Figures 6A-6C , Figures 7-10 , Figures 11A-11C , Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 14A and Figure 14B This is a cross-sectional view of a nanostructured field-effect transistor device according to an embodiment at various stages of its fabrication.

[0010] Figure 15 This is a flowchart of a method for forming a semiconductor device in some embodiments. Detailed Implementation

[0011] The following disclosure provides many different embodiments or examples for implementing various features of the invention. Specific examples of elements and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature can include embodiments in which the first and second features are formed in direct contact, and can also include embodiments in which an additional feature can be formed between the first and second features such that the first and second features do not need to be in direct contact.

[0012] In addition, for ease of description, spatially related terms (e.g., "below," "below," "lower than," "above," "upper") may be used herein to describe the relationship of one element or feature shown in the figure relative to another element(s) or feature(s). These spatially related terms are intended to cover different orientations of the device in use or operation other than those shown in the figure. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein shall be interpreted accordingly.

[0013] According to some embodiments, an air gap is formed below the source / drain region of the nanostructured device, for example, between the source / drain region and the underlying fin. The air gap advantageously reduces the edge capacitance and leakage current of the formed device. To form the air gap, source / drain openings are formed in the fin structure between adjacent dummy gate structures. Next, an ion implantation process is performed to convert the upper layer of the fin exposed by the source / drain openings into a seed layer. Next, a dielectric layer is selectively formed on the seed layer. Next, epitaxial source / drain material is selectively grown on the semiconductor material exposed to the sidewalls of the source / drain openings. The dielectric layer at the bottom of the source / drain openings prevents the growth of epitaxial source / drain material from the bottom of the source / drain openings. Therefore, the source / drain material grows laterally from the sidewalls of the semiconductor material exposed by the source / drain openings and merges to form the source / drain region, forming an air gap between the source / drain region and the underlying dielectric layer disposed on the fin.

[0014] Figure 1An example of a nanostructured field-effect transistor (NSFET) device 30 according to some embodiments is shown in a three-dimensional view. The NSFET device 30 includes a semiconductor fin 90 (also referred to as a fin) protruding above a substrate 50. A gate electrode 122 (e.g., a metal gate) is disposed above the fin, and source / drain regions 112 are formed on opposite sides of the gate electrode 122. A plurality of nanostructures 54 (e.g., nanowires or nanosheets) are formed above the fin 90 and between the source / drain regions 112. An isolation region 96 is formed on opposite sides of the fin 90. A gate dielectric layer 120 is formed around the nanostructures 54. The gate electrode 122 is above and around the gate dielectric layer 120.

[0015] Figure 1 Reference cross sections used in later figures are also shown. Cross section AA is along the longitudinal axis of the gate electrode 122 and in a direction perpendicular to, for example, the direction of current flow between the source / drain regions 112 of the NSFET device 30. Cross section BB is perpendicular to cross section AA and along the longitudinal axis of the fin 90 in the direction of current flow between, for example, the source / drain regions 112 of the NSFET device. Cross section CC is parallel to cross section BB and lies between two adjacent fins 90. Cross section DD is parallel to cross section AA and extends through the source / drain regions 112 of the NSFET device. For clarity, subsequent figures refer to these reference cross sections.

[0016] Figure 2 , Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figures 5A-5C , Figures 6A-6C , Figures 7-10 , Figures 11A-11C , Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 14A and Figure 14B This is a cross-sectional view of a nanostructured field-effect transistor (NSFET) device 100 according to an embodiment at various stages of its fabrication.

[0017] exist Figure 2A substrate 50 is provided. The substrate 50 can be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., which may be doped (e.g., using p-type or n-type dopants) or undoped. The substrate 50 can be a wafer, such as a silicon wafer. Typically, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is disposed on the substrate (typically a silicon substrate or a glass substrate). Other substrates may also be used, such as multilayer substrates or gradient substrates. In some embodiments, the semiconductor material of the substrate 50 includes: silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof.

[0018] A multilayer stack 64 is formed on the substrate 50. The multilayer stack 64 includes alternating layers of a first semiconductor material 52 and a second semiconductor material 54. Figure 2 In the process, the layers formed by the first semiconductor material 52 are labeled as 52A, 52B and 52C, and the layers formed by the second semiconductor material 54 are labeled as 54A, 54B and 54C. Figure 2 The number of layers formed from the first semiconductor material and the second semiconductor material shown is merely a non-limiting example. Other numbers of layers are also possible and are fully intended to be included within the scope of this disclosure.

[0019] In some embodiments, the first semiconductor material 52 is an epitaxial material suitable for forming the channel region of a p-type FET, such as silicon germanium (Si). x Ge 1-x Where x can be in the range of 0 to 1), and the second semiconductor material 54 is an epitaxial material suitable for forming the channel region of an n-type FET, such as silicon. A multilayer stack 64 (which may also be referred to as an epitaxial material stack) will be patterned to form the channel region of the NSFET in subsequent processing. Specifically, the multilayer stack 64 will be patterned and etched to form horizontal nanostructures (e.g., nanosheets or nanowires), the resulting NSFET channel region comprising multiple horizontal nanostructures.

[0020] A multilayer stack 64 can be formed by an epitaxial growth process, which can be performed in a growth chamber. In some embodiments, during the epitaxial growth process, the growth chamber is cyclically exposed to a first set of precursors to selectively grow a first semiconductor material 52, and then exposed to a second set of precursors to selectively grow a second semiconductor material 54. The first set of precursors includes precursors for the first semiconductor material (e.g., silicon-germanium), and the second set of precursors includes precursors for the second semiconductor material (e.g., silicon). In some embodiments, the first set of precursors includes a silicon precursor (e.g., silane) and a germanium precursor (e.g., germanane), and the second set of precursors includes a silicon precursor but omits the germanium precursor. Thus, the epitaxial growth process can include continuously flowing silicon precursors into the growth chamber, and then cyclically: (1) flowing germanium precursors into the growth chamber while growing the first semiconductor material 52; and (2) preventing the flow of germanium precursors into the growth chamber while growing the second semiconductor material 54. The cyclic exposure can be repeated until a target number of layers are formed.

[0021] Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figures 5A-5C , Figures 6A-6C , Figures 7-10 , Figures 11A-11C , Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 14A and Figure 14B This is a cross-sectional view of an NSFET device 100 according to an embodiment during a later stage of manufacturing. Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figures 7-10 , Figure 11A , Figure 12A , Figure 13A and Figure 14A It is along Figure 1 Cross-sectional view of cross section BB in the diagram. Figure 3B , Figure 4B , Figure 5C , Figure 6C , Figure 11C , Figure 12B , Figure 13B and Figure 14B It is along Figure 1 The cross-sectional view of cross section AA in the diagram. Figure 5B , Figure 6B and Figure 11B It is along Figure 1The figure shows a cross-sectional view of the cross section DD. Although the two fins and two gate structures are shown in the figure as a non-limiting example, it should be understood that other numbers of fins and other numbers of gate structures may also be formed.

[0022] exist Figure 3A and Figure 3B In the substrate 50, fin structures 91 are formed to protrude above the substrate 50. Each fin structure 91 includes a semiconductor fin 90 (also referred to as a fin) and a layer stack 92 covering the semiconductor fin 90. The layer stack 92 and the semiconductor fin 90 can be formed by etching trenches in the multilayer stack 64 and the substrate 50, respectively. The layer stack 92 and the semiconductor fin 90 can be formed by the same etching process.

[0023] The fin structure 91 can be patterned using any suitable method. For example, the fin structure 91 can be patterned using one or more photolithography processes, including dual patterning or multiple patterning processes. Typically, dual patterning or multiple patterning processes combine photolithography and self-alignment processes, allowing the creation of patterns with, for example, smaller pitches than that achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern, for example, the fin structure 91.

[0024] In some embodiments, the remaining spacers are used to pattern a mask 94, which is then used to pattern a fin structure 91. The mask 94 can be a single-layer mask or a multi-layer mask, such as a multi-layer mask including a first mask layer 94A and a second mask layer 94B. The first mask layer 94A and the second mask layer 94B can each be formed from a dielectric material such as silicon oxide, silicon nitride, or combinations thereof, and can be deposited or thermally grown according to suitable techniques. The first mask layer 94A and the second mask layer 94B are different materials with high etch selectivity. For example, the first mask layer 94A can be silicon oxide, and the second mask layer 94B can be silicon nitride. The mask 94 can be formed by patterning the first mask layer 94A and the second mask layer 94B using any acceptable etch process. The mask 94 can then be used as an etch mask to etch the substrate 50 and the multilayer stack 64. The etching can be any acceptable etch process, such as reactive ion etching (RIE), neutral beam etching (NBE), or combinations thereof. In some embodiments, etching is an anisotropic etching process. Following the etching process, a patterned multilayer stack 64 forms a layer stack 92, and a patterned substrate 50 forms fins 90, such as... Figure 3A and Figure 3BAs shown. Therefore, in the illustrated embodiment, the layer stack 92 further includes alternating layers of a first semiconductor material 52 and a second semiconductor material 54, and the fin 90 is formed of the same material as the substrate 50 (e.g., silicon).

[0025] Next, in Figure 4A and Figure 4B In this embodiment, a shallow trench isolation (STI) region 96 is formed above the substrate 50 and on the opposite side of the fin structure 91. As an example of forming the STI region 96, an insulating material may be formed above the substrate 50. The insulating material may be an oxide (e.g., silicon oxide), a nitride, or a combination thereof, and may be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., depositing a CVD-based material in a remote plasma system and post-curing it to transform it into another material, such as an oxide), or a combination thereof. Other insulating materials formed by any acceptable process may be used. In the illustrated embodiment, the insulating material is silicon oxide formed by an FCVD process. An annealing process may be performed after the formation of the insulating material.

[0026] In some embodiments, the insulating material is formed such that excess insulating material covers the fin structure 91. In some embodiments, a liner is first formed along the surfaces of the substrate 50 and the fin structure 91, and a filler material, such as those discussed above, is formed over the liner. In some embodiments, the liner is omitted.

[0027] Next, a removal process is applied to the insulating material to remove excess insulating material above the fin structure 91. In some embodiments, planarization processes, such as chemical mechanical polishing (CMP), etch-back processes, combinations thereof, can be utilized. The planarization process exposes the layer stack 92 such that after the planarization process, the layer stack 92 is flush with the top surface of the insulating material. Next, the insulating material is recessed to form STI regions 96. The insulating material is recessed such that the layer stack 92 protrudes between adjacent STI regions 96. The top of the semiconductor fin 90 may also protrude between adjacent STI regions 96. Furthermore, the top surface of the STI region 96 may have a flat surface, a raised surface, a recessed surface (e.g., a depression), or a combination thereof, as shown. The top surface of the STI region 96 can be formed as flat, raised, and / or recessed by suitable etching. The STI region 96 can be recessed using acceptable etching processes, such as material-selective etching processes for the insulating material (e.g., etching the insulating material at a faster rate than the materials of the fin 90 and the layer stack 92). For example, chemical oxide removal can be used, which employs a suitable etchant such as dilute hydrofluoric acid (dHF).

[0028] Still referencing Figure 4A and Figure 4B A pseudo-dielectric layer 97 is formed above the layer stack 92 and above the STI region 96. The pseudo-dielectric layer 97 can be, for example, silicon oxide, silicon nitride, a combination thereof, etc., and can be deposited or thermally grown according to acceptable techniques. In one embodiment, a silicon layer is conformally formed above the layer stack 92 and above the upper surface of the STI region 96, and a thermal oxidation process is performed to transform the deposited silicon layer into an oxide layer as the pseudo-dielectric layer 97.

[0029] Next, in Figures 5A-5C In this configuration, a dummy gate 102 is formed above the fin structure 91. To form the dummy gate 102, a dummy gate layer can be formed above the dummy dielectric layer 97. The dummy gate layer can be deposited above the dummy dielectric layer 97 and then planarized, for example, by CMP. The dummy gate layer can be a conductive material and can be selected from the group including amorphous silicon, polysilicon, poly-SiGe, etc. The dummy gate layer can be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques known and used in the art. The dummy gate layer can be made of other materials that have high etch selectivity relative to the STI region 96.

[0030] A mask 104 is then formed over the dummy gate layer. The mask 104 may be formed of silicon nitride, silicon oxynitride, combinations thereof, etc., and may be patterned using acceptable photolithography and etching techniques. In the illustrated embodiment, the mask 104 includes a first mask layer 104A (e.g., a silicon oxide layer) and a second mask layer 104B (e.g., a silicon nitride layer). The pattern of the mask 104 is then transferred to the dummy gate layer using an acceptable etching technique to form a dummy gate 102, and then the pattern of the mask 104 is transferred to the dummy dielectric layer using an acceptable etching technique to form a dummy gate dielectric 97. The dummy gates 102 cover the corresponding channel regions of the stack 92. The pattern of the mask 104 can be used to physically separate each of the dummy gates 102 from adjacent dummy gates. The dummy gates 102 may also have a longitudinal direction substantially perpendicular to the longitudinal direction of the fin structure 91. In some embodiments, the dummy gates 102 and the dummy gate dielectric 97 are collectively referred to as the dummy gate structure.

[0031] Next, a gate spacer layer 108 is formed by conformally depositing an insulating material over the layer stack 92, the STI region 96, and the dummy gate 102. The insulating material may be silicon nitride, silicon carbonitride, a combination thereof, etc. In some embodiments, the gate spacer layer 108 includes multiple sublayers. For example, a first sublayer (sometimes referred to as a gate sealing spacer layer) may be formed by thermal oxidation or deposition, and a second sublayer (sometimes referred to as a main gate spacer layer) may be conformally deposited on the first sublayer.

[0032] Figure 5Band Figure 5C They are shown respectively Figure 5A NSFET device 100 in Figure 5A Cross-sectional views of sections EE and FF. Sections EE and FF correspond to... Figure 1 The cross sections DD and AA in the diagram.

[0033] Next, in Figures 6A-6C In this process, the gate spacer layer 108 is etched using an anisotropic etching process to form the gate spacer 108. The anisotropic etching process can remove the horizontal portion of the gate spacer layer 108 (e.g., the portion above the STI region 96 and the dummy gate 102), and the remaining vertical portion of the gate spacer layer 108 (e.g., the portion along the sidewalls of the dummy gate 102 and the dummy gate dielectric 97) forms the gate spacer 108.

[0034] Figure 6B and Figure 6C They are shown respectively Figure 6A Cross-sectional views of the NSFET device 100 along cross sections EE and FF. Figure 6B In this embodiment, portions of the gate spacer layer 108 are shown between adjacent fins on the upper surface of the STI region 96. Those portions of the gate spacer layer 108 may be left intact because the anisotropic etching process discussed above may reduce the efficiency of the anisotropic etching process due to the small distance between adjacent fins, and may not completely remove the gate spacer layer 108 disposed between adjacent fins. In other embodiments, portions of the gate spacer layer 108 disposed on the upper surface of the STI region 96 between adjacent fins are completely removed by the anisotropic etching process used to form the gate spacer 108.

[0035] Next, an opening 110 (which may also be referred to as a groove) is formed in the layer stack 92. The opening 110 may extend through the layer stack 92 and into the fin 90. The opening 110 may be formed by an anisotropic etching process using, for example, a dummy gate 102 and a gate spacer 108 as an etching mask.

[0036] After the opening 110 is formed, a selective etching process is performed to recess the end of the first semiconductor material 52 exposed by the opening 110 without substantially eroding the second semiconductor material 54. After the selective etching process, a groove (also called a sidewall groove) is formed at the location where the end removed from the first semiconductor material 52 was once located.

[0037] Next, an internal spacer layer is formed (e.g., conformally) in the opening 110. The internal spacer layer also fills the sidewall recesses of the first semiconductor material 52 formed by the previous selective etching process. The internal spacer layer can be a suitable dielectric material, such as silicon carbonitride (SiCN), silicon carbonitride oxycarbonyl (SiOCN), etc., formed by a suitable deposition method, such as PVD, CVD, atomic layer deposition (ALD), etc. Next, an etching process, such as anisotropic etching, is performed to remove the portion of the internal spacer layer disposed outside the sidewall recesses of the first semiconductor material 52. The remaining portion of the internal spacer layer (e.g., the portion disposed inside the sidewall recesses of the first semiconductor material 52) forms the internal spacer 55. Figure 6A As shown, opening 110 exposes the sidewalls of the second semiconductor material 54 and the upper surface 90U of the fin 90. Figure 6A In the example, the upper surface 90U of the fin 90 is located in the vertical direction between the upper and lower surfaces of the lowermost internal spacer 55A.

[0038] Next, in Figure 7 In this process, implantation process 130 is performed to transform the upper layer of fin 90 exposed by opening 110 into seed layer 111. In some embodiments, implantation process 130 is performed using a gas source comprising carbon, nitrogen, oxygen, or combinations thereof. Examples of gas sources may be, for example, O2, N2, or CO2. In some embodiments, the gas source is ignited into a plasma comprising ions of carbon, nitrogen, and / or oxygen, and the ions are implanted into the upper layer (e.g., silicon) of fin 90 via implantation process 130. Implantation process 130 may be performed at a temperature between about 200°C and about 500°C. Following the implantation process, an annealing process, such as rapid thermal annealing (RTA) or furnace annealing, may be performed at a temperature between about 400°C and 800°C. In some embodiments, the annealing process repairs lattice damage caused by the implantation process. In the illustrated embodiment, implantation process 130 and annealing process transform the upper layer of fin 90 into seed layer 111. As an example, seed layer 111 may comprise silicon oxide (e.g., SiO), silicon carbide (e.g., SiC), silicon nitride (e.g., SiN), or silicon carbonitride (e.g., SiCN). Seed layer 111 facilitates the subsequent selective deposition of dielectric layer 113 on seed layer 111 (see...). Figure 8 ).exist Figure 7 In the example, the upper surface 111U of the seed layer 111 is located between the upper and lower surfaces of the bottommost internal spacer 55A.

[0039] Next, in Figure 8In this process, a dielectric layer 113 is selectively formed on a seed layer 111. In some embodiments, a selective ALD process is performed to selectively deposit the dielectric layer 113 on the seed layer 111. The selective ALD process can be performed using precursors including silicon (e.g., silane) and one or more precursors including oxygen, nitrogen, and / or carbon. In some embodiments, the seed layer 111 and the dielectric layer 113 comprise the same material, such as SiO, SiC, SiN, or SiCN. Due to the seed layer 111, the deposition rate of the dielectric layer 113 on the seed layer 111 is higher than the deposition rate of the dielectric layer 113 on other surfaces (e.g., the surfaces of the internal spacer 55, the second semiconductor material 54, and the gate spacer 108) (e.g., five times or more).

[0040] like Figure 8 As shown, after the selective ALD process, the dielectric layer 113 is formed on the seed layer 111, and the surfaces of other structures (e.g., internal spacers 55, second semiconductor material 54, and gate spacers 108) are not covered by the dielectric layer 113. In other words, the seed layer 111 is covered by the dielectric layer 113, while other structures (e.g., internal spacers 55, second semiconductor material 54, and gate spacers 108) are exposed by the dielectric layer 113. Figure 8 In one example, the upper surface 113U of the dielectric layer 113 is located between the upper and lower surfaces of the lowermost internal spacer 55A. In other embodiments, the upper surface 113U is higher than the upper surface of the lowermost internal spacer 55A (e.g., farther from the substrate), but between the upper and lower surfaces of another internal spacer 55 (e.g., an internal spacer 55 farther from the substrate 50 than the lowermost internal spacer 55A).

[0041] The currently disclosed method allows for the selective deposition of a dielectric layer 113 on the seed layer 111, which may not be achievable by other ALD processes (e.g., ALD processes that do not utilize the currently disclosed method). In the illustrated embodiment, a dielectric layer 113 of uniform thickness is achieved on the surface of the seed layer 111, independent of the space dimensions between the dummy gates 102, thereby reducing or avoiding the space loading effects encountered by other ALD processes that do not utilize the currently disclosed method. As described below, the selective deposition and uniform thickness of the dielectric layer 113 facilitate the selective growth of source / drain materials in subsequent processes.

[0042] Next, in Figure 9 In this embodiment, a source / drain material 112 is selectively formed in an opening 110 on the exposed sidewall of the second semiconductor material 54. In the illustrated embodiment, the source / drain material 112 is formed of one or more epitaxial materials and may therefore also be referred to as an epitaxial source / drain material 112.

[0043] In some embodiments, the epitaxial source / drain material 112 is epitaxially grown in the opening 110. The epitaxial source / drain material 112 may include any acceptable material, such as materials suitable for n-type or p-type devices. For example, when forming an n-type device, the epitaxial source / drain material 112 may include a material that applies tensile strain to the channel region, such as silicon, SiC, SiCP, SiP, etc. Similarly, when forming a p-type device, the epitaxial source / drain material 112 may include a material that applies compressive strain to the channel region, such as SiGe, SiGeB, Ge, GeSn, etc.

[0044] like Figure 9 As shown, the epitaxial source / drain material 112 is selectively formed on the exposed sidewalls of the second semiconductor material 54. In some embodiments, the lattice constant of the epitaxial source / drain material 112 matches the lattice constant of the second semiconductor material 54, thus the epitaxial source / drain material 112 has a high deposition rate (also referred to as growth rate) on the second semiconductor material 54. On the other hand, the dielectric materials of, for example, the internal spacer 55, the gate spacer 108, and the dielectric layer 113 are unfavorable for the growth of the epitaxial source / drain material 112, so the deposition rate of the epitaxial source / drain material 112 on these dielectric surfaces is essentially zero.

[0045] In some embodiments, due to the selective growth of the epitaxial source / drain material 112 on the second semiconductor material 54, the epitaxial source / drain material 112 has a higher lateral growth rate than a vertical growth rate. The epitaxial source / drain material 112 grows and merges on the opposing sidewalls of the second semiconductor material 54 exposed by the opening 110 to form the source / drain region 112 (also referred to as the epitaxial source / drain region 112), such as... Figure 10 As shown.

[0046] like Figure 10 As shown, the source / drain region 112 extends continuously from the first dummy gate 102 (e.g., the left dummy gate 102) to the second adjacent dummy gate 102 (e.g., the right dummy gate 102). Notably, an air gap 115 is formed between each source / drain region 112 and the underlying dielectric layer 113. In the illustrated embodiment, the air gap 115 is formed due to the selective growth of the source / drain material 112 (e.g., the source / drain material 112 is not grown on the dielectric layer 113), also referred to as bottom-to-sidewall growth selectivity of the source / drain material 112. The air gap 115 advantageously reduces or eliminates leakage current (e.g., leakage current from the source / drain region 112 to the fin 90) and reduces the edge capacitance of the formed device. Figure 10In the example, the upper surface of the air gap 115, which is away from the substrate 50, is closer to the substrate 50 than the lower surface of the bottommost nanostructure 54, which faces the substrate 50. Note that although the upper surface of the air gap 115 (which is the lower surface of the source / drain region 112) is shown as a horizontal linear surface, the upper surface of the air gap 115 may have an irregular shape, such as including multiple intersecting liner segments, and / or having a curved surface.

[0047] The epitaxial source / drain region 112 can be implanted with a dopant, followed by an annealing process. A suitable type of dopant (e.g., p-type or n-type) can be implanted into the epitaxial source / drain region 112. The n-type impurity can be any suitable n-type impurity, such as phosphorus, arsenic, antimony, etc., and the p-type impurity can be any suitable p-type impurity, such as boron, BF2, indium, etc. The impurity concentration in the source / drain region can be approximately 10-1. 19 cm -3 Peace Treaty 10 21 cm -3 In some embodiments, the epitaxial source / drain region 112 may be doped in situ during growth. An annealing process may be performed after the implantation process to activate the dopant.

[0048] In some embodiments, epitaxial source / drain regions 112 are formed to apply stress to the respective channel regions of the formed NSFET device, thereby improving performance. The epitaxial source / drain regions 112 are formed such that each dummy gate 102 is disposed between corresponding adjacent epitaxial source / drain regions 112. In some embodiments, gate spacers 108 are used to space the epitaxial source / drain regions 112 and the dummy gates 102 by an appropriate lateral distance such that the epitaxial source / drain regions 112 do not short-circuit subsequently formed replacement gates of the resulting NSFET device.

[0049] Due to the epitaxial process used to form the epitaxial source / drain regions 112, the upper surface of the epitaxial source / drain regions 112 has small planes that extend laterally outward beyond the sidewalls of the fin structure 91. In some embodiments, after the epitaxial process is completed, adjacent epitaxial source / drain regions 112 remain separated (see, for example...). Figure 11B In other embodiments, these small planes cause adjacent epitaxial source / drain regions 112 of the same NSFET to merge.

[0050] Next, in Figure 11AIn this process, a contact etch stop layer (CESL) 116 is formed over the source / drain region 112 and over the dummy gate 102 (e.g., conformally), and a first interlayer dielectric (ILD) 114 is then deposited over the CESL 116. The CESL 116 is formed of a material having a different etch rate than the first ILD 114, and can be formed from silicon nitride using PECVD, although other dielectric materials such as silicon oxide, silicon oxynitride, combinations thereof, etc., and alternative techniques for forming the CESL 116, such as low-pressure CVD (LPCVD), PVD, etc., can be used instead.

[0051] The first ILD 114 can be formed from a dielectric material and can be deposited by any suitable method such as CVD, plasma-enhanced CVD (PECVD), or FCVD. The dielectric material used for the first ILD 114 can include silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable process can be used. Figure 11B and Figure 11C It shows Figure 11A A cross-sectional view of the NSFET device 100, but along... Figure 11A The sections EE and FF are shown. Note that in... Figure 11B In this configuration, an air gap 115 exists between each source / drain region 112 and the dielectric layer 113 on the underlying fin 90. In some embodiments, the air gap 115 is sealed by a CESL 116 to form a closed space.

[0052] Next, in Figure 12A and Figure 12B In the process, the dummy gate 102 and the dummy gate dielectric 97 are removed. To remove the dummy gate 102, a planarization process, such as CMP, is performed to make the top surfaces of the first ILD 114 and CESL 116 flush with the top surfaces of the dummy gate 102 and the gate spacer 108. The planarization process can also remove the mask 104 on the dummy gate 102 (see [link to documentation]). Figure 11A The dummy gate 102, the gate spacer 108, and the top surfaces of the first ILD 114 are flush after the planarization process. Therefore, the top surface of the dummy gate 102 is exposed by the first ILD 114.

[0053] Next, the dummy gate 102 is removed in one or more etching steps, forming a recess 103 between the gate spacers 108. The recess 103 exposes portions of the first semiconductor material 52 and the second semiconductor material 54 below the dummy gate 102. In some embodiments, the dummy gate 102 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using one or more reactive gases that selectively etch the dummy gate 102 without etching the first ILD 114 or the gate spacers 108. Each recess 103 exposes a channel region of the NSFET. Each channel region is disposed between adjacent epitaxial source / drain regions 112. During the removal of the dummy gate 102, the dummy gate dielectric 97 may be used as an etch stop layer as the dummy gate 102 is etched. The dummy gate dielectric 97 may then be removed after the removal of the dummy gate 102. In some embodiments, an etching process such as an isotropic etching process may be performed to remove the dummy gate dielectric 97. In one embodiment, an isotropic etching process using etching gases including HF and NH3 is performed to remove the dummy gate dielectric 97. Figure 11B It shows Figure 11A A cross-sectional view of the NSFET device 100 along the cross section FF.

[0054] Next, in Figure 13A and Figure 13B In the process, the first semiconductor material 52 is removed to release the second semiconductor material 54. After removing the first semiconductor material 52, the second semiconductor material 54 forms a plurality of horizontally extending (e.g., parallel to the main upper surface of the substrate 50) nanostructures 54. The nanostructures 54 may be collectively referred to as the channel region 93 or channel layer 93 of the formed NSFET device 100. Figure 13A As shown, gaps 53 (e.g., blank spaces) are formed between nanostructures 54 by removing the first semiconductor material 52. In some embodiments, the nanostructures 54 are nanosheets or nanowires, depending on, for example, the size (e.g., size and / or aspect ratio) of the nanostructures 54.

[0055] In some embodiments, the first semiconductor material 52 is removed by a selective etching process using an etchant that is selective to the first semiconductor material 52 (e.g., has a higher etching rate to the first semiconductor material 52), such that the first semiconductor material 52 is removed without substantially eroding the second semiconductor material 54. In some embodiments, an isotropic etching process is performed to remove the first semiconductor material 52. The isotropic etching process can be performed using an etching gas and optionally a carrier gas, wherein the etching gas includes F2 and HF, and the carrier gas can be an inert gas, such as Ar, He, N2, combinations thereof, etc.

[0056] Figure 13A A cross-sectional view of the NSFET device 100 along the longitudinal axis of the fin (e.g., along the direction of current flow in the fin) is shown, and Figure 13B The NSFET device 100 is shown along Figure 13A The cross-sectional view of the cross-section FF is a cross-section along the direction perpendicular to the longitudinal axis of the fin and passing through the middle portion of the nanostructure 54.

[0057] Next, in Figure 14A and Figure 14B In this configuration, a gate dielectric layer 120 and a gate electrode 122 are formed to replace the gate. The gate dielectric layer 120 is conformally deposited in a recess 103, for example, deposited on the top surface and sidewalls of the fin 90, and on the sidewalls of the gate spacer 108. The gate dielectric layer 120 may also be formed on the top surface of the first ILD 114. Notably, the gate dielectric layer 120 surrounds the nanostructure 54. According to some embodiments, the gate dielectric layer 120 comprises silicon oxide, silicon nitride, or a multilayer thereof. In some embodiments, the gate dielectric layer 120 comprises a high-k dielectric material, and in these embodiments, the gate dielectric layer 120 may have a k value greater than about 7.0, and may comprise metal oxides or silicates of Hf, Al, Zr, La, Mg, Ba, Ti, or Pb, or combinations thereof. Methods for forming the gate dielectric layer 120 may include molecular beam deposition (MBD), ALD, PECVD, etc.

[0058] Next, a gate electrode 122 is deposited above and around the gate dielectric layer 120, filling the remaining portion of the recess 103. The gate electrode 122 may comprise a metallic material, such as TiN, TiO, TaN, TaC, Co, Ru, Al, W, combinations thereof, or multiples thereof. For example, although a single-layer gate electrode 122 is shown, the gate electrode 122 may comprise any number of liner layers (e.g., barrier layers), any number of work function adjustment layers, and filler material. After filling the gate electrode 122, a planarization process such as CMP may be performed to remove excess portions of the gate dielectric layer 120 and excess material of the gate electrode 122 above the top surface of the first ILD 114. The material of the gate electrode 122 and the remaining portion of the gate dielectric layer 120 thus form the alternative gate of the resulting NSFET device 100. Each gate electrode 122 and the corresponding gate dielectric layer 120 may be collectively referred to as a gate stack, an alternative gate structure, or a metallic gate structure. Each gate stack extends around its respective nanostructure 54. Figure 14A The cross-sectional view of the NSFET device 100 along the cross section EE and Figure 11B They are the same or similar, so I will not go into details here.

[0059] As will be readily understood by those skilled in the art, additional processes can be performed to complete the fabrication of the NSFET device 100, and therefore details will not be repeated here. For example, a second ILD can be deposited over the first ILD 114. Furthermore, gate contacts and source / drain contacts can be formed via the second ILD and / or the first ILD 114 to be electrically coupled to the gate electrode 122 and the source / drain region 112, respectively.

[0060] Variations of the disclosed embodiments are possible and are fully intended to be included within the scope of this disclosure. For example, depending on the type of device formed (e.g., n-type or p-type device), the second semiconductor material 54 may be removed, and the first semiconductor material 52 may be retained to form a nanostructure that serves as the channel region of the formed NSFET device. In embodiments where the first semiconductor material 52 is retained to form a nanostructure, as will be readily understood by those skilled in the art, internal spacers are formed in sidewall recesses at the ends of the second semiconductor material 54 prior to removal of the second semiconductor material 54.

[0061] Figure 15 A flowchart of a method 1000 for manufacturing a semiconductor device according to some embodiments is shown. It should be understood that... Figure 15 The illustrated embodiments are merely examples of many possible embodiments. Those skilled in the art will recognize many variations, substitutions, and modifications. For example, additions, removals, substitutions, rearrangements, or repetitions may be made. Figure 15 The various steps shown.

[0062] refer to Figure 15 In block 1010, a fin structure is formed protruding above the substrate, wherein the fin structure includes a fin and a layer stack above the fin, the layer stack including alternating layers of a first semiconductor material and a second semiconductor material. In block 1020, a first dummy gate structure and a second dummy gate structure are formed above the fin structure. In block 1030, an opening is formed in the fin structure between the first dummy gate structure and the second dummy gate structure. In block 1040, the upper layer of the fin exposed at the bottom of the opening is converted into a seed layer by performing an implantation process. In block 1050, a dielectric layer is selectively deposited above the seed layer at the bottom of the opening. In block 1060, source / drain materials are selectively grown on the opposite sidewalls of the second semiconductor material exposed by the opening.

[0063] The embodiments offer advantages. The disclosed method achieves selective growth of the source / drain material 112 (e.g., bottom-to-sidewall growth selectivity) through features such as ion implementation and selective deposition of the dielectric layer 113, resulting in the formation of an air gap 115 between the source / drain region 112 and the underlying fin 90. The air gap 115 reduces the edge capacitance of the formed device and reduces or eliminates the leakage current of the formed device.

[0064] In one embodiment, a method of forming a semiconductor device includes: forming a fin structure protruding above a substrate, wherein the fin structure includes a fin and a layer stack above the fin, the layer stack including alternating layers of a first semiconductor material and a second semiconductor material; forming a first dummy gate structure and a second dummy gate structure above the fin structure; forming an opening in the fin structure between the first dummy gate structure and the second dummy gate structure; converting the upper layer of the fin exposed at the bottom of the opening into a seed layer by performing an implantation process; selectively depositing a dielectric layer above the seed layer at the bottom of the opening; and selectively growing source / drain material on opposite sidewalls of the second semiconductor material exposed by the opening. In one embodiment, the source / drain material grown on opposite sidewalls of the second semiconductor material merges to form a source / drain region, wherein an air gap exists between the source / drain region and the dielectric layer. In one embodiment, the method further includes: replacing the exposed end of the first semiconductor material with an internal spacer after forming the opening and before conversion. In one embodiment, after selectively depositing the dielectric layer, the upper surface of the dielectric layer remote from the substrate is located between the lower and upper surfaces of the lowermost internal spacer in the internal spacer. In one embodiment, the method further includes performing an annealing process after the implantation process and before selectively depositing a dielectric layer. In one embodiment, the fin comprises silicon, and the implantation process is performed using a gas source comprising carbon, nitrogen, oxygen, or a combination thereof. In one embodiment, the dielectric layer is formed of silicon oxide, silicon carbide, silicon nitride, or silicon carbonitride. In one embodiment, after selectively depositing the dielectric layer, a seed layer at the bottom of the opening is covered by the dielectric layer, while the opposite sidewalls of the second semiconductor material exposed by the opening are not covered by the dielectric layer. In one embodiment, a first lattice constant of the source / drain material is matched with a second lattice constant of the second semiconductor material. In one embodiment, the method further includes forming an interlayer dielectric (ILD) layer over the fin structure surrounding a first dummy gate structure and a second dummy gate structure; replacing the first dummy gate structure and the second dummy gate structure with a first alternative gate structure and the second alternative gate structure, respectively. In one embodiment, replacing the first dummy gate structure and the second dummy gate structure includes: removing the first dummy gate structure and the second dummy gate structure to form an opening in the ILD layer to expose a first semiconductor material and a second semiconductor material beneath the first dummy gate structure and the second dummy gate structure; selectively removing the exposed first semiconductor material using a first etching process, wherein after the first etching process, the exposed second semiconductor material is retained and forms a channel region of the semiconductor device; forming a gate dielectric material around the channel region; and forming a gate material around the gate dielectric material.

[0065] In one embodiment, a method of forming a semiconductor device includes: forming a fin structure over a substrate, the fin structure including a fin and a layer stack over the fin, the layer stack including alternating layers of a first semiconductor material and a second semiconductor material; forming a dummy gate structure over the fin structure; forming an opening in the fin structure adjacent to the dummy gate structure, wherein the sidewalls of the opening expose a first end of the first semiconductor material and a second end of the second semiconductor material, and wherein the bottom of the opening exposes an upper surface of the fin; replacing the first end of the first semiconductor material with an internal spacer; and forming a source / drain region in the opening, including: selectively depositing a dielectric layer over the upper surface of the fin; selectively growing source / drain material on the second end of the second semiconductor material using an epitaxial growth process, wherein, after the epitaxial growth process, the source / drain material is spaced apart from the dielectric layer. In one embodiment, the method further includes: performing an implantation process to convert the upper layer of the fin into a seed layer before selectively depositing the dielectric layer, wherein the seed layer includes the same material as the dielectric layer. In one embodiment, the method further includes: performing an annealing process after performing the implantation process. In one embodiment, the implantation process is performed using a gas source comprising carbon, nitrogen, oxygen, or a combination thereof, wherein the dielectric layer comprises silicon oxide, silicon carbide, silicon nitride, or silicon carbonitride. In one embodiment, source / drain materials grown on opposite sidewalls of a second semiconductor material are merged to form source / drain regions, wherein an air gap exists between the source / drain regions and the dielectric layer.

[0066] In one embodiment, a semiconductor device includes: a fin protruding above a substrate; a first gate structure located above the fin; a second gate structure located above the fin; a source / drain region located above the fin between the first gate structure and the second gate structure, wherein an air gap exists between the source / drain region and the fin; and a first channel layer below the first gate structure and a second channel layer below the second gate structure, wherein the source / drain region extends continuously from the first channel layer to the second channel layer. In one embodiment, the first channel layer and the second channel layer are nanosheets or nanowires. In one embodiment, the upper surface of the air gap, away from the substrate, is closer to the substrate than the lower surface of the lowest channel layer of the first channel layer facing the substrate. In one embodiment, the semiconductor device further includes: a dielectric layer located between the first gate structure and the second gate structure, wherein the dielectric layer is on the upper surface of the fin, and wherein the air gap is between the source / drain region and the dielectric layer.

[0067] Here are some examples.

[0068] Example 1. A method for forming a semiconductor device, the method comprising:

[0069] A fin structure protruding above a substrate is formed, wherein the fin structure includes a fin and a layer stack located above the fin, the layer stack including alternating layers of a first semiconductor material and a second semiconductor material;

[0070] A first pseudo-gate structure and a second pseudo-gate structure are formed above the fin structure;

[0071] An opening is formed between the first pseudo-gate structure and the second pseudo-gate structure in the fin structure;

[0072] The upper layer of the fin exposed at the bottom of the opening is transformed into a seed layer by performing an injection process;

[0073] A dielectric layer is selectively deposited above the seed layer at the bottom of the opening; and

[0074] Source / drain materials are selectively grown on the opposite sidewalls of the second semiconductor material exposed by the opening.

[0075] Example 2. The method according to Example 1, wherein the source / drain materials grown on opposite sidewalls of the second semiconductor material are combined to form a source / drain region, wherein an air gap exists between the source / drain region and the dielectric layer.

[0076] Example 3. The method according to Example 2 further includes: after forming the opening and before the transformation, replacing the end of the first semiconductor material exposed by the opening with an internal spacer.

[0077] Example 4. The method according to Example 3, wherein, after selectively depositing the dielectric layer, the upper surface of the dielectric layer away from the substrate is located between the lower and upper surfaces of the lowermost inner spacer in the inner spacers.

[0078] Example 5. The method according to Example 2 further includes: performing an annealing process after the implantation process and before selectively depositing the dielectric layer.

[0079] Example 6. The method according to Example 2, wherein the fin comprises silicon, and the implantation process is performed using a gas source comprising carbon, nitrogen, oxygen, or a combination thereof.

[0080] Example 7. The method according to Example 6, wherein the dielectric layer is formed of silicon oxide, silicon carbide, silicon nitride or silicon carbonitride.

[0081] Example 8. The method according to Example 2, wherein, after selectively depositing the dielectric layer, the seed layer at the bottom of the opening is covered by the dielectric layer, while the opposite sidewalls of the second semiconductor material exposed by the opening are not covered by the dielectric layer.

[0082] Example 9. The method according to Example 8, wherein the first lattice constant of the source / drain material matches the second lattice constant of the second semiconductor material.

[0083] Example 10. The method according to Example 2 further includes:

[0084] An interlayer dielectric (ILD) layer is formed above the fin structure surrounding the first dummy gate structure and the second dummy gate structure; and

[0085] The first pseudo-gate structure and the second pseudo-gate structure are replaced by a first alternative gate structure and a second alternative gate structure, respectively.

[0086] Example 11. The method according to Example 10, wherein replacing the first pseudo-gate structure and the second pseudo-gate structure comprises:

[0087] Remove the first dummy gate structure and the second dummy gate structure to form an opening in the ILD layer to expose the first semiconductor material and the second semiconductor material beneath the first dummy gate structure and the second dummy gate structure;

[0088] The first etching process is used to selectively remove the exposed first semiconductor material, wherein after the first etching process, the exposed second semiconductor material is retained and forms the channel region of the semiconductor device;

[0089] A gate dielectric material is formed around the channel region; and

[0090] A gate material is formed around the gate dielectric material.

[0091] Example 12. A method of forming a semiconductor device, the method comprising:

[0092] A fin structure is formed above a substrate, the fin structure including a fin and a layer stack located above the fin, the layer stack including alternating layers of a first semiconductor material and a second semiconductor material;

[0093] A pseudo-gate structure is formed above the fin structure;

[0094] An opening is formed in the fin structure adjacent to the dummy gate structure, wherein the sidewall of the opening exposes a first end of the first semiconductor material and a second end of the second semiconductor material, and wherein the bottom of the opening exposes the upper surface of the fin;

[0095] Replace the first end of the first semiconductor material with an internal spacer; and

[0096] A source / drain region is formed in the opening, including:

[0097] A dielectric layer is selectively deposited above the upper surface of the fin; and

[0098] Source / drain materials are selectively grown on the second end of the second semiconductor material using an epitaxial growth process, wherein the source / drain materials are spaced apart from the dielectric layer after the epitaxial growth process.

[0099] Example 13. The method according to Example 12 further includes: performing an implantation process to convert the upper layer of the fin into a seed layer before selectively depositing the dielectric layer, wherein the seed layer comprises the same material as the dielectric layer.

[0100] Example 14. The method according to Example 13 further includes: performing an annealing process after performing the injection process.

[0101] Example 15. The method according to Example 13, wherein the implantation process is performed using a gas source comprising carbon, nitrogen, oxygen, or a combination thereof, wherein the dielectric layer comprises silicon oxide, silicon carbide, silicon nitride, or silicon carbonitride.

[0102] Example 16. The method according to Example 12, wherein the source / drain materials grown on opposite sidewalls of the second semiconductor material are combined to form the source / drain region, wherein an air gap exists between the source / drain region and the dielectric layer.

[0103] Example 17. A semiconductor device comprising:

[0104] Fins protruding above the substrate;

[0105] The first gate structure located above the fin;

[0106] The second gate structure located above the fin;

[0107] A source / drain region located above the fin between the first gate structure and the second gate structure, wherein an air gap exists between the source / drain region and the fin; and

[0108] The first channel layer below the first gate structure and the second channel layer below the second gate structure, wherein the source / drain regions extend continuously from the first channel layer to the second channel layer.

[0109] Example 18. The semiconductor device according to Example 17, wherein the first channel layer and the second channel layer are nanosheets or nanowires.

[0110] Example 19. The semiconductor device according to Example 18, wherein the upper surface of the air gap, which is away from the substrate, is closer to the substrate than the lower surface of the lowermost channel layer of the first channel layer facing the substrate.

[0111] Example 20. The semiconductor device according to Example 17 further includes: a dielectric layer located between the first gate structure and the second gate structure, wherein the dielectric layer is on the upper surface of the fin, and wherein the air gap is between the source / drain region and the dielectric layer. The features of several embodiments have been summarized above to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

Claims

1. A method for forming a semiconductor device, the method comprising: A fin structure protruding above a substrate is formed, wherein the fin structure includes a fin and a layer stack located above the fin, the layer stack including alternating layers of a first semiconductor material and a second semiconductor material; A first pseudo-gate structure and a second pseudo-gate structure are formed above the fin structure; An opening is formed between the first pseudo-gate structure and the second pseudo-gate structure in the fin structure; The upper layer of the fin exposed at the bottom of the opening is transformed into a seed layer by performing an injection process; A dielectric layer is selectively deposited above the seed layer at the bottom of the opening; as well as Source / drain materials are selectively grown on the opposite sidewalls of the second semiconductor material exposed by the opening.

2. The method according to claim 1, wherein, The source / drain materials grown on opposite sidewalls of the second semiconductor material merge to form a source / drain region, wherein an air gap exists between the source / drain region and the dielectric layer.

3. The method according to claim 2, further comprising: After the opening is formed and before the transformation, the end of the first semiconductor material exposed by the opening is replaced with an internal spacer.

4. The method according to claim 3, wherein, After selectively depositing the dielectric layer, the upper surface of the dielectric layer, away from the substrate, is located between the lower and upper surfaces of the lowermost internal spacer in the internal spacers.

5. The method according to claim 2, further comprising: An annealing process is performed after the injection process and before the selective deposition of the dielectric layer.

6. The method according to claim 2, wherein, The fin comprises silicon, and the implantation process is performed using a gas source comprising carbon, nitrogen, oxygen, or a combination thereof.

7. The method according to claim 6, wherein, The dielectric layer is formed of silicon oxide, silicon carbide, silicon nitride, or silicon carbonitride.

8. The method according to claim 2, wherein, After selectively depositing the dielectric layer, the seed layer at the bottom of the opening is covered by the dielectric layer, while the opposite sidewalls of the second semiconductor material exposed by the opening are not covered by the dielectric layer.

9. The method according to claim 8, wherein, The first lattice constant of the source / drain material matches the second lattice constant of the second semiconductor material.

10. The method according to claim 2, further comprising: An interlayer dielectric (ILD) layer is formed above the fin structure, surrounding the first dummy gate structure and the second dummy gate structure; as well as The first pseudo-gate structure and the second pseudo-gate structure are replaced by a first alternative gate structure and a second alternative gate structure, respectively.

11. The method according to claim 10, wherein, The alternatives to the first pseudo-gate structure and the second pseudo-gate structure include: Remove the first dummy gate structure and the second dummy gate structure to form an opening in the interlayer dielectric (ILD) layer to expose the first semiconductor material and the second semiconductor material beneath the first dummy gate structure and the second dummy gate structure; The first etching process is used to selectively remove the exposed first semiconductor material, wherein after the first etching process, the exposed second semiconductor material is retained and forms the channel region of the semiconductor device; A gate dielectric material is formed around the channel region; and A gate material is formed around the gate dielectric material.

12. A method of forming a semiconductor device, the method comprising: A fin structure is formed above a substrate, the fin structure including a fin and a layer stack located above the fin, the layer stack including alternating layers of a first semiconductor material and a second semiconductor material; A pseudo-gate structure is formed above the fin structure; An opening is formed in the fin structure adjacent to the dummy gate structure, wherein the sidewall of the opening exposes a first end of the first semiconductor material and a second end of the second semiconductor material, and wherein the bottom of the opening exposes the upper surface of the fin; Replace the first end of the first semiconductor material with an internal spacer; as well as A source / drain region is formed in the opening, including: The upper layer of the fin exposed at the bottom of the opening is transformed into a seed layer by performing an injection process; A dielectric layer is selectively deposited over the seed layer; and Source / drain materials are selectively grown on the second end of the second semiconductor material using an epitaxial growth process, wherein the source / drain materials are spaced apart from the dielectric layer after the epitaxial growth process.

13. The method according to claim 12, wherein, The seed layer comprises the same material as the dielectric layer.

14. The method of claim 13, further comprising: After the injection process is performed, an annealing process is performed.

15. The method according to claim 13, wherein, The injection process is performed using a gas source containing carbon, nitrogen, oxygen, or a combination thereof, wherein the dielectric layer comprises silicon oxide, silicon carbide, silicon nitride, or silicon carbonitride.

16. The method according to claim 12, wherein, The source / drain materials grown on opposite sidewalls of the second semiconductor material merge to form the source / drain region, wherein an air gap exists between the source / drain region and the dielectric layer.

17. A semiconductor device, comprising: Fins protruding above the substrate; The first gate structure located above the fin; The second gate structure located above the fin; A source / drain region located above the fin between the first gate structure and the second gate structure, wherein an air gap exists between the source / drain region and the fin; The first channel layer beneath the first gate structure and the second channel layer beneath the second gate structure, wherein the source / drain regions extend continuously from the first channel layer to the second channel layer. A seed layer located between the first gate structure and the second gate structure, wherein the seed layer is formed by performing an implantation process on the upper layer of the fin located between the first gate structure and the second gate structure; as well as A dielectric layer located above the seed layer, wherein the air gap is between the source / drain region and the dielectric layer.

18. The semiconductor device according to claim 17, wherein, The first channel layer and the second channel layer are nanosheets or nanowires.

19. The semiconductor device according to claim 18, wherein, The upper surface of the air gap, which is away from the substrate, is closer to the substrate than the lower surface of the lowest channel layer in the first channel layer that faces the substrate.

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