Transistor, semiconductor storage device, and method for manufacturing transistor

Abstract

The embodiments relate to a transistor, a semiconductor memory device, and a method for manufacturing a transistor. The transistor of the embodiment includes: a semiconductor layer; a convex element region disposed on the semiconductor layer, having a specified width in a first direction along a surface of the semiconductor layer, and extending in a second direction along the surface of the semiconductor layer and intersecting the first direction; a gate electrode disposed above the element region; and a liner covering the gate electrode; element separation portions extending in the second direction on both sides of the element region in the first direction, and the liner continuously extending from the gate electrode to the element separation portions, and lying beneath the element separation portions.

Description

[0001] [Related Applications]

[0002] This application enjoys the benefit of priority to Japanese Patent Application No. 2021-99736, filed on June 15, 2021, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments of the present invention relate to a transistor, a semiconductor memory device, and a method for manufacturing a transistor. Background Technology

[0004] CMOS (Complementary Metal Oxide Semiconductor) transistors, for example, have a device region and a gate electrode disposed on the device region. During transistor manufacturing, considering that the gate electrode may shift relative to the device region, the width of the gate electrode is sometimes made larger than the width of the device region. This can sometimes become a major factor hindering transistor miniaturization. Summary of the Invention

[0005] The embodiments provide a transistor, a semiconductor memory device, and a method for manufacturing a transistor capable of suppressing positional offset of the gate electrode relative to a component region.

[0006] The transistor of the embodiment includes: a semiconductor layer; a convex element region disposed on the semiconductor layer, having a specified width in a first direction along a surface of the semiconductor layer, and extending in a second direction along a surface of the semiconductor layer and intersecting the first direction; a gate electrode disposed above the element region; and a liner covering the gate electrode; element separation portions extending in the second direction on both sides of the element region in the first direction, and the liner extending continuously from the gate electrode to the element separation portions, and lying beneath the element separation portions. Attached Figure Description

[0007] Figure 1 This is a block diagram of the semiconductor memory device according to Embodiment 1.

[0008] Figure 2 This is an equivalent circuit diagram illustrating an example of the configuration of the memory cell array, sense amplifier circuit, and latch circuit included in the semiconductor memory device of Embodiment 1.

[0009] Figure 3 This is a schematic diagram illustrating an example of the layout of the sense amplifier module and data register included in the semiconductor memory device of Embodiment 1.

[0010] Figure 4A and Figure 4B This is a schematic diagram illustrating an example of the layout of transistors in the semiconductor memory device of Embodiment 1.

[0011] Figures 5A to 5D This is a diagram showing an example of the configuration of a transistor applied to the semiconductor memory device of Embodiment 1.

[0012] Figure 6A and Figure 6B This is a diagram showing an example of the configuration of a template used to manufacture the transistor of Embodiment 1.

[0013] Figures 7A to 7D This is a diagram illustrating an example of the sequence of the template manufacturing method in Embodiment 1.

[0014] Figures 8Aa to 8Cb This is a diagram illustrating an example of the sequence of the transistor manufacturing method according to Embodiment 1.

[0015] Figures 9Aa to 9Cb This is a diagram illustrating an example of the sequence of the transistor manufacturing method according to Embodiment 1.

[0016] Figures 10Aa to 10Cb This is a diagram illustrating an example of the sequence of the transistor manufacturing method according to Embodiment 1.

[0017] Figures 11Aa to 11Cb This is a diagram illustrating an example of the sequence of the transistor manufacturing method according to Embodiment 1.

[0018] Figure 12A and Figure 12B This is a schematic diagram illustrating an example of the layout of transistors in the semiconductor memory device of Embodiment 1 and the comparative example.

[0019] Figures 13A-13C This is a diagram illustrating an example of the configuration of a transistor in a variation of Embodiment 1 of a semiconductor memory device.

[0020] Figures 14Aa to 14Cb This is a diagram illustrating an example of the sequence of the transistor manufacturing method of a variation of Embodiment 1, Example 1.

[0021] Figure 15A and Figure 15B This is a schematic diagram illustrating an example of the transistor layout in a semiconductor memory device of a variation 2 and a comparative example of Embodiment 1.

[0022] Figure 16 This is a circuit diagram illustrating an example of the configuration of the line decoder included in the semiconductor memory device of Embodiment 2.

[0023] Figure 17A and Figure 17BThis is a schematic diagram illustrating an example of the layout of transistors in the semiconductor memory device of Embodiment 2.

[0024] Figure 18 This is a block diagram of the semiconductor memory device according to Embodiment 3.

[0025] Figure 19 This is a circuit diagram illustrating an example of the circuit configuration of the sense amplifier circuit included in the semiconductor memory device of Embodiment 3.

[0026] Figure 20A and Figure 20B This is a schematic diagram illustrating an example of the layout of transistors in the semiconductor memory device of Embodiment 3 and the comparative example. Detailed Implementation

[0027] The present invention will now be described in detail with reference to the accompanying drawings. Furthermore, the present invention is not limited to the embodiments described below. Additionally, the constituent elements in the following embodiments include constituent elements that are readily conceived by the industry or substantially the same constituent elements.

[0028] [Implementation Method 1]

[0029] Hereinafter, with reference to the accompanying drawings, Embodiment 1 will be described in detail.

[0030] (Brief Structure of a Semiconductor Memory Device)

[0031] Figure 1 This is a block diagram of the semiconductor memory device 1 according to Embodiment 1. (As shown...) Figure 1 As shown, the semiconductor memory device 1 includes an input / output circuit 110, a logic control circuit 120, a status register 130, an address register 140, an instruction register 150, a sequencer 160, a ready / busy circuit 170, a voltage generation circuit 180, a memory cell array 10, a row decoder 20, a sense amplifier module 30, a data register 40, and a column decoder 50.

[0032] The input / output circuit 110 controls the input and output of signals DQ to external devices such as a memory controller (not shown) that control the semiconductor memory device 1. The input / output circuit 110 includes input circuitry and output circuitry (not shown).

[0033] The input circuit sends the write data WD and other data DAT received from the external device to the data register 40, the address ADD to the address register 140, and the instruction CMD to the instruction register 150.

[0034] The output circuit sends the status information STS received from the status register 130, the read data RD received from the data register 40, and the address ADD received from the address register 140 to an external device.

[0035] The logic control circuit 120 receives signals from external devices, such as chip enable signal CEn, instruction latch enable signal CLE, address latch enable signal ALE, write enable signal WEn, and read enable signal REn. Furthermore, the logic control circuit 120 controls the input / output circuit 110 and the sequencer 160 based on the received signals.

[0036] Status register 130, for example, stores status information STS for write, read, and erase operations that temporarily store data, and notifies external devices whether the operation has been completed normally.

[0037] Address register 140 temporarily stores the address ADD received from the external device via input / output circuit 110. Additionally, address register 140 transmits the row address RA to row decoder 20 and the column address CA to column decoder 50.

[0038] The instruction register 150 temporarily stores the instruction CMD received from the external device via the input / output circuit 110 and transmits it to the sequencer 160.

[0039] The sequencer 160 controls the operation of the entire semiconductor memory device 1. More specifically, the sequencer 160 controls, according to the instruction CMD stored in the instruction register 150, components such as the status register 130, the ready / busy circuit 170, the voltage generation circuit 180, the row decoder 20, the sense amplifier module 30, the data register 40, and the column decoder 50 to perform write operations, read operations, and erase operations.

[0040] The ready / busy circuit 170 sends the ready / busy signal R / Bn to an external device based on the operating status of the sequencer 160.

[0041] The voltage generation circuit 180 generates the voltages required for write, read, and erase operations under the control of the sequencer 160, and supplies the generated voltages to components such as the memory cell array 10, the line decoder 20, and the sense amplifier module 30. The line decoder 20 and the sense amplifier module 30 apply the voltages supplied from the voltage generation circuit 180 to the memory cells within the memory cell array 10.

[0042] The memory cell array 10 contains multiple blocks BLK (BLK0 to BLKn). n is an integer greater than or equal to 2. A block BLK is a collection of multiple memory cells associated with bit lines and word lines, serving as a data erasure unit, for example. The memory cells are configured, for example, as transistors, to store non-volatile data.

[0043] By incorporating such storage cells, the semiconductor storage device 1 is configured as, for example, a NAND (Not AND) type non-volatile memory. However, the semiconductor storage device 1 can also be configured as, for example, a NOR (Not OR) type or other non-volatile memory.

[0044] The row decoder 20 decodes the row address RA. Additionally, based on the decoding result, the row decoder 20 selects any block BLK. Furthermore, the row decoder 20 applies the required voltage to the block BLK.

[0045] During a read operation, the sensing amplifier module 30 senses the data read from the memory cell array 10. Additionally, the sensing amplifier module 30 sends the read data RD to the data register 40. During a write operation, the sensing amplifier module 30 sends the write data WD to the memory cell array 10.

[0046] Data register 40 has multiple latching circuits. The latching circuits store write data WD and read data RRD. For example, during a write operation, data register 40 temporarily stores the write data WD received from input / output circuit 110 and sends it to sense amplifier module 30. Similarly, for example, during a read operation, data register 40 temporarily stores the read data RD received from sense amplifier module 30 and sends it to input / output circuit 110.

[0047] The column decoder 50 decodes the column address CA during write, read, and erase operations, and selects the latch circuit in the data register 40 based on the decoding result.

[0048] Furthermore, the various components of the semiconductor memory device 1 other than the memory cell array 10 are also referred to as peripheral circuits. That is, the peripheral circuits include input / output circuits 110, logic control circuits 120, status registers 130, address registers 140, instruction registers 150, sequencers 160, ready / busy circuits 170, voltage generation circuits 180, row decoders 20, sense amplifier modules 30, data registers 40, and column decoders 50.

[0049] In this way, the semiconductor memory device 1 of Embodiment 1 includes a memory cell array 10 comprising a plurality of memory cells and peripheral circuitry for operating the plurality of memory cells.

[0050] (Circuit configuration of a memory cell array)

[0051] Figure 2This is an equivalent circuit diagram illustrating an example of the configuration of the memory cell array 10, the sense amplifier circuit SA, and the latch circuits DL and XDL included in the semiconductor memory device 1 according to Embodiment 1. First, an example of the circuit configuration of the memory cell array 10 included in the semiconductor memory device 1 will be described below.

[0052] As described above, the memory cell array 10 has multiple blocks BLK. Each block BLK has multiple string components SU. Each string component SU has multiple memory strings MS. One end of each memory string MS is connected to peripheral circuits such as the row decoder 20 and the sense amplifier module 30 via bit lines BL. The other end of each memory string MS is connected to peripheral circuits via a common source line SL.

[0053] The memory string (MS) has a drain selection transistor (STD) connected in series between the bit line (BL) and the source line (SL), multiple memory cells (MC), and a source selection transistor (STS). Hereinafter, the drain selection transistor (STD) and the source selection transistor (STS) are sometimes simply referred to as selection transistors (STD, STS).

[0054] A memory cell MC is, for example, a field-effect transistor (FET) with a charge storage layer contained in its gate insulating layer. The threshold voltage of the memory cell MC varies depending on the amount of charge in the charge storage layer. By setting one or more threshold voltages, the memory cell MC can store one or more bits of data. The gate electrodes of multiple memory cells MC corresponding to a memory string MS are connected to word lines WL. These word lines WL are all connected to all memory strings MS in a block BLK.

[0055] The selection transistors (STD, STS) are, for example, field-effect transistors. The gate electrodes of the selection transistors (STD, STS) are connected to selection gate lines (SGD, SGS). The drain select line SGD, connected to the drain select transistor STD, is configured corresponding to the string assembly SU and is commonly connected to all memory strings MS in one string assembly SU. The source select line SGS, connected to the source select transistor STS, is commonly connected to all memory strings MS in one block BLK.

[0056] (Composition of the sensing amplifier module)

[0057] Next, using Figure 2 and Figure 3 Here is an example of the configuration of the sensing amplifier module 30.

[0058] The sensing amplifier module 30 includes multiple sensing amplifier circuits SA for each bit line BL. Each sensing amplifier circuit SA, for example, senses the data that has been read to the corresponding bit line BL during a readout operation and determines whether the read data is "0" or "1".

[0059] Furthermore, the data register 40 includes multiple latch circuits DL and XDL corresponding to the multiple sense amplifier circuits SA. Additionally, latch circuit XDL is also provided for each bit line BL. On the other hand, multiple latch circuits DL are provided for each corresponding sense amplifier circuit SA. In this case, the number of latch circuits DL is designed, for example, based on the number of bits of data that one memory cell MC can store. The latch circuits DL and XDL temporarily store data related to the corresponding bit line BL.

[0060] First, then use Figure 2 An example of the circuit configuration of the sensing amplifier module 30 will be described. Figure 2 The diagram shows a sense amplifier circuit SA within the sense amplifier module 30 and latch circuits DL and XDL within the data register 40. Furthermore, multiple control signals supplied to the sense amplifier circuit SA, etc., are controlled by a sequencer 160.

[0061] like Figure 2 As shown, the sensing amplifier circuit SA includes transistor TR. 31 ~TR 38 And capacitor CAP. In the diagram, transistor TR... 31 It is a low-voltage P-channel MOS (Metal-Oxide-Semiconductor) transistor. Additionally, the transistor TR... 32 ~TR 38 It is a low-voltage N-channel MOS transistor. Hereinafter, the transistor TR included in the sense amplifier circuit SA will sometimes be referred to as... 31 ~TR 38 It is abbreviated as transistor TR.

[0062] transistor TR 31 One end of the transistor TR is connected to the power supply line that supplies the power supply voltage Vdd. 31 The gate electrode of transistor TR is connected to node INV. 32 One end is connected to transistor TR 31 At the other end, transistor TR 32 The other end is connected to node COM, for transistor TR 32 The gate electrode input control signal BLX is used to control the transistor TR. 33 One end is connected to node COM, transistor TR 33The other end is connected to the corresponding bit line BL, for transistor TR 33 The gate electrode input control signal BLC.

[0063] transistor TR 34 One end is connected to node COM, transistor TR 34 The other end is connected to node SRC, transistor TR 34 The gate electrode is connected to node INV.

[0064] transistor TR 35 One end is connected to transistor TR 31 At the other end, transistor TR 35 The other end is connected to node SEN, for transistor TR 35 The gate electrode input control signal HLL is used for transistor TR. 36 One end is connected to node SEN, transistor TR 36 The other end is connected to node COM, for transistor TR 36 The gate electrode input control signal XXL.

[0065] For transistor TR 37 One end receives the clock CLK, and the transistor TR... 37 The gate electrode of transistor TR is connected to node SEN. 38 One end is connected to transistor TR 37 At the other end, transistor TR 38 The other end is connected to the LBUS bus, for transistor TR 38 The gate electrode input control signal STB is used. One end of capacitor CAP is connected to node SEN, and the other end of capacitor CAP is used to input the clock signal CLK.

[0066] The latch circuit DL includes inverters IVa and IVb and transistor TR. 41 TR 42 In the diagram, transistor TR 41 TR 42 It is a low-voltage N-channel MOS transistor. Hereinafter, the transistor TR included in data register 40 will sometimes be referred to as... 41 TR 42 It is abbreviated as transistor TR.

[0067] also, Figure 2 One latch circuit DL is shown, but the data register 40 can also have multiple latch circuits DL relative to a single sense amplifier circuit SA, as described. Other latch circuits DL, not shown, have similar characteristics to... Figure 2 The latching circuit DL has the same configuration.

[0068] The input terminal of inverter IVa is connected to node LAT, and the output terminal is connected to node INV. The input terminal of inverter IVb is connected to node INV, and the output terminal is connected to node LAT.

[0069] transistor TR 41 One end of the transistor is connected to node INV, and the other end is connected to the bus LBUS, providing a control signal STI to the gate electrode. Transistor TR 42 One end is connected to node LAT, and the other end is connected to bus LBUS, which inputs control signal STL to the gate electrode.

[0070] The latch circuit XDL has a configuration substantially the same as that of the latch circuit DL, and is connected to the LBUS bus in a manner that allows it to transmit and receive data with the sense amplifier circuit SA and the latch circuit DL. Furthermore, the latch circuit XDL is connected to the input / output circuit 110 and is used for inputting and outputting data between the sense amplifier circuit SA and the input / output circuit 110.

[0071] In addition, the latch circuit XDL is also used for high-speed buffering of the semiconductor memory device 1. That is, even if all the latch circuits DL corresponding to the sense amplifier circuit SA are in use, the semiconductor memory device 1 can still receive data from the outside as long as the latch circuit XDL is idle.

[0072] In this case, the sense amplifier circuit SA and latch circuits DL and XDL, which belong to the peripheral circuit, have multiple transistors TR.

[0073] Next, the operation of the constructed sensing amplifier circuit SA will be briefly explained.

[0074] As an example of writing data to the memory cell MC, when charge is injected into the memory cell MC to raise the threshold, an "H" level ("1" data) is stored in node INV of the latch circuit DL. This causes the transistor TR to... 34 Connect and set bit line BL to 0 V.

[0075] As another example of writing data to the memory cell MC, when no charge is injected into the memory cell MC and the threshold is not changed, an "L" level ("0" data) is stored in node INV of the latch circuit DL. This causes the transistor TR to... 31 When connected, a specified positive voltage is applied to the bit line BL.

[0076] During readout, node INV is set to "L" level, causing transistor TR to... 31 Connected. Additionally, via transistor TR... 41 TR 42 Through transistor TR 31Precharge the bit line BL. Additionally, enable transistor TR. 35 It is also connected, charging the node SEN to the specified potential.

[0077] Then, make transistor TR 35 Disconnect, set signal XXL to "H" level, and enable transistor TR 36 Turn on. Therefore, if the corresponding memory cell MC is turned on, the potential of node SEN decreases, and transistor TR... 37 Disconnect. On the other hand, if the corresponding memory cell MC is disconnected, then the potential of node SEN remains at the "H" level, and transistor TR... 37 Connected.

[0078] Additionally, the transistor TR is activated via the signal STB. 38 When connected, it will interact with transistor TR 37 The potential corresponding to the on / off state is read out to the bus LBUS and stored in the latch circuit DL.

[0079] also, Figure 2 The circuit configuration, interconnection, and data transmission methods of the shown sense amplifier circuit SA and latch circuits DL and XDL are examples. Besides the described configuration, the sense amplifier circuit SA and latch circuits DL and XDL can also employ various other configurations, connection methods, or data transmission methods. In such cases, the number and type of transistors TR included in the sense amplifier circuit SA and latch circuits DL and XDL can also vary. For example, the sense amplifier circuit SA and latch circuits DL and XDL can also be configured to include high-voltage P-channel MOS transistors or high-voltage N-channel MOS transistors.

[0080] Figure 3 This is a schematic diagram illustrating an example of the layout of the sense amplifier module 30 and data register 40 included in the semiconductor memory device 1 of Embodiment 1. Figure 3 In this example, the configuration employed is such that the sensing amplifier circuit SA and the latch circuits DL and XDL have the aforementioned... Figure 2 The connection method and data transmission method.

[0081] Here, the direction along the multiple bit lines BL that are connected to the multiple memory cells MC is defined as the Y direction and is used as the second direction. Additionally, the direction intersecting the X direction, i.e., the direction along the multiple word lines WL that are connected to the multiple memory cells MC, is defined as the X direction and is used as the first direction.

[0082] like Figure 3As shown, in the physical configuration of the semiconductor memory device 1, multiple latch circuits DL of the data register 40 are combined with one sense amplifier circuit SA of the sense amplifier module 30 via the bus LBUS to form multiple groups SA / DL (SA / DL<0> to SA / DL<15>).

[0083] These groups of SA / DL are clustered together in units of a specified number of bit lines BL. Figure 3 In the example, the 16 groups SA / DL<0> to SA / DL<15> converge and are arranged in a column along the Y direction of the 16 bit lines BL.

[0084] In addition, the latch circuits XDL (XDL<0> to XDL<15>) of the data register 40 are also set in groups of 16, corresponding to the groups SA / DL<0> to SA / DL<15> of the sense amplifier circuit SA and the latch circuit DL arranged in a row, and are arranged in a row along the Y direction of the 16 bit lines BL.

[0085] The sensing amplifier circuit SA and the latch circuit DL, group SA / DL, are connected to the corresponding latch circuit XDL via the LBUS bus in a manner that enables them to send and receive data. Figure 3 In the example, the 16 groups SA / DL<0> to SA / DL<15> arranged in a row share a single bus LBUS.

[0086] (The structure of a transistor)

[0087] Next, using Figures 4A to 5D The physical configuration of the transistor TR contained in the sense amplifier circuit SA and the latch circuits DL and XDL will be explained.

[0088] Figure 4A and Figure 4B This is a schematic diagram showing an example of the layout of the transistor TRs included in the semiconductor memory device 1 of Embodiment 1. Figure 4A This is a simplified top view of multiple transistor TRs. Figure 4B It is a simplified cross-sectional view of multiple transistors TR along the Y direction.

[0089] like Figure 4A As shown, the transistors TR contained in the sense amplifier circuit SA and latch circuits DL and XDL arranged in a row are arranged in a row, for example, within a spacing of 16 bit lines BL. Each transistor TR has a component region AA and a gate electrode GC disposed above the component region AA.

[0090] The element region AA has a channel at a position overlapping the gate electrode GC in the vertical direction, and source / drain regions on both sides of the channel in the Y direction. However, the transistors TR arranged in a row share the source / drain regions with the transistors TR adjacent to each other in the Y direction along the bit line BL.

[0091] Figure 4A The diagram shows an example of four transistors (TRs) arranged in a row along the Y direction, sharing a common source / drain region. However, the number of transistors (TRs) sharing a common source / drain region is arbitrary and not limited to four.

[0092] In addition, a component separation section STI is provided between the component regions AA of the transistor TR adjacent in the X direction.

[0093] Furthermore, in order to increase the gate width W of the transistor TR and suppress threshold variation caused by the narrow channel effect (NCE) or the anti-narrow channel effect, it is preferable to increase the width of the element region AA in the Y direction as much as possible and minimize the width of the element separation portion STI as much as possible.

[0094] Under the narrow-channel effect, narrowing the transistor's gate width leads to an increase in the threshold voltage. Therefore, the turn-on current becomes less affected than the effect of gate width reduction. On the other hand, under the inverse narrow-channel effect, narrowing the transistor's gate width leads to an increase in leakage current flowing through the lower part of the channel, even when the transistor is turned off at a specified voltage. This is due to the transistor's gate length (…). Figure 4A The short-channel effect caused by the narrowing of the "L" in the transistor also leads to this threshold variation. Furthermore, generally, the threshold deviation between transistors depends on 1 / √LW (where L represents the gate length and W represents the gate width). Since there are many sense amplifiers and data latches that require configuration for each bit line, it is desirable to minimize this threshold deviation from the perspective of readout stability. The gate electrode GC of transistor TR is connected to a gate contact CG, which is connected to upper-layer wiring (not shown). The element region AA is connected to a source / drain contact CS, which is also connected to upper-layer wiring (not shown). Transistors TR arranged in a row in the Y direction share a common source / drain region, and similarly share a common source / drain contact CS with transistors TR adjacent in the Y direction.

[0095] Furthermore, among the multiple transistors TR, there are transistors TR whose gate electrodes GC are input with the same control signal. In this case, the gate electrodes GC of these transistors TR are electrically connected, for example, through upper layer wiring (not shown). In this way, even though the gate electrodes GC contained in the multiple transistors TR of the sense amplifier circuit SA and the latch circuits DL and XDL are input with the same control signal, they are physically separated at the level of the layer constituting the gate electrode GC (hereinafter, gate electrode layer GCr).

[0096] exist Figure 4B The diagram illustrates a situation where multiple transistors TR share a common source / drain region and source / drain junction CS in the Y direction, but their gate electrodes GC are separate. For example... Figure 4B As shown, the transistors TR arranged in a row along the Y direction, except for the transistors TR at the Y-direction ends, share a common source / drain region and a source / drain junction CS among the multiple transistors TR. Additionally, a component separation section STI is disposed on the Y-direction side of the transistors TR at the Y-direction ends.

[0097] Figures 5A to 5D This is a diagram showing an example of the configuration of the transistor TR applied to the semiconductor memory device 1 in Embodiment 1. Figure 5A This is a schematic top view showing the gate electrode GC and the element region AA of transistor TR. Figure 5B It is in the Y direction, that is Figure 5A A cross-sectional view of transistor TR on line A-A'. Figure 5C It is the X direction, that is Figure 5A A cross-sectional view of transistor TR on the B-B' line. Figure 5D It is a cross-sectional view of multiple transistors TR along the Y direction. Figures 5A to 5D In this paper, the gate contact CG and the source / drain contact CS are omitted.

[0098] also, Figures 5A-5C In the example shown, a single transistor TR, which can be applied to a semiconductor memory device 1, is illustrated. However, when multiple transistor TRs are arranged in a row as described above, sharing source / drain regions with each other, such as... Figure 5D As shown, in a cross-section along the Y direction, no element separation section (STI) is provided on either side of the transistor TR except at both ends of the arrangement. Furthermore, the element separation section (STI) is provided only on one side of the transistor TR, relative to both ends of the arrangement.

[0099] like Figures 5A-5C As shown, the transistor TR of Embodiment 1 includes a substrate WF, a device region AA, a gate electrode GC, sidewalls SWg, SWA, SWga, and a liner LR.

[0100] The substrate WF is, for example, a semiconductor substrate such as a silicon substrate. A well AAr is formed in the substrate WF, extending from the surface of the substrate WF to a specified depth. The well AAr is, for example, a layer containing impurities such as arsenic, phosphorus, or boron. The impurities are appropriately selected depending on whether the transistor TR is an N-channel or P-channel transistor.

[0101] The element region AA has a specified width in the X direction and is configured to be convex, extending along the Y direction. That is, the element region AA has a configuration in which the surface of the substrate WF, on which the well AAr is formed, is processed into a convex shape.

[0102] On both sides of the element region AA in the X direction and on both sides in the Y direction, a pair of element separation sections STI are disposed within the recesses RCw that are recessed from the surface of the substrate WF. That is, the element separation sections STI are disposed around a single transistor TR in a manner that surrounds the transistor TR.

[0103] The component separation section STI includes an interlayer insulating layer (ILD) such as a silicon oxide layer filled within the recess RCw. Thus, the component separation section STI electrically separates each transistor TR in the X and Y directions.

[0104] On the element region AA, at a position overlapping the gate electrode GC when viewed from above, a gate insulating layer Gox is disposed. The gate insulating layer Gox is, for example, a silicon oxide layer or a high-k layer containing hafnium oxide or zirconium oxide.

[0105] The gate electrode GC is disposed above the gate insulating layer Gox, which is located above the device region AA. More specifically, a polysilicon gate electrode GCp is disposed on the gate insulating layer Gox, and a metal gate electrode GCm is disposed on the polysilicon gate electrode GCp. The polysilicon gate electrode GCp is a conductive polysilicon layer doped with P-type or N-type impurities. The metal gate electrode GCm is a metal layer containing tungsten, tungsten silicide, or nickel silicide, etc.

[0106] In this way, the gate electrode GC is configured as, for example, a multi-metal gate electrode formed by combining a polysilicon gate electrode GCp with a metal gate electrode GCm.

[0107] A capping layer CP is disposed on the gate electrode GC. The capping layer CP is, for example, a silicon nitride layer or a silicon oxide layer.

[0108] In addition, such as Figure 5BAs shown, in the Y direction, the gate insulating layer Gox, the polysilicon gate electrode GCp, the metal gate electrode GCm, and the capping layer CP have substantially equal widths, and their center positions in the Y direction are substantially the same. That is, the gate insulating layer Gox and the capping layer CP have widths substantially equal to the gate length L of the gate electrode GC.

[0109] Furthermore, in the Y direction, the two sides of the gate insulating layer Gox, the polysilicon gate electrode GCp, the metal gate electrode GCm, and the capping layer CP are substantially located on the same plane. That is to say, the Y-direction end positions of the gate insulating layer Gox, the polysilicon gate electrode GCp, the metal gate electrode GCm, and the capping layer CP substantially overlap when viewed from their stacking direction.

[0110] Here, the fact that their widths are substantially equal and their center and end positions in the Y direction are substantially consistent means that within the range of the processing errors of the gate insulating layer Gox, the polysilicon gate electrode GCp, the metal gate electrode GCm, and the capping layer CP, their widths are equal and their center and end positions in the Y direction are consistent.

[0111] In addition, such as Figure 5C As shown, in the X direction, the protruding upper surface of the element region AA, the gate insulating layer Gox, the polysilicon gate electrode GCp, the metal gate electrode GCm, and the capping layer CP have substantially equal widths, and their center positions in the X direction are substantially the same. That is, the upper surface of the element region AA, the gate insulating layer Gox, and the capping layer CP have a width substantially equal to the gate width W of the gate electrode GC.

[0112] Furthermore, in the X direction, the two sides of the device region AA, the gate insulating layer Gox, the polysilicon gate electrode GCp, the metal gate electrode GCm, and the capping layer CP are substantially located on the same plane. That is, the end positions of the device region AA, the gate insulating layer Gox, the polysilicon gate electrode GCp, the metal gate electrode GCm, and the capping layer CP in the X direction substantially overlap when viewed from their stacking direction.

[0113] Here, their widths are substantially equal, and their center and end positions in the X direction are substantially consistent. This means that within the processing error range of the upper surface of the element region AA, the gate insulating layer Gox, the polysilicon gate electrode GCp, the metal gate electrode GCm, and the capping layer CP, their widths are equal, and their center and end positions in the X direction are consistent.

[0114] Sidewall SWg, serving as the first sidewall, covers the opposing sides of the gate insulating layer Gox, the polysilicon gate electrode GCp, the metal gate electrode GCm, and the capping layer CP in the Y direction. Sidewall SWa, serving as the second sidewall, covers the opposing sides of the element region AA in the Y direction.

[0115] On the other hand, in the X direction, the sidewall SWg that covers the side of the gate insulating layer Gox, the polysilicon gate electrode GCp, the metal gate electrode GCm and the top cap layer CP, and the sidewall SWa that covers the side of the element region AA, which are integrated to form the first and second sidewalls, cover each side of the element region AA, the gate insulating layer Gox, the polysilicon gate electrode GCp, the metal gate electrode GCm and the top cap layer CP.

[0116] These sidewalls, SWg, SWA, and SWga, are, for example, silicon oxide layers.

[0117] The substrate LR has, for example, a multilayer structure obtained by sequentially stacking a silicon oxide layer OL and a silicon nitride layer NL, covering the top cap layer CP, the gate electrode GC, the gate insulating layer Gox, and the device region AA protruding from the substrate WF.

[0118] More specifically, the liner LR extends from the upper surface of the capping layer SP to the sides of the capping layer SP, the gate electrode GC, and the gate insulating layer Gox. Additionally, the liner LR has a median sidewall SWg or sidewall SWga covering the sides of the capping layer SP, the gate electrode GC, and the gate insulating layer Gox.

[0119] Furthermore, the liner LR extends continuously from the gate electrode GC to the device separation section STI. At the device separation section STI, the liner LR lies beneath it. That is, the liner LR lies beneath the interlayer insulating layer ILD filled within the recess RCw of the substrate WF, continuously covering the bottom surface of the recess RCw from the side of the gate electrode GC.

[0120] Including the gate electrode GC, the transistor TR is covered by an interlayer insulating layer (ILD). As described above, the ILD also fills the recesses RCw on both sides of the element region AA in the X and Y directions, forming the element separation layer (STI). In other words, the ILD covering the transistor TR and the element separation layer (STI) electrically separating each transistor TR are integrally formed. The substrate LR lies between the element separation layer (STI) composed of the ILD and the recesses RCw of the substrate WF. The ILD is, for example, an undoped silicon oxide (NSG) layer.

[0121] As described above, the transistor TR in Embodiment 1 is configured as, for example, an N-channel or P-channel MOS transistor, and the sense amplifier module 30 is configured to include, for example, a complementary MOS (CMOS) transistor.

[0122] (Transistor manufacturing method)

[0123] Next, using Figures 6A to 11Cb The manufacturing method of the transistor TR according to Embodiment 1 will be described. The transistor TR is manufactured using an imprinting technique that transfers a pattern onto a resist layer or the like by forming a patterned template. First, the template used to manufacture the transistor TR will be described below.

[0124] Figure 6A and Figure 6B This is a diagram illustrating an example of the configuration of the template TM used to manufacture the transistor TR in Embodiment 1. Figure 6A This is a perspective view of template TM. Figure 6B This is a top view taken from the SBt side of the transfer surface of the template TM.

[0125] like Figure 6A and Figure 6B As shown, the template TM has a transparent substrate SB and a pattern PT. The transparent substrate SB is, for example, a quartz substrate that allows ultraviolet light to pass through, and has a transfer surface SBt on which the pattern PT is provided. The shape of the transistor TR is formed by transferring the pattern PT onto the substrate WF. Therefore, the pattern PT has a device region pattern PTaa that is transferred onto the substrate WF to become the device region AA, and a gate electrode pattern PTgc that becomes the gate electrode GC.

[0126] The element region pattern PTaa is a groove-shaped pattern with an opening on the transfer surface SBt of the transparent substrate SB, extending from the transfer surface SBt to a specified depth on the transparent substrate SB. In other words, the element region pattern PTaa has a concave shape obtained by reversing the shape of the convex element region AA. Therefore, in Figure 6B In the middle, the element area pattern PTaa is recessed towards the inside of the paper.

[0127] The gate electrode pattern PTgc is positioned overlapping the element region pattern PTaa, extending further to a specified depth from the depth reached by the element region pattern PTaa. That is, the gate electrode pattern PTgc has a concave shape resulting from reversing the shape of the gate electrode GC protruding from the element region AA. Therefore, in Figure 6B In the middle, the gate electrode pattern PTgc is further recessed towards the inside of the paper from the element region pattern PTaa which is recessed towards the inside of the paper.

[0128] In the short side direction of the element region pattern PTaa extending along the specified direction, the width of the element region pattern PTaa is substantially equal to the width of the gate electrode pattern PTgc. Here, "substantially equal in width" means that their widths are equal within the range of the processing errors of the element region pattern PTaa and the gate electrode pattern PTgc.

[0129] In addition, Figure 6A and Figure 6B In the example shown, only one gate electrode pattern PTgc and one element region pattern PTaa are illustrated. However, in the imprinting process, the wafer-state substrate WF is divided into designated areas called shot regions, and a template TM is pressed against each shot region to transfer the pattern PT. Therefore, one template TM has the same number of patterns PT as the number of element regions AA and gate electrodes GC formed within the shot regions.

[0130] Figures 7A to 7D This is a diagram illustrating an example of the sequence of the manufacturing method of the template TM in Embodiment 1. Figures 7A to 7D This is a perspective view showing the transfer surface SBt facing the substrate SB above.

[0131] like Figure 7A As shown, a mask layer MS, such as a cobalt layer, is formed on the transfer surface SBt of the substrate SB. Furthermore, by means of patterning, for example using an electron beam, an opening OPgc is formed at the formation location of the gate electrode pattern PTgc in the mask layer MS.

[0132] like Figure 7B As shown, the transfer surface SBt of the substrate SB exposed from the mask layer MS is processed to form a gate electrode pattern PTgc with an opening on the transfer surface SBt.

[0133] like Figure 7C As shown, by drawing, for example, using an electron beam, an opening OPaa is formed at the formation location of the element region pattern PTaa in the mask layer MS.

[0134] like Figure 7D As shown, the portion of the substrate SB exposed from the mask layer MS is processed to form a device region pattern PTaa with an opening on the transfer surface SBt. At this time, the gate electrode pattern PTgc with an opening on the transfer surface SBt is further recessed, becoming a gate electrode pattern PTgc that is further recessed from the bottom surface of the device region pattern PTaa.

[0135] Through the above steps, the template TM of Implementation Method 1 is manufactured.

[0136] Next, a method for manufacturing the transistor TR using the template TM will be described. Furthermore, the manufacturing of the transistor TR is performed as part of the manufacturing steps of the semiconductor memory device 1 in Embodiment 1.

[0137] Figures 8Aa to 11Cb This diagram illustrates an example of the sequence of the manufacturing method for the transistor TR in Embodiment 1. Figures 8Aa to 11Cb In the diagram, the figure number marked with the lowercase letter "a" is a cross-sectional view along the Y direction of the substrate WF, and the figure number marked with the lowercase letter "b" is a cross-sectional view along the X direction of the substrate WF.

[0138] like Figure 8Aa and Figure 8Ab As shown, a well AAr is formed in a substrate WF, extending from the surface of the substrate WF to a specified depth. The well AAr is formed by implanting impurities such as arsenic, phosphorus, and boron into the substrate WF, which is a semiconductor substrate such as a silicon substrate, to the specified depth.

[0139] Furthermore, above the well AAr, a gate insulating layer Goxr is sequentially formed, followed by a gate electrode layer GCr and a resist layer RS. More specifically, a gate insulating layer Goxr is formed covering the entire surface of the well AAr. Additionally, a polysilicon gate electrode layer GCpr is formed covering the entire surface of the gate insulating layer Goxr, and P-type or N-type impurities are appropriately doped into the polysilicon gate electrode layer GCpr. Furthermore, a metal gate electrode layer GCmr is formed covering the entire surface of the polysilicon gate electrode layer GCpr, and a capping layer CPr is formed covering the entire surface of the metal gate electrode layer GCmr. Finally, a resist layer RS ​​is formed covering the entire surface of the capping layer CPr.

[0140] For example, a photoresist layer (RS) used as a mask layer is a photocurable resist layer that is cured by irradiation with ultraviolet light.

[0141] Furthermore, the gate insulating layer Goxr, the polysilicon gate electrode layer GCpr, the metal gate electrode layer GCmr, and the capping layer CPr can be formed, for example, by chemical vapor deposition (CVD).

[0142] Alternatively, the resist layer RS ​​can be formed, for example, using a spin coating method. However, it is not limited to... Figure 8Aa and Figure 8Ab For example, inkjet printing can also be used to drop the resist material into each injection area in droplet form.

[0143] like Figure 8Ba~Figure 8Cb As shown, the element region pattern RSpa and the gate electrode pattern RSpg are transferred to the resist layer RS ​​by pressing the pattern PT of the template TM against the resist layer RS.

[0144] More specifically, such as Figure 8Ba and Figure 8Bb As shown, with the extension direction of the element region pattern PTaa of the template TM aligned with the Y direction of the substrate WF, the transfer surface SBt of the template TM is aligned with the resist layer RS ​​on the substrate WF. In this state, the template TM is pressed against the resist layer RS. At this time, a gap is maintained between the top cap layer CPr of the substrate WF and the template TM, so that the substrate WF and its various components do not come into contact with the template TM.

[0145] like Figure 8 Ca and Figure 8Cb As shown, with the template TM pressed against the resist layer RSr, the resist layer RSr is hardened by irradiating the template TM with ultraviolet light. After the resist layer RSr hardens, the template TM is demolded.

[0146] Thus, a resist pattern RSp is formed, which has been transferred with the element area pattern RSpa and the gate electrode pattern RSpg. The resist pattern RSp, as a mask pattern, has the element area pattern RSpa and the gate electrode pattern RSpg.

[0147] The component area pattern RSpa is a pattern of the component area pattern PTaa transferred with the stencil TM. Therefore, the component area pattern RSpa has a specified width in the X direction and a convex shape extending in the Y direction. Additionally, the gate electrode pattern RSpg is a pattern of the gate electrode pattern PTgc transferred with the stencil TM. Therefore, the gate electrode pattern RSpg has a convex shape disposed on the upper surface of the component area pattern RSpa.

[0148] In addition, the resist pattern RSp has a resist residue layer RLT formed by hardening the resist layer RS ​​that forms the gap between the top cover layer CPr and the template TM.

[0149] like Figure 9Aa and Figure 9Ab As shown, the resist pattern RSp is treated with oxygen plasma, etc., to remove the residual resist layer RLT. As a result, the capping layer CPr outside the formation location of the element region AA is exposed.

[0150] like Figure 9Ba and Figure 9Bb As shown, using a resist pattern RSp, the element region pattern RSpa is transferred to the gate electrode layer GCr and the well AAr to form a convex element region AA with a specified width in the X direction and extending along the Y direction.

[0151] More specifically, the top cap layer CPr, metal gate electrode layer GCgr, polysilicon gate electrode layer GCpr, gate insulating layer Goxr, and trap AAr exposed from the resist pattern RSp are processed sequentially. Their processing can be performed using methods such as reactive ion etching (RIE). The processing time is controlled to process the trap AAr to the desired depth.

[0152] Thus, a device region AA with a well AAr is formed. However, at this point, the source / drain regions of the device region AA have not yet been formed. Furthermore, a recess RCw is formed in the substrate WF by excavating around the device region AA. Additionally, a gate electrode layer GCaa and a gate insulating layer Goxa are formed. The gate electrode layer GCaa comprises a capping layer CPa, a metal gate electrode layer GCga, and a polysilicon gate electrode layer GCpa, all of which are substantially overlapping the device region AA in the stacking direction of each layer.

[0153] Here, the shape in which these structures substantially overlap with the element region AA means that the top cap layer CPa, the metal gate electrode layer GCga, the polysilicon gate electrode layer GCpa, and the gate insulating layer Goxa are within the range of processing tolerances and overlap with the element region AA.

[0154] like Figure 9Ca and Figure 9Cb As shown, the residual element region pattern RSpa is removed by treating the anti-etching pattern RSp with oxygen plasma, thereby exposing the capping layer CPa outside the formation location of the gate electrode GC.

[0155] like Figure 10Aa and Figure 10Ab As shown, using the resist pattern RSp, the gate electrode pattern RSpg is transferred to the gate electrode layer GCaa to form the gate insulating layer Gox disposed above the device region AA, forming the gate electrode GC.

[0156] More specifically, the top cap layer CPa, the metal gate electrode layer GCga, the polysilicon gate electrode layer GCpa, and the gate insulating layer Goxa exposed from the resist pattern RSp are processed sequentially. Their processing can be performed using, for example, the RIE method, similar to the method described above. During this process, processing is performed while maintaining the selectivity relative to the well AAr, thereby preventing the processing of the upper surface of the element region AA and the bottom surface of the recess RCw.

[0157] Thus, a capping layer CP, a gate electrode GC, and a gate insulating layer Gox are formed above the element region AA. Their width in the X direction is substantially equal to the width of the element region AA, and their center position in the X direction is substantially the same as the center position of the element region AA.

[0158] Here, the width of these components is substantially equal to the width of the component region AA, and their center positions are substantially consistent with the center positions of the component region AA. This means that the top cap layer CP, the gate electrode GC, and the gate insulating layer Gox have widths equal to the width of the component region AA within the range of processing errors, and have center positions consistent with the center positions of the component region AA within the range of processing errors.

[0159] Furthermore, processing errors can sometimes cause lateral etching in at least a portion of the capping layer CP, gate electrode GC, and gate insulating layer Gox, resulting in a reduction in at least one dimension in the X and Y directions. Additionally, processing errors can sometimes cause the apex portions of at least a portion of the capping layer CP, gate electrode GC, and gate insulating layer Gox, which are rectangular in top view, to become rounded corners.

[0160] like Figure 10Ba and Figure 10Bb As shown, the residual resist pattern RSp is removed by ashing using oxygen plasma or similar methods.

[0161] Additionally, a diffusion layer is formed in the element region AA to diffuse impurities such as arsenic, phosphorus, and boron at low concentrations. The diffusion of any of these impurities is hindered by the capping layer CP, the gate electrode GC, and the gate insulating layer Gox, and does not diffuse directly below the gate insulating layer Gox.

[0162] like Figure 10 Ca and Figure 10Cb As shown, a sidewall layer SWr, such as a silicon oxide layer, is formed on the entire surface of a substrate WF containing a gate electrode GC. Thus, the sidewall layer SWr continuously covers the upper and side surfaces of the capping layer CP, the side surface of the gate electrode GC, the side surface of the gate insulating layer Gox, the upper and side surfaces of the element region AA, and the bottom surface of the recess RCw.

[0163] like Figure 11Aa and Figure 11Ab As shown, the sidewall layer SWr is etched back using methods such as RIE. During this process, the sidewall layer SWr is removed from the upper surface of the capping layer CP, the upper surface of the device region AA, and the bottom surface of the recess RCw by processing under conditions that allow for anisotropy. On the other hand, the sidewall layer SWr remains on the sides of the capping layer CP, the gate electrode GC, the gate insulating layer Gox, and the device region AA.

[0164] Therefore, sidewall SWg is formed on the opposite sides of the capping layer CP, gate electrode GC, and gate insulating layer Gox in the Y direction. Additionally, sidewall SWa is formed on the opposite side of the element region AA in the Y direction. Furthermore, sidewall SWga is formed on the opposite sides of the capping layer CP, gate electrode GC, gate insulating layer Gox, and element region AA in the X direction.

[0165] After the sidewalls SWg, SWA, and SWga are formed, a diffusion layer is formed in the element region AA to diffuse impurities such as arsenic, phosphorus, and boron at high concentrations. The diffusion of any of these impurities is hindered by the capping layer CP, the gate electrode GC, and the gate insulating layer Gox, which include the sidewalls SWg, SWA, and SWga, and does not diffuse directly below the gate insulating layer Gox.

[0166] Thus, source / drain regions with high impurity concentration diffusion are formed in the device regions AA on both sides of the capping layer CP, the gate electrode GC, and the gate insulating layer Gox. Additionally, the device region AA directly below the gate insulating layer Gox functions as a channel. Furthermore, the type of impurity is determined by whether an N-channel or P-channel transistor TR is formed.

[0167] like Figure 11Ba and Figure 11Bb As shown, a substrate LR is formed to cover the gate electrode GC and the device region AA. At this time, the recesses RCw on both sides of the device region AA in the X direction and on both sides of the device region AA are also continuously covered by the substrate LR from the upper surface of the device region AA.

[0168] More specifically, a silicon oxide layer OL and a silicon nitride layer NL are sequentially deposited on the entire surface of a substrate WF, including a gate electrode GC. Thus, the silicon oxide layer OL and the silicon nitride layer NL continuously cover the upper surface and side surface of the capping layer CP, the side surface of the gate electrode GC, the side surface of the gate insulating layer Gox, the upper surface and side surface of the device region AA, and the bottom surface of the recess RCw.

[0169] Furthermore, on each side of the capping layer CP, the gate electrode GC, and the gate insulating layer Gox, a sidewall SWg or a sidewall SWga is located between the respective side and the substrate LR. Additionally, on the side of the element region AA, a sidewall SWA or a sidewall SWga is located between that side and the substrate LR.

[0170] like Figure 11 Ca and Figure 11Cb As shown, an interlayer insulating layer (ILD) covers the gate electrode GC, the device region AA, and the recesses RCw on both sides of the device region AA in the X and Y directions. The ILD can be formed by supplying a raw material gas, such as polysilazane, to the substrate WF. In this case, the device separation portion STI is formed by the ILD covering the recesses RCw.

[0171] Through the above steps, the transistor TR of Embodiment 1 is manufactured.

[0172] (Effects of Implementation Method 1)

[0173] As mentioned above, miniaturization has been achieved, for example, in the sense amplifier circuit and latch circuit that read data from the memory cell. As part of this, the number of sense amplifier circuits arranged along the Y direction, i.e., the number of tiers, has been reduced from, for example, 16 tiers to 12 or 10 tiers, thus reducing the circuit area. To reduce the number of tiers, the width of these circuits in the X direction must be reduced, limiting it to a specified number of bit line spacings.

[0174] Previously, when forming transistors, considering the alignment offset between the device region and the gate electrode, the width of the gate electrode in the X direction was sometimes larger than the width of the device region. In this case, in order to ensure that the amount of the gate electrode protruding from the device region and the distance between adjacent gate electrodes in the X direction are appropriate, and to reduce the width of the transistor in the X direction, it is sometimes necessary to reduce the width of the device region in the X direction.

[0175] However, if the aforementioned method is used, the gate width of the gate electrode will become smaller, resulting in a narrow-channel effect, which will prevent the desired current value from being achieved. Furthermore, depending on the transistor structure, a reverse narrow-channel effect may also occur. In this case, there is a risk of increased leakage current, especially since there are many sense amplifiers connected to the bit lines and data latches connected to them, thus the impact of increased leakage current becomes very significant. Additionally, due to the narrow-channel and reverse narrow-channel effects, even small gate width deviations can easily lead to threshold changes, thus there is a risk of increased threshold deviation due to manufacturing deviations. Moreover, the threshold deviation between adjacent transistors, which depends on 1 / √LW, will also increase, thus posing a risk of hindering operational stability. Therefore, it is more ideal to achieve transistor miniaturization by reducing the width of the element separation portion in the X direction rather than reducing the width of the element region.

[0176] According to the manufacturing method of transistor TR in Embodiment 1, a convex element region pattern RSpa and a convex gate electrode pattern RSpg disposed on the upper surface of the element region pattern RSpa are transferred to the resist layer RS ​​by pressing the pattern PT of the template TM against the resist layer RS.

[0177] By using the resist pattern RSp formed in this way, the positional offset of the gate electrode GC relative to the element region AA can be suppressed. Therefore, the portion of the gate electrode GC protruding from the element region AA can be eliminated, and the distance between adjacent gate electrodes GC in the X direction can be reduced. Thus, the miniaturization of the transistor TR can be easily achieved by reducing the width of the element separation portion STI in the X direction, rather than reducing the width of the element region AA. In other words, narrow-channel or anti-narrow-channel effects can be suppressed, and the transistor TR can be miniaturized.

[0178] Furthermore, as mentioned above, by using imprinting technology to manufacture transistors (TR), it is possible to simultaneously pattern the device region (AA) and the gate electrode (GC). This reduces the number of steps, such as photolithography, and thus lowers manufacturing costs.

[0179] exist Figure 12A and Figure 12B The diagram shows a comparative example of a semiconductor memory device and a configuration example of semiconductor memory device 1 according to Embodiment 1. Figure 12A and Figure 12B This is a schematic diagram illustrating an example of the layout of transistors in the semiconductor memory device of Embodiment 1 and the comparative example.

[0180] like Figure 12A As shown, the transistor TR' in the comparative example semiconductor memory device has a gate electrode GC' that protrudes from the element region AA' at both ends in the X direction. Therefore, it is difficult to sufficiently reduce the width of the element separation portion STI' in the X direction of the transistor TR' in the comparative example.

[0181] Furthermore, from the perspective of resolution when patterning the gate electrode GC', it is necessary to maintain a specified distance between adjacent gate electrodes GC' in the X direction, which also hinders the reduction of the width of the element separation section STI'.

[0182] Therefore, within the same spacing of 16 bit lines BL, the element region AA' and gate width W' of the comparative example transistor TR' are greater than those of the transistor TR'. Figure 12B The transistor TR is narrow in Embodiment 1 shown.

[0183] Furthermore, in the manufacturing steps of the transistor TR' in the comparative example, firstly, the element region AA' is patterned, and then the gate electrode GC' is patterned. Therefore, in the recess formed by the patterning of the element region AA', an insulating layer is filled separately from the interlayer insulating layer, for example, forming the element separation portion STI' before the patterning of the gate electrode GC'.

[0184] Therefore, in the comparative example transistor TR', transistors TR' whose gate electrodes GC' are input with the same control signal are adjacent to each other in the X direction, and the gate electrodes GC' extend to the element separation portion STI' between the two transistors TR', so that the two transistors TR' share a gate electrode GC'. Thus, the control signal input from the common gate contact CG' is distributed to the two transistors TR'.

[0185] Based on these circumstances, the following lists several differences between the transistor TR of Embodiment 1 and the transistor TR' of the comparative example.

[0186] According to the transistor TR of Embodiment 1, in the X direction, the upper surface of the element region AA and the gate electrode GC have substantially the same width, and the center position of the upper surface of the element region AA and the center position of the gate electrode GC are substantially aligned in the X direction. According to the transistor TR' of the comparative example, considering the positional offset of the gate electrode GC' relative to the element region AA', the gate electrode GC' protrudes from the element region AA', and therefore does not have the configuration described above.

[0187] According to the transistor TR of Embodiment 1, the liner LR extends continuously from the gate electrode GC to the element separation portion STI, and lies beneath the element separation portion STI. According to the transistor TR' of the comparative example, after filling the recess that becomes the element separation portion STI' with an insulating layer, the gate electrode GC' and the liner are formed. Therefore, the liner is disposed on the element separation portion STI', and does not have the configuration described above.

[0188] Furthermore, according to the transistor TR of Embodiment 1, the substrate LR includes, for example, a silicon nitride layer NL. In this way, by having at least a portion of the substrate LR containing nitride, it is easy to identify that the substrate LR lies beneath the device separation portion STI.

[0189] According to the transistor TR of Embodiment 1, the interlayer insulating layer ILD forms element separation portions STI on both sides of the convex element region AA in the X direction. According to the transistor TR' of the comparative example, the interlayer insulating layer and the insulating layer of the element separation portion STI' are formed separately, and therefore, it does not have the configuration described above.

[0190] According to embodiment 1, the transistor TR has sidewalls SWA and SWA1 that cover the side of the element region AA. According to the comparative example transistor TR', after filling the recess that becomes the element separation portion STI' with an insulating layer, the gate electrode GC' and the sidewalls are formed. Therefore, no sidewalls are formed on the side of the element region AA', and it does not have the configuration described above.

[0191] According to the transistor TR of Embodiment 1, the gate electrodes GC included in the plurality of transistor TRs are each physically separated. According to the transistor TR' of the comparative example, the element separation portion STI' is formed before the gate electrode GC' is patterned. Therefore, the gate electrode GC' to which the common control signal is input is physically connected among the plurality of transistor TR', and does not have the configuration described above.

[0192] (Variation Example 1)

[0193] Next, using Figures 13A to 14Cb The transistor TRa applied to the semiconductor memory device of Variation 1 of Embodiment 1 will be described. The difference between the transistor TRa of Variation 1 and that of Embodiment 1 is that it has a miniaturized element region AAa.

[0194] If imprinting technology is used when manufacturing transistors, then as described above, it is possible to make the width of the element area substantially equal to that of the gate electrode in the X direction. However, as described above, sometimes due to processing errors, side etching may occur at the gate electrode GC, or the apex portion of the gate electrode GC may become rounded.

[0195] In Variation Example 1, when the size of the gate electrode GCa, etc., becomes smaller than the specified value due to these processing errors, the gate electrode GCa is prevented from entering the inner side of the element region AAa.

[0196] Figures 13A-13C This is a diagram illustrating an example of the configuration of the transistor TRa in a variation of Embodiment 1. Figure 13A This is a schematic top view showing the gate electrode GCa and the element region AAa of transistor TRa. Figure 13B It is in the Y direction, that is Figure 13A A cross-sectional view of transistor TRa on line A-A'. Figure 13C It is the X direction, that is Figure 13A A cross-sectional view of transistor TRa on the B-B' line. Furthermore, in Figures 13A-13C In this text, the gate contact and source / drain contact are omitted. Additionally, in... Figures 13A-13C The image shows an example where the gate electrode GCa is in a rounded corner shape RD.

[0197] like Figure 13A As shown, the gate electrode GCa of the transistor TRa is, for example, rectangular in shape when viewed from above, and the four apex portions of the gate electrode GCa are rounded into rounded corner shapes RD. More specifically, at least one of the polysilicon gate electrode GCp and the metal gate electrode GCm included in the gate electrode GCa has a rounded corner shape RD.

[0198] Furthermore, the gate electrode GCa has a shape that slightly protrudes from the element region AAa in the X direction. This is due to the side etching of the opposing side of the element region AAa in the X direction, as described below. Thus, the transistor TRa of Variation Example 1 has widened portions SE on both sides of the element region AAa in the X direction. Therefore, the width of the upper surface of the element region AAa in the X direction is narrower than the width of the gate electrode GCa. However, in this case, the positional offset of the gate electrode GCa relative to the element region AAa is also suppressed; therefore, the center position of the upper surface of the element region AAa and the center position of the gate electrode GCa are substantially aligned in the X direction.

[0199] Since the element region AAa has a slightly narrower width than the gate electrode GCa, the rounded corner portion of the gate electrode GCa is separated from the element region AAa, thereby preventing the gate electrode GCa from entering the inner side of the element region AAa.

[0200] exist Figure 13C The image shows a cross-section at the reduced width SE of transistor TRa. (Example:) Figure 13C As shown, by widening in the X direction, the element region AAa of variation example 1 has, for example, a width narrower in the X direction than the element region AA of embodiment 1.

[0201] In addition, although according to Figure 13B It is difficult to distinguish, but the Y-direction dimension of the element region AAa is also smaller than, for example, the Y-direction dimension of the element region AA in embodiment 1.

[0202] Figures 14Aa to 14Cb This diagram illustrates an example of the sequence of the manufacturing method for the transistor TRa according to Variation 1 of Embodiment 1. Figures 14Aa to 14Cb In the diagram, the figure number marked with the lowercase letter "a" is a cross-sectional view along the Y direction of the substrate WF, and the figure number marked with the lowercase letter "b" is a cross-sectional view along the X direction of the substrate WF.

[0203] In the manufacturing steps of transistor TRa in Variation Example 1, the same manufacturing method as that used for transistor TR in Embodiment 1 is employed until the element region AA is formed. Figure 14Aa and Figure 14Ab This refers to embodiment 1. Figure 9Ba and Figure 9Bb The processing has ended.

[0204] like Figure 14Ba and Figure 14Bb As shown, the manufacturing steps of the transistor TRa in Variation Example 1 include the following steps: side etching is performed on the side of the well AAr on which the element region pattern RSpa is transferred to form an element region AAa with a width in the X direction that is narrower than the width of the gate electrode GCa formed later.

[0205] More specifically, after forming the component region AA, the sides of the component region AA are etched to form a component region AAa that is narrower in both the X and Y directions than the component region AA. The sides of the component region AA can be etched using the RIE method, for example, under conditions that allow for isotropic etching.

[0206] At this time, by maintaining the selectivity ratio with each layer except the trap ACr while processing the device region AA, it is possible to suppress the side erosion of the top cap layer CPr, gate electrode layer GCr, and gate insulating layer Goxr, which are processed into shapes that overlap with the device region AA in the stacking direction of each layer.

[0207] In addition, before removing the component area pattern RSpa, the upper surface of the top cap layer CPa is protected by the component area pattern RSpa while the component area AA is processed. Therefore, the processing error of the gate electrode GCa and the like can be minimized.

[0208] Therefore, transistor TRa has a widened portion SE on the side facing each other in the X direction and the side facing each other in the Y direction of the element region AAa. In addition, through the processing of element region AA, the bottom surface of the recess RCw is also slightly etched, and the recess RCw is slightly deepened.

[0209] However, it is also conceivable that the bottom surface of the recess RCw is etched, and the depth is pre-adjusted when the recess RCw is formed, thereby becoming, for example, the same depth as the recess RCw in Embodiment 1.

[0210] like Figure 14 Ca and Figure 14Cb As shown, after forming the element region AAa, the remaining element region pattern RSpa is removed in the same way as in Embodiment 1, and the top cover layer CPa, the metal gate electrode layer GCga, the polysilicon gate electrode layer GCpa and the gate insulating layer Goxa are processed sequentially using the gate electrode pattern RSpg.

[0211] Thus, a capping layer CP, a gate electrode GCa, and a gate insulating layer Gox are formed on the device region AAa. Their width in the X direction is wider than the width of the device region AA, and their center position in the X direction is substantially the same as the center position of the device region AAa.

[0212] Furthermore, the rounded corners of at least one of the polysilicon gate electrode GCp and the metal gate electrode GCg may be... Figure 14Aa and Figure 14Ab The element region AA is generated during the patterning process. Alternatively, the rounded corners of at least one of the polysilicon gate electrode GCP and the metal gate electrode GCg may be generated during the patterning process. Figure 14 Ca and Figure 14Cb The rounded corners of at least one of the polysilicon gate electrode GCp and the metal gate electrode GCg may be generated during the patterning process of the element region AA and the patterning process of the gate electrode GC.

[0213] At least in Figure 14 Ca and Figure 14Cb The processing ends at the point in time, becoming the gate electrode GCa with a rounded corner shape RD.

[0214] Then, proceed with the implementation method described in Embodiment 1. Figure 10Ba and Figure 10Bb The same processing applies to the subsequent processing of these two graphs.

[0215] By following the steps above, the transistor TRa of Variation Example 1 is manufactured.

[0216] As mentioned above, for example, sometimes a processing error exceeding a specified value may occur in the gate electrode, causing the gate electrode to not completely cover the element region in the X direction, but instead extend into the inner side of the element region.

[0217] For example, when the gate electrode has a rounded corner shape, causing the apex portion of the gate electrode to extend into the inner side of the device region, the electric field from the gate electrode to the end of the device region that forms the channel is considered to be weakened. In this case, the controllability of the gate electrode decreases, and the leakage current increases. Furthermore, if the gate electrode has a rounded corner shape, the gate length of that portion is shorter than a specified value. This also causes an increase in leakage current.

[0218] Additionally, for example, if lateral etching or other defects occur in the gate electrode, causing the width of the gate electrode in the X direction to be narrower than the device region, then the control of the gate electrode may become completely ineffective at the X-direction end of the device region. In this case, current continuously flows through the transistor, thus preventing it from functioning as a transistor.

[0219] According to the transistor TRa of Variation Example 1, in the X direction, the width of the upper surface of the element region AAa is narrower than the width of the gate electrode GCa. This prevents the gate electrode GCa from entering the inner side of the element region AAa. Therefore, the controllability of the gate electrode GCa can be improved, and the gate length can be ensured to suppress the increase of leakage current in the transistor TRa.

[0220] According to the manufacturing method of transistor TRa in Variation Example 1, the side surface of the well AAr with the transferred element region pattern is etched to form an element region AAa with a width narrower than that of the gate electrode GCa in the X direction. Therefore, based on the gate electrode GCa and the element region AAa, which have substantially equal widths in the X direction, it is easy to form an element region AAa with a width narrower than that of the gate electrode GCa.

[0221] (Variation Example 2)

[0222] Next, using Figure 15A and Figure 15B The transistor TRb in the semiconductor memory device of Variation 2 of Embodiment 1 will be described. Regarding the transistor TRb of Variation 2, the arrangement of the transistor TRb along the Y direction differs from that of Embodiment 1.

[0223] Regarding the latch circuits DL and XDL in the peripheral circuitry of the semiconductor memory device 1 in Embodiment 1, there is still room to further reduce the gate width of the transistor TR compared to the gate width of the transistor TR in the sense amplifier circuit SA. Therefore, it is also possible in the future, for example, to arrange the transistors of the sense amplifier circuit SA in a single column as described above within a specified number of bit lines BL, and to arrange the transistors of the latch circuit in multiple columns. Figure 15A and Figure 15B The image shows an example of a latching circuit where transistors are arranged in multiple columns.

[0224] Figure 15A and Figure 15B This is a schematic diagram illustrating an example of the layout of transistors TRb and TRb' in a semiconductor memory device of a variation 2 and a comparative example of Embodiment 1. Figure 15A This is the layout of the comparative transistor TRb'. Figure 15B This is the layout of transistor TRb in variation example 2. Figure 15A and Figure 15B In this text, the gate contacts and source / drain contacts connected to transistors TRb and TRb' are omitted.

[0225] like Figure 15A and Figure 15B As shown, in Variation 2 and the Comparative Example, transistors TRb and TRb' are arranged in multiple columns within the spacing of 16 bit lines BL. As described above, these transistors TRb and TRb' are, for example, transistors belonging to a latching circuit.

[0226] like Figure 15A As shown, the comparative example transistor TRb' has gate electrodes GCb' protruding from the element region AAb' at both ends in the X direction. Therefore, in order to ensure the required gate width, multiple rows of transistors TRb' are arranged within the spacing of 16 bit lines BL, and the positions of the gate electrodes GCb' in the Y direction are staggered among the adjacent transistors TRb' in the X direction. That is, the configuration of the gate electrodes GCb' in the multiple rows of transistors TRb' is staggered.

[0227] However, if the gate electrodes GCb' are arranged in a staggered manner, the overall arrangement of the transistor TRb' increases in the Y direction.

[0228] like Figure 15B As shown, the transistor TRb in Variation Example 2 has a gate electrode GCb with a width in the X direction substantially equal to that of the element region AAB. Therefore, even if the required gate width is ensured and multiple rows of transistor TRb are arranged within the spacing of 16 bit lines BL, the positions of the gate electrodes GCb in the Y direction can be aligned in adjacent transistor TRb in the X direction. In other words, the configuration of the gate electrodes GCb in multiple rows of transistor TRb can be set as a grid.

[0229] In this way, by arranging the gate electrodes GCb in a grid pattern, more transistors TRb can be arranged at a shorter distance in the Y direction, thereby reducing the size of the transistor TRb arrangement in the Y direction.

[0230] [Implementation Method 2]

[0231] Hereinafter, Embodiment 2 will be described in detail with reference to the accompanying drawings. As will be explained below, the configuration of transistors TR and TRa in Embodiment 1 and Variation 1 can also be applied to the transistors of the line decoder 20.

[0232] (The structure of a line decoder)

[0233] First, using Figure 16 The circuit configuration of the line decoder 20 provided in the semiconductor memory device of Embodiment 2 will be described. Figure 16 This is a circuit diagram illustrating an example of the configuration of the line decoder 20 included in the semiconductor memory device of Embodiment 2.

[0234] like Figure 16 As shown, the semiconductor memory device of Embodiment 2 includes a memory cell array 10 configured in the same way as the semiconductor memory device 1 of Embodiment 1. The sequencer 160 and voltage generation circuit 180 of Embodiment 2 are also configured in the same way as those of Embodiment 1.

[0235] The row decoder 20 of Embodiment 2 includes an address decoder 21, a block selection circuit 22, and a voltage selection circuit 23. Furthermore, in terms of circuit configuration, the row decoder 20 may also be configured without alteration compared to the row decoder of Embodiment 1.

[0236] Address decoder 21 has multiple block select lines (BLKSEL) and multiple voltage select lines (VOLSEL).

[0237] Address decoder 21, for example, refers to the address register (see reference) included in the peripheral circuitry, based on control signals from sequencer 160. Figure 1 Address data.

[0238] In addition, the address decoder 21 decodes the referenced address data, causing the transistor TR corresponding to the address data to... 22 and transistor TR 23 Turn on, so that all other transistors TR are turned on. 22 and transistor TR 23 Disconnected. Additionally, transistor TR... 22 and transistor TR 23 These are the transistors included in the block selection circuit 22 and the voltage selection circuit 23 described below.

[0239] Additionally, the address decoder 21 sets the voltages of the block select line BLKSEL and the voltage select line VOLSEL corresponding to the address data to, for example, an "H" state, and sets all other voltages to an "L" state. Furthermore, the voltages applied to these lines depend on whether an N-channel or P-channel transistor is used in the block select circuit 22 and the voltage select circuit 23. The voltages are an example when the transistor is an N-channel transistor.

[0240] exist Figure 16 In the example, in address decoder 21, each block BLK within the memory cell array 10 is provided with one block select line BLKSEL. However, this configuration can be modified appropriately. For example, one block select line BLKSEL can also be provided for each of two or more block BLKs.

[0241] The block selection circuit 22 includes multiple block selection sections 220 corresponding to blocks BLK of the memory cell array 10. Each of the multiple block selection sections 220 includes multiple transistors TR corresponding to word lines WL and select gate lines (SGD, SGS). 22 .

[0242] transistor TR 22 It is a high-voltage N-channel MOS transistor, functioning as a block drive transistor. Transistor TR 22 The drain electrodes are electrically connected to the corresponding word line WL or select gate line (SGD, SGS). Transistor TR 22 The source electrodes are electrically connected to the voltage output terminal OTM via wiring WR and voltage selection circuit 23, respectively. Transistor TR 22 The gate electrodes are commonly connected to the corresponding block select line BLKSEL.

[0243] Additionally, the block selection circuit 22 includes a plurality of transistors (not shown). These transistors are high-voltage CMOS transistors connected between the select gate lines (SGD, SGS) and the ground voltage supply terminal. These transistors enable the select gate lines (SGD, SGS) within the unselected block BLK in the memory cell array 10 to be connected to the ground voltage supply terminal. Furthermore, the plurality of word lines WL within the unselected block BLK are in a floating state.

[0244] The voltage selection circuit 23 includes multiple voltage selection sections 230 corresponding to word lines WL and select gate lines (SGD, SGS). Each of the multiple voltage selection sections 230 includes multiple transistors TR. 23 .

[0245] transistor TR 23 It is a high-voltage N-channel MOS transistor, functioning as a voltage-selective transistor. Transistor TR 23 The drain terminals are electrically connected to the corresponding word line WL or select gate line (SGD, SGS) via wiring WR and block select circuit 22. The source terminals are electrically connected to the corresponding voltage output terminal OTM. The gate electrodes are connected to the corresponding voltage select line VOLSEL.

[0246] In this way, the line decoder 20, which belongs to the peripheral circuitry, has multiple transistors TR 22 TR 23 Wait. But... Figure 16 The circuit configuration of the line decoder 20 shown is an example, and the line decoder 20 includes transistor TR. 22 TR 23 The number and types of etc. can also vary.

[0247] (The structure of a transistor)

[0248] Next, using Figure 17A and Figure 17B The transistor TR included in the line decoder 20 of embodiment 2 22 The physical composition is explained using examples.

[0249] Figure 17A and Figure 17B This is a schematic diagram illustrating an example of the layout of transistors TRc and TRc' in the semiconductor memory device of Embodiment 2 and the comparative example. Figure 17A This is the layout of the transistor TRc in implementation method 2. Figure 17B This is the layout of the transistor TRc' in the comparative example. The transistor TRc in the figure is the transistor TRc that functions as, for example, a block drive transistor, included in the block selection circuit 22 of the line decoder 20. 22 .

[0250] like Figure 17A As shown, the transistor TRc of Embodiment 2 is configured with the transistor TR of Embodiment 1. That is, the transistor TRc includes a device region AAc extending along the Y direction and a plurality of gate electrodes GCc disposed on the device region AAc. The plurality of gate electrodes GCc have a width substantially equal to the width of the device region AAc in the X direction. A device separation portion STIc extends along the Y direction between adjacent device regions AAc in the X direction.

[0251] A gate contact CGc is connected to the gate electrode GCc of transistor TRc. The gate contact CGc is connected to the corresponding block select line BLKSEL.

[0252] A source / drain contact CSc is connected to the element region AAc of transistor TRc. Transistors TRc arranged in a row share the source / drain contact CSc with transistors TRc adjacent in the Y direction. The source / drain contact CSc on the drain electrode side of transistor TRc is connected to the corresponding word line WL. The source / drain contact CSc on the source electrode side of transistor TRc is connected to the corresponding voltage selection section 230 via wiring WR.

[0253] like Figure 17B As shown, the comparative example transistor TRc' has a gate electrode GCc' that protrudes from the element region AAc' at both ends in the X direction. Therefore, in transistor TRc', when the width of the element separation portion STIc' in the X direction is insufficient, the high voltage applied to the gate electrode GCc' may reach the bottom surface of the element separation portion STIc'. In this case, field reversal leakage occurs in the transistor TRc' adjacent in the X direction.

[0254] A high voltage, for example 30 V, is applied to the gate electrode GCc', which is a block drive transistor, via the block select line BLKSEL. If this high voltage is applied to the gate electrode GCc', an inversion layer is also formed on the bottom surface of the device separation section STIc'. Field inversion leakage is the leakage current flowing through this inversion layer to the adjacent transistor TRc' in the X direction.

[0255] According to the transistor TRc of Embodiment 2, the gate electrode GCc does not have a protruding portion. Therefore, the high voltage applied to the gate electrode GCc is less likely to reach the bottom surface of the element separation section STIc, thereby suppressing field reversal leakage. Furthermore, suppressing field reversal leakage and reducing the width of the element separation section STIc in the X direction facilitates miniaturization of the block selection circuit 22.

[0256] In addition, the transistor TR included in the block selection circuit 22 of the line decoder 20 22It may also have the configuration of transistor TRa of variation 1 of embodiment 1.

[0257] Furthermore, the configuration of transistors TR and TRa in Embodiment 1 and Variation 1 can also be applied to other transistors in the line decoder 20. That is, the transistor TR included in the voltage selection circuit 23... 23 Transistors, which are included in block selection circuit 22 and connected between the selection gate line (SGD, SGS) and the ground voltage supply terminal, may also have gate electrodes without the aforementioned protruding portion.

[0258] [Implementation Method 3]

[0259] Hereinafter, Embodiment 3 will be described in detail with reference to the accompanying drawings. As will be explained below, the configuration of transistors TR and TRa in Embodiment 1 and Variation 1 can also be applied to transistors in peripheral circuits of volatile memories such as DRAM (Dynamic Random Access Memory).

[0260] (Brief Structure of a Semiconductor Memory Device)

[0261] First, using Figure 18 Here, an example of the configuration of the semiconductor memory device 2 in Embodiment 3 will be described. Figure 18 This is a block diagram of the semiconductor memory device 2 according to embodiment 3.

[0262] like Figure 18 As shown, the semiconductor memory device 2 of Embodiment 3 includes a memory cell array 201, an input / output circuit 210, a row decoder 222, a read / write amplifier 233, an instruction decoder 241, a column decoder 250, an instruction address input circuit 260, a clock input circuit 271, an internal clock generation circuit 272, and a voltage generation circuit 280, as well as multiple external terminals such as clock terminals CK, CK / , instruction / address terminal CAT, data terminal DQT, data mask terminal DMT, and power supply terminals VPP, VDD, VSS, VDDQ, and VSSQ.

[0263] The memory cell array 201 includes multiple memory banks BNK0 to 7. Each memory bank BNK0 to 7 has multiple word lines WLv and multiple bit lines BLv and / BLv, and a memory cell MCv is disposed at each intersection of the word lines WLv and the bit lines BLv. The memory cell MCv is configured as, for example, a transistor and stores volatile data. Therefore, in order to maintain the data stored in the memory cell array 201, it is periodically updated. Figure 18 For ease of explanation, the update circuitry and other components located in the DRAM have been omitted.

[0264] By incorporating this storage cell MCv, the semiconductor storage device 2 can be configured as, for example, DRAM (Dynamic Random Access Memory). Alternatively, the semiconductor storage device 2 can also be configured as other volatile memories such as SRAM (Static RAM).

[0265] The sense amplifier circuit SAMP is configured corresponding to the bit lines BLv and / BLv. Furthermore, the sense amplifier circuit SAMP is connected to the local input / output lines LIOT and LIOB via the column switch YSW, and to the main input / output lines MIOT and MIOB via the transfer gate TG. The transfer gate TG functions as a switch. The sense amplifier circuit SAMP is similar to the sense amplifier circuit SA in Embodiment 1 (see...). Figure 2 Similarly, sense the data that has been read from the storage unit MCv.

[0266] Each memory cell MCv within the memory cell array 201 is associated with a memory address. Among multiple external terminals, the instruction / address terminal CAT receives the memory address from an external device, such as a memory controller. The memory address received by the instruction / address terminal CAT is transmitted to the instruction address input circuit 260. When the instruction address input circuit 260 receives the memory address, it sends the decoded row address XADD to the row decoder 222 and the decoded column address YADD to the column decoder 250.

[0267] Additionally, the instruction / address terminal CAT receives instructions from, for example, a memory controller. The instructions received by the instruction / address terminal CAT are sent to the instruction decoder 241 as an internal instruction signal ICMD via the instruction address input circuit 260.

[0268] The instruction decoder 241 includes circuitry for decoding the internal instruction ICMD to generate signals for executing the internal instruction. For example, the instruction decoder 241 sends the initiated instruction ACT and the update instruction AREF to the line decoder 222. The line decoder 222 is connected to the word line WLv and selects the word line WLv based on the instruction ACT and update instruction AREF received from the instruction decoder 241.

[0269] Additionally, instruction decoder 241 sends read / write instructions R / W to column decoder 250, for example. Column decoder 250 is connected to bit line BLv and selects bit line BLv based on the read / write instructions R / W received from instruction decoder 241.

[0270] When reading data, the instruction / address terminal CAT receives the read instruction and the memory address. Data is then read from the memory cell MCv within the memory cell array 201 specified by the memory address. The read data is output to the outside via the data terminal DQT through the read / write amplifier 233 and the input / output circuit 210.

[0271] When writing data, the instruction / address terminal CAT receives the write instruction and memory address, and the data terminal DQT receives the write data. Additionally, a data mask is sent to the data mask terminal DMT as needed. The write data is sent to the memory cell array 201 via the input / output circuit 210 and the read / write amplifier 233. Thus, the write data is written to the memory cell MCv specified by the memory address.

[0272] The read / write amplifier 233 includes various latching circuits for temporarily storing read and write data. The read / write amplifier 233 and the sense amplifier circuit SAMP together form a sense amplifier module 30 and a data register 40 corresponding to Embodiment 1 (see reference). Figure 1 The composition of ).

[0273] Power supply voltage is supplied to the power terminals VDD and VSS, and this power supply voltage is also supplied to the voltage generation circuit 280. The voltage generation circuit 280 generates various internal voltages VPP, VOD, VARY, and VPERI based on the power supply voltage. The internal voltage VPP is mainly used in the line decoder 222, the internal voltages VOD and VARY are mainly used in the sense amplifier circuit SAMP of the memory cell array 201, and the internal voltage VPERI is used in other peripheral circuit blocks.

[0274] In addition, power supply voltage is also supplied to power terminals VDDQ and VSSQ, and this power supply voltage is also supplied to input / output circuit 210. Dedicated power supply voltages are applied to power terminals VDDQ and VSSQ to prevent power supply noise generated in input / output circuit 210 from propagating to other circuit blocks. Furthermore, the power supply voltage supplied to power terminals VDDQ and VSSQ can be the same voltage supplied to power terminals VDD and VSS.

[0275] Complementary external clock signals are input to the clock terminals CK and / CK. These external clock signals are supplied to the clock input circuit 271. The clock input circuit 271 generates an internal clock signal ICLK. The internal clock signal ICLK is supplied to the internal clock generation circuit 272 and the instruction decoder 241.

[0276] When the internal clock generation circuit 272 is enabled by the clock enable CKE from the instruction address input circuit 260, it generates various internal clock signals LCLK. The internal clock signals LCLK are used to measure the timing of various internal operations. For example, the internal clock signal LCLK is output to the input / output circuit 210. The input / output circuit 210 operates based on the input internal clock signal LCLK, thereby sending and receiving data at the data terminal DQT.

[0277] (The structure of the sense amplifier circuit)

[0278] Next, using Figure 19 Hereinafter, an example of the configuration of the sense amplifier circuit SAMP included in the semiconductor memory device 2 of Embodiment 3 will be described. Figure 19 This is a circuit diagram illustrating an example of the circuit configuration of the sense amplifier circuit SAMP included in the semiconductor memory device 2 of Embodiment 3.

[0279] like Figure 19 As shown, within the memory cell array 201, the bit line BLv connected to the memory cell MCv and the bit line / BLv paired with the bit line BLv are connected to the sense amplifier circuit SAMP.

[0280] The sense amplifier circuit SAMP contains transistor TR 51 ~TR 54 Transistor TR 51 TR 53 It is a low-voltage P-channel MOS transistor, transistor TR 52 TR 54 It is a low-voltage N-channel MOS transistor.

[0281] transistor TR 51 One end is connected to the signal line that supplies the sensing signal SAP, and the other end is connected to the transistor TR. 52 One end of the transistor TR. 52 The other end is connected to the signal line supplying the sensing signal SAN. Additionally, in the transistor TR... 51 TR 52 Interconnect bit line BLv.

[0282] transistor TR 53 One end is connected to the signal line that supplies the sensing signal SAP, and the other end is connected to the transistor TR. 54 One end of the transistor TR. 54 The other end is connected to the signal line supplying the sensing signal SAN. Additionally, in the transistor TR... 53 TR 54 Interconnect bit line / BLv.

[0283] Additionally, transistor TR51 TR 52 The gate electrode is connected to the transistor TR 53 TR 54 Between, transistor TR 53 TR 54 The gate electrode is connected to the transistor TR 51 TR 52 between.

[0284] A column switch YSW is connected to the bit lines BLv and / BLv, which are located downstream of the sense amplifier circuit SAMP. The column switch YSW contains a transistor TR. 71 TR 72 Transistor TR 71 TR 72 It is a low-voltage N-channel MOS transistor.

[0285] transistor TR 71 One end is connected to the bit line BLv, and the other end is connected to the local input / output line LIOB. Transistor TR 72 One end is connected to the bit line / BLv, and the other end is connected to the local input / output line LIOT. Transistor TR 71 TR 72 The gate electrode is connected to the signal line that supplies the column select signal YS.

[0286] The bit lines BLv and / BLv on the downstream side of the proportional switch YSW are connected to the equalization circuit EQ.

[0287] Equalization circuits (EQ) include transistors (TR). 81 ~TR 83 Transistor TR 81 ~TR 83 It is a low-voltage N-channel MOS transistor.

[0288] transistor TR 81 One end is connected to the bit line BLv, and the other end is connected to the transistor TR. 82 Transistor TR 82 The other end is connected to the bit line / BLv. Additionally, in transistor TR... 81 TR 82 The power supply line for the equalization voltage VBLEQ is connected indirectly. The magnitude of the equalization voltage VBLEQ is half of the power supply voltage VDDSA used by the sense amplifier circuit SAMP.

[0289] transistor TR 83 One end is connected to bit line BLv, and the other end is connected to bit line / BLv.

[0290] transistor TR 81 ~TR 83The gate electrode is connected to the signal line that supplies the equalization signal BLEQ.

[0291] Next, the operation of the circuit including the aforementioned sensing amplifier circuit SAMP will be briefly described.

[0292] Normally, under steady-state conditions, the equalization signal BLEQ is driven high. Consequently, the transistor TR in the equalization circuit EQ... 81 ~TR 83 Turn on, so that bit lines BLv and / BLv are equalized to the pre-charge potential.

[0293] Next, upon issuing the activation command, the equalization is deactivated, and the corresponding word line WL is driven to VPP level based on the input row address XADD. The deactivation of equalization, i.e., the inactivity of the equalization circuit EQ, continues from the issuance of the activation command until the issuance of the precharge command.

[0294] Since the word line WL is driven to VPP level, the cell transistor of the corresponding memory cell MCv is turned on. Therefore, the cell capacitor of the memory cell MCv is connected to the bit line BLv or bit line / BLv. As a result, the potential of the bit line BLv or bit line / BLv changes slightly depending on the cell voltage VCEL of the memory cell MCv. Figure 19 The example shows a slight increase in the potential of the bit line BLv.

[0295] Then, at a specified timing, the sensing signals SAN and SAP change to low and high levels respectively, activating the sensing amplifier circuit SAMP. As a result, the potential difference between the bit lines BLv and / BLv is amplified. Figure 19 The example shows the case where bit line / BL is driven low and bit line BL is driven high.

[0296] Next, when a read command is issued, the corresponding column selection signal YS goes high based on the column address YADD input synchronously with the read command. Before the column selection signal YS is activated, the local input / output lines LIOT and LIOB are pre-charged to the power supply voltage VCC.

[0297] Since the column selection signal YS is activated, the transistor TR of the column switch YSW is activated. 71 TR 72 When the signal is turned on, bit lines BL and / BL are connected to the corresponding local input / output lines LIOB and LIOT. As a result, local input / output line LIOB remains at the precharge level, while local input / output line LIOT drops from the precharge level to a low level.

[0298] By following the steps above, data is read from the storage unit MCv.

[0299] (The structure of a transistor)

[0300] Next, using Figure 20A and Figure 20B The physical configuration example of the transistor TRd included in the sensing amplifier circuit SAMP of Embodiment 3 will be described.

[0301] Figure 20A This is a schematic diagram illustrating an example of the layout of the transistor TRd in the semiconductor memory device of Embodiment 3. Figure 20B This is a schematic diagram illustrating an example of the layout of the transistor TRd' in the comparative example.

[0302] like Figure 20A As shown, in the sense amplifier circuit SAMP, multiple transistors TRd each have multiple component regions AAd arranged in a grid pattern along the X and Y directions. The multiple component regions AAd are electrically separated from each other by component separation sections STId.

[0303] On each element region AAD, multiple gate electrodes GCd are arranged along the X direction. Figure 20A In this example, two gate electrodes GCd are configured on the element region AAd. Furthermore, the element region AAd extends along the Y direction in the region sandwiched between the two gate electrodes GCd and is connected to adjacent element regions AAd.

[0304] The transistor TRd of the sense amplifier circuit SAMP in Embodiment 3 is configured as described in Embodiment 1. That is, in the transistor TRd, the plurality of gate electrodes GCd have a width substantially equal to the width of the element region AAD in the Y direction. In other words, in the transistor TRd of Embodiment 3, the plurality of gate electrodes GCd also have a gate width substantially equal to the width of the element region AAD in the Y direction.

[0305] A gate contact CGd is connected to the gate electrode GCd of transistor TRd. A source / drain contact CSd is connected to the element region AAd of transistor TRd. Transistors TRd arranged along the X direction share the source / drain contact CSd with adjacent transistors TRd. The source / drain contact CSd is also located in the connection portion of element regions AAd that are connected to each other in the Y direction.

[0306] In a plurality of source / drain contacts CSd, the source / drain contacts CSd at one end of the transistor TRd located on the X-direction side are connected to the bit line BL. The source / drain contacts CSd at the other end of the transistor TRd located on the other side of the X-direction are connected to the bit line / BL. Figure 20AThe diagram illustrates a situation where a transistor TRd in one of two element regions AAD arranged along the X direction connects to bit lines BL and / BL.

[0307] In the X-direction, adjacent transistors TRd share a common source / drain contact CSd, which is connected to either the signal line supplying the sensing signal SAP or the signal line supplying the sensing signal SAN. Specifically, when transistor TRd is a P-channel MOS transistor, the source / drain contact CSd is connected to the signal line supplying the sensing signal SAP. When transistor TRd is an N-channel MOS transistor, the source / drain contact CSd is connected to the signal line supplying the sensing signal SAN.

[0308] When connected to the signal lines of the sensing signals SAP / SAN, the source / drain contact CSd is led out to the upper layer and then connected to any one of these signal lines extending along the X direction. That is, these signal lines are configured at a different level from the bit lines BL and / BL. Figure 20A The diagram illustrates a situation where a transistor TRd, belonging to one of two element regions AAD arranged along the X direction, is connected to the signal line of the sensing signal SAP / SAN.

[0309] like Figure 20B As shown, the comparative example transistor TRd' has a gate electrode GCd' that protrudes from the element region AAD' at both ends in the Y direction.

[0310] According to embodiment 3, the gate electrode GCd of the transistor TRd does not have a protruding portion. This allows for a reduction in the area of ​​the transistor TRd. Furthermore, by reducing the size of the transistor TRd, design freedom is increased, making miniaturization of the semiconductor memory device 3 easier.

[0311] Furthermore, the sense amplifier circuit SAMP of Embodiment 3 may also include a transistor configured using the transistor TRa of Variation 1 of Embodiment 1. Additionally, the configuration of the transistor TR in Embodiment 1 and Variation 1 may also be applied to the transistors included in the line decoder 222 of Embodiment 3.

[0312] In embodiments 1 to 3, transistors TR, TRa to TRd are disposed on a substrate WF, such as a silicon substrate. However, the substrate WF may not be a semiconductor substrate, and transistors TR, TRa to TRd may be configured to include a separate semiconductor layer formed on the substrate WF. In this case, the element regions AA, AAa to AAd of transistors TR, TRa to TRd are disposed in the semiconductor layer.

[0313] Several embodiments of the present invention have been described, but these embodiments are provided by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in many other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments or variations thereof are included in the scope or spirit of the invention, and are included within the scope of the invention as set forth in the claims and its equivalents.

Claims

1. A transistor, comprising: Semiconductor layer; A convex element region is disposed in the semiconductor layer, having a specified width in a first direction along the surface of the semiconductor layer, and extending in a second direction along the surface of the semiconductor layer and intersecting the first direction; A gate electrode is disposed above the element region; and A liner covering the top of the gate electrode; On both sides of the component region in the first direction, component separation portions extend along the second direction, and The liner extends continuously from the gate electrode to the element separation portion, and lies beneath the element separation portion.

2. The transistor according to claim 1, wherein The gate electrode is covered by an interlayer insulating layer, and The interlayer insulating layer forms the element separation portion on both sides of the convex element region in the first direction.

3. The transistor according to claim 1, wherein The center position of the upper surface of the element region in the first direction is substantially the same as the center position of the gate electrode in the first direction in the first direction.

4. The transistor according to claim 3, wherein In the first direction, the upper surface of the element region has a substantially equal width to the gate electrode.

5. The transistor according to claim 3, wherein In the first direction, the width of the upper surface of the element region is narrower than the width of the gate electrode.

6. The transistor according to claim 1, further comprising: The first sidewall covers the side surface of the gate electrode; and The second sidewall covers the side of the component area.

7. The transistor according to claim 1, wherein The liner contains at least a portion of nitrides.

8. The transistor according to claim 1, wherein The gate electrodes are arranged in a plurality of manner in the second direction.

9. A transistor, comprising: Semiconductor layer; A convex element region is disposed in the semiconductor layer, having a specified width in a first direction along the surface of the semiconductor layer, and extending in a second direction along the surface of the semiconductor layer and intersecting the first direction; and A gate electrode is disposed above the element region; and In the first direction, the upper surface of the element region has a substantially equal width to the gate electrode, and the center position of the upper surface of the element region in the first direction is substantially the same as the center position of the gate electrode in the first direction in the first direction. On both sides of the element region in the first direction, element separation portions extend along the second direction; The transistor also includes a liner that covers the gate electrode and extends continuously from the surface of the gate electrode to below the element separation portion.

10. The transistor according to any one of claims 1 to 9, further comprising: The gate contact is connected to the gate electrode.

11. The transistor according to any one of claims 1 to 9, further comprising: The source / drain contacts are connected to the component area.

12. The transistor according to any one of claims 1 to 9, wherein The liner covers the top of the gate electrode and the sides of the gate electrode.

13. A semiconductor memory device comprising: A storage cell array, comprising multiple storage cells; and Peripheral circuitry enables the plurality of memory cells to operate; and The peripheral circuitry includes a plurality of transistors as described in claim 1.

14. The semiconductor memory device of claim 13, wherein... The peripheral circuitry includes a sense amplifier circuit containing multiple of the transistors.

15. The semiconductor memory device according to claim 13, wherein The peripheral circuitry includes a latch circuit containing a plurality of the transistors.

16. The semiconductor memory device of claim 13, wherein... The peripheral circuitry has a block selection circuit that includes a plurality of the transistors.

17. The semiconductor memory device according to claim 13, wherein The plurality of transistors includes a first transistor and a second transistor, and The gate electrodes of the first and second transistors are electrically connected via contacts and wiring, but are physically separated.

18. The semiconductor memory device according to claim 13, wherein The storage unit stores non-volatile data.

19. The semiconductor memory device according to claim 13, wherein The storage unit stores volatile data.

20. The semiconductor memory device according to any one of claims 13 to 19, further comprising: An interlayer insulating layer covering multiple transistors.

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