Pixel, display device including pixel, and method of manufacturing display device

Abstract

The present disclosure relates to a pixel, a display device including the same, and a method for manufacturing the display device. The pixel includes: a first region and a second region, separated in a first direction; a (1-1) electrode and a (2-1) electrode, spaced apart in a first region and in a second direction different from the first direction; a (1-2) electrode and a (2-2) electrode, spaced apart in a second region and in a second direction; a plurality of light-emitting elements, between the (1-1) electrode and the (2-1) electrode and between the (1-2) electrode and the (2-2) electrode; a contact electrode, respectively on the (1-1) electrode and the (2-1) electrode and the (1-2) electrode and the (2-2) electrode; an insulating layer, between the (1-1) electrode and the (2-1) electrode and the (1-2) electrode and the (2-2) electrode and the contact electrode, and including a first opening exposing a portion of the (1-1) electrode; and a first intermediate electrode, connecting the contact electrode on the (2-1) electrode and the contact electrode on the (1-2) electrode.

Description

Technical Field

[0001] The present disclosure relates to a pixel, a display device (or a display apparatus) including the pixel, and a method of manufacturing the display device. Background Art

[0002] As interest in information display increases and demand for the use of portable information media increases, demand and commercialization of display devices continue. Summary of the invention

[0003] Technical issues

[0004] An aspect of the present disclosure is to provide a pixel including an emission unit that forms a plurality of series stages by disposing an intermediate electrode (or a bridge electrode) between consecutive series stages without increasing the number of alignment electrodes (or alignment lines).

[0005] Furthermore, an aspect of the present disclosure is to provide a pixel capable of improving light output efficiency of a light emitting element.

[0006] Furthermore, an aspect of the present disclosure is to provide a display device that can easily achieve high resolution.

[0007] Furthermore, an aspect of the present disclosure is to provide a method of manufacturing the above-mentioned display device.

[0008] Technical Solutions

[0009] According to an embodiment of the present disclosure, a pixel may include: a first region and a second region, which are separated in a first direction; a (1-1) electrode and a (2-1) electrode, which are arranged in the first region and are separated in a second direction different from the first direction; a (1-2) electrode and a (2-2) electrode, which are arranged in the second region and are separated in the second direction; a plurality of light-emitting elements, which are arranged between the (1-1) electrode and the (2-1) electrode and between the (1-2) electrode and the (2-2) electrode; contact electrodes, which are respectively arranged on the (1-1) electrode and the (2-1) electrode and the (1-2) electrode and the (2-2) electrode; an insulating layer, which is arranged between each of the (1-1) electrode and the (2-1) electrode and the (1-2) electrode and the (2-2) electrode and the contact electrode, and includes a first opening exposing a portion of the (1-1) electrode; and a first intermediate electrode, which connects the contact electrode on the (2-1) electrode and the contact electrode on the (1-2) electrode. Here, the insulating layer may completely cover the (2-1)th electrode and the (1-2)th electrode.

[0010] In an implementation, the insulating layer may further include a second opening exposing a portion of the (2-2)th electrode.

[0011] In an embodiment, the (1-1)th electrode may directly contact the contact electrode on the (1-1)th electrode through the first opening, and the (2-2)th electrode may directly contact the contact electrode on the (2-2)th electrode through the second opening.

[0012] In an embodiment, the (2-1)th electrode may be electrically insulated from a contact electrode on the (2-1)th electrode, and the (1-2)th electrode may be electrically insulated from a contact electrode on the (1-2)th electrode.

[0013] In an embodiment, the first intermediate electrode may be disposed between the first region and the second region. The first intermediate electrode may be integrated with the contact electrode on the (2-1)th electrode, or the first intermediate electrode may be integrated with the contact electrode on the (1-2)th electrode.

[0014] In an embodiment, the contact electrode on the (1-1)th electrode, the contact electrode on the (2-1)th electrode, the contact electrode on the (1-2)th electrode, the contact electrode on the (2-2)th electrode, and the first intermediate electrode may be provided on the same layer.

[0015] In an embodiment, the (1-1)th electrode and the (1-2)th electrode may extend in the first direction and may be connected to each other between the first region and the second region. The (2-1)th electrode and the (2-2)th electrode may extend in the first direction and may be connected to each other between the first region and the second region.

[0016] In an embodiment, the (1-1)th electrode may be an anode electrode, and the (2-2)th electrode may be a cathode electrode.

[0017] In an embodiment, the plurality of light emitting elements may include: a plurality of first light emitting elements disposed between the (1-1)th electrode and the (2-1)th electrode in the first region; and a plurality of second light emitting elements disposed between the (1-2)th electrode and the (2-2)th electrode in the second region.

[0018] In an embodiment, a plurality of first light emitting elements may form a first series stage connected in parallel between the (1-1)th electrode and the (2-1)th electrode, and a plurality of second light emitting elements may form a second series stage connected in parallel between the (1-2)th electrode and the (2-2)th electrode.

[0019] In an embodiment, the pixel may further include: a third region positioned at a lower end of the second region in the first direction. Here, the third region may include: a (1-3) electrode and a (2-3) electrode spaced apart in the second direction; a plurality of third light-emitting elements disposed between the (1-3) electrode and the (2-3) electrode; contact electrodes disposed on the (1-3) electrode and the (2-3) electrode, respectively; an insulating layer disposed between each of the (1-3) electrode and the (2-3) electrode and the contact electrode, and further including a second opening exposing a portion of the (2-3) electrode; and a second intermediate electrode connecting the contact electrode on the (2-2) electrode and the contact electrode on the (1-3) electrode.

[0020] In an embodiment, the insulating layer may completely cover the (2-2)th electrode and the (1-3)th electrode.

[0021] In an embodiment, the (1-1)th electrode may directly contact the contact electrode on the (1-1)th electrode through the first opening, and the (2-3)th electrode may directly contact the contact electrode on the (2-3)th electrode through the second opening.

[0022] In an embodiment, the second intermediate electrode and the contact electrode on the (2-2)th electrode may be integrated with each other, or the second intermediate electrode and the contact electrode on the (1-3)th electrode may be integrated with each other.

[0023] In an embodiment, a plurality of first light-emitting elements may form a first series stage connected in parallel between the (1-1)th electrode and the (2-1)th electrode, a plurality of second light-emitting elements may form a second series stage connected in parallel between the (1-2)th electrode and the (2-2)th electrode, and a plurality of third light-emitting elements may form a third series stage connected in parallel between the (1-3)th electrode and the (2-3)th electrode.

[0024] In an embodiment, the (1-1)th electrode may be an anode electrode, and the (2-3)th electrode may be a cathode electrode.

[0025] In an embodiment, in the first region, one of the (1-1)th electrode and the (2-1)th electrode may have a circular shape, and the other electrode may have a shape surrounding the periphery of the one electrode. In addition, in the second region, one of the (1-2)th electrode and the (2-2)th electrode may have a circular shape, and the other electrode may have a shape surrounding the periphery of the one electrode.

[0026] According to an embodiment, a display device may include: a plurality of pixels disposed on a substrate. Each of the plurality of pixels may include: a first region and a second region, separated in a first direction; a (1-1) electrode and a (2-1) electrode, arranged in the first region and spaced apart in a second direction different from the first direction; a (1-2) electrode and a (2-2) electrode, arranged in the second region and spaced apart in the second direction; a plurality of first light-emitting elements, arranged between the (1-1) electrode and the (2-1) electrode; a plurality of second light-emitting elements, arranged between the (1-2) electrode and the (2-2) electrode; a first contact electrode arranged on the (1-1) electrode, a second contact electrode arranged on the (2-1) electrode, a third contact electrode arranged on the (1-2) electrode, and a fourth contact electrode arranged on the (2-2) electrode; insulating layers, respectively arranged between the (1-1) electrode and the first contact electrode, between the (2-1) electrode and the second contact electrode, between the (1-2) electrode and the third contact electrode, and between the (2-2) electrode and the fourth contact electrode; and an intermediate electrode, connecting the second contact electrode and the third contact electrode.

[0027] In an embodiment, the insulating layer may include a first opening exposing a portion of the (1-1)th electrode and a second opening exposing a portion of the (2-2)th electrode. Here, the insulating layer may completely cover the (2-1)th electrode and the (1-2)th electrode.

[0028] In an embodiment, the (1-1)th electrode may be an anode electrode, and the (2-2)th electrode may be a cathode electrode.

[0029] The above-mentioned display device can be manufactured by arranging each pixel including a pixel region having a first region and a second region separated in a first direction. Here, arranging the pixel may include: forming a (1-1)th electrode and a (2-1)th electrode separated in a second direction different from the first direction in the first region, and forming a (1-2)th electrode and a (2-2)th electrode separated in the second direction in the second region; forming an insulating material layer on the (1-1)th electrode and the (2-1)th electrode and the (1-2)th electrode and the (2-2)th electrode; aligning a light-emitting element on the insulating material layer; forming an insulating layer by removing a portion of the insulating material layer, the insulating layer including a first opening exposing a portion of the (1-1)th electrode and a second opening exposing a portion of the (2-2)th electrode; and forming contact electrodes on the (1-1)th electrode and the (2-1)th electrode and the (1-2)th electrode and the (2-2)th electrode, respectively, and forming an intermediate electrode connecting the contact electrode on the (2-1)th electrode and the contact electrode on the (1-2)th electrode. Here, the insulating layer may completely cover the (2-1) electrode and the (1-2) electrode. In addition, the (2-1) electrode may be electrically insulated from the contact electrode on the (2-1) electrode, and the (1-2) electrode may be electrically insulated from the contact electrode on the (1-2) electrode.

[0030] Beneficial Effects

[0031] According to an embodiment of the present disclosure, an intermediate electrode can be disposed between two consecutive series stages, a region of a first alignment electrode of a previous series stage can be directly connected to a contact electrode, a region of a second alignment electrode of a subsequent series stage can be directly connected to another contact electrode, and a remaining region of each of the first alignment electrode and the second alignment electrode can be covered with an insulating layer to configure the emission unit of each pixel into a series-parallel hybrid structure without increasing the number of alignment electrodes. Therefore, a pixel with improved light output efficiency and a display device including the pixel can be provided.

[0032] Furthermore, according to the embodiments of the present disclosure, a display device capable of easily achieving high resolution can be provided.

[0033] Furthermore, according to an embodiment of the present disclosure, a method of manufacturing the above-mentioned display device may be provided.

[0034] The effects according to the embodiments of the present disclosure are not limited to the above contents, and additional various effects are included in this specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1a is a perspective view schematically showing a light emitting element according to an embodiment of the present disclosure.

[0036] Figure 1b yes Figure 1a A cross-sectional view of a light-emitting element.

[0037] Figure 2a is a perspective view schematically showing a light emitting element according to another embodiment of the present disclosure.

[0038] Figure 2b yes Figure 2a A cross-sectional view of a light-emitting element.

[0039] Figure 3a is a perspective view schematically showing a light emitting element according to another embodiment of the present disclosure.

[0040] Figure 3b yes Figure 3a A cross-sectional view of a light-emitting element.

[0041] Figure 4a is a perspective view schematically showing a light emitting element according to still another embodiment of the present disclosure.

[0042] Figure 4b yes Figure 4a A cross-sectional view of a light-emitting element.

[0043] Figure 5 is a diagram showing a display device according to an embodiment of the present disclosure, and is a schematic plan view of the display device, in particular, using Figure 1a , Figure 1b , Figure 2a , Figure 2b , Figure 3a , Figure 3b , Figure 4a and Figure 4b Any one of the light-emitting elements shown in is used as a light source.

[0044] Figures 6a to 6e It is shown that according to various embodiments, Figure 5 A circuit diagram showing the electrical connection relationship between components in one pixel shown in FIG.

[0045] Figure 7a and Figure 7b is a diagram showing a method according to another embodiment of the present invention including Figure 5 A circuit diagram showing the electrical connection relationship of components in one pixel is shown in FIG.

[0046] Figure 8 It is schematically shown Figure 5 A plan view of a pixel in the pixel shown in .

[0047] Fig. 9 Only shows Figure 8 A plan view of a first electrode and a second electrode, a contact electrode, a light emitting element, and an opening.

[0048] Fig.10 It is along Figure 8 A cross-sectional view taken along line II'.

[0049] Fig.11 It is along Figure 8 A cross-sectional view taken along line II-II'.

[0050] Fig.12 According to another embodiment, Fig.11 The first bank pattern of the embodiment shown in FIG. Figure 8 The cross-sectional view corresponding to the line II-II'.

[0051] Fig.13 According to another embodiment, Fig.11 The embodiment of the second contact electrode shown in FIG. Figure 8 The cross-sectional view corresponding to the line II-II'.

[0052] Fig.14 It is along Figure 8 A cross-sectional view taken along line III-III'.

[0053] Fig.15 is a plan view showing a driving current flowing through a pixel according to an embodiment of the present disclosure, and shows, for example, Figure 8 The driving current of the pixel flows.

[0054] Figures 16a to 16g It is shown in sequence that the manufacturing Figure 8 A schematic plan view of the pixel approach shown in FIG.

[0055] Figures 17a to 17h It is shown in sequence that the manufacturing Fig.10 A schematic cross-sectional view of a pixel approach is shown in FIG.

[0056] Figures 18a to 18c A pixel according to another embodiment of the present disclosure is schematically shown, and is a schematic plan view of a pixel including only a partial configuration of a display element layer.

[0057] Fig.19 A pixel according to still another embodiment of the present disclosure is schematically shown, and is a schematic plan view of a pixel including only a partial configuration of a display element layer. DETAILED DESCRIPTION

[0058] Since the present disclosure can be modified in various ways and have various forms, specific embodiments will be shown in the drawings and will be described in detail in the specification. However, it should be understood that the present disclosure is not intended to be limited to the specific forms disclosed, and the present disclosure includes all modifications, equivalents and substitutions within the technical scope of the present disclosure.

[0059] When describing each of the accompanying drawings, the same reference numerals are used for the same components. In the accompanying drawings, for the clarity of the present disclosure, the size of the structure may be shown, for example, enlarged from the actual size. The terms "first", "second", etc. may be used to describe various components, but the components should not be limited by these terms. These terms are only used for the purpose of distinguishing one component from another component. For example, without departing from the scope of the present disclosure, a first component may be referred to as a second component, and similarly, a second component may also be referred to as a first component.

[0060] It should be understood that in the present application, the terms "including", "having", etc. are used to specify the features, quantities, steps, operations, components, parts or combinations thereof described in the specification, but do not exclude the possibility of the existence or addition of one or more other features, quantities, steps, operations, components, parts or combinations thereof. In addition, a part of a layer, film, region, plate, etc. is referred to as being "on" another part, which includes not only the case where the part is "directly" "on" another part, but also the case where there is another part between the part and the other part. In addition, in the present specification, when a part of a layer, film, region, plate, etc. is formed on another part, the formation direction is not limited to the upper direction, but includes forming the part on the side surface or in the lower direction. On the contrary, when a part of a layer, film, region, plate, etc. is formed "under" another part, this includes not only the case where the part is "directly" "under" another part, but also the case where there is another part between the part and the other part.

[0061] In the present application, when a component (e.g., 'first component') is operably or communicatively coupled to / coupled to another component (e.g., 'second component') or is "connected to" another component (e.g., 'second component'), the situation should be understood as the component can be directly connected to the other component, or can be connected to the other component through another component (e.g., 'third component'). On the contrary, when a component (e.g., 'first component') is "directly coupled" / "directly coupled" to another component (e.g., 'second component') or is "directly connected" to another component (e.g., 'second component'), the situation can be understood as another component (e.g., 'third component') may not exist between the component and the other component.

[0062] Hereinafter, preferred embodiments of the present disclosure and other matters necessary for those skilled in the art to easily understand the contents of the present disclosure will be described in detail with reference to the accompanying drawings. In the following description, unless the context clearly indicates otherwise, a singular expression includes a plural expression.

[0063] Figure 1a is a perspective view schematically showing a light emitting element LD according to an embodiment of the present disclosure, Figure 1b yes Figure 1a A cross-sectional view of a light emitting element LD, Figure 2a is a perspective view schematically showing a light emitting element LD according to another embodiment of the present disclosure, Figure 2b yes Figure 2a A cross-sectional view of a light emitting element LD, Figure 3a is a perspective view schematically showing a light emitting element LD according to another embodiment of the present disclosure, Figure 3b yes Figure 3a A cross-sectional view of a light emitting element LD, Figure 4a is a perspective view schematically showing a light emitting element LD according to still another embodiment of the present disclosure, and Figure 4b yes Figure 4a A cross-sectional view of a light emitting element LD.

[0064] For convenience, in the description of the light emitting element LD manufactured by the etching method, Figure 1a , Figure 1b , Figure 2a , Figure 2b , Figure 3a and Figure 3b Next, a description is given showing the process of manufacturing the light emitting element LD by the growth method. Figure 4a and Figure 4b In the embodiments of the present disclosure, the type and / or shape of the light emitting element LD is not limited to Figure 1a , Figure 1b , Figure 2a , Figure 2b , Figure 3a , Figure 3b , Figure 4a and Figure 4b The embodiment shown in .

[0065] First, refer to Figure 1a , Figure 1b , Figure 2a , Figure 2b , Figure 3a and Figure 3b , the light emitting element LD may include a first semiconductor layer 11, a second semiconductor layer 13, and an active layer 12 interposed between the first semiconductor layer 11 and the second semiconductor layer 13. For example, the light emitting element LD may implement a light emitting stack in which the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13 are sequentially stacked.

[0066] The light emitting element LD may be provided in a shape extending in one direction. When the extending direction of the light emitting element LD is referred to as a length direction, the light emitting element LD may include one end (or a lower end) and the other end (or an upper end) along the extending direction. Any one of the first semiconductor layer 11 and the second semiconductor layer 13 may be provided at one end (or a lower end) of the light emitting element LD, and the other of the first semiconductor layer 11 and the second semiconductor layer 13 may be provided at the other end (or an upper end) of the light emitting element LD. For example, the first semiconductor layer 11 may be provided at one end (or a lower end) of the light emitting element LD, and the second semiconductor layer 13 may be provided at the other end (or an upper end) of the light emitting element LD.

[0067] The light emitting element LD may be provided in various shapes. For example, the light emitting element LD may have a rod-like shape, a bar-like shape, a column-like shape, etc., which may be long in the length direction (i.e., the aspect ratio may be greater than 1). In an embodiment of the present disclosure, the length L of the light emitting element LD in the length direction may be greater than its diameter D (or the width of the cross section). The light emitting element LD may include, for example, a light emitting diode (LED) that is manufactured to be extremely small to have a diameter D and / or a length L of about micrometer or nanometer order.

[0068] The diameter D of the light emitting element LD may be 0.5 μm to 500 μm, and the length L may be about 1 μm to 100 μm. However, the diameter D and the length L of the light emitting element LD are not limited thereto, and the size of the light emitting element LD may be changed to meet the required conditions (or design conditions) of the lighting device or the light emitting display device to which the light emitting element LD may be applied.

[0069] As an example, the first semiconductor layer 11 may include at least one n-type semiconductor layer. For example, the first semiconductor layer 11 may include any one of InAlGaN, GaN, AlGaN, InGaN, AlN and InN semiconductor materials, and may be an n-type semiconductor layer doped with a first conductive dopant (or n-type dopant) such as Si, Ge or Sn. However, the material configuring the first semiconductor layer 11 is not limited thereto, and various other materials may configure the first semiconductor layer 11. In an embodiment of the present disclosure, the first semiconductor layer 11 may include a gallium nitride (GaN) semiconductor material doped with a first conductive dopant (or n-type dopant). For example, the first semiconductor layer 11 may be an n-type GaN semiconductor layer. The first semiconductor layer 11 may include an upper surface contacting the active layer 12 along the length direction of the light emitting element LD and a lower surface exposed to the outside. The lower surface of the first semiconductor layer 11 may be one end (or lower end) of the light emitting element LD.

[0070] The active layer 12 may be disposed on the first semiconductor layer 11 and may be formed as a single quantum well structure or a multi-quantum well structure. For example, in the case where the active layer 12 is formed as a multi-quantum well structure, in the active layer 12, a barrier layer (not shown), a strain enhancement layer, and a well layer may be periodically and repeatedly stacked as a unit. The strain enhancement layer may have a lattice constant smaller than that of the barrier layer to further enhance the strain applied to the well layer, such as compressive strain. However, the structure of the active layer 12 is not limited to the above-described embodiments.

[0071] The active layer 12 may emit light having a wavelength of 400 nm to 900 nm, and a double heterostructure may be used. In an embodiment of the present disclosure, a cladding layer (not shown) doped with a conductive dopant may be formed on and / or below the active layer 12 along the length direction of the light emitting element LD. For example, the cladding layer may be formed of an AlGaN layer or an InAlGaN layer. According to an embodiment, materials such as AlGaN, InAlGaN, etc. may be used to form the active layer 12, and various other materials may configure the active layer 12. The active layer 12 may include a first surface contacting the first semiconductor layer 11 and a second surface contacting the second semiconductor layer 13. The first surface and the second surface of the active layer 12 may face each other in the length direction of the light emitting element LD.

[0072] When an electric field of a predetermined voltage or more is applied to both ends of the light emitting element LD, the light emitting element LD emits light while electron-hole pairs may be combined in the active layer 12. By controlling the light emission of the light emitting element LD by using this principle, the light emitting element LD can be used as a light source (or light emitting source) of various light emitting devices including pixels of a display device.

[0073] The second semiconductor layer 13 may be disposed on the second surface of the active layer 12, and may include a semiconductor layer of a type different from that of the first semiconductor layer 11. For example, the second semiconductor layer 13 may include at least one p-type semiconductor layer. For example, the second semiconductor layer 13 may include at least one semiconductor material of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and may include a p-type semiconductor layer doped with a second conductive dopant (or p-type dopant) such as Mg. However, the material configuring the second semiconductor layer 13 is not limited thereto, and various other materials may configure the second semiconductor layer 13. In an embodiment of the present disclosure, the second semiconductor layer 13 may include a gallium nitride (GaN) semiconductor material doped with a second conductive dopant (or p-type dopant). For example, the second semiconductor layer 13 may be a p-type GaN semiconductor layer. As Figure 1a and Figure 1bAs shown in , the second semiconductor layer 13 may include a lower surface contacting the second surface of the active layer 12 along the length direction of the light emitting element LD and an upper surface exposed to the outside. Here, the upper surface of the second semiconductor layer 13 may be the other end (or upper end) of the light emitting element LD.

[0074] In the embodiment of the present disclosure, the first semiconductor layer 11 and the second semiconductor layer 13 may have different thicknesses from each other in the length direction of the light emitting element LD. For example, the first semiconductor layer 11 may have a thickness relatively thicker than that of the second semiconductor layer 13 along the length direction of the light emitting element LD. Figure 1a and Figure 1b As shown in , the active layer 12 of the light emitting element LD may be positioned closer to the upper surface of the second semiconductor layer 13 than to the lower surface of the first semiconductor layer 11 .

[0075] At the same time, Figure 1a and Figure 1b In the embodiment of the present disclosure, the first semiconductor layer 11 and the second semiconductor layer 13 are configured as one layer, but the present disclosure is not limited thereto. In an embodiment of the present disclosure, each of the first semiconductor layer 11 and the second semiconductor layer 13 may further include one or more layers, such as a cladding layer and / or a tensile strain barrier reduction (TSBR) layer, depending on the material of the active layer 12. The TSBR layer may be a strain relief layer disposed between semiconductor layers having different lattice structures and used as a buffer to reduce the lattice constant difference. The TSBR layer may be configured by a p-type semiconductor layer such as p-GaInP, p-AlInP, and p-AlGaInP, but the present disclosure is not limited thereto.

[0076] According to the implementation mode, Figures 2a to 3b As shown in , in addition to the above-mentioned first semiconductor layer 11, active layer 12 and second semiconductor layer 13, the light emitting element LD may further include an additional electrode 15 (hereinafter referred to as "first additional electrode") provided on the second semiconductor layer 13. In addition, according to another embodiment, the light emitting element LD may further include another additional electrode (not shown, hereinafter referred to as "second additional electrode") provided at one end of the light emitting element LD.

[0077] The first additional electrode 15 and the second additional electrode may be ohmic contact electrodes, but are not limited thereto, and may be Schottky contact electrodes according to an embodiment. The first additional electrode 15 and the second additional electrode may include a metal or a metal oxide, and may use, for example, chromium (Cr), titanium (Ti), aluminum (Al), gold (Au), nickel (Ni), oxides or alloys thereof, indium tin oxide (ITO), etc., alone or in combination, but are not limited thereto.

[0078] The materials included in each of the first additional electrode 15 and the second additional electrode may be the same or different from each other. The first additional electrode 15 and the second additional electrode may be substantially transparent or translucent. Therefore, the light generated by the light emitting element LD may pass through the first additional electrode 15 and the second additional electrode, and may be emitted to the outside of the light emitting element LD. According to an embodiment, in the case where the light generated by the light emitting element LD does not pass through the first additional electrode 15 and the second additional electrode and is emitted to the outside of the light emitting element LD through an area other than the end of the light emitting element LD, the first additional electrode 15 and the second additional electrode may include an opaque metal.

[0079] In the embodiment of the present disclosure, the light emitting element LD may further include an insulating film 14 (or insulating layer). However, according to the embodiment, the insulating film 14 may be omitted or may be provided to cover only a portion of the first semiconductor layer 11 , the active layer 12 , and the second semiconductor layer 13 .

[0080] The insulating film 14 can prevent an electrical short circuit that may occur when the active layer 12 contacts a conductive material other than the first semiconductor layer 11 and the second semiconductor layer 13. In addition, by forming the insulating layer 14, the life and efficiency of the light-emitting element LD can be improved by minimizing surface defects of the light-emitting element LD. In addition, in the case where a plurality of light-emitting elements LD are closely arranged, the insulating film 14 can prevent an undesirable short circuit that may occur between the light-emitting elements LD. In the case where the active layer 12 can be prevented from being short-circuited with an external conductive material, the presence or absence of the insulating film 14 is not limited.

[0081] like Figure 1a and Figure 1b As shown in FIG. 1 , the insulating film 14 may be provided in a form that completely surrounds the outer circumferential surface of the light emitting stack including the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13. For ease of description, Figure 1a A portion of the insulating film 14 is removed, and the first semiconductor layer 11 , the active layer 12 , and the second semiconductor layer 13 included in the actual light emitting element LD may be surrounded by the insulating film 14 .

[0082] In the above-described embodiment, the insulating film 14 completely surrounds the outer circumferential surface of each of the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13, but the present disclosure is not limited thereto. According to an embodiment, in the case where the light emitting element LD includes the additional electrode 15, as shown in FIG. Figure 2a and Figure 2b As shown in , the insulating film 14 may completely surround the outer circumferential surface of each of the first semiconductor layer 11, the active layer 12, the second semiconductor layer 13, and the additional electrode 15. In addition, according to another embodiment, as Figure 3a and Figure 3bAs shown in , the insulating film 14 may not completely surround the outer circumferential surface of the additional electrode 15 provided on the second semiconductor layer 13, or may surround only a portion of the outer circumferential surface of the additional electrode 15 and may not surround the remaining portion of the outer circumferential surface of the additional electrode 15. However, the insulating film 14 may expose at least both ends of the light emitting element LD, and for example, the insulating film 14 may expose one end of the light emitting element LD and the additional electrode 15 provided at one end side of the second semiconductor layer 13. In addition, according to an embodiment, in the case where the first additional electrode 15 is provided at the other end of the light emitting element LD and the second additional electrode is provided at one end of the light emitting element LD, the insulating film 14 may expose at least one region of the first additional electrode 15 and at least one region of the second additional electrode. Alternatively, in yet another embodiment, the insulating film 14 may not be provided.

[0083] According to an embodiment of the present disclosure, the insulating film 14 may include a transparent insulating material. For example, the insulating film 14 may include a transparent insulating material made of silicon oxide (SiO x ), Silicon Nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum oxide (AlO x ), titanium dioxide (TiO 2 ) etc., but is not limited thereto, and various materials having insulating properties can be used.

[0084] In the case where the insulating film 14 is provided to the light emitting element LD, a short circuit between the active layer 12 and the driving electrode not shown can be prevented. In addition, by forming the insulating film 14, the life and efficiency of the light emitting element LD can be improved by minimizing surface defects of the light emitting element LD. In addition, in the case where a plurality of light emitting elements LD are closely arranged, the insulating film 14 can prevent an undesirable short circuit that may occur between the light emitting elements LD.

[0085] The above-mentioned light emitting element LD can be used as a light source of various display devices. The light emitting element LD can be manufactured by a surface treatment process. For example, when a plurality of light emitting elements LD are mixed in a fluid solution (or solvent) and supplied to each pixel area (for example, the emission area of ​​each pixel or the emission area of ​​each sub-pixel), each of the light emitting elements LD can be subjected to surface treatment so that the light emitting element LD can be uniformly sprayed without being unevenly aggregated in the solution.

[0086] The emission unit (or emission device) including the above-mentioned light-emitting element LD can be used in various types of devices (including display devices) that require a light source. For example, in the case where a plurality of light-emitting elements LD are arranged in a pixel region of each pixel of a display panel, the light-emitting element LD can be used as a light source for each pixel. However, the application field of the light-emitting element LD is not limited to the above-mentioned examples. For example, the light-emitting element LD can be used in another type of device (such as a lighting device) that requires a light source.

[0087] Next, refer to Figure 4a and Figure 4b The light emitting element LD manufactured by the growth method is described.

[0088] When describing the light-emitting element LD manufactured by the growth method, the present disclosure is described based on the differences from the above-mentioned embodiments, and features not specifically described in the light-emitting element LD manufactured by the growth method may be similar to the above-mentioned embodiments, and the same reference marks are given to components similar and / or identical to those of the above-mentioned embodiments.

[0089] refer to Figure 4a and Figure 4b , the light emitting element LD according to an embodiment of the present disclosure may include a first semiconductor layer 11, a second semiconductor layer 13, and an active layer 12 interposed between the first semiconductor layer 11 and the second semiconductor layer 13. According to an embodiment, the light emitting element LD may include a light emitting pattern 10 of a core-shell structure including the first semiconductor layer 11 positioned at the center (or middle) of the light emitting element LD, the active layer 12 surrounding at least one side of the first semiconductor layer 11, the second semiconductor layer 13 surrounding at least one side of the active layer 12, and the additional electrode 15 surrounding at least one side of the second semiconductor layer 13.

[0090] The light emitting element LD may be arranged in a polygonal trumpet shape extending in one direction. For example, the light emitting element LD may be arranged in a hexagonal trumpet shape. When the extending direction of the light emitting element LD is referred to as the length direction, the light emitting element LD may have one end (or lower end) and the other end (or upper end) along the length direction. A portion of one of the first semiconductor layer 11 and the second semiconductor layer 13 may be exposed at one end (or lower end) of the light emitting element LD, and a portion of the other of the first semiconductor layer 11 and the second semiconductor layer 13 may be exposed at the other end (or upper end) of the light emitting element LD. For example, a portion of the first semiconductor layer 11 may be exposed at one end (or lower end) of the light emitting element LD, and a portion of the second semiconductor layer 13 may be exposed at the other end (or upper end) of the light emitting element LD. In this case, in the case where the light emitting element LD is used as a light source of a display device, the exposed portion of the first semiconductor layer 11 may be in contact with one of the drive electrodes driving the light emitting element LD, and the exposed portion of the second semiconductor layer 13 may be in contact with the other drive electrode.

[0091] According to an embodiment, in the case where the light emitting element LD includes the additional electrode 15, a portion of the additional electrode 15 surrounding at least one side of the second semiconductor layer 13 may be exposed at the other end (or upper end) of the light emitting element LD. In this case, in the case where the light emitting element LD is used as a light source of a display device, the exposed portion of the additional electrode 15 may be in contact with the other driving electrode and may be electrically connected to the one driving electrode.

[0092] In an embodiment of the present disclosure, the first semiconductor layer 11 may be positioned at the core, that is, at the center (or middle) of the light emitting element LD. The light emitting element LD may be provided in a shape corresponding to the shape of the first semiconductor layer 11. For example, in the case where the first semiconductor layer 11 has a hexagonal trumpet shape, the light emitting element LD and the light emitting pattern 10 may also have a hexagonal trumpet shape.

[0093] The active layer 12 may be disposed and / or formed in a shape surrounding the outer circumferential surface of the first semiconductor layer 11 in the length direction of the light emitting element LD. Specifically, the active layer 12 may be disposed and / or formed in a shape surrounding a remaining area except for one end disposed at a lower side of an end portion of the first semiconductor layer 11 in the length direction of the light emitting element LD.

[0094] The second semiconductor layer 13 may be disposed and / or formed in a shape surrounding the active layer 12 in the length direction of the light emitting element LD, and may include a semiconductor layer of a type different from that of the first semiconductor layer 11. For example, in the case where the first semiconductor layer 11 includes an n-type semiconductor layer, the second semiconductor layer 13 may include a p-type semiconductor layer.

[0095] In an embodiment of the present disclosure, the light emitting element LD may include an additional electrode 15 surrounding at least one side of the second semiconductor layer 13. The additional electrode 15 may be an ohmic contact electrode or a Schottky contact electrode electrically connected to the second semiconductor layer 13, but is not limited thereto.

[0096] As described above, the light emitting element LD may be configured in a hexagonal trumpet shape having a shape in which an end portion protrudes, and may be implemented as a light emitting pattern 10 of a core-shell structure including a first semiconductor layer 11 disposed at the center thereof, an active layer 12 surrounding the first semiconductor layer 11, a second semiconductor layer 13 surrounding the active layer 12, and an additional electrode 15 surrounding the second semiconductor layer 13. The first semiconductor layer 11 may be disposed at one end (or lower end) of the light emitting element LD having the hexagonal trumpet shape, and the additional electrode 15 may be disposed at the other end (or upper end) of the light emitting element LD.

[0097] In addition, according to an embodiment, the light emitting element LD may further include an insulating film 14 disposed on the outer circumferential surface of the core-shell structured light emitting pattern 10. The insulating film 14 may include a transparent insulating material.

[0098] Figure 5 is a diagram showing a display device according to an embodiment of the present disclosure, and is a schematic plan view of the display device, in particular, using Figure 1a , Figure 1b , Figure 2a , Figure 2b , Figure 3a , Figure 3b , Figure 4a and Figure 4b Any one of the light emitting elements LD shown in FIG. 1 serves as a light emitting source.

[0099] exist Figure 5 , for convenience, the structure of the display device is briefly shown based on the display area DA where an image can be displayed. However, according to an embodiment, at least one driver (e.g., a scan driver, a data driver, etc.) and / or a plurality of signal lines not shown may also be provided in the display device.

[0100] refer to Figure 1a , Figure 1b , Figure 2a , Figure 2b , Figure 3a , Figure 3b , Figure 4a , Figure 4b and Figure 5A display device according to an embodiment of the present disclosure may include a substrate SUB, a plurality of pixels PXL disposed on the substrate SUB and including at least one light emitting element LD, a driver disposed on the substrate SUB and driving the pixels PXL, and a line unit connecting the pixels PXL and the driver to each other.

[0101] The present disclosure can be applied in the case where the display device is an electronic device whose display surface can be applied to at least one surface thereof (such as a smart phone, TV, tablet PC, mobile phone, video phone, e-book reader, desktop PC, laptop PC, netbook computer, workstation, server, PDA, portable multimedia player (PMP), MP3 player, medical device, camera or wearable device).

[0102] According to the method of driving the light emitting element LD, the display device can be classified into a passive matrix type display device and an active matrix type display device. For example, in the case where the display device is implemented as an active matrix type, each of the pixels PXL may include a driving transistor that controls the amount of current supplied to the light emitting element LD, a switching transistor that transmits a data signal to the driving transistor, and the like.

[0103] Recently, active matrix display devices that select and light up each pixel PXL in terms of resolution, contrast, and operating speed have become mainstream, but the present disclosure is not limited to this, and a passive matrix display device in which lighting can be performed on each pixel PXL group may also use components for driving the light-emitting element LD (for example, a first electrode and a second electrode, etc.).

[0104] The substrate SUB may include a display area DA and a non-display area NDA.

[0105] According to an embodiment, the display area DA may be disposed in the central area of ​​the display device, and the non-display area NDA may be disposed in the edge area of ​​the display device to surround the display area DA. However, the positions of the display area DA and the non-display area NDA are not limited thereto, and the positions of the display area DA and the non-display area NDA may be changed.

[0106] The display area DA may be an area where pixels PXL displaying an image are disposed. The non-display area NDA may be an area where a driver for driving the pixels PXL and a portion of a line unit connecting the pixels PXL and the driver to each other are disposed. Figure 5 Only one pixel PXL is shown in FIG. 4 , but a plurality of pixels PXL may be substantially disposed in the display area DA of the substrate SUB.

[0107] The display area DA may have various shapes. For example, the display area DA may be set to a polygonal shape including a closed shape whose sides are formed by straight lines. In addition, the display area DA may be set to a circular shape and / or an elliptical shape including a side formed by a curved line. In addition, the display area DA may be set to various shapes such as a semicircle, a semiellipse, etc. including a side formed by a straight line and a curved line.

[0108] The non-display area NDA may be disposed on at least one side of the display area DA. In an embodiment of the present disclosure, the non-display area NDA may surround a periphery (or edge) of the display area DA.

[0109] The non-display area NDA may be provided with a line unit connected to the pixels PXL and a driver connected to the line unit and driving the pixels PXL.

[0110] The line unit may electrically connect the driver and the pixel PXL to each other. The line unit may provide a signal to each pixel PXL, and may be a signal line connected to each pixel PXL, for example, a fan-out line connected to a scan line, a data line, an emission control line, etc. In addition, the line unit may be a signal line connected to each pixel PXL, for example, a fan-out line connected to a control line, a sensing line, etc., so as to compensate for changes in electrical characteristics of each pixel PXL in real time.

[0111] The substrate SUB may include a transparent insulating material and may transmit light. The substrate SUB may be a rigid substrate or a flexible substrate.

[0112] A region of the substrate SUB may be set as a display area DA to set the pixel PXL, and the remaining region of the substrate SUB may be set as a non-display area NDA. For example, the substrate SUB may include a display area DA including a pixel region in which each pixel PXL may be set, and a non-display area NDA set around the display area DA.

[0113] Each of the pixels PXL may be disposed in the display area DA of the substrate SUB. In an embodiment of the present disclosure, the pixels PXL may be arranged in the display area DA in a stripe or pentile array structure, but the present disclosure is not limited thereto.

[0114] Each pixel PXL may include at least one light emitting element LD driven by corresponding scan signals and data signals. The light emitting element LD may have a size as small as nanometer to micrometer, and may be connected in parallel with adjacent light emitting elements LD, but the present disclosure is not limited thereto. The light emitting element LD may configure the light source of each pixel PXL.

[0115] Each pixel PXL may include at least one light source driven by a predetermined signal (eg, a scan signal and a data signal) and / or a predetermined power (eg, a first driving power and a second driving power). Figures 1a to 4b At least one ultra-small light emitting element LD having a small size of about nanometer to micrometer level is shown in FIG. However, in an embodiment of the present disclosure, the type of the light emitting element LD that can be used as the light source of each pixel PXL is not limited thereto.

[0116] In the embodiment of the present disclosure, the color, type, number, etc. of the pixel PXL are not particularly limited, and for example, the color of light emitted from each pixel PXL may be variously changed.

[0117] The driver may provide a predetermined signal and predetermined power to each pixel PXL through the line unit, thereby controlling driving of the pixel PXL.

[0118] The driver may include a scan driver that provides a scan signal to the pixel PXL through a scan line, an emission driver that provides an emission control signal to the pixel PXL through an emission control line, a data driver that provides a data signal to the pixel PXL through a data line, and a timing controller. The timing controller may control the scan driver, the emission driver, and the data driver.

[0119] Figures 6a to 6e It is shown that according to various embodiments, Figure 5 A circuit diagram showing the electrical connection relationship between components in one pixel PXL is shown in FIG.

[0120] For example, Figures 6a to 6e The electrical connection relationship between components included in the pixel PXL applicable to the active type display device according to various embodiments is shown. However, the types of components included in the pixel PXL to which the embodiments of the present disclosure may be applied are not limited thereto.

[0121] exist Figures 6a to 6e In this, not only will it include Figure 5 Components in each of the pixels PXL shown in FIG. 1 and a region where the components may be disposed is referred to as a pixel PXL. According to an embodiment, Figures 6a to 6e Each pixel PXL shown in FIG. 1 may be included in Figure 5 The pixels PXL may be any one of the pixels PXL in the display device of the present invention, and the pixels PXL may have structures substantially the same as or similar to each other.

[0122] refer to Figures 1a to 4b , Figure 5 as well as Figures 6a to 6eThe pixel PXL may include an emission unit EMU that generates light having a brightness corresponding to the data signal. In addition, the pixel PXL may further selectively include a pixel circuit 144 for driving the emission unit EMU.

[0123] According to an embodiment, the emission unit EMU may include a plurality of light emitting elements LD connected in parallel between a first power line PL1 to which a voltage of a first driving power source VDD may be applied and a second power line PL2 to which a voltage of a second driving power source VSS may be applied. For example, the emission unit EMU may include a first electrode EL1 (or "first alignment electrode") connected to the first driving power source VDD via the pixel circuit 144 and the first power line PL1, a second electrode EL2 (or "second alignment electrode") connected to the second driving power source VSS via the second power line PL2, and a plurality of light emitting elements LD connected in parallel in the same direction between the first electrode EL1 and the second electrode EL2. In an embodiment of the present disclosure, the first electrode EL1 may be an anode electrode, and the second electrode EL2 may be a cathode electrode.

[0124] In an embodiment of the present disclosure, each of the light-emitting elements LD included in the emission unit EMU may include an end (or first end) connected to a first driving power source VDD through a first electrode EL1 and another end (or second end) connected to a second driving power source VSS through a second electrode EL2. The first driving power source VDD and the second driving power source VSS may have different potentials. For example, the first driving power source VDD may be set to a high potential power, and the second driving power source VSS may be set to a low potential power. At this time, during the emission period of the pixel PXL, the potential difference between the first driving power source VDD and the second driving power source VSS may be set to a threshold voltage or a greater voltage of the light-emitting element LD.

[0125] As described above, respective light emitting elements LD connected in parallel in the same direction (eg, forward direction) between the first and second electrodes EL1 and EL2 to which voltages of different potentials are supplied may configure respective effective light sources. Such effective light sources may be collected to configure the emission unit EMU of the pixel PXL.

[0126] The light emitting element LD of the emission unit EMU may emit light having a brightness corresponding to the driving current supplied by the corresponding pixel circuit 144. For example, the pixel circuit 144 may supply a driving current corresponding to the grayscale value of the corresponding frame data to the emission unit EMU during each frame period. The driving current supplied to the emission unit EMU may be divided and flow to the light emitting element LD. Therefore, each of the light emitting elements LD may emit light having a brightness corresponding to the current flowing therethrough, and thus the emission unit EMU may emit light having a brightness corresponding to the driving current.

[0127] at the same time, Figures 6a to 6e An embodiment is shown in which both ends of the light emitting element LD are connected between the first driving power source VDD and the second driving power source VSS in the same direction, but the present disclosure is not limited thereto. According to an embodiment, in addition to the light emitting element LD configuring each effective light source, the emission unit EMU may further include at least one ineffective light source. For example, Figure 6d and Figure 6e As shown in , at least one reverse light emitting element LDr may also be connected between the first electrode EL1 and the second electrode EL2 of the emission unit EMU. The reverse light emitting element LDr may be connected in parallel between the first electrode EL1 and the second electrode EL2 together with the light emitting element LD configuring the effective light source, and may be connected between the first electrode EL1 and the second electrode EL2 in a direction opposite to the light emitting element LD. Even if a predetermined driving voltage (e.g., a driving voltage in the forward direction) may be applied between the first electrode EL1 and the second electrode EL2, the reverse light emitting element LDr remains in an inactive state, and thus current may substantially not flow through the reverse light emitting element LDr.

[0128] The pixel circuit 144 may be connected to the scan line Si and the data line Dj of the corresponding pixel PXL. For example, in the case where the pixel PXL is disposed in the i-th (i may be a natural number greater than 0) row and the j-th (j may be a natural number greater than 0) column of the display area DA, the pixel circuit 144 of the pixel PXL may be connected to the i-th scan line Si and the j-th data line Dj of the display area DA. According to an embodiment, as Figure 6a and Figure 6b As shown in FIG. 1 , the pixel circuit 144 may include a first transistor T1, a second transistor T2 and a storage capacitor Cst. However, the structure of the pixel circuit 144 is not limited to Figure 6a and Figure 6b The embodiment shown in .

[0129] First, refer to Figure 6a , the pixel circuit 144 may include first and second transistors T1 and T2 and a storage capacitor Cst.

[0130] A first terminal of the second transistor T2 (or a switching transistor) may be connected to the j-th data line Dj, and a second terminal may be connected to the first node N1. Here, the first terminal and the second terminal of the second transistor T2 may be different terminals, and for example, in the case where the first terminal is a source electrode, the second terminal may be a drain electrode. In addition, a gate electrode of the second transistor T2 may be connected to the i-th scan line Si.

[0131] In the case where a scan signal of a voltage (e.g., a low voltage) at which the second transistor T2 can be turned on is supplied from the i-th scan line Si, the second transistor T2 can be turned on to electrically connect the j-th data line Dj and the first node N1 to each other. At this time, a data signal of a corresponding frame can be supplied to the j-th data line Dj, and thus the data signal can be transmitted to the first node N1. The data signal transmitted to the first node N1 can be stored in the storage capacitor Cst.

[0132] A first terminal of the first transistor T1 (or driving transistor) may be connected to a first driving power source VDD, and a second terminal may be electrically connected to a first electrode EL1 of each of the light emitting elements LD. A gate electrode of the first transistor T1 may be connected to a first node N1. The first transistor T1 controls the amount of driving current supplied to the light emitting element LD in response to a voltage of the first node N1.

[0133] One electrode of the storage capacitor Cst may be connected to the first driving power source VDD and the other electrode may be connected to the first node N1. The storage capacitor Cst charges a voltage corresponding to the data signal supplied to the first node N1 and maintains the charged voltage until a data signal of the next frame may be supplied.

[0134] Figure 6a and Figure 6b Each of them shows a pixel circuit 144, which includes a second transistor T2 for transmitting a data signal to the pixel PXL, a storage capacitor Cst for storing the data signal, and a first transistor T1 for supplying a driving current corresponding to the data signal to the light emitting element LD.

[0135] However, the present disclosure is not limited thereto, and the structure of the pixel circuit 144 may be variously modified and implemented. For example, the pixel circuit 144 may further include other circuit elements, such as at least one transistor element (such as a transistor element for compensating the threshold voltage of the first transistor T1, a transistor element for initializing the first node N1, and / or a transistor element for controlling the emission time of the light emitting element LD) or a boost capacitor for boosting the voltage of the first node N1.

[0136] In addition, Figure 6a In the embodiment, the transistors (eg, the first transistor T1 and the second transistor T2) included in the pixel circuit 144 are P-type transistors, but the present disclosure is not limited thereto. That is, at least one of the first transistor T1 and the second transistor T2 included in the pixel circuit 144 may be changed to an N-type transistor.

[0137] Next, refer to Figures 1a to 4b , Figure 5 as well as Figure 6bAccording to the embodiment of the present disclosure, the first transistor T1 and the second transistor T2 can be implemented as N-type transistors. In addition to the change in the connection position of some components due to the change in the transistor type, Figure 6b The configuration or operation of the pixel circuit 144 shown in FIG. 1 may be similar to that of Figure 6a The configuration or operation of the pixel circuit 144 is described below. Therefore, a description thereof is briefly provided.

[0138] In the embodiments of the present disclosure, Figure 6b The pixel circuit 144 shown in FIG. 1 may include a first transistor T1 and a second transistor T2 formed of N-type transistors and a storage capacitor Cst. In the case where the first transistor T1 and the second transistor T2 are formed of N-type transistors, the emission unit EMU may be connected between the first driving power source VDD and the pixel circuit 144 to stably charge the storage capacitor Cst for charging a voltage corresponding to a data signal supplied to the first node N1. However, the present disclosure is not limited thereto, and according to an embodiment, Figure 6b The emission unit EMU shown in FIG. 1 may be connected between the pixel circuit 144 and the second driving power source VSS. In the embodiment of the present disclosure, the configuration of the pixel circuit 144 is not limited to Figure 6a and Figure 6b For example, the pixel circuit 144 may be as shown in FIG. Figure 6c and Figure 6d The embodiment shown in FIG.

[0139] like Figure 6c and Figure 6d As shown in , the pixel circuit 144 can be connected to the i-th scan line Si and the j-th data line Dj of the pixel PXL. In addition, according to an embodiment, the pixel circuit 144 can also be connected to at least another scan line. For example, the pixel PXL arranged in the i-th row of the display area DA can also be connected to the (i-1)-th scan line Si-1 and / or the (i+1)-th scan line Si+1. In addition, according to an embodiment, in addition to the first driving power supply VDD and the second driving power supply VSS, the pixel circuit 144 can also be connected to a third power. For example, the pixel circuit 144 can also be connected to the initialization power Vint.

[0140] The pixel circuit 144 may include first to seventh transistors T1 to T7 and a storage capacitor Cst.

[0141] One terminal (e.g., source electrode) of the first transistor T1 (or driving transistor) may be connected to the first driving power source VDD via the fifth transistor T5, and the other terminal (e.g., drain electrode) may be connected to one end of the light emitting element LD via the sixth transistor T6. In addition, the gate electrode of the first transistor T1 may be connected to the first node N1. The first transistor T1 controls a driving current flowing between the first driving power source VDD and the second driving power source VSS via the light emitting element LD in response to a voltage of the first node N1.

[0142] The second transistor T2 (or the switching transistor) may be connected between the j-th data line Dj connected to the pixel PXL and the source electrode of the first transistor T1. In addition, the gate electrode of the second transistor T2 may be connected to the i-th scan line Si connected to the pixel PXL. In the case where a scan signal of a gate-on voltage (e.g., a low voltage) is supplied from the i-th scan line Si, the second transistor T2 may be turned on to electrically connect the j-th data line Dj to the source electrode of the first transistor T1. Therefore, in the case where the second transistor T2 is turned on, the data signal supplied from the j-th data line Dj may be transmitted to the first transistor T1.

[0143] The third transistor T3 may be connected between the drain electrode of the first transistor T1 and the first node N1. In addition, the gate electrode of the third transistor T3 may be connected to the i-th scan line Si. In the case where a scan signal of a gate-on voltage is supplied from the i-th scan line Si, the third transistor T3 may be turned on to electrically connect the drain electrode of the first transistor T1 and the first node N1 to each other.

[0144] The fourth transistor T4 may be connected between the first node N1 and the initialization power line to which the initialization power Vint may be applied. In addition, the gate electrode of the fourth transistor T4 may be connected to a previous scan line, for example, the (i-1)th scan line Si-1. In the case where a scan signal of a gate-on voltage is supplied to the (i-1)th scan line Si-1, the fourth transistor T4 may be turned on to transmit the voltage of the initialization power Vint to the first node N1. Here, the initialization power Vint may have a voltage equal to or less than the lowest voltage of the data signal.

[0145] The fifth transistor T5 may be connected between the first driving power source VDD and the first transistor T1. In addition, the gate electrode of the fifth transistor T5 may be connected to a corresponding emission control line, for example, the i-th emission control line Ei. When the emission control signal of the gate-off voltage is supplied to the i-th emission control line Ei, the fifth transistor T5 may be turned off, and may be turned on in other cases.

[0146] The sixth transistor T6 may be connected between the first transistor T1 and one end of the light emitting element LD. In addition, the gate electrode of the sixth transistor T6 may be connected to the i-th emission control line Ei. When the emission control signal of the gate-off voltage is supplied to the i-th emission control line Ei, the sixth transistor T6 may be turned off, and may be turned on in other cases.

[0147] The seventh transistor T7 may be connected between one end of the light emitting element LD and the initialization power line. In addition, the gate electrode of the seventh transistor T7 may be connected to any one of the following scan lines, for example, the (i+1)th scan line Si+1. When the scan signal of the gate-on voltage is supplied to the (i+1)th scan line Si+1, the seventh transistor T7 may be turned on to supply the voltage of the initialization power Vint to one end of the light emitting element LD.

[0148] The storage capacitor Cst may be connected between the first driving power source VDD and the first node N1. The storage capacitor Cst may store the data signal supplied to the first node N1 and a voltage corresponding to the threshold voltage of the first transistor T1 during each frame period.

[0149] exist Figure 6c and Figure 6d In the embodiment, the transistors (eg, the first to seventh transistors T1 to T7) included in the pixel circuit 144 are P-type transistors, but the present disclosure is not limited thereto. For example, at least one of the first to seventh transistors T1 to T7 may be changed to an N-type transistor.

[0150] In the embodiment of the present disclosure, the configuration of the pixel circuit 144 is not limited to Figures 6a to 6d For example, the pixel circuit 144 may be as shown in FIG. Figure 6e The embodiment shown in FIG.

[0151] like Figure 6e As shown in , the pixel circuit 144 may also be connected to the control line CLi and the sensing line SENj. For example, the pixel circuit 144 of the pixel PXL disposed in the i-th row and the j-th column of the display area DA may be connected to the i-th control line CLi and the j-th sensing line SENj of the display area DA. Figure 6a and Figure 6b In addition to the first transistor T1 and the second transistor T2 shown in FIG. 1 , the pixel circuit 144 may further include a third transistor T3 and another capacitor C OLED .

[0152] The third transistor T3 is connected between the first transistor T1 and the j-th sensing line SENj. For example, one terminal of the third transistor T3 may be connected to one terminal (e.g., source electrode) of the first transistor T1 connected to the first electrode EL1, and the other terminal of the third transistor T3 may be connected to the j-th sensing line SENj. Meanwhile, when the j-th sensing line SENj is omitted, the gate electrode of the third transistor T3 may be connected to the j-th data line Dj.

[0153] According to an embodiment, the gate electrode of the third transistor T3 may be connected to the i-th control line CLi. Meanwhile, in the case where the i-th control line CLi is omitted, the gate electrode of the third transistor T3 may be connected to the i-th scan line Si. The third transistor T3 may be turned on by a control signal of a gate-on voltage (e.g., a high level) supplied to the i-th control line CLi during a predetermined sensing period to electrically connect the j-th sensing line SENj and the first transistor T1 to each other.

[0154] According to an embodiment, the sensing period may be a period for extracting characteristic information (e.g., a threshold voltage of the first transistor T1, etc.) of each of the pixels PXL provided in the display area DA. During the above-mentioned sensing period, the first transistor T1 may be turned on by supplying a predetermined reference voltage at which the first transistor T1 may be turned on to the first node N1 via the j-th data line Dj and the second transistor T2 or by connecting each pixel PXL to a current source, etc. In addition, the first transistor T1 may be connected to the j-th sensing line SENj by supplying a control signal of a gate-on voltage to the third transistor T3 to turn on the third transistor T3. Therefore, characteristic information including the threshold voltage of the first transistor T1, etc., of each pixel PXL may be extracted through the j-th sensing line SENj. The extracted characteristic information may be used to convert image data, so that characteristic deviations between the pixels PXL may be compensated.

[0155] Another capacitor C OLED An electrode of the capacitor C may be connected to the first electrode EL1, and another electrode thereof may be connected to the second power line PL2 to which the second driving power source VSS is applied. OLED The coupling between the light emitting elements LD of the emission unit EMU can be reduced.

[0156] at the same time, Figure 6e An embodiment in which the first transistor T1 to the third transistor T3 are all N-type transistors is disclosed, but the present disclosure is not limited thereto. For example, at least one of the first transistor T1 to the third transistor T3 can be changed to a P-type transistor. In addition, Figure 6eAn embodiment is disclosed in which the emission unit EMU may be connected between the pixel circuit 144 and the second driving power source VSS, but the emission unit EMU may also be connected between the first driving power source VDD and the pixel circuit 144 .

[0157] also, Figures 6a to 6e An embodiment in which all light emitting elements LD of each emission unit EMU are connected in parallel is shown, but the present disclosure is not limited thereto. According to an embodiment, the emission unit EMU may include one or more series stages including a plurality of light emitting elements LD connected in parallel to each other. That is, the emission unit EMU may be configured in a series-parallel hybrid structure. This will be referred to later. Figure 7a and Figure 7b Give a description.

[0158] The structure of the pixel PXL applicable to the present disclosure is not limited to Figures 6a to 6e , and the corresponding pixel PXL may have various structures. In addition, in another embodiment of the present disclosure, each pixel PXL may be configured inside a passive type light-emitting display device or the like. In this case, the pixel circuit 144 may be omitted, and each of the two ends of the light-emitting element LD included in the emission unit EMU may be directly connected to each of the scan lines Si-1, Si and Si+1, the j-th data line Dj, the first power line PL1 to which the first drive power VDD may be applied, the second power line PL2 to which the second drive power VSS may be applied, a predetermined control line, and the like.

[0159] Figure 7a and Figure 7b is a diagram showing a method according to another embodiment of the present invention including Figure 5 0 is a circuit diagram of the electrical connection relationship of components in the pixel PXL shown in FIG.

[0160] exist Figure 7a and Figure 7b In the description, the emission unit EMU of each pixel PXL may include a plurality of series stages (or stages) that may be sequentially connected to each other. Figure 7a and Figure 7b In order to avoid redundant description, the following descriptions are omitted. Figures 6a to 6e A detailed description of a configuration similar to or identical to that of an embodiment of the present invention (e.g., pixel circuit 144).

[0161] First, refer to Figure 7a, the emission unit EMU may include a plurality of light emitting elements LD connected in series with each other. For example, the emission unit EMU may include a first light emitting element LD1, a second light emitting element LD2, a third light emitting element LD3, and a fourth light emitting element LD4 connected in series in a forward direction between a first driving power source VDD and a second driving power source VSS to configure an effective light source. In the following embodiments, at least one random light emitting element among the first light emitting element LD1 to the fourth light emitting element LD4 or the integrated first light emitting element LD1 to the fourth light emitting element LD4 may be referred to as a light emitting element LD or a plurality of light emitting elements LD.

[0162] One end of the first light emitting element LD1 (e.g., the second semiconductor layer) can be connected to the first driving power supply VDD through the first electrode EL1, and the other end of the first light emitting element LD1 (e.g., the first semiconductor layer) can be connected to one end of the second light emitting element LD2 (e.g., the second semiconductor layer) through the first intermediate electrode CTE1 connected between the first series stage and the second series stage.

[0163] One end of the second light emitting element LD2 (e.g., the second semiconductor layer) can be connected to the first intermediate electrode CTE1, and the other end of the second light emitting element LD2 (e.g., the first semiconductor layer) can be connected to one end of the third light emitting element LD3 (e.g., the second semiconductor layer) through the second intermediate electrode CTE2 connected between the second series stage and the third series stage.

[0164] One end of the third light emitting element LD3 can be connected to the second intermediate electrode CTE2, and the other end of the third light emitting element LD3 (e.g., the first semiconductor layer) can be connected to one end of the fourth light emitting element LD4 (e.g., the second semiconductor layer) through the third intermediate electrode CTE3 connected between the third series stage and the fourth series stage.

[0165] One end of the fourth light emitting element LD4 may be connected to the third intermediate electrode CTE3 , and the other end (eg, the first semiconductor layer) of the fourth light emitting element LD4 may be connected to the second driving power source VSS through the second electrode EL2 .

[0166] As described above, the first to fourth light emitting elements LD1 to LD4 may be connected in series between the first and second electrodes EL1 and EL2 of the emission unit EMU of the pixel PXL.

[0167] In the case of the emission unit EMU of the structure in which the light emitting elements LD are connected in series, the voltage applied between the first electrode EL1 and the second electrode EL2 can be increased, and the magnitude of the driving current flowing through the emission unit EMU can be reduced compared to the emission unit EMU of the structure in which the light emitting elements LD are connected in parallel. Therefore, in the case where the emission unit EMU of each pixel PXL is configured in a series structure, the power consumption of the display device can be reduced.

[0168] According to an embodiment, at least one series connection stage may be provided in the form of a plurality of light emitting elements LD connected in parallel to each other. In this case, the emission unit EMU of each pixel PXL may be configured as a series-parallel hybrid structure. For example, the emission unit EMU may be configured as follows: Figure 7b The configuration shown in .

[0169] Next, refer to Figure 7b , the emission unit EMU of the pixel PXL may include a plurality of series connection stages connected in sequence between a first driving power source VDD and a second driving power source VSS. In addition, each series connection stage may include one or more light-emitting elements LD connected in a forward direction between two electrodes of an electrode pair configuring a corresponding series connection stage. For example, the emission unit EMU may include a first series connection stage SET1 and a second series connection stage SET2 connected in sequence between a first driving power source VDD and a second driving power source VSS. Each of the first series connection stage SET1 and the second series connection stage SET2 may include two electrodes EL1 and CTE1 and CTE2 and EL2 of an electrode pair configuring a corresponding series connection stage, and a plurality of light-emitting elements LD connected in parallel in a forward direction between the two electrodes EL1 and CTE1 and CTE2 and EL2 (for example, in the same direction).

[0170] The first series stage SET1 may include a first electrode EL1 and a first intermediate electrode CTE1 of two electrodes EL1 and CTE1 and CTE2 and EL2 forming an electrode pair included in the emission unit EMU, and at least one first light emitting element LD1 connected between the first electrode EL1 and the first intermediate electrode CTE1. For example, the first series stage SET1 may include a first electrode EL1 connected to a first driving power source VDD via a pixel circuit 144, a first intermediate electrode CTE1 connected to a second driving power source VSS, and a plurality of first light emitting elements LD1 connected between the first electrode EL1 and the first intermediate electrode CTE1. One end (e.g., a p-type semiconductor layer) of each of the first light emitting elements LD1 may be electrically connected to the first electrode EL1 of the first series stage SET1, and the other end (e.g., an n-type semiconductor layer) thereof may be electrically connected to the first intermediate electrode CTE1 of the first series stage SET1. The first light emitting element LD1 may be connected in parallel between the first electrode EL1 and the first intermediate electrode CTE1 of the first series stage SET1, and may be connected between the first electrode EL1 and the first intermediate electrode CTE1 in the same direction (e.g., a forward direction). According to an embodiment, at least one reverse light emitting element (reference Figure 6d and Figure 6e The reverse light emitting element LDr may also be connected to the first series stage SET1. The reverse light emitting element LDr may be connected in parallel between the first electrode EL1 and the first intermediate electrode CTE1 together with the first light emitting element LD1 configuring the effective light source, and may be connected between the first electrode EL1 and the first intermediate electrode CTE1 in a direction opposite to the first light emitting element LD1. Even if a predetermined driving voltage (e.g., a forward driving voltage) is applied between the first electrode EL1 and the first intermediate electrode CTE1, the reverse light emitting element LDr remains in an inactive state, and thus current may substantially not flow through the reverse light emitting element LDr.

[0171] The second series stage SET2 may include a second intermediate electrode CTE2 and a second electrode EL2 of two electrodes EL1 and CTE1 and CTE2 and EL2 forming an electrode pair included in the emission unit EMU, and at least one second light emitting element LD2 connected between the second intermediate electrode CTE2 and the second electrode EL2. For example, the second series stage SET2 may include a second intermediate electrode CTE2 connected to the first driving power source VDD via the pixel circuit 144 and the first series stage SET1, a second electrode EL2 connected to the second driving power source VSS, and a plurality of second light emitting elements LD2 connected between the second intermediate electrode CTE2 and the second electrode EL2. One end (e.g., a p-type semiconductor layer) of each second light emitting element LD2 may be electrically connected to the second intermediate electrode CTE2 of the second series stage SET2, and the other end (e.g., an n-type semiconductor layer) may be electrically connected to the second electrode EL2 of the second series stage SET2. The second light emitting element LD2 may be connected in parallel between the second intermediate electrode CTE2 and the second electrode EL2 of the second series stage SET2, and may be connected between the first driving power source VDD and the second driving power source VSS in the same direction (e.g., a forward direction) through the second intermediate electrode CTE2 and the second electrode EL2. According to an embodiment, at least one reverse light emitting element LDr may also be connected between the second intermediate electrode CTE2 and the second electrode EL2. The reverse light emitting element LDr may be connected in parallel between the second intermediate electrode CTE2 and the second electrode EL2 together with the second light emitting element LD2 configuring the effective light source, and may be connected between the second intermediate electrode CTE2 and the second electrode EL2 in a direction opposite to the second light emitting element LD2.

[0172] In an embodiment of the present disclosure, the first intermediate electrode CTE1 of the first tandem stage SET1 and the second intermediate electrode CTE2 of the second tandem stage SET2 may be integrally provided to be connected to each other. That is, the first intermediate electrode CTE1 of the first tandem stage SET1 and the second intermediate electrode CTE2 of the second tandem stage SET2 may be configured to connect the intermediate electrodes CTE of the first tandem stage SET1 and the second tandem stage SET2. As described above, in the case where the first intermediate electrode CTE1 of the first tandem stage SET1 and the second intermediate electrode CTE2 of the second tandem stage SET2 are integrally provided, the first intermediate electrode CTE1 and the second intermediate electrode CTE2 may be different regions of the intermediate electrode CTE.

[0173] In the above embodiment, the first electrode EL1 of the first series stage SET1 may be the anode electrode of the emission unit EMU of each pixel PXL, and the second electrode EL2 of the second series stage SET2 may be the cathode electrode of the emission unit EMU.

[0174] As described above, the emission unit EMU of the pixel PXL including the light emitting element LD connected in a series-parallel hybrid structure can easily adjust the driving current / voltage conditions according to the application product specifications.

[0175] In particular, compared with the emission unit EMU of the structure in which the light-emitting elements LD are connected in parallel, the emission unit EMU of the pixel PXL including the light-emitting element LD that can be connected in a series-parallel hybrid structure can reduce the driving current. In addition, compared with the emission unit EMU of the structure in which all the light-emitting elements LD are connected in series, the emission unit EMU of the pixel PXL including the light-emitting element LD connected in a series-parallel hybrid structure can reduce the driving voltage applied to both ends of the emission unit EMU. In addition, in the case where all the light-emitting elements LD are connected only in series, at least one of the light-emitting elements LD connected in series is not fully connected in the forward direction (or includes the reverse light-emitting element LDr) in series-parallel, which can block the path through which the driving current can flow in the pixel PXL, and thus may cause dark spot defects. On the other hand, in the case where the light-emitting elements LD are connected in a series-parallel hybrid structure, even if some light-emitting elements LD are not connected in the forward direction (or include the reverse light-emitting element LDr) or defects occur in some light-emitting elements LD in each series stage, the driving current can also flow through another light-emitting element LD of the corresponding series stage. Therefore, the defects of the pixel PXL can be prevented or reduced.

[0176] Figure 8 It is schematically shown Figure 5 A plan view of a pixel PXL in the pixel PXL shown in FIG. Fig. 9 Only shows Figure 8 A plan view of the first electrode EL1 and the second electrode EL2, the contact electrode CNE, the light emitting element LD and the opening OPN, Fig.10 It is along Figure 8 A cross-sectional view taken along line II' of Fig.11 It is along Figure 8 A cross-sectional view taken along line II-II', Fig.12 According to another embodiment, Fig.11 The embodiment of the first bank pattern BNK1 shown in FIG. Figure 8 The cross-sectional view corresponding to the line II-II', Fig.13 According to another embodiment, Fig.11 The embodiment of the second contact electrode CNE2 shown in FIG. Figure 8 The cross-sectional view corresponding to the line II-II', Fig.14 It is along Figure 8 A cross-sectional view taken along line III-III', and Fig.152 is a plan view showing a driving current flowing through a pixel PXL according to an embodiment of the present disclosure, and shows, for example, a driving current flowing through Figure 8 The driving current of the pixel PXL flows.

[0177] Figure 8 The pixels PXL shown in FIG. 1 may be respectively Figures 6a to 6e as well as Figure 7a and Figure 7b Any one of the pixels PXL shown in . For example, Figure 8 The pixel PXL shown in FIG. 1 may be Figure 7b The pixel PXL shown in FIG.

[0178] exist Figure 8 In the figure, for the sake of convenience, illustration of the transistor connected to the light emitting element LD and some signal lines connected to the transistor are omitted.

[0179] Figures 8 to 15 The structure of one pixel PXL is simplified and illustrated, such as illustrating each electrode as a single-layer electrode and illustrating each insulating layer as a single-layer insulating layer, but the present disclosure is not limited thereto.

[0180] In addition, in the embodiments of the present disclosure, “formed and / or disposed on the same layer” may mean formed in the same process, and “formed and / or disposed on different layers” may mean formed in different processes.

[0181] Furthermore, in the embodiments of the present disclosure, “connection” between two components may mean inclusively using both electrical connection and physical connection, but the present disclosure is not limited thereto.

[0182] In addition, in the embodiment of the present disclosure, for the convenience of description, the width direction (or horizontal direction) is indicated as a first direction DR1, the height direction (or vertical direction) is indicated as a second direction DR2, and the thickness direction of the substrate SUB is indicated as a third direction DR3. Figures 1a to 5 , Figure 7b as well as Figures 8 to 15 , the display device according to the embodiment of the present disclosure may include a plurality of pixels PXL disposed on a substrate SUB.

[0183] The substrate SUB may include a transparent insulating material and may transmit light. The substrate SUB may be a rigid substrate or a flexible substrate.

[0184] For example, the rigid substrate may be one of a glass substrate, a quartz substrate, a glass ceramic substrate, and a crystallized glass substrate.

[0185] The flexible substrate may be one of a film substrate and a plastic substrate including a polymer organic material. For example, the flexible substrate may include at least one of polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyether sulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose triacetate, and cellulose acetate propionate.

[0186] However, the material configuring the substrate SUB may be variously changed, and may include fiber reinforced plastic (FRP), etc. The material applied to the substrate SUB may preferably have resistance (or heat resistance) to high process temperature during a manufacturing process of the display device.

[0187] The substrate SUB may include a display area DA including at least one pixel area PXA in which the pixel PXL may be disposed, and a non-display area NDA disposed around the display area DA.

[0188] The pixels PXL may be arranged in a matrix form and / or a stripe form according to a plurality of pixel rows extending in a first direction DR1 and a plurality of pixel columns extending in a second direction DR2 different from (e.g., intersecting) the first direction DR1 in a display area DA of a substrate SUB, but the present disclosure is not limited thereto. According to embodiments, the pixels PXL may be provided in the display area DA of a substrate SUB in various arrangement forms.

[0189] The pixel area PXA in which each pixel PXL may be disposed (or arranged) may include an emission area in which light may be emitted and a peripheral area adjacent to the emission area (or surrounding the periphery of the emission area). In an embodiment of the present disclosure, the peripheral area may include a non-emission area in which light may not be emitted.

[0190] The line unit electrically connected to the pixel PXL may be positioned on the substrate SUB. The line unit may include a plurality of signal lines that transmit a predetermined signal (or a predetermined voltage) to each pixel PXL. The signal line may include, for example, an i-th scan line Si that transmits a scan signal to each pixel PXL, a j-th data line Dj that transmits a data signal to each pixel PXL, and power lines PL1 and PL2 that transmit a driving power to each pixel PXL. According to an embodiment, the line unit may further include a plurality of signal lines that transmit a predetermined signal (or a predetermined voltage) to each pixel PXL. Figure 6c and Figure 6d The i-th emission control line Ei that transmits an emission control signal to each pixel PXL is shown in FIG. In addition, according to another embodiment, the line unit may further include the following Figure 6e , a j-th sensing line SENj and an i-th control line CLi connected to each pixel PXL are shown.

[0191] Each pixel PXL may include a pixel circuit layer PCL disposed on a substrate SUB and including a pixel circuit 144 and a display element layer DPL including a plurality of light emitting elements LD. The light emitting element LD may be positioned in a pixel area PXA of each pixel PXL.

[0192] For convenience, the pixel circuit layer PCL is described first, and then the display element layer DPL is described.

[0193] The pixel circuit layer PCL may include a buffer layer BFL, a pixel circuit 144 disposed on the buffer layer BFL, and a protection layer PSV (or a passivation layer) disposed on the pixel circuit 144 .

[0194] The buffer layer BFL may prevent impurities from diffusing into the transistor T included in the pixel circuit 144. The buffer layer BFL may include an inorganic insulating layer including an inorganic material. The buffer layer BFL may include silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ) and such as aluminum oxide (AlO x ) is at least one of the metal oxides of the substrate SUB. The buffer layer BFL may be set as a single layer, but may also be set as a double layer or more layers. In the case where the buffer layer BFL is set as a multilayer, each layer may be formed of the same material or may be formed of different materials. Depending on the material of the substrate SUB, process conditions, etc., the buffer layer BFL may be omitted.

[0195] The pixel circuit 144 may include at least one transistor T and a storage capacitor Cst. The transistor T may include a driving transistor Tdr that controls a driving current of the light emitting element LD and a switching transistor Tsw connected to the driving transistor Tdr. However, the present disclosure is not limited thereto, and in addition to the driving transistor Tdr and the switching transistor Tsw, the pixel circuit 144 may further include a circuit element that performs another function. In the following embodiments, when the driving transistor Tdr and the switching transistor Tsw are collectively referred to, the driving transistor Tdr and the switching transistor Tsw are referred to as a transistor T or a plurality of transistors T. The driving transistor Tdr may have a configuration similar to that of the reference transistor Tdr. Figures 6a to 7b The first transistor T1 described above has the same configuration, and the switch transistor Tsw may have the same configuration as that of the reference Figures 6a to 7b The same configuration is described for the second transistor T2.

[0196] Each of the driving transistor Tdr and the switching transistor Tsw may include a semiconductor pattern SCL, a gate electrode GE, a first terminal SE, and a second terminal DE. The first terminal SE may be one of a source electrode and a drain electrode, and the second terminal DE may be the other of the source electrode and the drain electrode. For example, in the case where the first terminal SE is a source electrode, the second terminal DE may be a drain electrode.

[0197] The semiconductor pattern SCL may be disposed and / or formed on the buffer layer BFL. The semiconductor pattern SCL may include a first contact region contacting the first terminal SE and a second contact region contacting the second terminal DE. The region between the first contact region and the second contact region may be a channel region. The channel region may overlap with the gate electrode GE of the corresponding transistor T. The semiconductor pattern SCL may be a semiconductor pattern formed of polycrystalline silicon, amorphous silicon, an oxide semiconductor, etc. The channel region may be, for example, a semiconductor pattern that may not be doped with impurities, and may be an intrinsic semiconductor. The first contact region and the second contact region may be semiconductor patterns doped with impurities.

[0198] The gate electrode GE may be disposed and / or formed on the semiconductor pattern SCL with the gate insulating layer GI interposed therebetween. For example, the gate electrode GE may be disposed and / or formed on the gate insulating layer GI to correspond to the channel region of the semiconductor pattern SCL. The gate electrode GE may be disposed on the gate insulating layer GI to overlap the channel region of the semiconductor pattern SCL. The gate electrode GE may be formed as a single layer using a material selected from the group consisting of copper (Cu), molybdenum (Mo), tungsten (W), neodymium (Nd), titanium (Ti), aluminum (Al), silver (Ag), and alloys thereof, either alone or in combination, or may be formed as a double-layer or multi-layer structure of molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al), or silver (Ag), which may be a low resistance material to reduce line resistance.

[0199] The gate insulating layer GI may be disposed and / or formed on the semiconductor pattern SCL. The gate insulating layer GI may be an inorganic insulating layer including an inorganic material. For example, the gate insulating layer GI may include silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ) and such as aluminum oxide (AlO x ) at least one of the metal oxides of the present invention. However, the material of the gate insulating layer GI is not limited to the above-mentioned embodiment. According to the embodiment, the gate insulating layer GI may be formed of an organic insulating layer including an organic material. The gate insulating layer GI may be set as a single layer, but may also be set as a multilayer of double layers or more layers.

[0200] The corresponding first terminal SE and the second terminal DE may be disposed and / or formed on the second interlayer insulating layer ILD2, and may contact the first contact region and the second contact region of the semiconductor pattern SCL through contact holes that sequentially pass through the gate insulating layer GI and the first interlayer insulating layer ILD1 and the second interlayer insulating layer ILD2. For example, the first terminal SE may contact the first contact region of the semiconductor pattern SCL, and the second terminal DE may contact the second contact region of the semiconductor pattern SCL. Each of the first terminal SE and the second terminal DE may include the same material as the gate electrode GE, or may include one or more materials selected from the materials disclosed as the configuration material of the gate electrode GE.

[0201] The first interlayer insulating layer ILD1 may be disposed and / or formed on the gate electrode GE, and may be formed of an inorganic insulating layer including an inorganic material. For example, the first interlayer insulating layer ILD1 may include silicon oxide (SiO x ), Silicon Nitride (SiN x ), silicon oxynitride (SiO x N y ) and such as aluminum oxide (AlO x ). The first interlayer insulating layer ILD1 may be formed of a single layer or a plurality of layers. According to an embodiment, the first interlayer insulating layer ILD1 may be an organic insulating layer including an organic material.

[0202] The second interlayer insulating layer ILD2 may be disposed and / or formed on the first interlayer insulating layer ILD1. The second interlayer insulating layer ILD2 may be an inorganic insulating layer including an inorganic material or an organic insulating layer including an organic material. According to an embodiment, the second interlayer insulating layer ILD2 may include the same material as the first interlayer insulating layer ILD1, but the present disclosure is not limited thereto. The second interlayer insulating layer ILD2 may be provided as a single layer, but may also be provided as a multilayer of double layers or more layers.

[0203] In the above-described embodiment, the first terminal SE and the second terminal DE of each of the driving transistor Tdr and the switching transistor Tsw are described as being electrically connected to a separate electrode of the semiconductor pattern SCL through a contact hole that sequentially passes through the gate insulating layer GI and the first interlayer insulating layer ILD1 and the second interlayer insulating layer ILD2, but the present disclosure is not limited thereto. According to an embodiment, the first terminal SE of each of the driving transistor Tdr and the switching transistor Tsw may be a first contact region adjacent to a channel region of the corresponding semiconductor pattern SCL, and the second terminal DE of each of the driving transistor Tdr and the switching transistor Tsw may be a second contact region adjacent to a channel region of the corresponding semiconductor pattern SCL. In this case, the second terminal DE of the driving transistor Tdr may be electrically connected to the light emitting element LD of the corresponding pixel PXL through a separate connector including a bridging electrode, etc.

[0204] In an embodiment of the present disclosure, the transistor T included in the pixel circuit 144 may be configured by an LTPS (low temperature polycrystalline silicon) thin film transistor, but the present disclosure is not limited thereto, and may be configured by an oxide semiconductor thin film transistor according to an embodiment. In addition, a case where the transistor T is a thin film transistor of a top gate structure is described as an example, but the present disclosure is not limited thereto. According to an embodiment, the transistor T may be a thin film transistor of a bottom gate structure.

[0205] According to an embodiment, in addition to the driving transistor Tdr and the switching transistor Tsw, the transistor T included in the pixel circuit layer PCL may also include additional or (other) transistors, such as a transistor for compensating for the threshold voltage of the driving transistor Tdr and a transistor for controlling the emission time of each of the light emitting elements LD.

[0206] The storage capacitor Cst may include a lower electrode LE disposed on the gate insulating layer GI and an upper electrode UE disposed on the first interlayer insulating layer ILD1 and overlapping the lower electrode LE.

[0207] The lower electrode LE may be disposed on the same layer as the gate electrode GE of each of the driving transistor Tdr and the switching transistor Tsw, and may include the same material. According to an embodiment, the lower electrode LE may be disposed integrally with the gate electrode GE of the driving transistor Tdr. In this case, the lower electrode LE may be considered as a region of the gate electrode GE of the driving transistor Tdr. According to another embodiment, the lower electrode LE may be disposed in a structure separated from the gate electrode GE of the driving transistor Tdr. In this case, the gate electrode GE and the lower electrode LE of the driving transistor Tdr may be electrically connected through a separate connector.

[0208] The upper electrode UE may overlap with and cover the lower electrode LE. The capacitance of the storage capacitor Cst may be increased by increasing the overlapping area of ​​the upper electrode UE and the lower electrode LE. The upper electrode UE may be electrically connected to the first power line PL1. Therefore, the first driving power VDD applied to the first power line PL1 may be transmitted to the upper electrode UE.

[0209] The second interlayer insulating layer ILD2 may be disposed and / or formed on the storage capacitor Cst. The second interlayer insulating layer ILD2 may cover the storage capacitor Cst.

[0210] The pixel circuit layer PCL may include a driving voltage line DVL disposed and / or formed on the second interlayer insulating layer ILD2. The driving voltage line DVL may have a voltage that is equal to the reference voltage. Figures 6a to 7b The pixel circuit layer PCL may further include a first power line PL1 to which the first driving power VDD may be applied. The first power line PL1 may be disposed on the same layer as the driving voltage line DVL, or may be disposed on a different layer from the driving voltage line DVL. In an embodiment of the present disclosure, it has been described that the driving voltage line DVL is disposed on the same layer as the first terminal SE and the second terminal DE of the driving transistor Tdr, but the present disclosure is not limited thereto. According to an embodiment, the driving voltage line DVL may be disposed on the same layer as any one of the conductive layers included in the pixel circuit layer PCL. That is, the position of the driving voltage line DVL in the pixel circuit layer PCL may be variously changed.

[0211] The first power line PL1 may be electrically connected to a portion of the display element layer DPL, such as the first electrode EL1, and the drive voltage line DVL may be electrically connected to a portion of the display element layer DPL, such as the second electrode EL2. The first power line PL1 and the drive voltage line DVL may transmit an alignment signal (or alignment voltage) to each of the first electrode EL1 and the second electrode EL2 to align the light emitting element LD in the pixel area PXA of each of the pixels PXL. In addition, after the light emitting element LD is aligned, each of the first power line PL1 and the drive voltage line DVL may transmit a corresponding driving power to each pixel PXL to drive the light emitting element LD.

[0212] Each of the first power line PL1 and the driving voltage line DVL may include a conductive material. For example, each of the first power line PL1 and the driving voltage line DVL may be formed of a single layer with a material selected from the group of copper (Cu), molybdenum (Mo), tungsten (W), neodymium (Nd), titanium (Ti), aluminum (Al), silver (Ag), and alloys thereof, either alone or in combination, or may be formed as a double-layer or multi-layer structure of molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al), or silver (Ag), which may be a low-resistance material to reduce line resistance. For example, each of the first power line PL1 and the driving voltage line DVL may be configured by a double layer stacked in the order of titanium (Ti) / copper (Cu).

[0213] In the above embodiment, it has been described that the driving voltage line DVL is disposed and / or formed on the second interlayer insulating layer ILD2, but the present disclosure is not limited thereto. According to an embodiment, the driving voltage line DVL may be disposed and / or formed on any one of the insulating layers disposed on the substrate SUB (e.g., the first interlayer insulating layer ILD1).

[0214] A protection layer PSV may be disposed and / or formed on the transistor T and the driving voltage line DVL.

[0215] The protective layer PSV may be provided in the form of an organic insulating layer, an inorganic insulating layer, or an organic insulating layer provided on an inorganic insulating layer. For example, the inorganic insulating layer may include silicon oxide (SiO x ), Silicon Nitride (SiN x ), silicon oxynitride (SiO x N y ) and such as aluminum oxide (AlO x The organic insulating layer may include at least one of acrylic resin (polyacrylate resin), epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin and benzocyclobutene resin.

[0216] The protection layer PSV may include a first contact hole CH1 exposing a region of the driving transistor Tdr and a second contact hole CH2 exposing a region of the driving voltage line DVL.

[0217] The display element layer DPL may be disposed on the protection layer PSV.

[0218] The display element layer DPL may include first and second bank patterns BNK1 and BNK2, first and second electrodes EL1 and EL2, a light emitting element LD, and a contact electrode CNE. In addition, the display element layer DPL may include an intermediate electrode CTE and first to third insulating layers INS1 to INS3.

[0219] The first bank pattern BNK1 (or the first pattern) may be positioned in an emission region in which light may be emitted from the pixel region PXA of each of the pixels PXL. The first bank pattern BNK1 may be a supporting member supporting each of the first electrode EL1 and the second electrode EL2 to change a surface profile (or shape) of each of the first electrode EL1 and the second electrode EL2, thereby guiding light emitted from the light emitting element LD in an image display direction of the display device.

[0220] The first bank pattern BNK1 may be disposed and / or formed between the protection layer PSV and the corresponding electrode in the emission region of the corresponding pixel PXL. For example, the first bank pattern BNK1 may be disposed and / or formed between the protection layer PSV and the first electrode EL1 and between the protection layer PSV and the second electrode EL2, respectively.

[0221] The first bank pattern BNK1 may be an inorganic insulating layer including an inorganic material or an organic insulating layer including an organic material. According to an embodiment, the first bank pattern BNK1 may include a single-layer organic insulating layer and / or a single-layer inorganic insulating layer, but the present disclosure is not limited thereto. According to an embodiment, the first bank pattern BNK1 may be provided in the form of a multilayer in which at least one organic insulating layer and at least one inorganic insulating layer are stacked. However, the material of the first bank pattern BNK1 is not limited to the above-mentioned embodiment, and according to an embodiment, the first bank pattern BNK1 may include a conductive material.

[0222] The first bank pattern BNK1 may have a cross-section in a trapezoidal shape that narrows from one surface (eg, upper surface) of the protective layer PSV toward an upper portion along the third direction DR3, but the present disclosure is not limited thereto. Fig.12 As shown in , the first bank pattern BNK1 may include a curved surface having a cross-section of a semi-elliptical shape, a semi-circular shape (or a hemispherical shape), etc., in which the width becomes narrower from one surface of the protective layer PSV toward the upper part along the third direction DR3. When viewed in cross section, the shape of the first bank pattern BNK1 is not limited to the above-mentioned embodiment, and may be variously changed within a range capable of improving the efficiency of light emitted from each of the light emitting elements LD. The first bank patterns BNK1 adjacent in the first direction DR1 may be disposed on the same surface of the protective layer PSV, and may have the same height (or thickness) in the third direction DR3.

[0223] When viewed in a plan view, the first bank pattern BNK1 may have a bar shape extending along the second direction DR2, but the present disclosure is not limited thereto. According to embodiments, the shape of the first bank pattern BNK1 may be variously changed.

[0224] The second bank pattern BNK2 (or bank) may surround at least one side of a peripheral area of ​​the pixel area PXA of each pixel PXL. The peripheral area may include a non-emission area from which light is not emitted.

[0225] The second bank pattern BNK2 may be a structure that defines (or separates) a pixel area PXA (or emission area) of each pixel PXL and each pixel PXL adjacent thereto, and may be, for example, a pixel defining layer. The second bank pattern BNK2 may include at least one light blocking material and / or a reflective material to prevent a light leakage defect in which light (or light) leaks between each pixel PXL and a pixel PXL adjacent thereto. According to an embodiment, the second bank pattern BNK2 may include a transparent material (or substance). The transparent material may include, for example, a polyamide resin, a polyimide resin, etc., but the present disclosure is not limited thereto. According to another embodiment, a reflective material layer may be formed on the second bank pattern BNK2 to further improve the efficiency of light emitted from each pixel PXL.

[0226] The second bank pattern BNK2 may be disposed and / or formed on a layer different from that of the first bank pattern BNK1, but the present disclosure is not limited thereto. According to an embodiment, the second bank pattern BNK2 may be disposed and / or formed on the same layer as the first bank pattern BNK1. In an embodiment of the present disclosure, the second bank pattern BNK2 may be formed on a layer different from that of the first bank pattern BNK1 and may be positioned on the first insulating layer INS1.

[0227] Each of the first electrode EL1 and the second electrode EL2 may be disposed in the pixel area PXA of each of the pixels PXL, and may extend in a direction (e.g., the second direction DR2). The first electrode EL1 and the second electrode EL2 may be disposed on the same surface, and may be disposed to be spaced apart from each other in the first direction DR1. The first electrode EL1 and the second electrode EL2 may be arranged in the order of the first electrode EL1 and the second electrode EL2 along the first direction DR1, but the present disclosure is not limited thereto. According to an embodiment, in the opposite case, for example, the second electrode EL2 and the first electrode EL1 may be arranged in the order of the second electrode EL2 and the first electrode EL1 along the first direction DR1.

[0228] The first electrode EL1 may be electrically connected to a portion of the configuration included in the pixel circuit layer PCL of the corresponding pixel PXL, such as the driving transistor Tdr, through a first contact hole CH1 passing through the protective layer PSV. The second electrode EL2 may be electrically connected to a portion of the configuration included in the pixel circuit layer PCL of the corresponding pixel PXL, such as the driving voltage line DVL, through a second contact hole CH2 passing through the protective layer PSV.

[0229] Each of the first electrode EL1 and the second electrode EL2 may be disposed and / or formed on the first bank pattern BNK1 to have a surface profile corresponding to the shape of the first bank pattern BNK1. For example, each of the first electrode EL1 and the second electrode EL2 has a protruding portion corresponding to the first bank pattern BNK1 and a flat portion corresponding to a surface (e.g., an upper surface) of the protective layer PSV in the third direction DR3.

[0230] Each of the first electrode EL1 and the second electrode EL2 may be formed of a material having a constant reflectivity to allow light emitted from each of the light emitting elements LD to travel in the image display direction of the display device. Each of the first electrode EL1 and the second electrode EL2 may be formed of a conductive material (or substance) having a constant reflectivity. The conductive material (or substance) may include an opaque metal that is conducive to reflecting the light emitted from the light emitting element LD in the image display direction of the display device. The opaque metal may include, for example, metals such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr) and titanium (Ti) and their alloys. According to an embodiment, each of the first electrode EL1 and the second electrode EL2 may include a transparent conductive material (or substance). The transparent conductive material may include conductive oxides such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO) and indium tin zinc oxide (ITZO), conductive polymers such as PEDOT, etc. In the case where each of the first electrode EL1 and the second electrode EL2 includes a transparent conductive material, a separate conductive layer formed of an opaque metal may be additionally included for reflecting light emitted from the light emitting element LD in the image display direction of the display device. However, the material of each of the first electrode EL1 and the second electrode EL2 is not limited to the above materials.

[0231] In addition, each of the first electrode EL1 and the second electrode EL2 may be arranged and / or formed as a single layer, but the present disclosure is not limited thereto. According to an embodiment, each of the first electrode EL1 and the second electrode EL2 may be arranged and / or formed as a multilayer in which two or more materials of metal, alloy, conductive oxide and conductive polymer are stacked. Each of the first electrode EL1 and the second electrode EL2 may be formed of a double layer or more multilayer to minimize the distortion caused by signal delay when transmitting a signal (or voltage) to both ends of each of the light-emitting elements LD. For example, each of the first electrode EL1 and the second electrode EL2 may be formed of a multilayer stacked in the order of indium tin oxide (ITO) / silver (Ag) / indium tin oxide (ITO).

[0232] As described above, since each of the first electrode EL1 and the second electrode EL2 has a surface profile corresponding to the shape of the first bank pattern BNK1 disposed thereunder, light emitted from each of the light emitting elements LD may be reflected by each of the first electrode EL1 and the second electrode EL2 and may further travel in the image display direction of the display device. Therefore, the efficiency of light emitted from each of the light emitting elements LD may be further improved.

[0233] The first bank pattern BNK1 and each of the first and second electrodes EL1 and EL2 may function as a reflective member to improve light efficiency of the display device by guiding light emitted from the light emitting element LD in a desired direction.

[0234] In an embodiment of the present disclosure, the first electrode EL1 and the second electrode EL2 may receive an alignment signal (or an alignment voltage) and may be used as an alignment electrode (or an alignment line) for aligning the light emitting element LD. For example, the first electrode EL1 may receive a first alignment signal (or a first alignment voltage) from the first power line PL1 to serve as a first alignment electrode (or a first alignment line), and the second electrode EL2 may receive a second alignment signal (or a second alignment voltage) from the driving voltage line DVL to serve as a second alignment electrode (or a second alignment line). Here, the first alignment signal and the second alignment signal (or the first alignment voltage and the second alignment voltage) may be signals having a voltage difference and / or a phase difference to the extent at which the light emitting element LD may be aligned between the first electrode EL1 and the second electrode EL2. At least one of the first alignment signal and the second alignment signal (or the first alignment voltage and the second alignment voltage) may be an AC signal (or an AC voltage), but the present disclosure is not limited thereto.

[0235] In the case of applying an alignment signal (or alignment voltage) corresponding to each of the first electrode EL1 and the second electrode EL2, an electric field may be formed between the first electrode EL1 and the second electrode EL2. The light emitting element LD may be aligned and / or disposed in the pixel region PXA of each pixel PXL by the electric field. In the step of aligning the light emitting element LD in the pixel region PXA of each of the pixels PXL, the alignment signal (or alignment voltage) applied to each of the first electrode EL1 and the second electrode EL2 may be controlled, or a magnetic field may be formed to control the relative deflection of the light emitting element LD to be aligned supplied to the pixel region PXA.

[0236] In an embodiment of the present disclosure, when viewed in a plan view, the pixel area PXA of each pixel PXL may be divided into a first area A1 and a second area A2 sequentially disposed along the second direction DR2. When viewed in a plan view, the first area A1 may be an area positioned at an upper side of the pixel area PXA along the second direction DR2, and the second area A2 may be an area positioned at a lower side of the pixel area PXA along the second direction DR2.

[0237] In this case, each of the first electrode EL1 and the second electrode EL2 may be divided into two regions according to the positions of the first area A1 and the second area A2. For example, a region of the first electrode EL1 positioned in the first area A1 may be the (1-1)th electrode EL1_1, and another region of the first electrode EL1 positioned in the second area A2 may be the (1-2)th electrode EL1_2. In addition, a region of the second electrode EL2 positioned in the first area A1 may be the (2-1)th electrode EL2_1, and another region of the second electrode EL2 positioned in the second area A2 may be the (2-2)th electrode EL2_2.

[0238] The (1-1)th electrode EL1_1 and the (1-2)th electrode EL1_2 may be connected to each other in a region between the first area A1 and the second area A2 to configure the first electrode EL1. The (2-1)th electrode EL2_1 and the (2-2)th electrode EL2_2 may be connected to each other in a region between the first area A1 and the second area A2 to configure the second electrode EL2.

[0239] In the first area A1, the (1-1)th electrode EL1_1 and the (2-1)th electrode EL2_1 may be spaced apart from each other in the first direction DR1. In the second area A2, the (1-2)th electrode EL1_2 and the (2-2)th electrode EL2_2 may be spaced apart from each other in the first direction DR1. The distance between the (1-1)th electrode EL1_1 and the (2-1)th electrode EL2_1 in the first direction DR1 may be the same as the distance between the (1-2)th electrode EL1_2 and the (2-2)th electrode EL2_2 in the first direction DR1, but is not limited thereto. According to an embodiment, the distance between the (1-1)th electrode EL1_1 and the (2-1)th electrode EL2_1 in the first direction DR1 may be different from the distance between the (1-2)th electrode EL1_2 and the (2-2)th electrode EL2_2 in the first direction DR1.

[0240] The (1-1)th electrode EL1_1 positioned in the first area A1 may be electrically connected to the driving transistor Tdr of the pixel circuit layer PCL, and the (2-2)th electrode EL2_2 positioned in the second area A2 may be electrically connected to the driving voltage line DVL of the pixel circuit layer PCL.

[0241] In the first area A1, the (1-1)th electrode EL1_1 and the (2-1)th electrode EL2_1 may configure a first series stage SET1 (or a first stage) together with a plurality of light emitting elements LD connected in parallel therebetween. In the second area A2, the (1-2)th electrode EL1_2 and the (2-2)th electrode EL2_2 may configure a second series stage SET2 (or a second stage) together with a plurality of light emitting elements LD connected in parallel therebetween. In an embodiment of the present disclosure, the first series stage SET1 and the second series stage SET2 may be disposed in the pixel area PXA of each pixel PXL, and the first series stage SET1 and the second series stage SET2 may configure an emission unit EMU of a corresponding pixel PXL.

[0242] The (1-1)th electrode EL1_1 included in the first series stage SET1 may be an anode electrode of the emission unit EMU of each pixel PXL, and the (2-2)th electrode EL2_2 included in the second series stage SET2 may be a cathode electrode of the emission unit EMU.

[0243] After the light emitting element LD is aligned in the pixel area PXA of each pixel PXL, a portion of the first electrode EL1 positioned between the pixels PXL adjacent to each other in the second direction DR2 may be removed to individually (or independently) drive each pixel PXL.

[0244] In the above-mentioned embodiment, each of the light-emitting elements LD can be an ultra-small light-emitting element using an inorganic crystal structure material, for example, having a size as small as nanometer to micrometer. For example, each of the light-emitting elements LD can be an ultra-small light-emitting element manufactured by an etching method or an ultra-small light-emitting element manufactured by a growth method.

[0245] At least two to tens of light emitting elements LD may be aligned and / or disposed in the pixel region PXA of each pixel PXL, but the number of light emitting elements LD is not limited thereto. According to embodiments, the number of light emitting elements LD aligned and / or disposed in the pixel region PXA may be variously changed.

[0246] exist Figure 8 , Fig. 9 and Fig.15In the embodiment, the light emitting element LD whose extension direction (or length direction) may be parallel to the first direction DR1 is disposed between the first electrode EL1 and the second electrode EL2, but the present disclosure is not limited thereto. According to an embodiment, at least one of the light emitting elements LD may be disposed such that its length direction may be parallel to the second direction DR2 and / or inclined to the direction of the second direction DR2 between the first electrode EL1 and the second electrode EL2. In addition, according to an embodiment, at least one reverse light emitting element LDr connected in opposite directions may also be disposed between adjacent first electrodes EL1 and second electrodes EL2. In addition, according to another embodiment, at least one defective light emitting element (e.g., an invalid light source) that may not be connected to the first electrode EL1 and the second electrode EL2 may also be disposed between the first electrode EL1 and the second electrode EL2.

[0247] In an embodiment of the present disclosure, each of the light emitting elements LD may emit any one of colored light and white light. Each of the light emitting elements LD may be aligned between the first electrode EL1 and the second electrode EL2 so that the length L direction may be parallel to the first direction DR1. The light emitting element LD may be provided in a form in which the light emitting element LD is ejected in a solution and may be input to the pixel area PXA of each pixel PXL.

[0248] The light emitting element LD may be input to the pixel area PXA of each pixel PXL by an inkjet printing method, a slit coating method, or other various methods. For example, the light emitting element LD may be mixed with a volatile solvent and may be supplied to the pixel area PXA by an inkjet printing method or a slit coating method. At this time, when an alignment signal (or alignment voltage) corresponding to each of the first electrode EL1 and the second electrode EL2 provided to the pixel area PXA is applied, an electric field may be formed between the two adjacent electrodes. Therefore, the light emitting element LD may be aligned between the first electrode EL1 and the second electrode EL2.

[0249] After the light emitting element LD may be aligned, the solvent may be evaporated or removed in another method, and thus the light emitting element LD may be finally aligned and / or disposed in the pixel area PXA of each pixel PXL.

[0250] One end of each of the light emitting elements LD may be directly connected to one of the first electrode EL1 and the second electrode EL2, or may be connected to the one electrode through a corresponding contact electrode CNE. In addition, the other end of each of the light emitting elements LD may be directly connected to the remaining electrode of the first electrode EL1 and the second electrode EL2, or may be connected to the remaining electrode through a corresponding contact electrode CNE.

[0251] In an embodiment of the present disclosure, the light emitting element LD may include a plurality of first light emitting elements LD1 and a plurality of second light emitting elements LD2 .

[0252] The first light emitting element LD1 may be disposed between the (1-1)th electrode EL1_1 and the (2-1)th electrode EL2_1 in the first area A1. The first light emitting element LD1 may be disposed between the (1-1)th electrode EL1_1 and the (2-1)th electrode EL2_1 in the same direction. For example, one end (e.g., p-type semiconductor layer) of each of the first light emitting elements LD1 may be connected to the (1-1)th electrode EL1_1, and the other end (e.g., n-type semiconductor layer) of each of the first light emitting elements LD1 may be connected to the contact electrode CNE on the (2-1)th electrode EL2_1. In the first area A1 of each pixel PXL, the (1-1)th electrode EL1_1, the contact electrode CNE positioned on the (1-1)th electrode EL1_1, the (2-1)th electrode EL2_1, and the contact electrode CNE positioned on the (2-1)th electrode EL2_1 may configure a first series stage SET1 together with the first light emitting element LD1 connected therebetween in the same direction (or in parallel).

[0253] The second light emitting element LD2 may be disposed between the (1-2)th electrode EL1_2 and the (2-2)th electrode EL2_2 in the second area A2. The second light emitting element LD2 may be disposed between the (1-2)th electrode EL1_2 and the (2-2)th electrode EL2_2 in the same direction. For example, one end (e.g., p-type semiconductor layer) of each of the second light emitting elements LD2 may be connected to the contact electrode CNE on the (1-2)th electrode EL1_2, and the other end (e.g., n-type semiconductor layer) may be connected to the (2-2)th electrode EL2_2. In the second area A2 of each pixel PXL, the (1-2)th electrode EL1_2, the contact electrode CNE positioned on the (1-2)th electrode EL1_2, the (2-2)th electrode EL2_2, and the contact electrode CNE positioned on the (2-2)th electrode EL2_2 may configure a second series stage SET2 together with the second light emitting element LD2 connected therebetween in the same direction (or in parallel).

[0254] In an embodiment of the present disclosure, the first series stage SET1 and the second series stage SET2 may be disposed in the pixel area PXA of each pixel PXL, and the first series stage SET1 and the second series stage SET2 may configure the emission unit EMU of the corresponding pixel PXL.

[0255] The light emitting element LD may be disposed and / or formed on the first insulating layer INS1.

[0256] The first insulating layer INS1 may be positioned under each of the light emitting elements LD disposed between the first electrode EL1 and the second electrode EL2. The first insulating layer INS1 may fill a space between each of the light emitting elements LD and the protective layer PSV to stably support the light emitting element LD and prevent the light emitting element LD from being separated from the protective layer PSV.

[0257] The first insulating layer INS1 may include an inorganic insulating layer formed of an inorganic material or an organic insulating layer formed of an organic material. In an embodiment of the present disclosure, the first insulating layer INS1 may be formed of an inorganic insulating layer that is beneficial to protecting the light emitting element LD from the influence of the pixel circuit layer PCL of each pixel PXL. For example, the first insulating layer INS1 may include silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ) and such as aluminum oxide (AlO x ), but the present disclosure is not limited thereto. According to an embodiment, the first insulating layer INS1 may be formed of an organic insulating layer that facilitates planarizing a support surface of the light emitting element LD.

[0258] The first insulating layer INS1 may include an opening OPN exposing a region of each of the first electrode EL1 and the second electrode EL2 . The first insulating layer INS1 may cover the remaining region except for the region.

[0259] The opening OPN may include a first opening OPN1 and a second opening OPN2. The first opening OPN1 may correspond to a region of the (1-1)th electrode EL1_1 in the first area A1, and may expose a region of the (1-1)th electrode EL1_1. The second opening OPN2 may correspond to a region of the (2-2)th electrode EL2_2 in the second area A2, and may expose a region of the (2-2)th electrode EL2_2. In an embodiment of the present disclosure, the first opening OPN1 may expose a region of the (1-1)th electrode EL1_1, which is an anode electrode of the emission unit EMU of the corresponding pixel PXL, to the outside, and the second opening OPN2 may expose a region of the (2-2)th electrode EL2_2, which may be a cathode electrode of the emission unit EMU, to the outside.

[0260] The (1-1)th electrode EL1_1 may directly contact the contact electrode CNE disposed on the (1-1)th electrode EL1_1 through the first opening OPN1 of the first insulating layer INS1, and the (2-2)th electrode EL2_2 may directly contact the contact electrode CNE disposed on the (2-2)th electrode EL2_2 through the second opening OPN2 of the first insulating layer INS1.

[0261] In an embodiment of the present disclosure, the first insulating layer INS1 may be disposed on the (2-1)th electrode EL2_1 in the first area A1 to cover the (2-1)th electrode EL2_1. The (2-1)th electrode EL2_1 may be completely covered by the first insulating layer INS1 to be electrically insulated from the contact electrode CNE disposed on the (2-1)th electrode EL2_1. In addition, the first insulating layer INS1 may be disposed on the (1-2)th electrode EL1_2 in the second area A2 to cover the (1-2)th electrode EL1_2. The (1-2)th electrode EL1_2 may be completely covered by the first insulating layer INS1 to be electrically insulated from the contact electrode CNE disposed on the (1-2)th electrode EL1_2.

[0262] The second insulating layer INS2 may be disposed and / or formed on each of the light emitting elements LD. The second insulating layer INS2 may be disposed and / or formed on each of the light emitting elements LD to cover a portion of the upper surface of each of the light emitting elements LD and expose both ends of each of the light emitting elements LD to the outside. The second insulating layer INS2 may be formed as an independent insulating pattern in the pixel area PXA of each of the pixels PXL, but the present disclosure is not limited thereto.

[0263] The second insulating layer INS2 may be configured as a single layer or a multilayer, and may include an inorganic insulating layer including at least one inorganic material or an organic insulating layer including at least one organic material. The second insulating layer INS2 may also be fixed to each of the light emitting elements LD aligned (or arranged) in the pixel area PXA of each of the pixels PXL. In an embodiment of the present disclosure, the second insulating layer INS2 may include an inorganic insulating layer that is beneficial to protecting the active layer 12 of each of the light emitting elements LD from external oxygen, moisture, etc. However, the present disclosure is not limited thereto. According to an embodiment, the second insulating layer INS2 may include an organic insulating layer including an organic material according to the design conditions of the display device to which the light emitting element LD may be applied, etc.

[0264] After the alignment of the light emitting element LD in the pixel area PXA of each of the pixels PXL can be completed, by forming the second insulating layer INS2 on the light emitting element LD, the light emitting element LD can be prevented from deviating from the alignment position. In the case where there is a gap (or space) between the first insulating layer INS1 and the light emitting element LD before the second insulating layer INS2 is formed, the gap can be filled with the second insulating layer INS2 in the process of forming the second insulating layer INS2. Therefore, the second insulating layer INS2 can be formed of an organic insulating layer that is conducive to filling the gap between the first insulating layer INS1 and the light emitting element LD.

[0265] In an embodiment of the present disclosure, a second insulating layer INS2 may be formed on the light emitting element LD so that the active layer 12 of each of the light emitting elements LD may not be in contact with an external conductive material. The second insulating layer INS2 may cover only a portion of the surface (or outer circumferential surface) of each of the light emitting elements LD, and may expose both ends of each of the light emitting elements LD to the outside.

[0266] The contact electrode CNE may be disposed and / or formed on the first electrode EL1 and the second electrode EL2. The contact electrode CNE may be a configuration for more stably electrically connecting each of the first electrode EL1 and the second electrode EL2 and the light emitting element LD.

[0267] The contact electrode CNE may include first to fourth contact electrodes CNE1 to CNE4 .

[0268] The first contact electrode CNE1 may be disposed and / or formed on the (1-1)th electrode EL1_1. Since a region of the (1-1)th electrode EL1_1 may be exposed by the first opening OPN1 of the first insulating layer INS1, the first contact electrode CNE1 may directly contact a region of the (1-1)th electrode EL1_1 through the first opening OPN1 to be connected to the (1-1)th electrode EL1_1. According to an embodiment, in the case where a capping layer (not shown) is disposed on a region of the (1-1)th electrode EL1_1 exposed by the first opening OPN1 of the first insulating layer INS1, the first contact electrode CNE1 may be disposed on the capping layer and may be connected to the (1-1)th electrode EL1_1 through the capping layer. Here, the capping layer may protect the (1-1)th electrode EL1_1 from defects generated during a manufacturing process of the display device, etc., and may also enhance the adhesive strength between the (1-1)th electrode EL1_1 and the pixel circuit layer PCL disposed thereunder. The capping layer may include a transparent conductive material such as indium zinc oxide (IZO) to minimize the loss of light emitted from each of the light emitting elements LD and reflected by the (1-1)th electrode EL1_1 in an image display direction of the display device.

[0269] The first contact electrode CNE1 may be positioned in the first area A1 of the pixel area PXA of each of the pixels PXL. The first contact electrode CNE1 may be directly disposed on one end (e.g., a p-type semiconductor layer) of each of the first light emitting elements LD1 to overlap the one end, and connected to the one end of each of the first light emitting elements LD1. Since the first contact electrode CNE1 directly contacts (or may be directly connected to) the (1-1)th electrode EL1_1, the signal of the driving transistor Tdr applied to the (1-1)th electrode EL1_1 may be transmitted to the first contact electrode CNE1. The signal transmitted to the first contact electrode CNE1 may be applied to the one end of each of the first light emitting elements LD1.

[0270] The second contact electrode CNE2 may be disposed and / or formed on the (2-1)th electrode EL2_1. In an embodiment of the present disclosure, the second contact electrode CNE2 may be disposed and / or formed on the (2-1)th electrode EL2_1, with the first insulating layer INS1 interposed therebetween. As described above, since the (2-1)th electrode EL2_1 may be completely covered by the first insulating layer INS1, the second contact electrode CNE2 may be electrically insulated from the (2-1)th electrode EL2_1. According to an embodiment, in the case where the capping layer is disposed on the (2-1)th electrode EL2_1, the first insulating layer INS1 may be disposed on the capping layer to completely cover the capping layer and the (2-1)th electrode EL2_1. In this case, the second contact electrode CNE2 may be electrically insulated from the (2-1)th electrode EL2_1 and the capping layer by the first insulating layer INS1.

[0271] In an embodiment of the present disclosure, the second contact electrode CNE2 may be positioned in the first area A1 of the pixel area PXA of the corresponding pixel PXL. The second contact electrode CNE2 may be directly disposed on the other end (e.g., the n-type semiconductor layer) of each of the first light emitting elements LD1 to overlap the other end, and may be connected to the other end of the first light emitting element LD1.

[0272] The first contact electrode CNE1 and the second contact electrode CNE2 may be formed of various transparent conductive materials (or substances) to allow light emitted from each of the first light emitting elements LD1 and reflected by the (1-1)th electrode EL1_1 and the (2-1)th electrode EL2_1 to travel without loss in the image display direction of the display device. For example, the first contact electrode CNE1 and the second contact electrode CNE2 may include at least one of various transparent conductive materials including indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), etc., and may be substantially transparent or translucent to meet a predetermined light transmittance (or transmittance). However, the materials of the first contact electrode CNE1 and the second contact electrode CNE2 are not limited to the above-mentioned embodiments. According to the embodiments, the first contact electrode CNE1 and the second contact electrode CNE2 may be formed of various opaque conductive materials. The opaque conductive material may include, for example, titanium (Ti), aluminum (Al), silver (Ag), etc., but the present disclosure is not limited thereto. In addition, the first contact electrode CNE1 and the second contact electrode CNE2 may be formed of a single layer or a plurality of layers.

[0273] The first contact electrode CNE1 and the second contact electrode CNE2 may be disposed on the same layer and may be formed by the same process. However, the present disclosure is not limited thereto, and according to an embodiment, the first contact electrode CNE1 and the second contact electrode CNE2 may be disposed on different layers and may be formed by different processes. In the case where the first contact electrode CNE1 and the second contact electrode CNE2 are disposed on different layers and are formed by different processes, such as Fig.13 As shown in , the auxiliary insulating layer AUINS may be disposed and / or formed between the first contact electrode CNE1 and the second contact electrode CNE2. The auxiliary insulating layer AUINS may be disposed on the first contact electrode CNE1 to cover the first contact electrode CNE1. At this time, the auxiliary insulating layer AUINS may include the same material as the first insulating layer INS1 and the second insulating layer INS2, or may include one or more materials selected from the materials disclosed as the configuration materials of the first insulating layer INS1 and the second insulating layer INS2. For example, the auxiliary insulating layer AUINS may be formed of an inorganic insulating layer including an inorganic material or an organic insulating layer including an organic material. As described above, in the case where the auxiliary insulating layer AUINS is disposed on the first contact electrode CNE1, the second contact electrode CNE2 may be disposed on the auxiliary insulating layer AUINS.

[0274] The third contact electrode CNE3 may be disposed and / or formed on the (1-2)th electrode EL1_2. In an embodiment of the present disclosure, the third contact electrode CNE3 may be disposed and / or formed on the (1-2)th electrode EL1_2, with the first insulating layer INS1 interposed therebetween. As described above, since the (1-2)th electrode EL1_2 may be completely covered by the first insulating layer INS1, the third contact electrode CNE3 may be electrically insulated from the (1-2)th electrode EL1_2. According to an embodiment, in the case where the capping layer is disposed on the (1-2)th electrode EL1_2, the first insulating layer INS1 may be disposed on the capping layer to completely cover the capping layer and the (1-2)th electrode EL1_2. In this case, the third contact electrode CNE3 may be electrically insulated from the (1-2)th electrode EL1_2 and the capping layer by the first insulating layer INS1.

[0275] In an embodiment of the present disclosure, the third contact electrode CNE3 may be positioned in the second area A2 of the pixel area PXA of the corresponding pixel PXL. The third contact electrode CNE3 may be directly disposed on one end (e.g., p-type semiconductor layer) of each of the second light emitting elements LD2 to overlap with the one end and be connected to the one end of each of the second light emitting elements LD2.

[0276] The fourth contact electrode CNE4 may be disposed and / or formed on the (2-2)th electrode EL2_2. Since a region of the (2-2)th electrode EL2_2 may be exposed by the second opening OPN2 of the first insulating layer INS1, the fourth contact electrode CNE4 may directly contact a region of the (2-2)th electrode EL2_2 through the second opening OPN2 to be electrically and / or physically connected to the (2-2)th electrode EL2_2. According to an embodiment, in the case where the capping layer is disposed on a region of the (2-2)th electrode EL2_2 exposed by the second opening OPN2 of the first insulating layer INS1, the fourth contact electrode CNE4 may be disposed on the capping layer to be electrically and / or physically connected to the (2-2)th electrode EL2_2 through the capping layer.

[0277] The fourth contact electrode CNE4 may be positioned in the second area A2 of the pixel area PXA of each of the pixels PXL. The fourth contact electrode CNE4 may be directly disposed on the other end (e.g., the n-type semiconductor layer) of each of the second light emitting elements LD2 to overlap the other end, and connected to the other end of each of the second light emitting elements LD2. Since the fourth contact electrode CNE4 directly contacts (or may be directly connected to) the (2-2)th electrode EL2_2, the second driving power VSS applied to the (2-2)th electrode EL2_2 may be transmitted to the fourth contact electrode CNE4. The second driving power VSS transmitted to the fourth contact electrode CNE4 may be applied to the other end of each of the second light emitting elements LD2.

[0278] The third contact electrode CNE3 and the fourth contact electrode CNE4 may be formed of various transparent conductive materials (or substances) to allow light emitted from each of the second light emitting elements LD2 and reflected by the (1-2)th electrode EL1_2 and the (2-2)th electrode EL2_2 to travel without loss in the image display direction of the display device. In an embodiment of the present disclosure, the third contact electrode CNE3 and the fourth contact electrode CNE4 may include the same material as the first contact electrode CNE1 and the second contact electrode CNE2, and may be formed by the same process as the first contact electrode CNE1 and the second contact electrode CNE2.

[0279] When viewed in a plan view, each of the first to fourth contact electrodes CNE1 to CNE4 may have a rod shape extending along the second direction DR2, but the present disclosure is not limited thereto. According to an embodiment, the shapes of the first to fourth contact electrodes CNE1 to CNE4 may be variously changed within a range of being stably electrically connected to each of the light emitting elements LD. In addition, the shape of each of the first to fourth contact electrodes CNE1 to CNE4 may be variously changed according to a connection relationship with an electrode disposed thereunder.

[0280] In the pixel area PXA of each of the pixels PXL, the first contact electrode CNE1 positioned in the first area A1 and the third contact electrode CNE3 positioned in the second area A2 may be disposed to be spaced apart at a constant distance in the second direction DR2. For example, the first contact electrode CNE1 and the third contact electrode CNE3 may be disposed in the same column along the second direction DR2 and may be spaced apart from each other. According to an embodiment, the first contact electrode CNE1 and the third contact electrode CNE3 may be positioned in columns different from each other within a range in which a spatial limitation according to a density degree of a configuration positioned in the pixel area PXA of each of the pixels PXL may be considered while maintaining a state in which the first contact electrode CNE1 and the third contact electrode CNE3 may be spaced apart from each other to be electrically insulated from each other.

[0281] In the pixel area PXA of each of the pixels PXL, the second contact electrode CNE2 positioned in the first area A1 and the fourth contact electrode CNE4 positioned in the second area A2 may be disposed to be spaced apart at a constant distance in the second direction DR2. For example, the second contact electrode CNE2 and the fourth contact electrode CNE4 may be positioned in the same column along the second direction DR2 and may be disposed to be spaced apart from each other. However, the present disclosure is not limited thereto, and the second contact electrode CNE2 and the fourth contact electrode CNE4 may be positioned in different columns.

[0282] The first and second contact electrodes CNE1 and CNE2 may configure a first series stage SET1 together with the first light emitting element LD1 and the (1-1)th and (2-1)th electrodes EL1_1 and EL2_1. The third and fourth contact electrodes CNE3 and CNE4 may configure a second series stage SET2 together with the second light emitting element LD2 and the (1-2)th and (2-2)th electrodes EL1_2 and EL2_2.

[0283] Meanwhile, the second contact electrode CNE2 disposed in the first series stage SET1 may be electrically and / or physically connected to the third contact electrode CNE3 disposed in the second series stage SET2 through the intermediate electrode CTE. The intermediate electrode CTE may be positioned between the first series stage SET1 and the second series stage SET2, and may be connected to the second contact electrode CNE2 of the first series stage SET1 and the third contact electrode CNE3 of the second series stage SET2.

[0284] In an embodiment of the present disclosure, the intermediate electrode CTE may be disposed between the first area A1 and the second area A2 so as not to overlap with the first opening OPN1 and the second opening OPN2 of the first insulating layer INS1. In particular, the intermediate electrode CTE may be electrically and / or physically connected to the contact electrode CNE electrically insulated from the corresponding electrode by the first insulating layer INS1. For example, the intermediate electrode CTE may be electrically and / or physically connected to the second contact electrode CNE2 on the (2-1)th electrode EL2_1 covered by the first insulating layer INS1. In addition, the intermediate electrode CTE may be electrically and / or physically connected to the third contact electrode CNE3 on the (1-2)th electrode EL1_2 covered by the first insulating layer INS1.

[0285] When viewed in a plan view, the intermediate electrode CTE may be disposed throughout a first region A1 where the first series stage SET1 may be located and a second region A2 where the second series stage SET2 may be located, and may overlap a portion of each of the first electrode EL1 and the second electrode EL2. The intermediate electrode CTE may be an electrode to which a predetermined signal (or voltage) may not be directly transmitted from the outside.

[0286] One end of the intermediate electrode CTE may be connected to the second contact electrode CNE2 in the first area A1, and the other end thereof may be connected to the third contact electrode CNE3 in the second area A2. Therefore, the intermediate electrode CTE may function as a bridging electrode (or connecting electrode) connecting the second contact electrode CNE2 of the first area A1 and the third contact electrode CNE3 of the second area A2 to each other. That is, the intermediate electrode CTE may be a bridging electrode (or connecting electrode) connecting the first series stage SET1 and the second series stage SET2.

[0287] The intermediate electrode CTE may be disposed on the same layer as the second contact electrode CNE2 and / or the third contact electrode CNE3, may include the same material as the second contact electrode CNE2 and / or the third contact electrode CNE3, and may be formed by the same process as the second contact electrode CNE2 and / or the third contact electrode CNE3. In an embodiment of the present disclosure, the intermediate electrode CTE may be formed integrally with the second contact electrode CNE2 and / or the third contact electrode CNE3. In the case where the intermediate electrode CTE is integrally disposed with the second contact electrode CNE2 and / or the third contact electrode CNE3, the intermediate electrode CTE may be considered as a region of the second contact electrode CNE2 and / or a region of the third contact electrode CNE3.

[0288] As described above, the intermediate electrode CTE, the second contact electrode CNE2, and the third contact electrode CNE3 may be integrally formed and may be electrically and / or physically connected to each other. Therefore, the first series stage SET1 and the second series stage SET2 of each pixel PXL may be electrically and / or physically connected to each other.

[0289] The intermediate electrode CTE may be disposed throughout the first region A1 and the second region A2 and may have a rod shape bent at least once. However, the shape of the intermediate electrode CTE is not limited to the above-described embodiment. According to the embodiment, the intermediate electrode CTE may be changed to various shapes within the range for stably connecting two consecutive series stages.

[0290] The third insulating layer INS3 may be disposed and / or formed on the first to fourth contact electrodes CNE1 to CNE4 and the intermediate electrode CTE. The third insulating layer INS3 may be an inorganic insulating layer including an inorganic material or an organic insulating layer including an organic material. For example, the third insulating layer INS3 may have a structure in which at least one inorganic insulating layer or at least one organic insulating layer may be alternately stacked. The third insulating layer INS3 may be an encapsulation layer that completely covers the display element layer DPL and blocks water, moisture, etc. from being input to the display element layer DPL including the light emitting element LD.

[0291] like Fig.15 As shown in FIG. 1 , when a driving current flows from the first power line PL1 to the driving voltage line DVL through the driving transistor Tdr of the pixel circuit layer PCL included in each pixel PXL, the driving current may flow into the emission unit EMU of each pixel PXL through the first contact hole CH1 .

[0292] For example, a driving current may be supplied to the (1-1)th electrode EL1_1 through the first contact hole CH1, and the driving current may flow to the second contact electrode CNE2 via the first light emitting element LD1 through the first contact electrode CNE1 that is in direct contact with (or may be connected to) the (1-1)th electrode EL1_1. Therefore, in the first series stage SET1, the first light emitting element LD1 may emit light having a brightness corresponding to the current distributed to each of the first light emitting elements LD1. At this time, the second contact electrode CNE2 may be electrically insulated from the (2-1)th electrode EL2_1 disposed thereunder by the first insulating layer INS1.

[0293] The driving current flowing to the second contact electrode CNE2 flows to the third contact electrode CNE3 via the intermediate electrode CTE. The driving current flowing to the third contact electrode CNE3 flows to the fourth contact electrode CNE4 via the second light emitting element LD2. The driving current flowing to the fourth contact electrode CNE4 may flow to the (2-2)th electrode EL2_2 that is in direct contact with (or may be connected to) the fourth contact electrode CNE4. Therefore, the second light emitting element LD2 may emit light with a brightness corresponding to the current distributed to each of the second light emitting elements LD2. At this time, the third contact electrode CNE3 may be electrically insulated from the (1-2)th electrode EL1_2 disposed thereunder by the first insulating layer INS1.

[0294] In the above method, the driving current of each pixel PXL may sequentially flow through the first light emitting element LD1 of the first series stage SET1 and the second light emitting element LD2 of the second series stage SET2. Therefore, each pixel PXL may emit light with brightness corresponding to the data signal supplied during each frame period.

[0295] In an embodiment of the present disclosure, after aligning the light emitting element LD in the pixel area PXA of each of the pixels PXL, each of the first to fourth contact electrodes CNE1 to CNE4 can be used as a driving electrode for driving the light emitting element LD together with the (1-1) electrode EL1_1 of the first series stage SET1 and the (2-2) electrode EL2_2 of the second series stage SET2.

[0296] In the embodiment of the present disclosure, in the step of forming the second contact electrode CNE2 of the first series stage SET1 and the third contact electrode CNE3 of the second series stage SET2, the intermediate electrode CTE for serially connecting the first light emitting element LD1 of the first series stage SET1 and the second light emitting element LD2 of the second series stage SET2 can be simultaneously formed. Therefore, the manufacturing process of each pixel PXL and the display device including the same can be simplified, and thus the product productivity can be improved.

[0297] According to the above-described embodiment, the pixel region PXA of each of the pixels PXL may be divided into a first region A1 and a second region A2 in one direction (e.g., a second direction DR2), and the intermediate electrode CTE may be disposed between the first region A1 and the second region A2 to connect two consecutive series stages in the pixel region PXA. The light-emitting elements LD included in each of the two consecutive series stages may be electrically connected to each other through the intermediate electrode CTE. For example, the first light-emitting element LD1 included in the first series stage SET1 and the second light-emitting element LD2 included in the second series stage SET2 may be electrically connected to each other through the intermediate electrode CTE. In this method, the light-emitting elements LD aligned in the pixel region PXA of each of the pixels PXL may be connected in a series-parallel hybrid structure to configure the emission unit EMU of each pixel PXL. Therefore, the emission unit EMU of each pixel PXL may be configured as a series-parallel hybrid structure without increasing the number of alignment electrodes (or alignment lines). In this case, the emission unit EMU can be configured as a series-parallel hybrid structure including two or more series stages without increasing the number of alignment electrodes (or alignment lines) in each pixel PXL (or minimizing the area occupied by the alignment electrodes), and thus a display device with high resolution and fine pitch can be easily realized.

[0298] In a display device for achieving high resolution and fine pitch, the size (area) of each pixel PXL can be reduced, and therefore it may be difficult to connect multiple series stages by increasing the number of alignment electrodes (or alignment lines) due to space limitations between configurations included in each pixel PXL, for example, a critical dimension (CD) of an electrode included in each pixel PXL ("a line width of each of the electrodes or a width of a gap between electrodes").

[0299] Therefore, in the present disclosure, by setting an intermediate electrode CTE between the consecutive first series stage SET1 and the second series stage SET2, directly connecting the (1-1) electrode EL1_1 of the first series stage SET1 to the first contact electrode CNE1, directly connecting the (2-2) electrode EL2_2 of the second series stage SET2 to the fourth contact electrode CNE4, and covering the (2-1) electrode EL2_1 of the first series stage SET1 and the (1-2) electrode EL1_2 of the second series stage SET2 with the first insulating layer INS1, the emission unit EMU of each pixel PXL can be configured into a series-parallel hybrid structure without increasing the number of alignment electrodes (or alignment lines).

[0300] According to the above-described embodiment, by configuring the emission unit EMU of the series-parallel hybrid structure, each pixel PXL can be stably driven to reduce the driving current flowing through the display panel of the display device, thereby improving power consumption efficiency.

[0301] In addition, according to the above embodiment, since each of a region of the first electrode EL1 (for example, the (1-2)th electrode EL1_2) and a region of the second electrode EL2 (for example, the (2-1)th electrode EL2_1) can be covered by the first insulating layer INS1, the region of the first electrode EL1 and the region of the second electrode EL2 can be unaffected by static electricity input from the outside.

[0302] Figures 16a to 16g It is shown in sequence that the manufacturing Figure 8 A schematic plan view of a pixel PXL method shown in FIG. Figures 17a to 17h It is shown in sequence that the manufacturing Fig.10 A schematic cross-sectional view of a pixel PXL is shown in FIG.

[0303] In the following, according to the manufacturing method combined Figures 16a to 16g as well as Figures 17a to 17h Describe in turn according to Figure 8 and Fig.10 The pixel PXL of the embodiment shown in FIG. Figures 16a to 16g as well as Figures 17a to 17h In the embodiment, the differences from the above-mentioned embodiment are mainly described to avoid redundant description.

[0304] refer to Figures 1a to 5 , Figure 7b , Figures 8 to 16a and Fig.17a , a pixel circuit layer PCL may be formed on the substrate SUB.

[0305] The pixel circuit layer PCL may include a buffer layer BFL, a transistor T, a storage capacitor Cst, a first power line PL1, a driving voltage line DVL, and a protection layer PSV. The protection layer PSV may include a first contact hole CH1 exposing a region of the driving transistor Tdr and a second contact hole CH2 exposing a region of the driving voltage line DVL.

[0306] refer to Figures 1a to 5 , Figure 7b , Figures 8 to 15 , Fig.16b , Fig.17a and Fig.17b , a first bank pattern BNK1 may be formed on the protection layer PSV. On the protection layer PSV, the first bank pattern BNK1 may be spaced apart from a first bank pattern BNK1 adjacent in the first direction DR1 by a predetermined distance.

[0307] refer to Figures 1a to 5 , Figure 7b , Figures 8 to 15 , Fig.16c and Figures 17a to 17c , a first electrode EL1 and a second electrode EL2 including a conductive material (or substance) having high reflectivity may be formed on the first bank pattern BNK1.

[0308] The first electrode EL1 may be divided into a (1-1)th electrode EL1_1 positioned in the first area A1 of the pixel area PXA of each pixel PXL and a (1-2)th electrode EL1_2 positioned in the second area A2 of the pixel area PXA. The second electrode EL2 may be divided into a (2-1)th electrode EL2_1 positioned in the first area A1 and a (2-2)th electrode EL2_2 positioned in the second area A2. The first electrode EL1 may be electrically and / or physically connected to the driving transistor Tdr through the first contact hole CH1. The second electrode EL2 may be electrically and / or physically connected to the driving voltage line DVL through the second contact hole CH2.

[0309] Each of the first electrode EL1 and the second electrode EL2 may extend along the second direction DR2 .

[0310] refer to Figures 1a to 5 , Figure 7b , Figures 8 to 15 , Fig.16d and Figures 17a to 17d , an insulating material layer INSM may be formed on the protective layer PSV including the first electrode EL1 and the second electrode EL2. The insulating material layer INSM may be an inorganic insulating layer including an inorganic material or an organic insulating layer including an organic material.

[0311] Subsequently, a second bank pattern BNK2 may be formed in the pixel area PXA of each pixel PXL. The second bank pattern BNK2 may be formed on the insulating material layer INSM. The second bank pattern BNK2 may be a pixel defining layer that defines (or separates) the pixel area PXA (or emission area) between each pixel PXL and the pixel PXL adjacent thereto.

[0312] refer to Figures 1a to 5 , Figure 7b , Figures 8 to 15 , Fig.16e and Figures 17a to 17e , an alignment signal (or an alignment voltage) corresponding to each of the first electrode EL1 and the second electrode EL2 may be applied to form an electric field between the first electrode EL1 and the second electrode EL2 adjacent to each other in the first direction DR1.

[0313] Subsequently, in a state in which an electric field may be formed between the first electrode EL1 and the second electrode EL2, a mixed solution including the light emitting element LD may be input to the pixel region PXA of each of the pixels PXL using an inkjet printing method or the like. For example, an inkjet nozzle may be provided on the insulating material layer INSM, and a solvent mixed with a plurality of light emitting elements LD may be input to the pixel region PXA of each of the pixels PXL through the inkjet nozzle. The method of inputting the light emitting element LD to the pixel region PXA of each of the pixels PXL is not limited to the above-described embodiment, and the method of inputting the light emitting element LD may be variously changed.

[0314] After the light emitting element LD is input to the pixel area PXA of each of the pixels PXL, the solvent may be removed.

[0315] In the case where the light emitting element LD is input to the pixel area PXA of each of the pixels PXL, self-alignment can be induced by the electric field formed between the first electrode EL1 and the second electrode EL2. Therefore, the light emitting element LD can be aligned between the first electrode EL1 and the second electrode EL2. In an embodiment of the present disclosure, the light emitting element LD can be divided into a first light emitting element LD1 and a second light emitting element LD2 according to the positions of the first area A1 and the second area A2 of the pixel area PXA of each of the pixels PXL. For example, the light emitting element LD positioned in the first area A1 of the pixel area PXA may be the first light emitting element LD1, and the light emitting element LD positioned in the second area A2 of the pixel area PXA may be the second light emitting element LD2.

[0316] The first and second light emitting elements LD1 and LD2 may be aligned on the insulating material layer INSM between the first and second electrodes EL1 and EL2 in the pixel area PXA of each of the pixels PXL.

[0317] refer to Figures 1a to 5 , Figure 7b , Figures 8 to 15 , Fig.16f and Figures 17a to 17f After aligning the light emitting element LD in the pixel area PXA of each pixel PXL, a second insulating layer INS2 may be formed on each light emitting element LD. The second insulating layer INS2 may cover at least a portion of the upper surface of each of the light emitting elements LD to expose both ends of each of the light emitting elements LD except the active layer 12 to the outside.

[0318] The first insulating layer INS1 including a first opening OPN1 exposing a portion of the (1-1)th electrode EL1_1 and a second opening OPN2 exposing a portion of the (2-2)th electrode EL2_2 can be formed by removing a portion of the insulating material layer INSM through a process of forming the second insulating layer INS2, an etching process performed before and after the process of forming the second insulating layer INS2, and the like.

[0319] The first insulating layer INS1 may cover each of the (1-2)th electrode EL1_2 and the (2-1)th electrode EL2_1. Therefore, the (1-2)th electrode EL1_2 and the (2-1)th electrode EL2_1 may be electrically insulated from a configuration disposed on the first insulating layer INS1.

[0320] In the case of performing the process of forming the first insulating layer INS1 and the second insulating layer INS2, a portion of the first electrode EL1 may be removed so that each pixel PXL may be driven independently (or separately) from the pixel PXL adjacent thereto. Therefore, the first electrode EL1 provided to each pixel PXL may be electrically and / or physically separated from the first electrode EL1 provided to the adjacent pixel PXL positioned in the same pixel column.

[0321] refer to Figures 1a to 5 , Figure 7b , Figures 8 to 15 , Figure 16g and Figures 17a to 17g , first to fourth contact electrodes CNE1 to CNE4 and an intermediate electrode CTE may be formed on the second insulating layer INS2 .

[0322] The first contact electrode CNE1 may be formed on the (1-1)th electrode EL1_1 and may be connected to one end of each of the (1-1)th electrode EL1_1 and the first light emitting element LD1. The second contact electrode CNE2 may be formed on the first insulating layer INS1 on the (2-1)th electrode EL2_1 and may be connected to the other end of each of the first light emitting element LD1. The third contact electrode CNE3 may be formed on the first insulating layer INS1 on the (1-2)th electrode EL1_2 and may be connected to one end of each of the second light emitting element LD2. The fourth contact electrode CNE4 may be formed on the (2-2)th electrode EL2_2 and may be connected to the other end of each of the (2-2)th electrode EL2_2 and the second light emitting element LD2.

[0323] The first contact electrode CNE1 and the second contact electrode CNE2 may be positioned in the first area A1 of the pixel area PXA of each of the pixels PXL, and the third contact electrode CNE3 and the fourth contact electrode CNE4 may be positioned in the second area A2 of the pixel area PXA of each of the pixels PXL. The first contact electrode CNE1 and the second contact electrode CNE2 may configure a first series stage SET1 together with the (1-1)th electrode EL1_1, the (2-1)th electrode EL2_1, and the first light emitting element LD1. The third contact electrode CNE3 and the fourth contact electrode CNE4 may configure a second series stage SET2 together with the (1-2)th electrode EL1_2, the (2-2)th electrode EL2_2, and the second light emitting element LD2.

[0324] The intermediate electrode CTE may be integrally provided with the second contact electrode CNE2 and / or the third contact electrode CNE3 to electrically and / or physically connect the second contact electrode CNE2 and the third contact electrode CNE3 to each other. In an embodiment of the present disclosure, the intermediate electrode CTE may electrically and / or physically connect the second contact electrode CNE2 of the first series stage SET1 and the third contact electrode CNE3 of the second series stage SET2 to each other to connect the first series stage SET1 and the second series stage SET2.

[0325] refer to Figures 1a to 5 , Figure 7b , Figures 8 to 15 and Figures 17a to 17h , a third insulating layer INS3 covering the first to fourth contact electrodes CNE1 to CNE4 may be formed. The third insulating layer INS3 may have a structure in which at least one inorganic layer and at least one organic layer are alternately stacked, but the present disclosure is not limited thereto.

[0326] Figures 18a to 18cA pixel PXL according to another embodiment of the present disclosure is schematically illustrated, and is a schematic plan view of the pixel PXL including only a partial configuration of the display element layer DPL.

[0327] about Figures 18a to 18c The pixel PXL of the embodiment described above is different from the above embodiment to avoid redundant description. Parts not specifically described in the present disclosure may be consistent with the above embodiment, and the same reference numerals indicate the same components.

[0328] First, refer to Figures 1a to 5 , Figure 7b and Fig.18a , when viewed in a plan view, the pixel area PXA of each pixel PXL may be divided into first to third areas A1 to A3 sequentially disposed along the second direction DR2. The first area A1 may be an area positioned at the upper side of the pixel area PXA along the second direction DR2, the second area A2 may be an area positioned at the center (or middle) of the pixel area PXA along the second direction DR2, and the third area A3 may be an area positioned at the lower side of the pixel area PXA along the second direction DR2.

[0329] In this case, each of the first electrode EL1 and the second electrode EL2 may be divided into three regions according to the positions of the first region A1 to the third region A3. For example, a region of the first electrode EL1 positioned in the first region A1 may be the (1-1)th electrode EL1_1, another region of the first electrode EL1 positioned in the second region A2 may be the (1-2)th electrode EL1_2, and another region of the first electrode EL1 positioned in the third region A3 may be the (1-3)th electrode EL1_3. In addition, a region of the second electrode EL2 positioned in the first region A1 may be the (2-1)th electrode EL2_1, another region of the second electrode EL2 positioned in the second region A2 may be the (2-2)th electrode EL2_2, and another region of the second electrode EL2 positioned in the third region A3 may be the (2-3)th electrode EL2_3.

[0330] In the first area A1, the (1-1)th electrode EL1_1 and the (2-1)th electrode EL2_1 may be spaced apart from each other in the first direction DR1. In the second area A2, the (1-2)th electrode EL1_2 and the (2-2)th electrode EL2_2 may be spaced apart from each other in the first direction DR1. In the third area A3, the (1-3)th electrode EL1_3 and the (2-3)th electrode EL2_3 may be spaced apart from each other in the first direction DR1.

[0331] The (1-1)th electrode EL1_1 positioned in the first area A1 may be electrically and / or physically connected to the first transistor T1 of the pixel circuit 144 through the first contact hole CH1, and the (2-3)th electrode EL2_3 positioned in the third area A3 may be electrically and / or physically connected to the second power line PL2 of the pixel circuit 144 through the second contact hole CH2.

[0332] In the first area A1, a region of the (1-1)th electrode EL1_1 may be exposed to the outside through the first opening OPN1 of the first insulating layer INS1. The first contact electrode CNE1 may be disposed on the (1-1)th electrode EL1_1, a region of which may be exposed to the outside, and thus, the (1-1)th electrode EL1_1 and the first contact electrode CNE1 may be in direct contact to be electrically and / or physically connected to each other. In the first area A1, the (2-1)th electrode EL2_1 may be covered by the first insulating layer INS1. The second contact electrode CNE2 may be disposed on the first insulating layer INS1 on the (2-1)th electrode EL2_1. The (2-1)th electrode EL2_1 and the second contact electrode CNE2 may be electrically insulated by the first insulating layer INS1 disposed therebetween.

[0333] In the first area A1, at least one first light emitting element LD1 may be aligned between the (1-1)th electrode EL1_1 and the (2-1)th electrode EL2_1. One end of the first light emitting element LD1 may be electrically and / or physically connected to one of the first contact electrode CNE1 and the second contact electrode CNE2, and the other end of the first light emitting element LD1 may be electrically and / or physically connected to the other of the first contact electrode CNE1 and the second contact electrode CNE2.

[0334] In an embodiment of the present disclosure, the (1-1)th and (2-1)th electrodes EL1_1 and EL2_1 , the first and second contact electrodes CNE1 and CNE2 , and the first light emitting element LD1 positioned in the first area A1 may configure a first series stage SET1 .

[0335] In the second area A2, the (1-2)th electrode EL1_2 may be covered by the first insulating layer INS1. The third contact electrode CNE3 may be disposed on the first insulating layer INS1 on the (1-2)th electrode EL1_2. The (1-2)th electrode EL1_2 and the third contact electrode CNE3 may be electrically insulated by the first insulating layer INS1. In the second area A2, the (2-2)th electrode EL2_2 may be covered by the first insulating layer INS1. The fourth contact electrode CNE4 may be disposed on the first insulating layer INS1 on the (2-2)th electrode EL2_2. The (2-2)th electrode EL2_2 and the fourth contact electrode CNE4 may be electrically insulated by the first insulating layer INS1.

[0336] In the second area A2, at least one second light emitting element LD2 may be aligned between the (1-2)th electrode EL1_2 and the (2-2)th electrode EL2_2. One end of the second light emitting element LD2 may be electrically and / or physically connected to one of the third contact electrode CNE3 and the fourth contact electrode CNE4, and the other end of the second light emitting element LD2 may be electrically and / or physically connected to the other of the third contact electrode CNE3 and the fourth contact electrode CNE4.

[0337] In an embodiment of the present disclosure, the (1-2)th and (2-2)th electrodes EL1_2 and EL2_2 , the third and fourth contact electrodes CNE3 and CNE4 , and the second light emitting element LD2 may configure a second series stage SET2 .

[0338] The first intermediate electrode CTE1 may be disposed between the first area A1 and the second area A2. The first intermediate electrode CTE1 may be disposed throughout the first area A1 and the second area A2. One end of the first intermediate electrode CTE1 may be electrically and / or physically connected to the second contact electrode CNE2, and the other end of the first intermediate electrode CTE1 may be electrically and / or physically connected to the third contact electrode CNE3. The first intermediate electrode CTE1 may be integrally disposed with the second contact electrode CNE2 and / or the third contact electrode CNE3. Therefore, the second contact electrode CNE2 and the third contact electrode CNE3 may be electrically and / or physically connected to each other through the first intermediate electrode CTE1.

[0339] In an embodiment of the present disclosure, the first intermediate electrode CTE1 may be a first bridging electrode (or a first connection electrode) electrically connecting the first series stage SET1 and the second series stage SET2 .

[0340] In the third area A3, the (1-3)th electrode EL1_3 may be covered by the first insulating layer INS1. The fifth contact electrode CNE5 may be disposed on the first insulating layer INS1 on the (1-3)th electrode EL1_3. The (1-3)th electrode EL1_3 and the fifth contact electrode CNE5 may be electrically insulated by the first insulating layer INS1. One region of the (2-3)th electrode EL2_3 may be exposed to the outside through the second opening OPN2 of the first insulating layer INS1. The sixth contact electrode CNE6 may be disposed on the (2-3)th electrode EL2_3, one region of which may be exposed to the outside, and therefore, the (2-3)th electrode EL2_3 and the sixth contact electrode CNE6 may be in direct contact to be electrically and / or physically connected to each other.

[0341] In the third area A3, at least one third light emitting element LD3 may be aligned between the (1-3)th electrode EL1_3 and the (2-3)th electrode EL2_3. One end of the third light emitting element LD3 may be electrically and / or physically connected to one of the fifth contact electrode CNE5 and the sixth contact electrode CNE6, and the other end of the third light emitting element LD3 may be electrically and / or physically connected to the other of the fifth contact electrode CNE5 and the sixth contact electrode CNE6.

[0342] In an embodiment of the present disclosure, the (1-3)th and (2-3)th electrodes EL1_3 and EL2_3, the fifth and sixth contact electrodes CNE5 and CNE6, and the third light emitting element LD3 may configure a third series stage.

[0343] The second intermediate electrode CTE2 may be disposed between the second area A2 and the third area A3. The second intermediate electrode CTE2 may be disposed throughout the second area A2 and the third area A3. One end of the second intermediate electrode CTE2 may be electrically and / or physically connected to the fourth contact electrode CNE4, and the other end of the second intermediate electrode CTE2 may be electrically and / or physically connected to the fifth contact electrode CNE5. The second intermediate electrode CTE2 may be integrally disposed with the fourth contact electrode CNE4 and / or the fifth contact electrode CNE5. Therefore, the fourth contact electrode CNE4 and the fifth contact electrode CNE5 may be electrically and / or physically connected to each other through the second intermediate electrode CTE2.

[0344] In an embodiment of the present disclosure, the second intermediate electrode CTE2 may be a second bridging electrode (or a second connection electrode) connecting the second series stage SET2 and the third series stage.

[0345] One region of the first electrode EL1 that may be exposed by the first opening OPN1 of the first insulating layer INS1 to directly contact the first contact electrode CNE1 (e.g., the (1-1)th electrode EL1_1) may be an anode electrode of the emission unit EMU of each pixel PXL. In addition, another region of the second electrode EL2 that may be exposed by the second opening OPN2 of the first insulating layer INS1 to directly contact the sixth contact electrode CNE6 (e.g., the (2-3)th electrode EL2_3) may be a cathode electrode of the emission unit EMU.

[0346] In the case where the driving current flows from the first power line PL1 to the second power line PL2 through the first transistor T1, the driving current flows to the (1-1)th electrode EL1_1 and the first contact electrode CNE1 through the first contact hole CH1, and the driving current flows to the second contact electrode CNE2 via the first light emitting element LD1. The driving current flowing to the second contact electrode CNE2 flows to the third contact electrode CNE3 through the first intermediate electrode CTE1, and the driving current flows to the fourth contact electrode CNE4 via the second light emitting element LD2. The driving current flowing to the fourth contact electrode CNE4 flows to the fifth contact electrode CNE5 through the second intermediate electrode CTE2. The driving current flowing to the fifth contact electrode CNE5 flows to the (2-3)th electrode EL2_3 and the sixth contact electrode CNE6 via the third light emitting element LD3.

[0347] As described above, by setting an intermediate electrode CTE between consecutive series stages, directly connecting the (1-1)th electrode EL1_1 of the first series stage SET1 to the first contact electrode CNE1, directly connecting the (2-3)th electrode EL2_3 of the third series stage to the sixth contact electrode CNE6, and covering the (2-1)th electrode EL2_1, the (1-2)th electrode EL1_2, the (2-2)th electrode EL2_2 and the (1-3)th electrode EL1_3 with the first insulating layer INS1, the emission unit EMU of each pixel PXL can be configured into a series-parallel hybrid structure without increasing the number of alignment electrodes.

[0348] Next, refer to Figures 1a to 5 and Fig.18b , the first to third electrodes EL1 to EL3 may be disposed in the pixel area PXA of each pixel PXL.

[0349] In an embodiment of the present disclosure, the pixel area PXA of each pixel PXL may include a first emission area E1 and a second emission area E2. The first electrode EL1, the second electrode EL2, and the light emitting element LD aligned between the first electrode EL1 and the second electrode EL2 may be disposed in the first emission area E1. The third electrode EL3, the second electrode EL2, and the light emitting element LD aligned between the third electrode EL3 and the second electrode EL2 may be disposed in the second emission area E2. The second electrode EL2 may be disposed between the first emission area E1 and the second emission area E2, and the second electrode EL2 may be disposed in common.

[0350] When viewed in a plan view, each of the first emission region E1 and the second emission region E2 may be divided into first to third regions A1 to A3 along the second direction DR2.

[0351] In this case, each of the first to third electrodes EL1 to EL3 may be divided into three regions according to the position of the first to third regions A1 to A3 of each of the first emission region E1 and the second emission region E2. The first electrode EL1 may be divided into the (1-1)th electrode EL1_1 of the first region A1, the (1-2)th electrode EL1_2 of the second region A2, and the (1-3)th electrode EL1_3 of the third region A3. The second electrode EL2 may be divided into the (2-1)th electrode EL2_1 of the first region A1, the (2-2)th electrode EL2_2 of the second region A2, and the (2-3)th electrode EL2_3 of the third region A3. The third electrode EL3 may be divided into the (3-1)th electrode EL3_1 positioned in the first region A1, the (3-2)th electrode EL3_2 positioned in the second region A2, and the (3-3)th electrode EL3_3 positioned in the third region A3.

[0352] In the first area A1, the (1-1)th electrode EL1_1, the (2-1)th electrode EL2_1, and the (3-1)th electrode EL3_1 may be spaced apart from each other in the first direction DR1. In the second area A2, the (1-2)th electrode EL1_2, the (2-2)th electrode EL2_2, and the (3-2)th electrode EL3_2 may be spaced apart from each other in the first direction DR1. In the third area A3, the (1-3)th electrode EL1_3, the (2-3)th electrode EL2_3, and the (3-3)th electrode EL3_3 may be spaced apart from each other in the first direction DR1.

[0353] The (1-1)th electrode EL1_1 positioned in the first area A1 may be electrically and / or physically connected to the first transistor T1 of each pixel PXL through the first contact hole CH1, and the (3-1)th electrode EL3_1 positioned in the first area A1 may be electrically and / or physically connected to the first transistor T1 through the third contact hole CH3. The (2-3)th electrode EL2_3 positioned in the third area A3 may be electrically and / or physically connected to the second power line PL2 through the second contact hole CH2.

[0354] In the first area A1 of the first emission region E1, a region of the (1-1)th electrode EL1_1 may be exposed to the outside through the first opening OPN1 of the first insulating layer INS1 and may be directly connected to the first contact electrode CNE1 through the first opening OPN1.

[0355] In addition, in the first area A1 of the second emission area E2, a region of the (3-1)th electrode EL3_1 may be exposed to the outside through the second opening OPN2 of the first insulating layer INS1. The third contact electrode CNE3 may be disposed on the (3-1)th electrode EL3_1, a region of which may be exposed to the outside, and thus the (3-1)th electrode EL3_1 and the third contact electrode CNE3 may directly contact to be electrically and / or physically connected to each other.

[0356] Furthermore, in the first region A1 between the first emission region E1 and the second emission region E2, the (2-1)th electrode EL2_1 may be covered by the first insulating layer INS1 to be electrically insulated from the second contact electrode CNE2 disposed on the (2-1)th electrode EL2_1.

[0357] At least one (1-1)th light emitting element LD1_1 may be aligned between the (1-1)th electrode EL1_1 and the (2-1)th electrode EL2_1. One end of the (1-1)th light emitting element LD1_1 may be electrically and / or physically connected to the first contact electrode CNE1, and the other end of the (1-1)th light emitting element LD1_1 may be electrically and / or physically connected to the second contact electrode CNE2.

[0358] At least one (1-2)th light emitting element LD1_2 may be aligned between the (2-1)th electrode EL2_1 and the (3-1)th electrode EL3_1. One end of the (1-2)th light emitting element LD1_2 may be electrically and / or physically connected to the third contact electrode CNE3, and the other end of the (1-2)th light emitting element LD1_2 may be electrically and / or physically connected to the second contact electrode CNE2.

[0359] In an embodiment of the present disclosure, the (1-1)th electrode EL1_1, the (2-1)th electrode EL2_1, the (3-1)th electrode EL3_1, the first contact electrode CNE1, the second contact electrode CNE2 and the third contact electrode CNE3 positioned in the first area A1 of the first emission area E1 and the second emission area E2, and the (1-1)th light emitting element LD1_1 and the (1-2)th light emitting element LD1_2 can configure the first series stage SET1.

[0360] In the second area A2 of the first emission region E1, the (1-2)th electrode EL1_2 may be covered by the first insulating layer INS1 to be electrically insulated from the fourth contact electrode CNE4 disposed on the (1-2)th electrode EL1_2.

[0361] In the second area A2 of the second emission region E2, the (3-2)th electrode EL3_2 may be covered by the first insulating layer INS1 to be electrically insulated from the sixth contact electrode CNE6 disposed on the (3-2)th electrode EL3_2.

[0362] Furthermore, in the second region A2 between the first emission region E1 and the second emission region E2, the (2-2)th electrode EL2_2 may be covered by the first insulating layer INS1 to be electrically insulated from the fifth contact electrode CNE5 disposed on the (2-2)th electrode EL2_2.

[0363] In the second area A2 of the first emission area E1, at least one (2-1)th light emitting element LD2_1 may be aligned between the (1-2)th electrode EL1_2 and the (2-2)th electrode EL2_2. One end of the (2-1)th light emitting element LD2_1 may be electrically and / or physically connected to the fourth contact electrode CNE4, and the other end of the (2-1)th light emitting element LD2_1 may be electrically and / or physically connected to the fifth contact electrode CNE5.

[0364] In addition, in the second area A2 of the second emission area E2, at least one (2-2)th light emitting element LD2_2 may be aligned between the (2-2)th electrode EL2_2 and the (3-2)th electrode EL3_2. One end of the (2-2)th light emitting element LD2_2 may be electrically and / or physically connected to the sixth contact electrode CNE6, and the other end of the (2-2)th light emitting element LD2_2 may be electrically and / or physically connected to the fifth contact electrode CNE5.

[0365] In an embodiment of the present disclosure, the (1-2)th electrode EL1_2, the (2-2)th electrode EL2_2, the (3-2)th electrode EL3_2, the fourth contact electrode CNE4, the fifth contact electrode CNE5 and the sixth contact electrode CNE6, and the (2-1)th light-emitting element LD2_1 and the (2-2)th light-emitting element LD2_2 positioned in the second area A2 of the first emission area E1 and the second emission area E2 can configure the second series stage SET2.

[0366] In the first emission region E1 and the second emission region E2, the first intermediate electrode CTE1 may be disposed between the first region A1 and the second region A2. The first intermediate electrode CTE1 may be disposed throughout the first region A1 and the second region A2. One end of the first intermediate electrode CTE1 may be electrically and / or physically connected to the second contact electrode CNE2, the other end of the first intermediate electrode CTE1 may be electrically and / or physically connected to the fourth contact electrode CNE4, and another end of the first intermediate electrode CTE1 may be electrically and / or physically connected to the sixth contact electrode CNE6. The first intermediate electrode CTE1 may be integrally disposed with the second contact electrode CNE2, the fourth contact electrode CNE4, and / or the sixth contact electrode CNE6. Therefore, the second contact electrode CNE2, the fourth contact electrode CNE4, and the sixth contact electrode CNE6 may be electrically and / or physically connected to each other through the first intermediate electrode CTE1.

[0367] In an embodiment of the present disclosure, the first intermediate electrode CTE1 may be a first bridging electrode (or a first connection electrode) electrically connecting the first series stage SET1 and the second series stage SET2 .

[0368] In the third area A3 of the first emission region E1, the (1-3)th electrode EL1_3 may be covered by the first insulating layer INS1 to be electrically insulated from the seventh contact electrode CNE7 disposed on the (1-3)th electrode EL1_3.

[0369] Furthermore, in the third area A3 of the second emission area E2, the (3-3)th electrode EL3_3 may be covered by the first insulating layer INS1 to be electrically insulated from the ninth contact electrode CNE9 disposed on the (3-3)th electrode EL3_3.

[0370] In addition, in the third area A3 between the first emission area E1 and the second emission area E2, a region of the (2-3)th electrode EL2_3 may be exposed to the outside through the third opening OPN3 of the first insulating layer INS1. The eighth contact electrode CNE8 may be disposed on the (2-3)th electrode EL2_3, a region of which may be exposed to the outside, and thus the (2-3)th electrode EL2_3 and the eighth contact electrode CNE8 may directly contact to be electrically and / or physically connected to each other.

[0371] In the third area A3 of the first emission area E1, at least one (3-1)th light emitting element LD3_1 may be aligned between the (1-3)th electrode EL1_3 and the (2-3)th electrode EL2_3. One end of the (3-1)th light emitting element LD3_1 may be electrically and / or physically connected to the seventh contact electrode CNE7, and the other end of the (3-1)th light emitting element LD3_1 may be electrically and / or physically connected to the eighth contact electrode CNE8.

[0372] In addition, in the third area A3 of the second emission area E2, at least one (3-2)th light emitting element LD3_2 may be aligned between the (2-3)th electrode EL2_3 and the (3-3)th electrode EL3_3. One end of the (3-2)th light emitting element LD3_2 may be electrically and / or physically connected to the ninth contact electrode CNE9, and the other end of the (3-2)th light emitting element LD3_2 may be electrically and / or physically connected to the eighth contact electrode CNE8.

[0373] In an embodiment of the present disclosure, the (1-3)th electrode EL1_3, the (2-3)th electrode EL2_3, the (3-3)th electrode EL3_3, the seventh contact electrode CNE7, the eighth contact electrode CNE8 and the ninth contact electrode CNE9, and the (3-1)th light emitting element LD3_1 and the (3-2)th light emitting element LD3_2 may configure a third series stage.

[0374] In the first emission region E1 and the second emission region E2, the second intermediate electrode CTE2 may be disposed between the second region A2 and the third region A3. The second intermediate electrode CTE2 may be disposed throughout the second region A2 and the third region A3. One end of the second intermediate electrode CTE2 may be electrically and / or physically connected to the fifth contact electrode CNE5, the other end of the second intermediate electrode CTE2 may be electrically and / or physically connected to the seventh contact electrode CNE7, and another end of the second intermediate electrode CTE2 may be electrically and / or physically connected to the ninth contact electrode CNE9. The second intermediate electrode CTE2 may be integrally disposed with the fifth contact electrode CNE5, the seventh contact electrode CNE7, and / or the ninth contact electrode CNE9. Therefore, the fifth contact electrode CNE5, the seventh contact electrode CNE7, and the ninth contact electrode CNE9 may be electrically and / or physically connected to each other through the second intermediate electrode CTE2.

[0375] In an embodiment of the present disclosure, the second intermediate electrode CTE2 may be a second bridging electrode (or a second connection electrode) electrically connecting the second series stage SET2 and the third series stage.

[0376] The (1-1)th electrode EL1_1 having an area exposed by the first opening OPN1 of the first insulating layer INS1 to directly contact the first contact electrode CNE1 and the (3-1)th electrode EL3_1 having an area exposed by the second opening OPN2 of the first insulating layer INS1 to directly contact the third contact electrode CNE3 may be an anode electrode of the emission unit EMU of each pixel PXL. In addition, the (2-3)th electrode EL2_3 having an area exposed by the third opening OPN3 of the first insulating layer INS1 to directly contact the eighth contact electrode CNE8 may be a cathode electrode of the emission unit EMU.

[0377] In the case where the drive current flows from the first power line PL1 to the second power line PL2 through the first transistor T1, the drive current may be supplied to the (1-1)th electrode EL1_1 and the first contact electrode CNE1 through the first contact hole CH1, and the drive current flows to the second contact electrode CNE2 via the (1-1)th light emitting element LD1_1. In addition, in the case where the drive current flows from the first power line PL1 to the second power line PL2, the drive current may be supplied to the (3-1)th electrode EL3_1 and the third contact electrode CNE3 through the third contact hole CH3, and the drive current flows to the second contact electrode CNE2 via the (1-2)th light emitting element LD1_2.

[0378] The driving current flowing to the second contact electrode CNE2 flows to the fourth contact electrode CNE4 and the sixth contact electrode CNE6 through the first intermediate electrode CTE1. The driving current flowing to the fourth contact electrode CNE4 flows to the fifth contact electrode CNE5 via the (2-1)th light emitting element LD2_1. In addition, the driving current flowing to the sixth contact electrode CNE6 flows to the fifth contact electrode CNE5 via the (2-2)th light emitting element LD2_2.

[0379] The driving current flowing to the fifth contact electrode CNE5 flows to the seventh contact electrode CNE7 and the ninth contact electrode CNE9 through the second intermediate electrode CTE2. The driving current flowing to the seventh contact electrode CNE7 flows to the eighth contact electrode CNE8 via the (3-1)th light emitting element LD3_1. In addition, the driving current flowing to the ninth contact electrode CNE9 flows to the eighth contact electrode CNE8 via the (3-2)th light emitting element LD3_2.

[0380] Next, refer to Figures 1a to 5 and Fig.18c , the first to fifth electrodes EL1 to EL5 may be disposed in the pixel area PXA of each pixel PXL.

[0381] In an embodiment of the present disclosure, the pixel area PXA of each pixel PXL may include first to fourth emission areas E1 to E4 .

[0382] The first electrode EL1, the second electrode EL2, and the light emitting element LD aligned between the first electrode EL1 and the second electrode EL2 may be disposed in the first emission region E1. The third electrode EL3, the second electrode EL2, and the light emitting element LD aligned between the third electrode EL3 and the second electrode EL2 may be disposed in the second emission region E2. The second electrode EL2 may be disposed between the first emission region E1 and the second emission region E2. That is, the second electrode EL2 may be commonly disposed to the first emission region E1 and the second emission region E2.

[0383] The third electrode EL3, the fourth electrode EL4, and the light emitting element LD aligned between the third electrode EL3 and the fourth electrode EL4 may be disposed in the third emission region E3. The third electrode EL3 may be disposed between the second emission region E2 and the third emission region E3.

[0384] The fifth electrode EL5, the fourth electrode EL4, and the light emitting element LD aligned between the fifth electrode EL5 and the fourth electrode EL4 may be disposed in the fourth emission region E4. The fourth electrode EL4 may be disposed between the third emission region E3 and the fourth emission region E4. That is, the fourth electrode EL4 may be commonly disposed to the third emission region E3 and the fourth emission region E4.

[0385] When viewed in a plan view, each of the first to fourth emission regions E1 to E4 may be divided into first to third regions A1 to A3 along the second direction DR2. In this case, each of the first to fifth electrodes EL1 to EL5 may be divided into three regions according to the positions of the first to third regions A1 to A3. The first electrode EL1 may be divided into a (1-1)th electrode EL1_1 of the first region A1, a (1-2)th electrode EL1_2 of the second region A2, and a (1-3)th electrode EL1_3 of the third region A3. The second electrode EL2 may be divided into a (2-1)th electrode EL2_1 of the first region A1, a (2-2)th electrode EL2_2 of the second region A2, and a (2-3)th electrode EL2_3 of the third region A3. The third electrode EL3 may include a (3-1)th electrode EL3_1 positioned in the first region A1, a (3-2)th electrode EL3_2 positioned in the second region A2, and a (3-3)th electrode EL3_3 positioned in the third region A3. The fourth electrode EL4 may include a (4-1)th electrode EL4_1 positioned in the first area A1, a (4-2)th electrode EL4_2 positioned in the second area A2, and a (4-3)th electrode EL4_3 positioned in the third area A3. The fifth electrode EL5 may include a (5-1)th electrode EL5_1 positioned in the first area A1, a (5-2)th electrode EL5_2 positioned in the second area A2, and a (5-3)th electrode EL5_3 positioned in the third area A3.

[0386] In the first area A1, the (1-1)th electrode EL1_1, the (2-1)th electrode EL2_1, the (3-1)th electrode EL3_1, the (4-1)th electrode EL4_1, and the (5-1)th electrode EL5_1 may be spaced apart from each other in the first direction DR1. In the second area A2, the (1-2)th electrode EL1_2, the (2-2)th electrode EL2_2, the (3-2)th electrode EL3_2, the (4-2)th electrode EL4_2, and the (5-2)th electrode EL5_2 may be spaced apart from each other in the first direction DR1. In the third area A3, the (1-3)th electrode EL1_3, the (2-3)th electrode EL2_3, the (3-3)th electrode EL3_3, the (4-3)th electrode EL4_3, and the (5-3)th electrode EL5_3 may be spaced apart from each other in the first direction DR1.

[0387] The (1-1)th electrode EL1_1 positioned in the first area A1 may be electrically and / or physically connected to the first transistor T1 of each pixel PXL through the first contact hole CH1, the (3-1)th electrode EL3_1 positioned in the first area A1 may be electrically and / or physically connected to the first transistor T1 through the third contact hole CH3, and the (5-1)th electrode EL5_1 positioned in the first area A1 may be electrically and / or physically connected to the first transistor T1 through the fifth contact hole CH5.

[0388] The (2-3)th electrode EL2_3 positioned in the third area A3 may be electrically and / or physically connected to the second power line PL2 through the second contact hole CH2, and the (4-3)th electrode EL4_3 positioned in the third area A3 may be electrically and / or physically connected to the second power line PL2 through the fourth contact hole CH4.

[0389] A region of the (1-1)th electrode EL1_1 may be exposed to the outside through the first opening OPN1 of the first insulating layer INS1, and may be directly connected to the first contact electrode CNE1 through the first opening OPN1. The (2-1)th electrode EL2_1 may be covered by the first insulating layer INS1 to be electrically insulated from the second contact electrode CNE2 disposed on the (2-1)th electrode EL2_1. A region of the (3-1)th electrode EL3_1 may be exposed to the outside through the second opening OPN2 of the first insulating layer INS1. The third contact electrode CNE3 may be disposed on the (3-1)th electrode EL3_1, a region of which may be exposed to the outside, and thus the (3-1)th electrode EL3_1 and the third contact electrode CNE3 may be directly in contact to be electrically and / or physically connected to each other. The (4-1)th electrode EL4_1 may be covered by the first insulating layer INS1 to be electrically insulated from the fourth contact electrode CNE4 disposed on the (4-1)th electrode EL4_1. A region of the (5-1)th electrode EL5_1 may be exposed to the outside through the third opening OPN3 of the first insulating layer INS1. The fifth contact electrode CNE5 may be disposed on the (5-1)th electrode EL5_1, a region of which may be exposed to the outside, and thus, the (5-1)th electrode EL5_1 and the fifth contact electrode CNE5 may directly contact to be electrically and / or physically connected to each other.

[0390] At least one (1-1)th light emitting element LD1_1 may be aligned between the (1-1)th electrode EL1_1 and the (2-1)th electrode EL2_1. One end of the (1-1)th light emitting element LD1_1 may be electrically and / or physically connected to one of the first contact electrode CNE1 and the second contact electrode CNE2, and the other end of the (1-1)th light emitting element LD1_1 may be electrically and / or physically connected to the other of the first contact electrode CNE1 and the second contact electrode CNE2.

[0391] At least one (1-2)th light emitting element LD1_2 may be aligned between the (2-1)th electrode EL2_1 and the (3-1)th electrode EL3_1. One end of the (1-2)th light emitting element LD1_2 may be electrically and / or physically connected to one of the second contact electrode CNE2 and the third contact electrode CNE3, and the other end of the (1-2)th light emitting element LD1_2 may be electrically and / or physically connected to the other of the second contact electrode CNE2 and the third contact electrode CNE3.

[0392] At least one (1-3)th light emitting element LD1_3 may be aligned between the (3-1)th electrode EL3_1 and the (4-1)th electrode EL4_1. One end of the (1-3)th light emitting element LD1_3 may be electrically and / or physically connected to one of the third contact electrode CNE3 and the fourth contact electrode CNE4, and the other end of the (1-3)th light emitting element LD1_3 may be electrically and / or physically connected to the other of the third contact electrode CNE3 and the fourth contact electrode CNE4.

[0393] At least one (1-4)th light emitting element LD1_4 may be aligned between the (4-1)th electrode EL4_1 and the (5-1)th electrode EL5_1. One end of the (1-4)th light emitting element LD1_4 may be electrically and / or physically connected to one of the fourth contact electrode CNE4 and the fifth contact electrode CNE5, and the other end of the (1-4)th light emitting element LD1_4 may be electrically and / or physically connected to the other of the fourth contact electrode CNE4 and the fifth contact electrode CNE5.

[0394] The (1-1)th light emitting element LD1_1, the (1-2)th light emitting element LD1_2, the (1-3)th light emitting element LD1_3, and the (1-4)th light emitting element LD1_4 aligned in the first area A1 may configure a first light emitting element LD1 group.

[0395] In an embodiment of the present disclosure, a group of (1-1)th, (2-1)th, EL2_1, (3-1)th, EL3_1, (4-1)th, and (5-1)th electrodes EL5_1, first to fifth contact electrodes CNE1 to CNE5, and a first light emitting element LD1 may configure a first series stage SET1.

[0396] The (1-2)th electrode EL1_2 may be covered by the first insulating layer INS1 to be electrically insulated from the sixth contact electrode CNE6 disposed on the (1-2)th electrode EL1_2. The (2-2)th electrode EL2_2 may be covered by the first insulating layer INS1 to be electrically insulated from the seventh contact electrode CNE7 disposed on the (2-2)th electrode EL2_2. The (3-2)th electrode EL3_2 may be covered by the first insulating layer INS1 to be electrically insulated from the eighth contact electrode CNE8 disposed on the (3-2)th electrode EL3_2. The (4-2)th electrode EL4_2 may be covered by the first insulating layer INS1 to be electrically insulated from the ninth contact electrode CNE9 disposed on the (4-2)th electrode EL4_2. The (5-2)th electrode EL5_2 may be covered by the first insulating layer INS1 to be electrically insulated from the tenth contact electrode CNE10 disposed on the (5-2)th electrode EL5_2.

[0397] At least one (2-1)th light emitting element LD2_1 may be aligned between the (1-2)th electrode EL1_2 and the (2-2)th electrode EL2_2. One end of the (2-1)th light emitting element LD2_1 may be electrically and / or physically connected to one of the sixth contact electrode CNE6 and the seventh contact electrode CNE7, and the other end of the (2-1)th light emitting element LD2_1 may be electrically and / or physically connected to the other of the sixth contact electrode CNE6 and the seventh contact electrode CNE7.

[0398] At least one (2-2)th light emitting element LD2_2 may be aligned between the (2-2)th electrode EL2_2 and the (3-2)th electrode EL3_2. One end of the (2-2)th light emitting element LD2_2 may be electrically and / or physically connected to one of the seventh contact electrode CNE7 and the eighth contact electrode CNE8, and the other end of the (2-2)th light emitting element LD2_2 may be electrically and / or physically connected to the other of the seventh contact electrode CNE7 and the eighth contact electrode CNE8.

[0399] At least one (2-3)th light emitting element LD2_3 may be aligned between the (3-2)th electrode EL3_2 and the (4-2)th electrode EL4_2. One end of the (2-3)th light emitting element LD2_3 may be electrically and / or physically connected to one of the eighth contact electrode CNE8 and the ninth contact electrode CNE9, and the other end of the (2-3)th light emitting element LD2_3 may be electrically and / or physically connected to the other of the eighth contact electrode CNE8 and the ninth contact electrode CNE9.

[0400] At least one (2-4)th light emitting element LD2_4 may be aligned between the (4-2)th electrode EL4_2 and the (5-2)th electrode EL5_2. One end of the (2-4)th light emitting element LD2_4 may be electrically and / or physically connected to one of the ninth contact electrode CNE9 and the tenth contact electrode CNE10, and the other end of the (2-4)th light emitting element LD2_4 may be electrically and / or physically connected to the other of the ninth contact electrode CNE9 and the tenth contact electrode CNE10.

[0401] The (2-1)th light emitting element LD2_1, the (2-2)th light emitting element LD2_2, the (2-3)th light emitting element LD2_3, and the (2-4)th light emitting element LD2_4 aligned in the second area A2 may configure a second light emitting element LD2 group.

[0402] In an embodiment of the present disclosure, the (1-2)th electrode EL1_2, (2-2)th electrode EL2_2, (3-2)th electrode EL3_2, (4-2)th electrode EL4_2 and (5-2)th electrode EL5_2, the sixth to tenth contact electrodes CNE6 to CNE10, and the second light emitting element LD2 group may configure a second series stage SET2.

[0403] The first intermediate electrode CTE1 may be disposed between the first area A1 and the second area A2. The first intermediate electrode CTE1 may be disposed throughout the first area A1 and the second area A2. One end of the first intermediate electrode CTE1 may be electrically and / or physically connected to the second contact electrode CNE2, and the other end of the first intermediate electrode CTE1 may be electrically and / or physically connected to the fourth contact electrode CNE4. In addition, yet another end of the first intermediate electrode CTE1 may be electrically and / or physically connected to the sixth contact electrode CNE6, and yet another end of the first intermediate electrode CTE1 may be electrically and / or physically connected to the eighth contact electrode CNE8, and yet another end of the first intermediate electrode CTE1 may be electrically and / or physically connected to the tenth contact electrode CNE10.

[0404] In an embodiment of the present disclosure, the first intermediate electrode CTE1 may be a first bridging electrode (or a first connection electrode) electrically connecting the first series stage SET1 and the second series stage SET2 .

[0405] The (1-3)th electrode EL1_3 may be covered by the first insulating layer INS1 to be electrically insulated from the eleventh contact electrode CNE11 disposed on the (1-3)th electrode EL1_3. The (2-3)th electrode EL2_3 may be exposed to the outside through the fourth opening OPN4 of the first insulating layer INS1, and may be directly connected to the twelfth contact electrode CNE12 through the fourth opening OPN4. The (3-3)th electrode EL3_3 may be covered by the first insulating layer INS1 to be electrically insulated from the thirteenth contact electrode CNE13 disposed on the (3-3)th electrode EL3_3. The (4-3)th electrode EL4_3 may be exposed to the outside through the fifth opening OPN5 of the first insulating layer INS1, and may be directly connected to the fourteenth contact electrode CNE14 through the fifth opening OPN5. The (5-3)th electrode EL5_3 may be covered by the first insulating layer INS1 to be electrically insulated from the fifteenth contact electrode CNE15 disposed on the (5-3)th electrode EL5_3.

[0406] At least one (3-1)th light emitting element LD3_1 may be aligned between the (1-3)th electrode EL1_3 and the (2-3)th electrode EL2_3. One end of the (3-1)th light emitting element LD3_1 may be electrically and / or physically connected to one of the eleventh contact electrode CNE11 and the twelfth contact electrode CNE12, and the other end of the (3-1)th light emitting element LD3_1 may be electrically and / or physically connected to the other of the eleventh contact electrode CNE11 and the twelfth contact electrode CNE12.

[0407] At least one (3-2)th light emitting element LD3_2 may be aligned between the (2-3)th electrode EL2_3 and the (3-3)th electrode EL3_3. One end of the (3-2)th light emitting element LD3_2 may be electrically and / or physically connected to one of the twelfth contact electrode CNE12 and the thirteenth contact electrode CNE13, and the other end of the (3-2)th light emitting element LD3_2 may be electrically and / or physically connected to the other of the twelfth contact electrode CNE12 and the thirteenth contact electrode CNE13.

[0408] At least one (3-3)th light emitting element LD3_3 may be aligned between the (3-3)th electrode EL3_3 and the (4-3)th electrode EL4_3. One end of the (3-3)th light emitting element LD3_3 may be electrically and / or physically connected to one of the thirteenth contact electrode CNE13 and the fourteenth contact electrode CNE14, and the other end of the (3-3)th light emitting element LD3_3 may be electrically and / or physically connected to the other of the thirteenth contact electrode CNE13 and the fourteenth contact electrode CNE14.

[0409] At least one (3-4)th light emitting element LD3_4 may be aligned between the (4-3)th electrode EL4_3 and the (5-3)th electrode EL5_3. One end of the (3-4)th light emitting element LD3_4 may be electrically and / or physically connected to one of the fourteenth contact electrode CNE14 and the fifteenth contact electrode CNE15, and the other end of the (3-4)th light emitting element LD3_4 may be electrically and / or physically connected to the other of the fourteenth contact electrode CNE14 and the fifteenth contact electrode CNE15.

[0410] The (3-1)th light emitting element LD3_1, the (3-2)th light emitting element LD3_2, the (3-3)th light emitting element LD3_3, and the (3-4)th light emitting element LD3_4 aligned in the third area A3 may configure a third light emitting element LD3 group.

[0411] In an embodiment of the present disclosure, the (1-3)th electrode EL1_3, (2-3)th electrode EL2_3, (3-3)th electrode EL3_3, (4-3)th electrode EL4_3, (5-3)th electrode EL5_3, eleventh to fifteenth contact electrodes CNE11 to CNE15, and the third light emitting element LD3 group may configure a third series stage.

[0412] The second intermediate electrode CTE2 may be disposed between the second area A2 and the third area A3. The second intermediate electrode CTE2 may be disposed throughout the second area A2 and the third area A3. One end of the second intermediate electrode CTE2 may be electrically and / or physically connected to the seventh contact electrode CNE7, and the other end of the second intermediate electrode CTE2 may be electrically and / or physically connected to the ninth contact electrode CNE9. In addition, another end of the second intermediate electrode CTE2 may be electrically and / or physically connected to the eleventh contact electrode CNE11, and another end of the second intermediate electrode CTE2 may be electrically and / or physically connected to the thirteenth contact electrode CNE13, and another end of the second intermediate electrode CTE2 may be electrically and / or physically connected to the fifteenth contact electrode CNE15.

[0413] In an embodiment of the present disclosure, the second intermediate electrode CTE2 may be a second bridging electrode (or a second connection electrode) electrically connecting the second series stage SET2 and the third series stage.

[0414] A region thereof may be exposed by the first opening OPN1 of the first insulating layer INS1 to directly contact the (1-1) electrode EL1_1 of the first contact electrode CNE1, a region thereof may be exposed by the second opening OPN2 of the first insulating layer INS1 to directly contact the (3-1) electrode EL3_1 of the third contact electrode CNE3, and a region thereof may be exposed by the third opening OPN3 of the first insulating layer INS1 to directly contact the (5-1) electrode EL5_1 of the fifth contact electrode CNE5 may be an anode electrode of the emission unit EMU of each pixel PXL. In addition, a region thereof may be exposed by the fourth opening OPN4 of the first insulating layer INS1 to directly contact the (2-3) electrode EL2_3 of the twelfth contact electrode CNE12, and a region thereof may be exposed by the fifth opening OPN5 of the first insulating layer INS1 to directly contact the (4-3) electrode EL4_3 of the fourteenth contact electrode CNE14 may be a cathode electrode of the emission unit EMU.

[0415] Fig.19 A pixel PXL according to still another embodiment of the present disclosure is schematically illustrated, and is a schematic plan view of the pixel PXL including only a partial configuration of the display element layer DPL.

[0416] about Fig.19 The pixel PXL of the embodiment described above is mainly described with respect to the differences from the above embodiment to avoid redundant description. Parts not specifically described in the present disclosure may be consistent with the above embodiment, and the same reference numerals indicate the same components.

[0417] refer to Figures 1a to 5 , Figure 7b and Fig.19 , the pixel area PXA of each pixel PXL may include first to third areas A1 to A3 spaced apart along the second direction DR2 .

[0418] The (1-1)th electrode EL1_1 and the (2-1)th electrode EL2_1 separated from each other may be disposed in the first area A1, the (1-2)th electrode EL1_2 and the (2-2)th electrode EL2_2 separated from each other may be disposed in the second area A2, and the (1-3)th electrode EL1_3 and the (2-3)th electrode EL2_3 separated from each other may be disposed in the third area A3.

[0419] Before aligning the light emitting element LD in the pixel area PXA of each pixel PXL, the (1-1)th electrode EL1_1, the (1-2)th electrode EL1_2, and the (1-3)th electrode EL1_3 may be configured with an alignment line electrically and / or physically connected to each other. After the light emitting element LD is aligned in the pixel area PXA, a portion of the alignment line may be removed or disconnected, and thus the (1-1)th electrode EL1_1, the (1-2)th electrode EL1_2, and the (1-3)th electrode EL1_3 may be electrically and / or physically separated from each other.

[0420] Regardless of whether the light emitting element LD is aligned, the (2-1)th electrode EL2_1, the (2-2)th electrode EL2_2, and the (2-3)th electrode EL2_3 may be electrically connected through the connection line CNL. For example, the (2-1)th electrode EL2_1 may be connected to the connection line CNL through the second contact hole CH2, the (2-2)th electrode EL2_2 may be connected to the connection line CNL through the third contact hole CH3, and the (2-3)th electrode EL2_3 may be connected to the connection line CNL through the fourth contact hole CH4. The connection line CNL may be electrically connected to the second power line PL2 of the pixel circuit 144 of each pixel PXL through the fifth contact hole CH5.

[0421] When viewed in a plan view, the (2-1)th electrode EL2_1 may be positioned at the center (or middle) of the first area A1 and may have a circular shape. The (1-1)th electrode EL1_1 may have a shape that surrounds the (2-1)th electrode EL2_1 in its circumferential direction. For example, the (1-1)th electrode EL1_1 may have a shape that surrounds at least a portion of the (2-1)th electrode EL2_1. In an embodiment of the present disclosure, the (1-1)th electrode EL1_1 may have a shape that surrounds only the remaining area except at least one area of ​​the (2-1)th electrode EL2_1, for example, a "C" shape in which a portion may be opened without forming a perfect circular ring shape.

[0422] In an embodiment of the present disclosure, the (1-1)th electrode EL1_1 may be electrically and / or physically connected to the first transistor T1 of the pixel circuit 144 through the first contact hole CH1. A region of the (1-1)th electrode EL1_1 may be exposed to the outside through the first opening OPN1 of the first insulating layer INS1. The first contact electrode CNE1 may be disposed on the (1-1)th electrode EL1_1, a region of which may be exposed to the outside, and thus the (1-1)th electrode EL1_1 and the first contact electrode CNE1 may be in direct contact to be electrically and / or physically connected to each other. The (2-1)th electrode EL2_1 may be covered by the first insulating layer INS1 to be electrically insulated from the second contact electrode CNE2 disposed on the (2-1)th electrode EL2_1.

[0423] In the first area A1, a plurality of first light emitting elements LD1 may be aligned between the (1-1)th electrode EL1_1 and the (2-1)th electrode EL2_1. One end of each of the first light emitting elements LD1 may be connected to any one of the first contact electrode CNE1 and the second contact electrode CNE2, and the other end of each of the first light emitting elements LD1 may be connected to the other of the first contact electrode CNE1 and the second contact electrode CNE2. The first light emitting elements LD1 may be aligned along the periphery of the (2-1)th electrode EL2_1. For example, the first light emitting elements LD1 may be radially aligned around the circular (2-1)th electrode EL2_1 between the (1-1)th electrode EL1_1 and the (2-1)th electrode EL2_1.

[0424] In an embodiment of the present disclosure, the (1-1)th and (2-1)th electrodes EL1_1 and EL2_1 , the first and second contact electrodes CNE1 and CNE2 , and the first light emitting element LD1 positioned in the first area A1 may configure a first series stage SET1 .

[0425] When viewed in a plan view, the (2-2)th electrode EL2_2 may be positioned at the center (or middle) of the second area A2 and may have a circular shape. The (1-2)th electrode EL1_2 may have a shape surrounding the (2-2)th electrode EL2_2 in its circumferential direction. For example, the (1-2)th electrode EL1_2 may have a shape surrounding at least a portion of the (2-2)th electrode EL2_2. In an embodiment of the present disclosure, the (1-2)th electrode EL1_2 may have a shape surrounding only the remaining area except at least one area of ​​the (2-2)th electrode EL2_2, for example, a "C" shape in which a portion may be opened without forming a perfect circular ring shape.

[0426] In an embodiment of the present disclosure, the (1-2)th electrode EL1_2 may be covered by the first insulating layer INS1 to be electrically insulated from the third contact electrode CNE3 disposed on the (1-2)th electrode EL1_2. The (2-2)th electrode EL2_2 may be covered by the first insulating layer INS1 to be electrically insulated from the fourth contact electrode CNE4 disposed on the (2-2)th electrode EL2_2.

[0427] In the second area A2, a plurality of second light emitting elements LD2 may be aligned between the (1-2)th electrode EL1_2 and the (2-2)th electrode EL2_2. One end of each of the second light emitting elements LD2 may be connected to one of the third contact electrode CNE3 and the fourth contact electrode CNE4, and the other end of each of the second light emitting elements LD2 may be connected to the other of the third contact electrode CNE3 and the fourth contact electrode CNE4. The second light emitting elements LD2 may be aligned along the periphery of the (2-2)th electrode EL2_2. For example, the second light emitting elements LD2 may be radially aligned around the circular (2-2)th electrode EL2_2 between the (1-2)th electrode EL1_2 and the (2-2)th electrode EL2_2.

[0428] In an embodiment of the present disclosure, the (1-2)th and (2-2)th electrodes EL1_2 and EL2_2 , the third and fourth contact electrodes CNE3 and CNE4 , and the second light emitting element LD2 positioned in the second area A2 may configure a second series stage SET2 .

[0429] The first intermediate electrode CTE1 may be disposed between the first area A1 and the second area A2. The first intermediate electrode CTE1 may be disposed throughout the first area A1 and the second area A2. One end of the first intermediate electrode CTE1 may be electrically and / or physically connected to the second contact electrode CNE2, and the other end of the first intermediate electrode CTE1 may be electrically and / or physically connected to the third contact electrode CNE3. The first intermediate electrode CTE1 may be integrally disposed with the second contact electrode CNE2 and / or the third contact electrode CNE3. Therefore, the second contact electrode CNE2 and the third contact electrode CNE3 may be electrically and / or physically connected to each other through the first intermediate electrode CTE1.

[0430] In an embodiment of the present disclosure, the first intermediate electrode CTE1 may be a first bridging electrode (or a first connection electrode) electrically connecting the first series stage SET1 and the second series stage SET2 .

[0431] When viewed in a plan view, the (2-3)th electrode EL2_3 may be positioned at the center (or middle) of the third area A3 and may have a circular shape. The (1-3)th electrode EL1_3 may have a shape surrounding the periphery of the (2-3)th electrode EL2_3 along its circumferential direction. For example, the (1-3)th electrode EL1_3 may have a circular ring shape (or a closed loop shape) surrounding the periphery of the (2-3)th electrode EL2_3. The (1-3)th electrode EL1_3 may have a circular ring shape, but the present disclosure is not limited thereto. According to an embodiment, the (1-3)th electrode EL1_3 is not limited to a circular ring shape, and may have a polygonal ring shape including a quadrilateral ring shape, an octagonal ring shape of a quadrilateral shape, an octagonal shape, etc. that form a closed circuit.

[0432] In an embodiment of the present disclosure, the (2-3)th electrode EL2_3 may be electrically connected and / or physically connected to the second power line PL2 of the pixel circuit 144 through the fourth contact hole CH4 and the connection line CNL. The (1-3)th electrode EL1_3 may be covered by the first insulating layer INS1 to be electrically insulated from the fifth contact electrode CNE5 disposed on the (1-3)th electrode EL1_3. A region of the (2-3)th electrode EL2_3 may be exposed to the outside through the second opening OPN2 of the first insulating layer INS1. The sixth contact electrode CNE6 may be disposed on the (2-3)th electrode EL2_3, a region of which may be exposed to the outside, and therefore, the (2-3)th electrode EL2_3 and the sixth contact electrode CNE6 may be in direct contact to be electrically and / or physically connected to each other.

[0433] In the third area A3, a plurality of third light emitting elements LD3 may be aligned between the (1-3)th electrode EL1_3 and the (2-3)th electrode EL2_3. One end of each of the third light emitting elements LD3 may be connected to any one of the fifth contact electrode CNE5 and the sixth contact electrode CNE6, and the other end of each of the third light emitting elements LD3 may be connected to the other of the fifth contact electrode CNE5 and the sixth contact electrode CNE6. The third light emitting elements LD3 may be aligned along the periphery of the (2-3)th electrode EL2_3. For example, the third light emitting elements LD3 may be radially aligned around the circular (2-3)th electrode EL2_3 between the (1-3)th electrode EL1_3 and the (2-3)th electrode EL2_3.

[0434] In an embodiment of the present disclosure, the (1-3)th and (2-3)th electrodes EL1_3 and EL2_3 , the fifth and sixth contact electrodes CNE5 and CNE6 , and the third light emitting element LD3 positioned in the third area A3 may configure a third series stage.

[0435] The second intermediate electrode CTE2 may be disposed between the second area A2 and the third area A3. The second intermediate electrode CTE2 may be disposed throughout the second area A2 and the third area A3. One end of the second intermediate electrode CTE2 may be electrically and / or physically connected to the fourth contact electrode CNE4, and the other end of the second intermediate electrode CTE2 may be electrically and / or physically connected to the fifth contact electrode CNE5. The second intermediate electrode CTE2 may be integrally disposed with the fourth contact electrode CNE4 and / or the fifth contact electrode CNE5. Therefore, the fourth contact electrode CNE4 and the fifth contact electrode CNE5 may be electrically and / or physically connected to each other through the second intermediate electrode CTE2.

[0436] In an embodiment of the present disclosure, the second intermediate electrode CTE2 may be a second bridging electrode (or a second connection electrode) connecting the second series stage SET2 and the third series stage.

[0437] The (1-1)th electrode EL1_1, a region of which may be exposed by the first opening OPN1 of the first insulating layer INS1 to directly contact the first contact electrode CNE1, may be an anode electrode of the emission unit EMU of each pixel PXL. In addition, the (2-3)th electrode EL2_3, a region of which may be exposed by the second opening OPN2 of the first insulating layer INS1 to directly contact the sixth contact electrode CNE6, may be a cathode electrode of the emission unit EMU.

[0438] Although the above description has been made with reference to the preferred embodiments of the present disclosure, those skilled in the art or those having ordinary knowledge in the corresponding technical field will understand that various changes and modifications may be made to the present disclosure without departing from the technical scope of the present disclosure described in the appended claims.

[0439] Therefore, the technical scope of the present disclosure should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims

1. Pixels, including: A first region and a second region are separated in a first direction; A 1-1 electrode and a 2-1 electrode are disposed in the first region and are spaced apart in a second direction different from the first direction; A 1-2 electrode and a 2-2 electrode, disposed in the second region and spaced apart in the second direction; A plurality of light-emitting elements are arranged between the 1-1 electrode and the 2-1 electrode and between the 1-2 electrode and the 2-2 electrode; Contact electrodes are respectively arranged on the 1-1 electrode and the 2-1 electrode and on the 1-2 electrode and the 2-2 electrode; an insulating layer disposed between each of the 1-1 electrode and the 2-1 electrode and the 1-2 electrode and the 2-2 electrode and the contact electrode, and including a first opening exposing a portion of the 1-1 electrode; as well as a first intermediate electrode, connecting the contact electrode on the 2-1 electrode and the contact electrode on the 1-2 electrode, Wherein, the insulating layer completely covers the 2-1st electrode and the 1-2nd electrode.

2. The pixel according to claim 1, wherein: The insulating layer further includes a second opening exposing a portion of the 2-2 electrode.

3. The pixel according to claim 2, wherein: The 1-1 electrode directly contacts the contact electrode on the 1-1 electrode through the first opening, and The 2-2 electrode directly contacts the contact electrode on the 2-2 electrode through the second opening.

4. The pixel according to claim 3, wherein: The 2-1st electrode is electrically insulated from the contact electrode on the 2-1st electrode, and The 1-2 electrode is electrically insulated from the contact electrode on the 1-2 electrode.

5. The pixel according to claim 2, wherein: The first intermediate electrode is disposed between the first region and the second region, and The first intermediate electrode and the contact electrode on the 2-1 electrode are integrated with each other, or the first intermediate electrode and the contact electrode on the 1-2 electrode are integrated with each other.

6. The pixel according to claim 2, wherein: The contact electrode on the 1-1 electrode, the contact electrode on the 2-1 electrode, the contact electrode on the 1-2 electrode, the contact electrode on the 2-2 electrode, and the first intermediate electrode are provided on the same layer.

7. The pixel according to claim 2, wherein: The 1-1 electrode and the 1-2 electrode extend in the first direction and are connected to each other between the first region and the second region, and The 2-1 electrode and the 2-2 electrode extend in the first direction and are connected to each other between the first region and the second region.

8. The pixel according to claim 2, wherein: The 1-1th electrode is an anode electrode, and the 2-2th electrode is a cathode electrode.

9. The pixel according to claim 1, wherein: The plurality of light emitting elements include: a plurality of first light emitting elements disposed between the 1-1 electrode and the 2-1 electrode in the first region; and A plurality of second light emitting elements are provided between the 1-2 electrode and the 2-2 electrode in the second region.

10. The pixel according to claim 9, wherein: The plurality of first light emitting elements form a first series stage connected in parallel between the 1-1 electrode and the 2-1 electrode, and The plurality of second light emitting elements form a second series stage connected in parallel between the 1-2 electrode and the 2-2 electrode.

11. The pixel according to claim 9, further comprising: a third region located at a lower end of the second region in the first direction, Wherein, the third area includes: The 1st-3rd electrodes and the 2nd-3rd electrodes are spaced apart in the second direction; A plurality of third light emitting elements, arranged between the 1st-3rd electrodes and the 2nd-3rd electrodes; The contact electrodes are respectively arranged on the 1st-3rd electrodes and the 2nd-3rd electrodes; the insulating layer being disposed between each of the 1-3 electrode and the 2-3 electrode and the contact electrode, and further comprising a second opening exposing a portion of the 2-3 electrode; and The second intermediate electrode connects the contact electrode on the 2-2 electrode and the contact electrode on the 1-3 electrode.

12. The pixel according to claim 11, wherein: The insulating layer completely covers the 2-2 electrode and the 1-3 electrode.

13. The pixel according to claim 12, wherein: The 1-1 electrode directly contacts the contact electrode on the 1-1 electrode through the first opening, and The 2-3 electrode directly contacts the contact electrode on the 2-3 electrode through the second opening.

14. The pixel according to claim 12, wherein: The second intermediate electrode and the contact electrode on the 2-2 electrode are integrated with each other, or the second intermediate electrode and the contact electrode on the 1-3 electrode are integrated with each other.

15. The pixel according to claim 13, wherein: The plurality of first light emitting elements form a first series stage connected in parallel between the 1-1 electrode and the 2-1 electrode, The plurality of second light emitting elements form a second series stage connected in parallel between the 1-2 electrode and the 2-2 electrode, and The plurality of third light emitting elements form a third series stage connected in parallel between the 1-3 electrode and the 2-3 electrode.

16. The pixel according to claim 15, wherein: The 1-1th electrode is an anode electrode, and the 2-3th electrode is a cathode electrode.

17. The pixel according to claim 1, wherein: In the first region, one of the 1-1 electrode and the 2-1 electrode has a circular shape, and the other electrode has a shape surrounding a periphery of the one electrode, and In the second region, one of the 1-2 electrode and the 2-2 electrode has a circular shape, and the other electrode has a shape surrounding a periphery of the one electrode.

18. A display device comprising: A plurality of pixels are disposed on a substrate. Wherein, each of the plurality of pixels comprises: A first region and a second region are separated in a first direction; A 1-1 electrode and a 2-1 electrode are disposed in the first region and are spaced apart in a second direction different from the first direction; A 1-2 electrode and a 2-2 electrode, disposed in the second region and spaced apart in the second direction; A plurality of first light-emitting elements are arranged between the 1-1 electrode and the 2-1 electrode; A plurality of second light emitting elements, arranged between the 1-2 electrode and the 2-2 electrode; a first contact electrode disposed on the 1-1 electrode, a second contact electrode disposed on the 2-1 electrode, a third contact electrode disposed on the 1-2 electrode, and a fourth contact electrode disposed on the 2-2 electrode; Insulating layers are respectively disposed between the 1-1 electrode and the first contact electrode, between the 2-1 electrode and the second contact electrode, between the 1-2 electrode and the third contact electrode, and between the 2-2 electrode and the fourth contact electrode; and an intermediate electrode, connecting the second contact electrode and the third contact electrode, wherein: The insulating layer includes a first opening exposing a portion of the 1-1 electrode and a second opening exposing a portion of the 2-2 electrode, and The insulating layer completely covers the 2-1st electrode and the 1-2nd electrode.

19. The display device according to claim 18, wherein: The 1-1th electrode is an anode electrode, and the 2-2th electrode is a cathode electrode.

20. A method for manufacturing a display device, the method comprising: each pixel is provided to include a pixel region having a first region and a second region spaced apart in a first direction, Wherein, setting the pixel comprises: forming a 1-1 electrode and a 2-1 electrode spaced apart in a second direction different from the first direction in the first region, and forming a 1-2 electrode and a 2-2 electrode spaced apart in the second direction in the second region; forming an insulating material layer on the 1-1 electrode and the 2-1 electrode and the 1-2 electrode and the 2-2 electrode; aligning a light emitting element on the insulating material layer; forming an insulating layer by removing a portion of the insulating material layer, the insulating layer comprising a first opening exposing a portion of the 1-1 electrode and a second opening exposing a portion of the 2-2 electrode; and Contact electrodes are formed on the 1-1 electrode and the 2-1 electrode and the 1-2 electrode and the 2-2 electrode respectively, and an intermediate electrode is formed to connect the contact electrode on the 2-1 electrode and the contact electrode on the 1-2 electrode, wherein: The insulating layer completely covers the 2-1 electrode and the 1-2 electrode, and The 2-1 electrode is electrically insulated from the contact electrode on the 2-1 electrode, and the 1-2 electrode is electrically insulated from the contact electrode on the 1-2 electrode.

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