All-optical logic OR gate structure based on topological edge states of valley photonic crystals

Abstract

The present invention relates to the field of topological photonics and optical communication systems, and discloses a silicon-based valley photonic crystal structure for realizing an all-optical logic OR gate, comprising a silicon substrate, wherein the silicon substrate is divided into four regions by three dividing lines; first circular air holes and fourth air holes are staggered in the four regions, and defects are arranged at the dividing lines to respectively form INA and INB input waveguides, and OUT1 and OUT2 output waveguides; the present invention can be used to realize the function of an all-optical logic OR gate, realizes the logic OR function by inputting light of different wavelengths at dual input ends, and when the output of the OUT1 output waveguide is logic 1, the transmittance is high, both above 0.8, and the logic contrast is high.

Description

Technical Field

[0001] The present invention relates to the fields of topological photonics and optical communication systems, and in particular to an all-optical logic OR gate based on topological edge states of valley photonic crystals. Background Art

[0002] The development trend of optical quantum computing and optical communication systems is the miniaturization and integration of optical quantum technology, and all-optical logic gates are the basic components of optical signal processors and optical communication systems, and are key devices in optical quantum computing chips. However, in the current optical information processing process, due to the use of electronic logic gates, it is necessary to always use complex and cumbersome electro-optical conversion. Therefore, strict requirements are placed on the design of all-optical logic gates.

[0003] A logic gate with ideal performance is one that performs operations on Boolean values ​​in the abstract, it should not dissipate power and change state instantaneously, similar to a step function. Such gates operate on discrete logic inputs and should not have propagation delays. For all-optical logic gates, propagation delays can be ignored due to the high speed of light. In addition, power consumption can be minimized by achieving high transmittance. Moreover, for operation in photonic integrated circuits (PICs), logic gates should have miniaturized package forms. Finally, in general, for quantum computing, different spin states of light need to be used, and therefore, logic gates should have the chirality of spin-up (right-hand circular polarization, RCP) and spin-down (left-hand circular polarization, LCP) light.

[0004] Many all-optical logic gate designs have been demonstrated, such as semiconductor optical amplifiers (SOAs), periodically poled lithium niobate (PPLN) waveguides, ring resonators, and photonic crystals (PCs). The performance of logic gates based on SOAs is limited by spontaneous emission noise and high integration complexity. Logic gates based on semiconductor ring resonators have advantages such as simple structure and low input power, but are very slow. Logic gates based on PPLN waveguides have fast switching speeds and low spontaneous emission noise. However, these gates have a strong dependence on temperature and polarization, which limits their applications. The above logic gates are all relatively large in size and are not suitable for on-chip integration. In contrast, the use of nanostructures can significantly reduce the footprint of all-optical logic gates, and photonic crystal structures are the most widely used. Different effects of PCs have been applied to the design of logic gates, such as:

[0005] 1. Self-collimation effect; for example, in 2016, Fan Ranran and his colleagues (2D photonic crystal logic gatesbased on self-collimated effect, 2016, Journal Of Physics D-applied Physics, 49, 325104) proposed four logic gates that can be used in photonic integrated circuit design, namely NOT, OR, AND and XOR gates, by using the interference between self-collimated beams in photonic crystals. By adjusting the radius of the beam splitter and the optical path difference between the beam splitters, a certain phase difference is generated between the reflected beam and the transmitted beam, thereby generating constructive or destructive interference and realizing logical operations.

[0006] 2. Multi-mode interference effect: In 2014, Yin Hongxi's group (Design of all-optical logic gates avoiding external phase shifters in a two-dimensional photonic crystal based on multi-mode interference for BPSK signals, 2014, Journal Of Physics D-applied Physics, 49, 325104) proposed and designed several new structures of two-dimensional photonic crystal (PC) all-optical logic gates based on multi-mode interference (MMI). Between the two input ports of the photonic crystal device, a 3π / 2 phase shift is introduced through waveguides of different lengths at the two input ports, so that the logic gate can be directly used for the logic operation of binary phase shift keying (BPSK) signals. XOR, XNOR, OR and NAND logic gates were realized.

[0007] 3. Interference waveguide: In 2020, Dalai et al. (Performance analysis of all-optical NAND, NOR, and XNOR logic gates using photonic crystal waveguide for optical computing applications, 2020, 59(5):057101) proposed a photonic crystal structure that can realize logical functions such as NAND, NOR, and XNOR using the principle of waveguide interference. However, the contrast of the structure is not high, and light leaks from other waveguides.

[0008] 4. Nonlinear effect: In 2014, Lin et al. (Design and Optimization of All-optical AND and NOR Logic Gates in a Two-dimensional Photonic Crystal for Binary-Phase-Shift-Keyed Signals, 2014, 965-969) introduced nonlinear materials into two-dimensional photonic crystals and used the nonlinearity of the materials to realize AND and NOR logic functions. However, the structure requires a phase shifter. However, due to the loss caused by scattering, all designs still have relatively low transmittance.

[0009] Recent developments in topological photonic crystals (TPCs) allow for scattering-free transmission of topological edge states, which opens up new possibilities for the design of photonic devices. In different TPC designs, valley photonic crystals based on dielectric materials can be realized, pushing the operating wavelength to the telecommunications and visible light regions. If valley photonic crystals are used to design logic gates, it is expected to improve the transmittance of the logic gates and thus improve their logic contrast. Summary of the invention

[0010] The present invention overcomes the deficiencies of the prior art and aims to solve the technical problem of providing an all-optical logic OR gate structure based on the topological edge state of a valley photonic crystal to achieve an OR gate logic function with high contrast and high transmittance.

[0011] In order to solve the above technical problems, the technical solution adopted by the present invention is: an all-optical logic or gate structure based on the topological edge state of the valley photonic crystal, comprising a silicon substrate; the silicon substrate is divided into a first area, a second area, a third area and a fourth area by a first dividing line, a second dividing line and a third dividing line; the second dividing line is located on the straight line where the light incident direction is located, the first dividing line and the third dividing line are symmetrically arranged on both sides thereof, and one end thereof is connected to the middle part of the second dividing line, and the other end is inclined away from the light incident side, and then extends to the edge of the structure in a direction parallel to the first dividing line and close to the light incident side;

[0012] In the first region and the third region, the first circular air holes and the fourth circular air holes are respectively arranged in a triangular lattice staggered to form a first energy valley type photonic crystal, and in the second region and the fourth region, the first circular air holes and the fourth circular air holes are respectively arranged in a triangular lattice staggered to form a second energy valley type photonic crystal; and the pattern distribution in the second region and the third region is symmetrical about the second dividing line, and the pattern distribution in the first region and the fourth region is symmetrical about the second dividing line;

[0013] A row of first circular air holes is arranged near the first dividing line in the first region and the second region respectively to form an INA input waveguide, and the first circular air holes arranged near the third dividing line in the third region and the fourth region are set as third circular air holes to form an INB input waveguide; the first circular air holes arranged near the second dividing line in the first region and the fourth region are set as second circular air holes to form an OUTI output waveguide, and a row of fourth circular air holes arranged near the second dividing line in the second region and the third region respectively are removed to form an OUT2 output waveguide;

[0014] The radii of the first circular air hole, the second circular air hole, the third circular air hole and the fourth circular air hole are r1, r2, r3 and r4 respectively, which satisfy the condition: r1>r2>r3>r4.

[0015] The lattice constant of the triangular lattice formed by the first circular air hole and the fourth circular air hole is both a=450nm.

[0016] The radii of the first circular air hole, the second circular air hole, the third circular air hole and the fourth circular air hole are 120 nm, 116 nm, 110 nm and 40 nm respectively.

[0017] The depths of the first circular air hole, the second circular air hole, the third circular air hole and the fourth circular air hole are equal to the thickness of the silicon substrate.

[0018] The thickness of the silicon substrate is 220 nm.

[0019] The refractive index of the silicon substrate is 3.48, and the refractive indexes of the first circular air hole, the second circular air hole, the third circular air hole and the fourth circular air hole are 1.

[0020] The wavelength of light input from the INA input waveguide is 1490 nm, and the wavelength of light input from the INB input waveguide is 1528 nm.

[0021] Compared with the prior art, the present invention has the following beneficial effects:

[0022] Compared with the existing all-optical logic gate devices based on photonic crystal resonant cavities, the present invention provides an all-optical logic OR gate structure based on the topological edge states of valley photonic crystals, which is not affected by the phase of the incident light wave, so there is no need to add a phase shifter, and a smaller structure can be designed; compared with the all-optical logic gate devices based on photonic crystal waveguide interference, it has higher transmission contrast of incident light transmission performance, can realize optical path control, and can be integrated in photonic chips to achieve high integration requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1A schematic diagram of a valley photonic crystal structure capable of realizing an all-optical logic OR gate function provided by an embodiment of the present invention;

[0024] Figure 2 A schematic diagram of an embodiment of the present invention providing a valley photonic crystal structure capable of realizing an all-optical logic OR gate function, in which the fourth circular air hole is not deleted in the INB input waveguide.

[0025] Figure 3 : is the energy band diagram of the valley photonic crystal VPC1 according to an embodiment of the present invention;

[0026] Figure 4 1 is an edge state energy band diagram of the INA input waveguide, the INB input waveguide, the OUT1 output waveguide, and the OUT2 output waveguide in an embodiment of the present invention;

[0027] Figure 5 The electric field distribution diagram when the light source is input to the INA input waveguide only at 1488nm, the electric field distribution diagram when the light source is input to the INB input waveguide only at 1528nm, and the electric field distribution diagram when the light sources are input to the INA and INB simultaneously at 1489nm and 1528nm;

[0028] Figure 6 is a transmission diagram of the waveguide output when the light source is input only to INA (1||0), when the light source is input only to INB (0||1), and when the light source is input to both INA and INB (1||1);

[0029] In the figure: 1 is the silicon substrate, 2 is the first dividing line, 3 is the second dividing line, 4 is the third dividing line, 5 is the first area, 6 is the second area, 7 is the third area, 8 is the fourth area, 9 is the first circular air hole, 10 is the second circular air hole, 11 is the third circular air hole, 12 is the fourth circular air hole, 13 is the INA input waveguide, 14 is the INB input waveguide, 15 is the OUTI output waveguide, and 16 is the OUT2 output waveguide. DETAILED DESCRIPTION

[0030] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all the embodiments; based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0031] like Figure 1As shown, an embodiment of the present invention provides an all-optical logic or gate structure based on the topological edge state of a valley photonic crystal, comprising a silicon substrate 1; the silicon substrate 1 is divided into a first region 5, a second region 6, a third region 7 and a fourth region 8 by a first dividing line 2, a second dividing line 3 and a third dividing line 4; the second dividing line 3 is located on a straight line where the light incident direction is located, the first dividing line 2 and the third dividing line 4 are symmetrically arranged on both sides thereof, and one end thereof is connected to the middle part of the second dividing line 3, and the other end is inclined away from the light incident side, and then extends to the edge of the structure in a direction parallel to the first dividing line 2 and close to the light incident side.

[0032] Specifically, the first dividing line 2 and the third dividing line 4 both include an inclined segment and a parallel segment, wherein one end of the inclined segment is connected to the middle of the second dividing line 3, and the other end is inclined away from the light incident side with an inclination angle of 60°, and one end of the parallel segment is connected to the other end of the inclined segment, and the other end of the parallel segment extends to the edge of the structure in a direction parallel to the first dividing line 2 and close to the light incident side.

[0033] Specifically, in the first region 5 and the third region 7, the first circular air hole 9 and the fourth circular air hole 12 are arranged in a triangular lattice to form a first energy valley type photonic crystal, and in the second region 6 and the fourth region 8, the first circular air hole 9 and the fourth circular air hole 12 are arranged in different triangular lattices to form a second energy valley type photonic crystal; and the pattern distribution in the second region 6 and the third region 7 is symmetrical about the second dividing line 3, and the pattern distribution in the first region 5 and the fourth region 8 is symmetrical about the second dividing line 3. Specifically, in this embodiment, the first energy valley type photonic crystal and the second energy valley type photonic crystal are mirror structures, that is, in the first energy valley type photonic crystal, in the minimum hexagonal honeycomb structure formed with the center of the first circular air hole as the vertex, the triangle formed by the fourth circular air hole is an inverted equilateral triangle, on the contrary, in the second energy valley type photonic crystal, in the minimum hexagonal honeycomb structure formed with the center of the first circular air hole as the vertex, the triangle formed by the fourth circular air hole is an upright equilateral triangle. One side of the equilateral triangle is parallel to the incident direction of the light beam.

[0034] Specifically, a row of first circular air holes 9 are arranged near the first dividing line 2 in the first area 5 and the second area 6 to form an INA input waveguide 13, and the first circular air holes 9 arranged near the third dividing line 4 in the third area 7 and the fourth area 8 are set as third circular air holes 11 to form an INB input waveguide 14; the first circular air holes 9 arranged near the second dividing line 3 in the first area 5 and the fourth area 8 are set as second circular air holes 10 to form an OUTI output waveguide 15, and a row of fourth circular air holes 12 arranged near the second dividing line 3 in the second area 6 and the third area 7 are removed to form an OUT2 output waveguide 16. Figure 2 shown.

[0035] Specifically, the radii of the first circular air hole 9 , the second circular air hole 10 , the third circular air hole 11 and the fourth circular air hole 12 are r1 , r2 , r3 and r4 respectively, which satisfy the condition: r1>r2>r3>r4.

[0036] Preferably, in this embodiment, before removing two rows of fourth circular air holes 12 from the OUT2 output waveguide 16, the centers of the circular air holes (including the first circular air holes 9, the second circular air holes 10, the third circular air holes 11 and the fourth circular air holes 12) in all regions (including the first region 5, the second region 6, the third region 7 and the fourth region 8) on the silicon substrate 1 all follow a uniform hexagonal honeycomb structure arrangement, and the side length of the hexagonal honeycomb is Wherein a represents the lattice constant of the triangular lattice formed by the first circular air holes 9 or the fourth circular air holes 12 .

[0037] Specifically, in this embodiment, the lattice constant of the triangular lattice formed by the first circular air hole 9 and the fourth circular air hole 12 is a=450 nm, wherein the lattice constant is the distance between the two closest identical circular air holes.

[0038] Specifically, in this embodiment, the radii of the first circular air hole 9 , the second circular air hole 10 , the third circular air hole 11 and the fourth circular air hole 12 are 120 nm, 116 nm, 110 nm and 40 nm respectively.

[0039] Specifically, in this embodiment, the depths of the first circular air hole 9 , the second circular air hole 10 , the third circular air hole 11 and the fourth circular air hole 12 are equal to the thickness of the silicon substrate 1 .

[0040] Specifically, in this embodiment, the thickness of the silicon substrate 1 is 220 nm, the refractive index of the silicon substrate 1 is 3.48, and the refractive index of the first circular air hole 9, the second circular air hole 10, the third circular air hole 11 and the fourth circular air hole 12 is 1.

[0041] Specifically, in this embodiment, the wavelength of light input from the INA input waveguide 13 is 1490 nm, and the wavelength of light input from the INB input waveguide 14 is 1528 nm.

[0042] The preparation method of an all-optical logic or gate structure based on the topological edge state of a valley photonic crystal provided by an embodiment of the present invention is implemented based on CMOS technology, and includes the following steps: first, a standard SOI wafer with a 220nm thick top silicon and a 3μm thick silicon dioxide layer is selected, and the first step is to coat a photoresist (ZEP520A) on the silicon surface, and then use electron beam lithography to expose the photoresist, and then use the photoresist as a mask layer for reactive ion etching. In this process, it is important to obtain a vertically etched side wall to maintain the mirror symmetry of the photonic crystal structure relative to the xy plane located in the middle of the photonic crystal plate. Then, on this basis, a photoresist is coated on the fabricated structure, and a pattern to be etched is made on the photoresist at the same time, and then the photoresist is used as a mask, and diluted hydrofluoric acid is used for etching for 15 minutes to remove the silicon dioxide substrate. This can obtain an all-optical or logic gate structure.

[0043] like Figure 3 As shown, it is the energy band diagram of the first energy valley photonic crystal in the embodiment of the present invention. In the figure, the shaded areas on both sides are air light cones. It can be seen that there is a TE mode band gap in the range of 1410nm-1676nm, which is marked by the thin line shaded area. The second energy valley photonic crystal has the same energy band structure as the first energy valley photonic crystal.

[0044] like Figure 4 As shown, it is the edge state energy band diagram of INA input waveguide, INB input waveguide, OUT1 output waveguide and OUT2 output waveguide in the embodiment of the present invention. The gray shaded areas above and below the figure are body bands, and the thick line shaded area on the left is the air light cone. It can be seen from the figure that the INA output waveguide and the INB output waveguide are in two different bands, while part of the band of the OUT1 output waveguide is in the band of the INA input waveguide, and the other part is in the band of the waveguide of the INB input waveguide. The waveguide of the OUT2 output waveguide is not in the band of the other three waveguides, and the edge state group velocity vector direction of the OUT2 output waveguide is opposite to that of the other three waveguides.

[0045] like Figure 5 As shown, (a) is the electric field distribution diagram of the input light source (1||0) at 1490nm only in the INA input waveguide, (b) is the electric field distribution diagram of the input light source (0||1) at 1528nm only in the INB input waveguide, (c) and (d) are the electric field distribution diagrams of the INA input waveguide and INB input waveguide when the light source (1||1) is input at 1490nm and 1528nm respectively.

[0046] like Figure 6As shown in the figure, the transmittance curves of the output of the OUT2 output waveguide for three input conditions are shown. 1||0 represents the input of the light source only in the INA input waveguide, 0||1 represents the input of the light source only in the INB input waveguide, and 1||1 represents the input of the light source in both the INA and INB input waveguides. Figure 5 It can be seen that when the light source (1||0) is input only into the INA input waveguide, the transmittance is as high as 0.86 at a wavelength of 1490nm. When the light source (0||1) is input only into the INB input waveguide, the transmittance is as high as 0.9 at a wavelength of 1528nm. The transmittance of the light source (1||1) input into both the INA input waveguide and the INB input waveguide at the same time is 0.82 and 0.81 at 1490nm and 1528nm, respectively.

[0047] The above data show that the all-optical logic OR gate structure based on the topological edge state of the valley photonic crystal provided by the present invention realizes the logic OR function when different wavelengths of light are input into the dual input ends, and the transmittance when the output of the OUT1 output waveguide is logic 1 is high, all above 0.8, and the logic contrast is high.

[0048] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. An all-optical logic OR gate structure based on the topological edge state of a valley photonic crystal, characterized in that: The invention comprises a silicon substrate (1); the silicon substrate (1) is divided into a first region (5), a second region (6), a third region (7) and a fourth region (8) by a first dividing line (2), a second dividing line (3) and a third dividing line (4); the second dividing line (3) is located on a straight line in the direction of light incidence, the first dividing line (2) and the third dividing line (4) are symmetrically arranged on both sides thereof, one end of the second dividing line (3) is connected to the middle of the second dividing line (3), and the other end is inclined away from the light incidence side and then extends to the edge of the structure in a direction parallel to the first dividing line (2) and close to the light incidence side; In the first region (5) and the third region (7), the first circular air holes (9) and the fourth circular air holes (12) are arranged in a triangular lattice to form a first energy valley type photonic crystal, and in the second region (6) and the fourth region (8), the first circular air holes (9) and the fourth circular air holes (12) are arranged in a triangular lattice to form a second energy valley type photonic crystal; and the pattern distribution in the second region (6) and the third region (7) is symmetrical about the second dividing line (3), and the pattern distribution in the first region (5) and the fourth region (8) is symmetrical about the second dividing line (3); A row of first circular air holes (9) are arranged near the first dividing line (2) in the first region (5) and the second region (6) to form an INA input waveguide (13); the first circular air holes (9) arranged near the third dividing line (4) in the third region (7) and the fourth region (8) are configured as third circular air holes (11) to form an INB input waveguide (14); the first circular air holes (9) arranged near the second dividing line (3) in the first region (5) and the fourth region (8) are configured as second circular air holes (10) to form an OUTI output waveguide (15); and a row of fourth circular air holes (12) arranged near the second dividing line (3) in the second region (6) and the third region (7) are removed to form an OUT2 output waveguide (16); The radii of the first circular air hole (9), the second circular air hole (10), the third circular air hole (11) and the fourth circular air hole (12) are r1, r2, r3 and r4 respectively, which satisfy the following conditions: r1>r2>r3>r4; and the depths of the first circular air hole (9), the second circular air hole (10), the third circular air hole (11) and the fourth circular air hole (12) are equal to the thickness of the silicon substrate (1).

2. According to claim 1, an all-optical logic OR gate structure based on topological edge states of valley photonic crystals is characterized in that: The lattice constant of the triangular lattice formed by the first circular air hole (9) and the fourth circular air hole (12) is both a=450nm.

3. According to claim 1, an all-optical logic OR gate structure based on topological edge states of valley photonic crystals is characterized in that: The radii of the first circular air hole (9), the second circular air hole (10), the third circular air hole (11) and the fourth circular air hole (12) are respectively 120 nm, 116 nm, 110 nm and 40 nm.

4. The all-optical logic OR gate structure based on the topological edge state of the valley photonic crystal according to claim 1, characterized in that: The thickness of the silicon substrate (1) is 220 nm.

5. The all-optical logic OR gate structure based on the topological edge state of the valley photonic crystal according to claim 1, characterized in that: The refractive index of the silicon substrate (1) is 3.48, and the refractive index of the first circular air hole (9), the second circular air hole (10), the third circular air hole (11) and the fourth circular air hole (12) is 1.

6. The all-optical logic OR gate structure based on the topological edge state of the valley photonic crystal according to claim 1, characterized in that: The wavelength of light input from the INA input waveguide (13) is 1490 nm, and the wavelength of light input from the INB input waveguide (14) is 1528 nm.

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