Signal generation circuit, microcontroller and control method

Abstract

A signal generating circuit, a microcontroller and a control method, the signal generating circuit comprising a first control circuit, a second control circuit, an arbitration circuit and a digital-to-analog conversion circuit, the first control circuit storing a first data string, the first control circuit enabling a first trigger signal when a first event occurs, the second control circuit storing a second data string, the second control circuit enabling a second trigger signal when a second event occurs, the arbitration circuit reading one of the first control circuit and the second control circuit according to a priority order when the first trigger signal and the second trigger signal are both enabled to use the first data string or the second data string as a digital input, the digital-to-analog conversion circuit converting the digital input to generate an analog output.

Description

TECHNICAL FIELD

[0001] The present application relates to a signal generation circuit, and more particularly to a signal generation circuit for generating an analog output. BACKGROUND

[0002] A conventional signal generation circuit generates an output signal according to an input data. The input data is provided by a specific data source. If the data source is desired to be changed, a central processing unit (CPU) is required to intervene to change the data source. When the intervention of the CPU is too frequent, the resources of the CPU are consumed and the system performance is degraded. SUMMARY

[0003] An embodiment of the present application provides a signal generation circuit, which includes a first control circuit, a second control circuit, an arbitration circuit, and a digital-to-analog conversion circuit. The first control circuit stores a first data string. When a first event occurs, the first control circuit enables a first trigger signal. The second control circuit stores a second data string. When a second event occurs, the second control circuit enables a second trigger signal. When the first trigger signal and the second trigger signal are both enabled, the arbitration circuit reads one of the first control circuit and the second control circuit according to a priority order to use the first or second data string as a digital input. The digital-to-analog conversion circuit converts the digital input to generate an analog output.

[0004] Another embodiment of the present application provides a microcontroller, which includes a CPU, a first peripheral circuit, a first control circuit, a second control circuit, an arbitration circuit, a digital-to-analog conversion circuit, and a second peripheral circuit. The first peripheral circuit is coupled to the CPU. The first control circuit is coupled to the first peripheral circuit and stores a first data string. When a first event occurs in the first peripheral circuit, the first control circuit enables a first trigger signal. The second control circuit is coupled to the first peripheral circuit and stores a second data string. When a second event occurs in the first peripheral circuit, the second control circuit enables a second trigger signal. When the first trigger signal and the second trigger signal are both enabled, the arbitration circuit reads one of the first control circuit and the second control circuit according to a priority order to use the first or second data string as a digital input. The digital-to-analog conversion circuit converts the digital input to generate an analog output. The second peripheral circuit is operated according to the analog output.

[0005] Another embodiment of the present application provides a control method, which is applicable to a microcontroller. The microcontroller includes a central processing unit. During an initial period: a first peripheral circuit is set up and a digital-to-analog conversion circuit is activated by the central processing unit. During an operation period: a first data string is written into a first control circuit; a second data string is written into a second control circuit; a first trigger signal is enabled when a first event occurs in the first peripheral circuit; a second trigger signal is enabled when a second event occurs in the first peripheral circuit; when both the first trigger signal and the second trigger signal are enabled, one of the first control circuit and the second control circuit is read according to a priority order to take the first or second data string as a digital input; and the digital input is converted to generate an analog output.

[0006] The control method of the present application can be implemented by the microcontroller and the signal generation circuit of the present application, which are hardware or firmware capable of performing specific functions, or can be implemented by program codes recorded in a recording medium and combined with specific hardware. When the program codes are loaded and executed by an electronic device, a processor, a computer or a machine, the electronic device, the processor, the computer or the machine become the microcontroller and the signal generation circuit of the present application for implementing the present application. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figure 1 a schematic diagram of the microcontroller of the present application;

[0008] Figure 2 a schematic diagram of the signal generation circuit of the present application;

[0009] Figure 3 a schematic diagram of the control method of the microcontroller of the present application.

[0010] [LIST OF SYMBOLS]

[0011] 100: microcontroller

[0012] 110: central processing unit

[0013] 120, 130, 150: peripheral circuit

[0014] 140, 200: signal generation circuit

[0015] SS1-SS3: set signal

[0016] EV1-EVn: event

[0017] DAC_OUT: analog output

[0018] 151: memory

[0019] 152, 210_1-210_n: control circuit

[0020] 220: arbitration circuit

[0021] 230: digital-analog conversion circuit

[0022] TR1-TRn: trigger signal

[0023] DGI: digital input

[0024] NT: notification signal

[0025] DT: data string

[0026] 231: controller

[0027] 232: digital-analog converter

[0028] DIN: input data

[0029] 233: counting circuit

[0030] 234: specific pin

[0031] pd: power-down signal

[0032] EN: enable signal

[0033] AVDD, DVDD, AGND, DGND: operating voltage

[0034] PON: power-on control signal

[0035] VREFP, VREFM: reference voltage DETAILED DESCRIPTION

[0036] In order to make the objects, features and advantages of the present application more obvious and easy to understand, examples are specifically given below, and detailed description is made with the aid of the accompanying drawings. The present application provides different examples to explain the technical features of different embodiments of the present application. The configuration of each element in the examples is for illustration, and is not intended to limit the present application. In addition, part of the reference numerals of the drawings in the examples is repeated, in order to simplify the description, and is not intended to mean the relevance between different examples.

[0037] Figure 1A schematic diagram of a microcontroller of the present application is shown in FIG. 1. As shown, the microcontroller 100 includes a central processing unit (CPU) 110, a peripheral circuit 120, 130, and a signal generation circuit 140. During an initialization period, the central processing unit 110 initializes the peripheral circuit 120 and the signal generation circuit 140. The present application does not limit how the central processing unit 110 initializes the peripheral circuit 120 and the signal generation circuit 140. In one possible embodiment, the central processing unit 110 can issue a set signal SS1 to enable logic circuits (not shown) within the peripheral circuit 120 and to set registers (not shown) within the peripheral circuit 120. In addition, the central processing unit 110 can issue a set signal SS2 to start the signal generation circuit 140.

[0038] The peripheral circuit 120 is coupled between the central processing unit 110 and the signal generation circuit 140. During the initialization period, the peripheral circuit 120 receives the set signal SS1 and sets internal registers according to the set signal SS1. Then, during an operation period, the peripheral circuit 120 starts to operate. In this embodiment, the central processing unit 110 does not interfere with the operation of the peripheral circuit 120 during the operation period. In other words, when the peripheral circuit 120 operates, the central processing unit 110 can be idle or enter a power saving mode. During the operation period, the peripheral circuit 120 performs at least one specific operation and generates an event after the specific operation is completed. In this embodiment, the peripheral circuit 120 can perform at least one specific operation to generate events EV1-EVn.

[0039] The present application does not limit the types of the events EV1-EVn. One of the events EV1-EVn can be the same as another one of the events EV1-EVn. For example, the event EV1 can be an overflow event of a count value of a timer circuit (not shown) within the peripheral circuit 120 reaching a first target value. The event EV2 can be an overflow event of the count value of the same timer circuit or another timer circuit within the peripheral circuit 120 reaching a second target value. The second target value can be different from the first target value. In this example, the events EV1 and EV2 are the same event (overflow event).

[0040] In other embodiments, one of the events EV1-EVn can be different from another of the events EV1-EVn. For example, event EV1 can refer to an overflow event of the timer circuit, and event EVn can refer to a level of a particular pin (not shown) within the peripheral circuit 120 being equal to a particular level (e.g., a high level or a low level). In some embodiments, at least one of the events EV1-EVn is triggered by software. In this example, event EV1 can refer to a particular software being started, or a controller (not shown) within the peripheral circuit 120 executing a particular program code.

[0041] The signal generation circuit 140 extracts a digital data string from the corresponding data source according to the event EV1-EVn, and converts the digital data string to generate an analog output DAC_OUT. For example, when event EV1 occurs, the signal generation circuit 140 reads a first data string from a first data source, and converts the first data string to generate the analog output DAC_OUT. When event EV2 occurs, the signal generation circuit 140 reads a second data string from a second data source, and converts the second data string to generate the analog output DAC_OUT.

[0042] Since the signal generation circuit 140 selects the corresponding data source according to the event occurring without the intervention of the central processing unit 110, the central processing unit 110 can enter a power saving mode after initializing the peripheral circuit 120, thereby reducing the power consumption of the microcontroller 100. In other embodiments, the central processing unit 110 is in an idle state when the signal generation circuit 140 is operating. In addition, since the central processing unit 110 does not need to control the signal generation circuit 140, the central processing unit 110 can perform other operations. Therefore, the performance of the microcontroller 100 is greatly improved.

[0043] Further, since the signal generation circuit 140 generates the analog output according to the data string of different data sources, the signal generation circuit 140 can generate many waveforms with different slopes. For example, when the signal generation circuit 140 generates the analog output according to the plurality of data strings of the first data source, the analog output DAC_OUT has a first slope. When the signal generation circuit 140 generates the analog output according to the plurality of data strings of the second data source, the analog output DAC_OUT has a second slope. In this example, the first slope is different from the second slope.

[0044] The peripheral circuit 130 operates according to the analog output DAC_OUT. The present application does not limit the type of the analog output DAC_OUT. In one possible embodiment, the analog output DAC_OUT is a reference voltage. In other embodiments, the microcontroller 100 further comprises a peripheral circuit 150. The peripheral circuit 150 comprises a memory 151 and a control circuit 152. In this example, the central processor 110 uses the setting signal SS3 to instruct the control circuit 152 to read the memory 151 so as to transfer the data string stored in the memory 151 to the corresponding data source in the signal generation circuit 140.

[0045] Suppose the memory 151 stores a first data string, a second data string, a third data string and a fourth data string. The central processor 110 uses the setting signal SS3 to assign the first and third data strings to the first data source in the signal generation circuit 140, and to assign the second and fourth data strings to the second data source in the signal generation circuit 140. In one possible embodiment, the control circuit 152 can first store the first and second data strings to the first and second data sources in the signal generation circuit 140. Then, when the event EV1 occurs, the signal generation circuit 140 reads and converts the first data string in the first data source. When the signal generation circuit 140 starts converting the first data string, the control circuit 152 transfers the third data string in the memory 151 to the first data source so as to replace the first data string. At this time, if the event EV1 occurs again, the signal generation circuit 140 reads and converts the third data string in the first data source. However, if the event EV2 occurs, the signal generation circuit 140 reads and converts the second data string in the second data source. When the signal generation circuit 140 starts converting the second data string, the control circuit 152 transfers the fourth data string in the memory 151 to the second data source so as to replace the second data string.

[0046] The present application does not limit the type of the memory 151. In one possible embodiment, the memory 151 is a static random access memory (SRAM). The present application also does not limit the architecture of the control circuit 152. In one possible embodiment, the control circuit 152 is a peripheral direct memory access (PDMA) controller.

[0047] During an initial period, the central processor 110 uses the setting signals SS1-SS3 to initialize the peripheral circuit 120, the signal generation circuit 140 and the peripheral circuit 150. Then, during an operation period, the peripheral circuit 120, the signal generation circuit 140 and the peripheral circuit 150 operate according to the information informed by the central processor 110 during the initial period. During the operation period, the central processor 110 does not intervene the operation of the peripheral circuit 120, the signal generation circuit 140 and the peripheral circuit 150.

[0048] Figure 2 Figure 2 is a schematic diagram of a signal generation circuit according to the present application. As shown, the signal generation circuit 200 includes control circuits 210_1-210_n, an arbitration circuit 220, and a digital-to-analog conversion circuit 230. Since the control circuits 210_1-210_n operate similarly, only control circuits 210_1 and 210_2 are described below. The control circuit 210_1 stores a first data string, and the control circuit 210_2 stores a second data string. In one possible embodiment, the control circuit 210_1 acts as a first data source, and the control circuit 210_2 acts as a second data source. In addition, the control circuit 210_1 receives an event EV1, and the control circuit 210_2 receives an event EV2. When the event EV1 occurs, the control circuit 210_1 enables a trigger signal TR1. When the event EV2 occurs, the control circuit 210_2 enables a trigger signal TR2.

[0049] The arbitration circuit 220 is coupled to the control circuits 210_1-210_n to receive the trigger signals TR1-TRn. In the present embodiment, the arbitration circuit 220 stores a priority. The priority is related to the priority weight of the control circuits 210_1-210_n. When multiple trigger signals are enabled, the arbitration circuit 220 reads the corresponding control circuit according to the priority to use the data string stored by the control circuit as a digital input DGI. For example, assume that the control circuit 210_1 has the highest priority weight, the control circuit 210_2 has the second highest priority weight, and the control circuit 210_n has the lowest priority weight. In this example, when the trigger signals TR1 and TR2 are enabled, the arbitration circuit 220 reads the control circuit 210_1 to use the first data string stored by the control circuit 210_1 as the digital input DGI.

[0050] In this embodiment, arbitration circuit 220 also receives a notification signal NT. When notification signal NT is enabled, arbitration circuit 220 determines which trigger signal is enabled. If only a single trigger signal is enabled, arbitration circuit 220 reads the data string of the corresponding control circuit. If multiple trigger signals are enabled, arbitration circuit 220 reads the data string of the control circuit with the highest priority weight according to the priority order. For example, if only trigger signal TR2 is enabled, arbitration circuit 220 reads the data string of control circuit 210_2 for updating digital input DGI. Arbitration circuit 220 can directly use the second data string stored by control circuit 210_2 as digital input DGI. However, if trigger signals TRl and TR2 are both enabled upon receiving notification signal NT, arbitration circuit 220 still reads the data string of control circuit 210_1 and uses the data string stored by control circuit 210_1 as digital input DGI because control circuit 210_1 has a higher priority weight than control circuit 210_2. In some embodiments, if only a single trigger signal is enabled, arbitration circuit 220 uses the data string of the corresponding control circuit as digital input DGI.

[0051] In one possible embodiment, after arbitration circuit 220 uses the first data string stored by control circuit 210_1 as digital input DGI, arbitration circuit 220 stores the data string DT provided by external peripheral device (e.g., 150) to control circuit 210_1 for updating the data string stored by control circuit 210_1. Since central processing unit 110 has previously filled the data strings intended for control circuits 210_1 through 210_n at specific addresses of memory 151, peripheral circuit 150 updates the data string of the corresponding control circuit through arbitration circuit 220 after arbitration circuit 220 outputs the corresponding data string. In other embodiments, peripheral circuit 150 can directly provide data string DT to the corresponding control circuit.

[0052] Digital-to-analog conversion circuit 230 converts digital input DGI to generate analog output DAC_OUT. The present application does not limit the architecture of digital-to-analog conversion circuit 230. In this embodiment, digital-to-analog conversion circuit 230 includes a controller 231 and a digital-to-analog converter 232. Controller 231 generates an input data DIN according to digital input DGI. In one possible embodiment, controller 231 is a digital-to-analog conversion controller (DAC controller). Digital-to-analog converter 232 converts input data DIN to generate analog output DAC_OUT. In one possible embodiment, digital-to-analog converter 232 is a resistive digital-to-analog converter (RDAC).

[0053] In other embodiments, the controller 231 has a counting circuit 233. When the digital-to-analog converter 232 starts to convert the input data DIN, the counting circuit 233 performs a counting operation. When the counting circuit 233 performs the counting operation for a set time (e.g., 5 seconds), it indicates that the digital-to-analog converter 232 has completed the conversion operation. Thus, the counting circuit 233 enables the notification signal NT to instruct the arbitration circuit 220 to read the corresponding control circuit according to the trigger signals TR1-TRn and the weights of the control circuits 210_1-210_n. In some embodiments, the counting circuit 233 can be independent of the controller 231.

[0054] In one possible embodiment, the controller 231 also provides a power down signal pd to the digital-to-analog converter 232. When the power down signal pd is enabled, the digital-to-analog converter 232 stops operating. At this time, the digital-to-analog converter 232 can enter a power saving mode. In addition, the controller 231 can provide an enable signal EN to enable the digital-to-analog converter 232.

[0055] In other embodiments, the digital-to-analog converter 232 also receives operating voltages AVDD, DVDD, AGND, and DGND. The operating voltages AVDD and AGND are used for analog components inside the digital-to-analog converter 232, where the operating voltage AVDD is higher than the operating voltage AGND. The operating voltages DVDD and DGND are used for digital components inside the digital-to-analog converter 232, where the operating voltage DVDD is higher than the operating voltage DGND.

[0056] In some embodiments, the digital-to-analog converter 232 also receives a power on control signal PON. When the operating voltages AVDD, DVDD, AGND, and DGND are not stable, the power on control signal PON is disabled. Thus, the digital-to-analog converter 232 does not operate. When the operating voltages AVDD, DVDD, AGND, and DGND are stable, the power on control signal PON is enabled. Thus, the digital-to-analog converter 232 starts operating.

[0057] In other embodiments, the digital-to-analog converter 232 also receives reference voltages VREFP and VREFM. The reference voltage VREFP can come from a specific pin 234. The digital-to-analog converter 232 can have a resistor string. The resistor string receives the reference voltages VREFP and VREFM and performs a voltage dividing operation on the reference voltage VREFP to generate a number of divided voltages. In one possible embodiment, the digital-to-analog converter 232 selects a corresponding divided voltage according to the input data DIN and uses the divided voltage as the analog output DAC_OUT.

[0058] During an initial period, the central processing unit 110 enables the digital-to-analog converter circuit 230. Therefore, the digital-to-analog converter circuit 230 begins operation. During an operational period, the central processing unit 110 does not intervene in the operation of the control circuits 210_1 to 210_n, the arbitration circuit 220, and the digital-to-analog converter circuit 230. During this period, the central processing unit 110 may operate in a power-saving mode. In other embodiments, the central processing unit 110 is in an idle state when the control circuits 210_1 to 210_n, the arbitration circuit 220, and the digital-to-analog converter circuit 230 are operating.

[0059] Additionally, during operation, when trigger signal TR1 is enabled and trigger signals TR2 to TRn are disabled, arbitration circuit 220 reads control circuit 210_1 to use the data string (or first data string) stored in control circuit 210_1 as digital input DGI. At this time, when arbitration circuit 220 uses the first data string as digital input DGI, control circuit 210_1 reads and stores a data string (or third data string) from an external memory (such as 151).

[0060] During operation, when trigger signal TR2 is enabled and trigger signals TR1 and TR3-TRn are disabled, arbitration circuit 220 reads control circuit 210_2 to use the data string (or second data string) of control circuit 210_2 as digital input DGI. When arbitration circuit 220 uses the second data string as digital input DGI, control circuit 210_2 reads and stores the data string (or fourth data string) from external memory.

[0061] Figure 3 This is a schematic diagram of the control method of the microcontroller of the present invention. During an initial period 310, step S311 is executed. During an operation period 320, steps S321 to 323 are executed. Step S311 uses a central processing unit to set up a peripheral circuit and activate a digital-to-analog converter circuit. Step S321 writes the data string into the corresponding control circuit. Step S322 determines whether an event has occurred. When an event occurs, step S323 reads and converts the data string of the corresponding control circuit.

[0062] by Figure 1 For example, in step S311, the central processing unit 110 sets the peripheral circuit 120 and activates the digital-to-analog conversion circuit in the signal generation circuit 140. The present invention does not limit how the central processing unit 110 sets the peripheral circuit 120. In one possible embodiment, the central processing unit 110 sets the value of a register in the peripheral circuit 120. In this example, the peripheral circuit 120 operates according to the value of the register.

[0063] by Figure 2For example, step S321 writes the data strings into the control circuits 210_1 to 210_n. Step S322 determines whether the events EV1 to EVn have occurred based on the trigger signals TR1 to TRn. For example, when the trigger signal TR1 is enabled, it indicates that the event EV1 has occurred. Similarly, when the trigger signal TR2 is enabled, it indicates that the event EV2 has occurred. Step S323 converts the corresponding data string based on the occurred event to generate an analog output. For example, when the event EV1 has occurred and the events EV2 to EVn have not occurred, the arbitration circuit 220 takes the data string (or first data string) of the control circuit 210_1 as a digital input DGI. The digital-to-analog conversion circuit 230 converts the digital input DGI to generate the analog output DAC_OUT. Similarly, if only the event EV2 has occurred, the arbitration circuit 220 takes the data string (or second data string) of the control circuit 210_2 as the digital input DGI.

[0064] However, when multiple trigger signals are enabled, step S323 reads the corresponding control circuit based on a priority order. For example, when the trigger signals TR1 and TR2 are enabled, if the priority order indicates that the control circuit 210_1 has a higher priority weight than the control circuit 210_2, the arbitration circuit 220 takes the data string of the control circuit 210_1 with the higher priority weight as the digital input DGI. In this example, the priority order can be stored in the arbitration circuit 220 or in a memory external to the arbitration circuit 220. In other embodiments, after the arbitration circuit 220 takes the data string of the control circuit 210_1 as the digital input DGI, if the trigger signals TR1 and TR2 are still enabled, the arbitration circuit 220 again takes the data string of the control circuit 210_1 as the digital input DGI. In this example, after the arbitration circuit 220 takes the data string of the control circuit 210_1 as the digital input DGI, if only the trigger signal TR2 is enabled, the arbitration circuit 220 takes the data string of the control circuit 210_2 as the digital input DGI.

[0065] In this embodiment, during the operation period 320, steps S321 to S323 are performed without intervention of the central processing unit 110. Therefore, during the operation period 320, the central processing unit can enter an idle state or enter a power saving mode. In other embodiments, step S323 updates the data string of the corresponding control circuit when the digital-to-analog conversion circuit 230 converts the digital input DGI.

[0066] For example, when the arbitration circuit 220 takes the data string of the control circuit 210_1 as the digital input DGI, the step S323 writes a new data string (or a third data string) to the control circuit 210_1. Similarly, when the arbitration circuit 220 takes the data string of the control circuit 210_2 as the digital input DGI, the step S323 writes a new data string (or a fourth data string) to the control circuit 210_2.

[0067] The control method of the present application, or a specific form or part thereof, can exist in the form of program code. The program code can be stored in a physical medium, such as a floppy disk, an optical disk, a hard disk, or any other machine-readable (e.g., computer-readable) storage medium, or is not limited to an external form of computer program product, wherein when the program code is loaded and executed by a machine, such as a computer, the machine becomes a microcontroller for participating in the present application. The program code can also be transmitted through some transmission medium, such as a wire or cable, an optical fiber, or any transmission form, wherein when the program code is received, loaded and executed by a machine, such as a computer, the machine becomes a microcontroller for participating in the present application. When implemented in a general-purpose processing unit, the program code combines the processing unit to provide a unique device whose operation is similar to that of an application-specific logic circuit.

[0068] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. In addition, unless explicitly stated otherwise, the definitions of words in common dictionaries should be interpreted consistent with their meanings in articles related to the technical field, and should not be interpreted as ideal states or overly formal language. Although the terms "first", "second", etc. can be used to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another.

[0069] Although the present application has been disclosed in the above-mentioned preferred embodiments, it is not intended to limit the present application, and anyone having ordinary knowledge in the art can make some changes and modifications without departing from the scope of the present application. For example, the system, device or method described in the embodiments of the present application can be implemented in a physical embodiment of hardware, software or a combination of hardware and software.

Claims

1. A signal generation circuit, characterized in that, include: A first control circuit stores a first data string and enables a first trigger signal when a first event occurs. A second control circuit stores a second data string and enables a second trigger signal when a second event occurs. An arbitration circuit, when both the first trigger signal and the second trigger signal are enabled, reads one of the first control circuit and the second control circuit according to a priority order, and uses the first data string or the second data string as a digital input. as well as A digital-to-analog converter circuit converts the digital input to generate an analog output, and includes: A counting circuit performs a counting operation. When the counting circuit performs the counting operation for a set time, the counting circuit enables a notification signal to command the arbitration circuit to read one of the first control circuit and the second control circuit according to the first trigger signal and the second trigger signal.

2. The signal generation circuit according to claim 1, characterized in that, When the first trigger signal is enabled and the second trigger signal is not enabled, the arbitration circuit reads the first control circuit to use the first data string as the digital input.

3. The signal generation circuit according to claim 2, characterized in that, When the arbitration circuit uses the first data string as the digital input, the first control circuit stores a third data string in an external memory.

4. The signal generation circuit according to claim 3, characterized in that, When the second trigger signal is enabled and the first trigger signal is not enabled, the arbitration circuit reads the second control circuit to use the second data string as the digital input.

5. The signal generation circuit according to claim 4, characterized in that, When the arbitration circuit uses the second data string as the digital input, the second control circuit stores a fourth data string in the external memory.

6. The signal generation circuit according to claim 1, characterized in that, After the digital-to-analog conversion circuit generates the analog output, the arbitration circuit reads one of the first control circuit and the second control circuit according to the first trigger signal and the second trigger signal, in order to update the digital input.

7. A microcontroller, characterized in that, include: One central processing unit; A first peripheral circuit is coupled to the central processing unit; A first control circuit is coupled to the first peripheral circuit and stores a first data string. When a first event occurs in the first peripheral circuit, the first control circuit enables a first trigger signal. A second control circuit is coupled to the first peripheral circuit and stores a second data string. When a second event occurs in the first peripheral circuit, the second control circuit enables a second trigger signal. An arbitration circuit, when both the first trigger signal and the second trigger signal are enabled, reads one of the first control circuit and the second control circuit according to a priority order, and uses the first data string or the second data string as a digital input. A digital-to-analog converter circuit converts the digital input to generate an analog output, and includes: A counting circuit that performs a counting operation; and A second peripheral circuit operates according to the analog output. When the counting circuit performs the counting operation for a set time, the counting circuit enables a notification signal to command the arbitration circuit to read one of the first control circuit and the second control circuit according to the first trigger signal and the second trigger signal.

8. The microcontroller according to claim 7, characterized in that, During an initial period, the central processing unit sets up the first peripheral circuit and the digital-to-analog conversion circuit. During an operation period, the first peripheral circuit, the first control circuit, the second control circuit, the arbitration circuit, and the digital-to-analog conversion circuit begin to operate. During the operation period, the central processing unit does not intervene in the operation of the first control circuit, the second control circuit, the arbitration circuit, and the digital-to-analog conversion circuit.

9. A control method, characterized in that, Applicable to a microcontroller, the microcontroller including a central processing unit, the control method includes: During an initial period: Using the central processing unit, a first peripheral circuit is set up, and a digital-to-analog conversion circuit is activated; During an operation: Write a first data string into a first control circuit; Write a second data string into a second control circuit; When a first event occurs in the first peripheral circuit, a first trigger signal is enabled; When a second event occurs in the first peripheral circuit, a second trigger signal is enabled; When both the first trigger signal and the second trigger signal are enabled, one of the first control circuit and the second control circuit is read according to a priority order to use the first data string or the second data string as a digital input. The digital input is converted to produce an analog output; When converting the digital input, a counting operation is performed; and When the counting operation reaches a set time, one of the first control circuit and the second control circuit is read according to the first trigger signal and the second trigger signal.

10. The control method according to claim 9, characterized in that, When the first trigger signal is enabled and the second trigger signal is not enabled, the first control circuit is read to use the first data string as the digital input; when the second trigger signal is enabled and the first trigger signal is not enabled, the second control circuit is read to use the second data string as the digital input.

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