A method, device, equipment and medium for envelope control of a three-level ANPC circuit

Abstract

The application discloses a clamp control method, device and equipment of a three-level ANPC circuit and a medium, and belongs to the technical field of power electronics. The method comprises the following steps: monitoring the driving signal level state and its duration of the three-level ANPC circuit in real time; when the three-level ANPC circuit fails, determining the driving signal level state corresponding to the three-level ANPC circuit when the three-level ANPC circuit fails; and based on the principle of sequentially turning off the outer tube, the inner tube and the clamping tube of the three-level ANPC circuit, and according to the driving signal level state corresponding to the three-level ANPC circuit when the three-level ANPC circuit fails and the duration thereof, the clamp control is performed on the three-level ANPC circuit. By the method, the protection action time of the three-level ANPC circuit when the three-level ANPC circuit encounters a fault can be further shortened.

Description

Technical Field

[0001] This invention relates to the field of power electronics technology, and in particular to a method, apparatus, equipment and medium for blocking control of a three-level ANPC circuit. Background Technology

[0002] In the existing technology, when a three-level ANPC (Active Neutral point Clamp) circuit fails, in order to ensure the reliability of the three-level ANPC circuit during the blocking process, it is usually necessary to perform the blocking operation on the three-level ANPC circuit according to the following turn-off strategy: first turn off the outer transistor, then turn off the inner transistor, and finally turn off the clamping transistor.

[0003] However, this blocking strategy for three-level ANPC circuits fails to consider the level switching states of the circuit when encountering a fault. Therefore, it cannot combine the on / off states of the corresponding switching transistors under each level switching state to perform blocking operations. It mechanically follows a turn-off strategy of first turning off the outer transistor, then the inner transistor, and finally the clamping transistor. This results in a longer protection action time for the three-level ANPC circuit when encountering a fault. Currently, there is no effective solution to this technical problem. Summary of the Invention

[0004] In view of this, the purpose of this invention is to provide a method, apparatus, device, and medium for blocking control of a three-level ANPC circuit, so as to shorten the protection action time of the three-level ANPC circuit when encountering a fault. The specific solution is as follows:

[0005] A method for blocking control of a three-level ANPC circuit includes:

[0006] Real-time monitoring of the driving signal level and duration of the three-level ANPC circuit;

[0007] When the three-level ANPC circuit fails, the driving signal level state corresponding to the failure of the three-level ANPC circuit is determined.

[0008] Based on the principle of sequentially turning off the outer transistor, inner transistor, and clamping transistor of the three-level ANPC circuit, and according to the driving signal level state and duration corresponding to the fault of the three-level ANPC circuit, the three-level ANPC circuit is subjected to wave blocking control.

[0009] Preferably, the three-level ANPC circuit includes: three bridge arm circuits with the same structure, each bridge arm circuit being provided with a first outer tube, a second outer tube, a first inner tube, a second inner tube, a first clamping tube, and a second clamping tube;

[0010] Wherein, the first end of the first outer tube is connected to the positive terminal of the busbar, the second end of the first outer tube is connected to the first end of the first inner tube, the second end of the first inner tube is connected to the first end of the second inner tube, the second end of the second inner tube is connected to the first end of the second outer tube, the second end of the second outer tube is connected to the negative terminal of the busbar, the first end of the first clamping tube is connected to the second end of the first outer tube, the second end of the first clamping tube is connected to the first end of the second clamping tube, and the second end of the second clamping tube is connected to the second end of the second inner tube;

[0011] Correspondingly, the second end of the first clamping tube is connected to the midpoint of the busbar, and the second end of the first inner tube is the output terminal of the bridge arm circuit.

[0012] Preferably, the process of controlling the three-level ANPC circuit by sequentially turning off the outer transistor, inner transistor, and clamping transistor in the three-level ANPC circuit, and by controlling the three-level ANPC circuit to block out signals according to the driving signal level state and duration corresponding to the fault in the three-level ANPC circuit, includes:

[0013] When the three-level ANPC circuit malfunctions in the P-level state of the target phase, the first external transistor of the target phase is turned off at the moment of the malfunction. When the first external transistor of the target phase is in the off state, the first internal transistor of the target phase is turned off. And when the first internal transistor of the target phase is in the off state, the second clamping transistor of the target phase is turned off.

[0014] When the three-level ANPC circuit fails in the N-level state of the target phase, the second external transistor of the target phase is turned off at the moment of the fault. When the second external transistor of the target phase is in the off state, the second internal transistor of the target phase is turned off. And when the second internal transistor of the target phase is in the off state, the first clamping transistor of the target phase is turned off.

[0015] When the three-level ANPC circuit fails in the 0+ level state of the target phase, the first inner tube of the target phase is turned off at the moment of the fault, and when the first inner tube of the target phase is in the off state, the first clamping tube and the second clamping tube of the target phase are turned off.

[0016] When the three-level ANPC circuit fails in the 0-level state of the target phase, the second inner tube of the target phase is turned off at the moment of the fault, and when the second inner tube of the target phase is in the off state, the first clamping tube and the second clamping tube of the target phase are turned off.

[0017] Preferably, the process of controlling the three-level ANPC circuit by sequentially turning off the outer transistor, inner transistor, and clamping transistor in the three-level ANPC circuit, and by controlling the three-level ANPC circuit to block out signals according to the driving signal level state and duration corresponding to the fault in the three-level ANPC circuit, includes:

[0018] When the three-level ANPC circuit malfunctions during the process of the target phase switching from P level to 0+ level, the first inner tube of the target phase is turned off when the first outer tube of the target phase reaches the first preset threshold, and the second clamping tube of the target phase is turned off when the first inner tube of the target phase is in the off state.

[0019] When the three-level ANPC circuit malfunctions during the transition of the target phase from 0+ level to P level, the first inner transistor of the target phase is turned off at the moment of the malfunction, and the second clamping transistor of the target phase is turned off when the first inner transistor of the target phase is in the off state.

[0020] Preferably, the process of controlling the three-level ANPC circuit by sequentially turning off the outer transistor, inner transistor, and clamping transistor in the three-level ANPC circuit, and by controlling the three-level ANPC circuit to block out signals according to the driving signal level state and duration corresponding to the fault in the three-level ANPC circuit, includes:

[0021] When the three-level ANPC circuit malfunctions during the process of the target phase switching from N level to 0- level, the second inner tube of the target phase is turned off when the second outer tube of the target phase reaches the second preset threshold, and the first clamping tube of the target phase is turned off when the second inner tube of the target phase is in the off state.

[0022] When the three-level ANPC circuit malfunctions during the transition of the target phase from 0-level to N-level, the first inner transistor of the target phase is turned off at the moment of the malfunction, and the second clamping transistor of the target phase is turned off when the first inner transistor of the target phase is in the off state.

[0023] Preferably, the process of controlling the three-level ANPC circuit by sequentially turning off the outer transistor, inner transistor, and clamping transistor in the three-level ANPC circuit, and by controlling the three-level ANPC circuit to block out signals according to the driving signal level state and duration corresponding to the fault in the three-level ANPC circuit, includes:

[0024] When the three-level ANPC circuit malfunctions during the process of the target phase switching from 0+ level to 0- level, the first inner tube and the second inner tube of the target phase are turned off at the moment of the malfunction, and when the first inner tube and the second inner tube of the target phase are in the off state, the first clamping tube and the second clamping tube of the target phase are turned off.

[0025] When the three-level ANPC circuit malfunctions during the transition of the target phase from 0- level to 0+ level, the first and second inner tubes of the target phase are turned off at the moment of the malfunction, and the first and second clamping tubes of the target phase are turned off when the first and second inner tubes of the target phase are in the off state.

[0026] Preferably, the process of controlling the three-level ANPC circuit by sequentially turning off the outer transistor, inner transistor, and clamping transistor in the three-level ANPC circuit, and by controlling the three-level ANPC circuit to block out signals according to the driving signal level state and duration corresponding to the fault in the three-level ANPC circuit, includes:

[0027] When the three-level ANPC circuit malfunctions during the process of the target phase switching from 0+ level to P level, the first inner transistor of the target phase is turned off at the moment of the malfunction, and the second clamping transistor of the target phase is turned off when the first inner transistor of the target phase is in the off state.

[0028] When the three-level ANPC circuit malfunctions during the transition of the target phase from 0-level to N-level, the second inner transistor of the target phase is turned off at the moment of the malfunction, and the first clamping transistor of the target phase is turned off when the second inner transistor of the target phase is in the off state.

[0029] Accordingly, the present invention also discloses a blocking control device for a three-level ANPC circuit, comprising:

[0030] The status monitoring module is used to monitor the level status and duration of the drive signal of the three-level ANPC circuit in real time.

[0031] The level determination module is used to determine the driving signal level state corresponding to the fault of the three-level ANPC circuit when the three-level ANPC circuit fails.

[0032] The blocking control module is used to control the blocking of the three-level ANPC circuit based on the principle of sequentially turning off the outer tube, inner tube and clamping tube of the three-level ANPC circuit, and according to the driving signal level state and duration corresponding to the fault of the three-level ANPC circuit.

[0033] Accordingly, the present invention also discloses a blocking control device for a three-level ANPC circuit, comprising:

[0034] Memory, used to store computer programs;

[0035] A processor is configured to implement the steps of a blocking control method for a three-level ANPC circuit as disclosed above when executing the computer program.

[0036] Accordingly, the present invention also discloses a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of a blocking control method for a three-level ANPC circuit as disclosed above.

[0037] As can be seen, in the blocking control method provided by this invention, the driving signal level state and its duration of the three-level ANPC circuit are first monitored in real time. When a fault occurs in the three-level ANPC circuit, the driving signal level state corresponding to the fault is determined. Then, based on the principle of sequentially turning off the outer transistor, inner transistor, and clamping transistor of the three-level ANPC circuit, blocking control is performed on the three-level ANPC circuit according to the driving signal level state and its duration corresponding to the fault. Compared with the prior art, since the blocking control method provided by this invention combines the driving signal level state change and its duration corresponding to the fault of the three-level ANPC circuit, it is equivalent to introducing the on or off state of each switch under the level state change corresponding to the fault of the three-level ANPC circuit into the blocking strategy of the three-level ANPC circuit. Therefore, based on the principle of sequentially turning off the outer transistor, inner transistor, and clamping transistor of the three-level ANPC circuit, and according to the drive signal level state and duration corresponding to the fault in the three-level ANPC circuit, the process of turning off the switching transistors already in the off state in the three-level ANPC circuit can be eliminated. This further shortens the protection action time of the three-level ANPC circuit when encountering a fault. Correspondingly, the three-level ANPC circuit blocking control device, equipment, and medium provided by this invention also have the above-mentioned beneficial effects. Attached Figure Description

[0038] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0039] Figure 1 A flowchart illustrating a wave blocking control method for a three-level ANPC circuit provided in an embodiment of the present invention;

[0040] Figure 2 This is a structural diagram of a three-level ANPC circuit provided in an embodiment of the present invention;

[0041] Figure 3 This is a schematic diagram of the level switching waveform of the positive modulation wave after inserting dead time on each switch of a three-level ANPC circuit.

[0042] Figure 4 This is a schematic diagram of the level switching waveform of the negative modulation wave after inserting dead time on each switch of a three-level ANPC circuit.

[0043] Figure 5 The protection timing diagram for the three-level ANPC circuit when the P level of the target phase fails, using the blocking control method provided by this invention to perform blocking control on the three-level ANPC circuit;

[0044] Figure 6 The timing diagram for protection of a three-level ANPC circuit when a fault occurs at the N level of the target phase, using the blocking control method provided by this invention to perform blocking control on the three-level ANPC circuit;

[0045] Figure 7 The timing diagram for protection of a three-level ANPC circuit when a fault occurs at the 0+ level of the target phase, using the blocking control method provided by this invention to control the blocking of the three-level ANPC circuit.

[0046] Figure 8 The timing diagram for protection of a three-level ANPC circuit when a fault occurs at the 0-level of the target phase, using the blocking control method provided by this invention to control the blocking of the three-level ANPC circuit;

[0047] Figure 9 The following is a protection timing diagram for the three-level ANPC circuit when a fault occurs during the transition of the target phase from P level to 0+ level, and the blocking control method provided by this invention is used to block the three-level ANPC circuit for protection timing control.

[0048] Figure 10 The following is a protection timing diagram for the three-level ANPC circuit when a fault occurs during the transition of the target phase from 0+ level to P level, and the blocking control method provided by this invention is used to block the three-level ANPC circuit for protection timing control.

[0049] Figure 11The protection timing diagram for the three-level ANPC circuit when a fault occurs during the transition of the target phase from N level to 0- level, using the blocking control method provided by this invention to perform blocking control on the three-level ANPC circuit;

[0050] Figure 12 The protection timing diagram for the three-level ANPC circuit when a fault occurs during the transition of the target phase from 0-level to N-level, using the blocking control method provided by this invention to perform blocking control on the three-level ANPC circuit;

[0051] Figure 13 This is the normal timing diagram of a three-level ANPC circuit switching from 0+ level to 0- level in the target phase;

[0052] Figure 14 This is the normal timing diagram of a three-level ANPC circuit switching from 0- level to 0+ level in the target phase;

[0053] Figure 15 This is the timing diagram for transient protection of a three-level ANPC circuit when switching from 0+ level to 0- level.

[0054] Figure 16 This is the timing diagram for transient protection of a three-level ANPC circuit when switching from 0- level to 0+ level.

[0055] Figure 17 The following is a protection timing diagram for the three-level ANPC circuit when a fault occurs during the transition of the target phase from 0+ level to P level, and the blocking control method provided by this invention is used to block the three-level ANPC circuit for protection timing control.

[0056] Figure 18 The protection timing diagram for the three-level ANPC circuit when a fault occurs during the transition of the target phase from 0-level to N-level, using the blocking control method provided by this invention to perform blocking control on the three-level ANPC circuit;

[0057] Figure 19 This is a schematic diagram of a three-level ANPC circuit during level switching.

[0058] Figure 20 The transient freewheeling current path diagram of a three-level ANPC circuit when switching from 0+ level to 0- level;

[0059] Figure 21 This is a structural diagram of a three-level ANPC circuit blocking control device provided in an embodiment of the present invention;

[0060] Figure 22 This is a structural diagram of a three-level ANPC circuit blocking control device provided in an embodiment of the present invention. Detailed Implementation

[0061] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0062] Please see Figure 1 , Figure 1 A flowchart of a blocking control method for a three-level ANPC circuit provided in an embodiment of the present invention is shown. The method includes:

[0063] Step S11: Monitor the driving signal level and duration of the three-level ANPC circuit in real time;

[0064] Step S12: When the three-level ANPC circuit fails, determine the driving signal level state corresponding to the failure of the three-level ANPC circuit;

[0065] Step S13: Based on the principle of sequentially turning off the outer tube, inner tube and clamping tube of the three-level ANPC circuit, and according to the driving signal level state and duration corresponding to the fault of the three-level ANPC circuit, the three-level ANPC circuit is subjected to wave blocking control.

[0066] In this embodiment, a blocking control method for a three-level ANPC circuit is provided. This method can not only shorten the protection action time of the three-level ANPC circuit when encountering a fault, but also improve the protection efficiency of the three-level ANPC circuit when encountering a fault.

[0067] This method first involves real-time monitoring of the drive signal level and duration of the three-level ANPC circuit to observe the corresponding drive signal level and duration at various operating moments. When a fault occurs in the three-level ANPC circuit, it is necessary to determine the corresponding drive signal level at the time of the fault. Understandably, during normal operation, the three-level ANPC circuit can output P, ​​N, and 0 levels, with the 0 level further divided into 0+ and 0- levels. Furthermore, the switching states of the corresponding transistors differ under various level states and during level switching. Therefore, once the drive signal level at the time of the fault is determined, the conduction and cutoff states of each transistor can be determined based on the corresponding drive signal level and its duration.

[0068] Please see Figure 2 , Figure 2 This is a structural diagram of a three-level ANPC circuit provided in an embodiment of the present invention. In a preferred embodiment, the three-level ANPC circuit includes three identical bridge arm circuits, each bridge arm circuit having a first external transistor Q1, a second external transistor Q4, a first internal transistor Q2, a second internal transistor Q3, a first clamping transistor Q5, and a second clamping transistor Q6.

[0069] Among them, the first end of the first outer tube Q1 is connected to the positive pole of the busbar, the second end of the first outer tube Q1 is connected to the first end of the first inner tube Q2, the second end of the first inner tube Q2 is connected to the first end of the second inner tube Q3, the second end of the second inner tube Q3 is connected to the first end of the second outer tube Q4, the second end of the second outer tube Q4 is connected to the negative pole of the busbar, the first end of the first clamping tube Q5 is connected to the second end of the first outer tube Q1, the second end of the first clamping tube Q5 is connected to the first end of the second clamping tube Q6, and the second end of the second clamping tube Q6 is connected to the second end of the second inner tube Q3.

[0070] Correspondingly, the second end of the first clamping transistor Q5 is connected to the midpoint of the busbar, and the second end of the first inner transistor Q2 is the output terminal of the bridge arm circuit.

[0071] exist Figure 2 In the circuit diagram shown, the three-level ANPC circuit consists of three identical bridge arm circuits, and each bridge arm circuit has two external transistors, two internal transistors, and two clamping transistors. Figure 2 In this context, Vdc represents the bus voltage, C1 and C2 are DC bus capacitors, and each phase of the three-phase AC power can output P level, N level, and 0 level. The 0 level includes 0+ level and 0- level.

[0072] Table 1

[0073] Q1 Q2 Q3 Q4 Q5 Q6 P level 1 1 0 0 0 1 transition state 0 1 0 0 0 1 0+ level 0 1 0 0 1 1 transition state 0 1 1 0 1 1 0-level 0 0 1 0 1 1 transition state 0 0 1 0 1 0 N level 0 0 1 1 1 0

[0074] Please refer to Table 1, which shows the on / off states of the switching transistors in a three-level ANPC circuit under various level states and level switching states. In Table 1, the number 1 indicates that the driving signal received by the switching transistor is an on command, and the number 0 indicates that the driving signal received by the switching transistor is an off command.

[0075] It's conceivable that once the drive signal level state corresponding to a fault in the three-level ANPC circuit is determined, the conduction and cutoff states of each switch in the three-level ANPC circuit during the fault can be determined. Then, based on the principle of sequentially turning off the outer, inner, and clamping transistors of the three-level ANPC circuit, and simultaneously performing waveform blocking control on the three-level ANPC circuit according to the drive signal level state and its duration during the fault, it's clear that since some of the drive signal level states corresponding to a fault in the three-level ANPC circuit will inevitably correspond to a cutoff state for some switches, if the switches are in the cutoff state, then the cumbersome process of turning off the cutoff switches can be eliminated during the sequential turn-off process. This shortens the protection action time of the three-level ANPC circuit when encountering a fault, thereby improving the protection efficiency.

[0076] As can be seen, in the blocking control method provided in this embodiment, the driving signal level state and its duration of the three-level ANPC circuit are first monitored in real time. When a fault occurs in the three-level ANPC circuit, the driving signal level state corresponding to the fault is determined. Then, based on the principle of sequentially turning off the outer transistor, inner transistor, and clamping transistor of the three-level ANPC circuit, blocking control is performed on the three-level ANPC circuit according to the driving signal level state and its duration corresponding to the fault. Compared with the prior art, since the blocking control method provided in this embodiment combines the change in the driving signal level state and its duration corresponding to the fault of the three-level ANPC circuit, it is equivalent to introducing the on or off state of each switch under the level state change corresponding to the fault of the three-level ANPC circuit into the blocking strategy of the three-level ANPC circuit. Therefore, based on the principle of sequentially turning off the outer tube, inner tube, and clamping tube of the three-level ANPC circuit, and in the process of controlling the three-level ANPC circuit by blocking the wave according to the driving signal level state and duration corresponding to the fault of the three-level ANPC circuit, the turn-off process of the switching tube that is already in the off state in the three-level ANPC circuit can be eliminated, thereby further shortening the protection action time of the three-level ANPC circuit when encountering a fault.

[0077] Based on the above embodiments, this embodiment further explains and optimizes the technical solution. As a preferred implementation, the above steps, based on the principle of sequentially turning off the outer transistor, inner transistor, and clamping transistor of the three-level ANPC circuit, and the process of performing wave blocking control on the three-level ANPC circuit according to the driving signal level state and duration corresponding to the fault of the three-level ANPC circuit, include:

[0078] When a fault occurs in the three-level ANPC circuit under the P-level state of the target phase, the first external transistor Q1 of the target phase is turned off at the moment of the fault. When the first external transistor Q1 of the target phase is in the off state, the first internal transistor Q2 of the target phase is turned off. And when the first internal transistor Q2 of the target phase is in the off state, the second clamping transistor Q6 of the target phase is turned off.

[0079] When a fault occurs in the three-level ANPC circuit under the N-level state of the target phase, the second external transistor Q4 of the target phase is turned off at the moment of the fault. When the second external transistor Q4 of the target phase is in the off state, the second internal transistor Q3 of the target phase is turned off. And when the second internal transistor Q3 of the target phase is in the off state, the first clamping transistor Q5 of the target phase is turned off.

[0080] When a fault occurs in the three-level ANPC circuit at the 0+ level of the target phase, the first internal transistor Q2 of the target phase is turned off at the moment the fault occurs, and when the first internal transistor Q2 of the target phase is in the off state, the first clamping transistor Q5 and the second clamping transistor Q6 of the target phase are turned off.

[0081] When a fault occurs in the three-level ANPC circuit under the 0-level state of the target phase, the second inner transistor Q3 of the target phase is turned off at the moment the fault occurs, and when the second inner transistor Q3 of the target phase is in the off state, the first clamping transistor Q5 and the second clamping transistor Q6 of the target phase are turned off.

[0082] During the process of controlling the three-level ANPC circuit by blocking the waveform based on the level state corresponding to the fault of the three-level ANPC circuit, we analyze the driving waveforms of the first external transistor Q1, the first internal transistor Q2, the first clamping transistor Q5, and the second clamping transistor Q6 under the positive modulation waveform, at which time the second internal transistor Q3 and the second external transistor Q4 are assumed to be in the off state; under the negative modulation waveform, we analyze the driving waveforms of the second external transistor Q4, the second internal transistor Q3, the first clamping transistor Q5, and the second clamping transistor Q6, and at which time the first external transistor Q1 and the first internal transistor Q2 are assumed to be in the off state; during the switching between positive and negative modulation waveforms, we analyze the first internal transistor Q2, the second internal transistor Q3, the first clamping transistor Q5, and the second clamping transistor Q6, and at which time the first external transistor Q1 and the second external transistor Q4 are assumed to be in the off state.

[0083] Furthermore, in this application, the dead time of each switching transistor has been taken into account when analyzing the waveform changes of the three-level ANPC circuit. Please refer to [link / reference]. Figure 3 and Figure 4 , Figure 3 This is a schematic diagram of the level switching waveform of the positive modulation wave after inserting dead time on each switch of a three-level ANPC circuit. Figure 4 This is a schematic diagram of the level switching waveform of the negative modulation wave after inserting dead zones on each switch of a three-level ANPC circuit. Figure 3 and Figure 4 In this context, DT represents the dead time, Qx(ideal) represents the ideal drive waveform of the switching transistor Qx (x = 1, 2, ... 6), and Qx(DT) represents the drive waveform of the switching transistor Qx (x = 1, 2, ... 6) after the dead time is inserted.

[0084] If a fault occurs in the three-level ANPC circuit at the P-level of the target phase, as shown in Table 1, during the wave blocking control of the three-level ANPC circuit, the first external transistor Q1 of the three-level ANPC circuit in the target phase needs to be turned off at the moment of the fault. When the first external transistor Q1 of the target phase is off, the first internal transistor Q2 of the target phase is turned off. When the first internal transistor Q2 of the target phase is off, the second clamping transistor Q6 of the three-level ANPC circuit in the target phase is then turned off. It should be noted that in this embodiment, the target phase refers to any one of the three phases.

[0085] Please see Figure 5 , Figure 5 This is a timing diagram illustrating the protection mechanism for a three-level ANPC circuit when a fault occurs at the P level of the target phase, using the blocking control method provided in this invention to control the blocking of the three-level ANPC circuit. Figure 5 middle, Figure 5 The various parameters and Figure 3 and Figure 4 The parameters are kept consistent. Enable indicates the drive signal received by the three-level ANPC circuit, Fault indicates the fault signal received by the three-level ANPC circuit, t1 indicates the time when the fault occurs, t2 indicates the time when the first external transistor Q1 is in the off state, and t3 indicates the time when the first internal transistor Q2 is in the off state.

[0086] When a fault occurs in the three-level ANPC circuit under the N-level state of the target phase, according to the states of each switch shown in Table 1, during the process of blocking the three-level ANPC circuit, the second external transistor Q4 of the three-level ANPC circuit in the target phase needs to be turned off first at the moment the fault occurs. When the second external transistor Q4 of the target phase is in the off state, the second internal transistor Q3 of the target phase is turned off. When the second internal transistor Q3 of the target phase is in the off state, the first clamping transistor Q5 of the three-level ANPC circuit in the target phase is turned off.

[0087] Please see Figure 6 , Figure 6 This is a timing diagram illustrating the protection mechanism for a three-level ANPC circuit when a fault occurs at the N-level of the target phase, using the blocking control method provided in this invention to control the blocking of the three-level ANPC circuit. Figure 6 middle, Figure 6 The various parameters and Figure 3 and Figure 4 The parameters are kept consistent. Enable indicates the drive signal received by the three-level ANPC circuit, Fault indicates the fault signal received by the three-level ANPC circuit, t1 indicates the time when the fault occurs, t2 indicates the time when the second external transistor Q4 is in the off state, and t3 indicates the time when the second internal transistor Q3 is in the off state.

[0088] When a fault occurs in the three-level ANPC circuit at the 0+ level of the target phase, as shown in Table 1, the first external transistor Q1 of the three-level ANPC circuit on the target phase is in the off state. In this case, the first internal transistor Q2 of the three-level ANPC circuit on the target phase can be turned off at the moment the fault occurs; when the first internal transistor Q2 of the target phase is in the off state, the first clamping transistor Q5 and the second clamping transistor Q6 of the three-level ANPC circuit on the target phase are also turned off.

[0089] Please see Figure 7 , Figure 7 This is a timing diagram illustrating the protection mechanism used by the blocking control method provided in this invention to control the blocking of a three-level ANPC circuit when a fault occurs at the 0+ level of the target phase. Figure 7 middle, Figure 7 The various parameters and Figure 3 and Figure 4 The parameters are kept consistent. Enable indicates the drive signal received by the three-level ANPC circuit, Fault indicates that the three-level ANPC circuit received a fault signal, t1 indicates the time when the fault occurred, and t2 indicates the time when the first internal transistor Q2 was in the off state.

[0090] When a fault occurs in the three-level ANPC circuit at the 0-level state of the target phase, it can be seen from the states of the switches shown in Table 1 that the second external switch Q4 of the three-level ANPC circuit in the target phase is in the off state. In this case, the second internal switch Q3 of the three-level ANPC circuit in the target phase can be turned off at the moment the fault occurs; when all the second internal switches Q3 of the target phase are in the off state, the first clamping switch Q5 and the second clamping switch Q6 of the three-level ANPC circuit in the target phase are then turned off.

[0091] Please see Figure 8 , Figure 8 This is a timing diagram illustrating the protection mechanism used by the blocking control method provided in this invention to control the blocking of a three-level ANPC circuit when a fault occurs at the 0-level of the target phase. Figure 8 middle, Figure 8 The various parameters and Figure 3 and Figure 4 The parameters are kept consistent. Enable indicates the drive signal received by the three-level ANPC circuit, Fault indicates the fault signal received by the three-level ANPC circuit, t1 indicates the time when the fault occurs, and t2 indicates the time when the second inner transistor Q3 is in the off state.

[0092] As a preferred embodiment, the above steps, based on the principle of sequentially turning off the outer transistor, inner transistor, and clamping transistor of the three-level ANPC circuit, and the process of controlling the three-level ANPC circuit by blocking the signal according to the driving signal level state and duration corresponding to the fault of the three-level ANPC circuit, include:

[0093] When a fault occurs in the three-level ANPC circuit during the process of switching the target phase from P level to 0+ level, the first inner tube of the target phase is turned off when the first outer tube of the target phase reaches the first preset threshold, and the second clamping tube of the target phase is turned off when the first inner tube of the target phase is in the off state.

[0094] When a fault occurs in the three-level ANPC circuit during the transition of the target phase from 0+ level to P level, the first internal transistor of the target phase is turned off at the moment of the fault, and the second clamping transistor of the target phase is turned off when the first internal transistor of the target phase is in the off state.

[0095] When a fault occurs in the three-level ANPC circuit during the switching process from P level to 0+ level of the target phase, as shown in Table 1, the first external transistor Q1 has just received the drive signal to turn off. In this case, in order to ensure that the three-level ANPC circuit can safely and reliably perform the blocking operation, the three-level ANPC circuit needs to turn off the first internal transistor Q2 of the target phase when the turn-off time of the first external transistor Q1 of the target phase reaches the first preset threshold T1, and ensure that the first external transistor Q1 of the target phase is in the off state. When the first internal transistor Q2 of the target phase is in the off state, the second clamping transistor Q6 of the target phase is then turned off.

[0096] Please see Figure 9 , Figure 9 This is a timing diagram illustrating the protection mechanism used in this invention to control the blocking of a three-level ANPC circuit when a fault occurs during the transition of the target phase from P level to 0+ level. Figure 9 middle, Figure 9 The various parameters and Figure 3 and Figure 4 The parameters are kept consistent. Enable indicates the drive signal received by the three-level ANPC circuit, Fault indicates that the three-level ANPC circuit has received a fault signal, t0 indicates the moment when the first external transistor Q1 receives the turn-off signal, t1 indicates the moment when the fault occurs, t2 indicates the moment when the first external transistor Q1 is in the off state, t3 indicates the moment when the first internal transistor Q2 is in the off state, and T1 = t2 - t0.

[0097] When a fault occurs in the three-level ANPC circuit during the switching process from 0+ level to P level of the target phase, according to the drive signals received by each switch in the three-level ANPC circuit shown in Table 1, the first external switch Q1 of the target phase is in the off state. In this case, the first internal switch Q2 of the target phase can be turned off at the moment of the fault, and the second clamping switch Q6 of the target phase can be turned off when the first internal switch Q2 of the target phase is in the off state.

[0098] Please see Figure 10 , Figure 10 This is a timing diagram illustrating the protection mechanism for a three-level ANPC circuit when a fault occurs during the transition of the target phase from 0+ level to P level. The protection mechanism utilizes the blocking control method provided in this invention to control the blocking of the three-level ANPC circuit. Figure 10 middle, Figure 10 The various parameters and Figure 3 and Figure 4 The parameters are kept consistent. Enable indicates the drive signal received by the three-level ANPC circuit, Fault indicates that the three-level ANPC circuit received a fault signal, t1 indicates the time when the fault occurred, and t2 indicates the time when the first internal transistor Q2 was in the off state.

[0099] As a preferred embodiment, the above steps, based on the principle of sequentially turning off the outer transistor, inner transistor, and clamping transistor of the three-level ANPC circuit, and the process of controlling the three-level ANPC circuit by blocking the signal according to the driving signal level state and duration corresponding to the fault of the three-level ANPC circuit, include:

[0100] When a fault occurs in the three-level ANPC circuit during the switching of the target phase from N level to 0 level, the second inner tube of the target phase is turned off when the second outer tube of the target phase reaches the second preset threshold, and the first clamping tube of the target phase is turned off when the second inner tube of the target phase is in the off state.

[0101] When a fault occurs in the three-level ANPC circuit during the switching of the target phase from 0-level to N-level, the first internal transistor of the target phase is turned off at the moment the fault occurs, and the second clamping transistor of the target phase is turned off when the first internal transistor of the target phase is in the off state.

[0102] When a fault occurs in the three-level ANPC circuit during the switching process of the target phase from N level to 0- level, according to the state of each switch in the three-level ANPC circuit shown in Table 1, the second external transistor Q4 of the target phase has just received the drive signal to turn off. In this case, in order to ensure that the three-level ANPC circuit can safely and reliably perform the blocking operation, the three-level ANPC circuit needs to turn off the second internal transistor Q3 of the target phase when the turn-off time of the second external transistor Q4 of the target phase reaches the second preset threshold T2, while ensuring that the second external transistor Q4 of the target phase is in the off state. When the second internal transistor Q3 of the target phase is in the off state, the first clamping transistor Q5 of the target phase is then turned off.

[0103] Please see Figure 11 , Figure 11 This is a protection timing diagram for a three-level ANPC circuit when a fault occurs during the transition of the target phase from N-level to 0-level, using the blocking control method provided in this invention to control the blocking of the three-level ANPC circuit. Figure 11 middle, Figure 11 The various parameters and Figure 3 and Figure 4 The parameters are kept consistent. Enable indicates the drive signal received by the three-level ANPC circuit, Fault indicates that the three-level ANPC circuit has received a fault signal, t0 indicates the time when the second external transistor Q4 receives the turn-off signal, t1 indicates the time when the fault occurs, t2 indicates the time when the second external transistor Q4 is in the turn-off state, t3 indicates the time when the second internal transistor Q3 is in the turn-off state, and T2 = t2 - t0.

[0104] When a fault occurs in the three-level ANPC circuit during the transition of the target phase from 0-level to N-level, according to the drive signals received by each switch in the three-level ANPC circuit shown in Table 1, the second external transistor Q4 of the target phase is in the off state. In this case, the first internal transistor Q2 of the target phase can be turned off at the moment of the fault, and the second clamping transistor Q6 of the target phase can be turned off when the first internal transistor Q2 of the target phase is in the off state.

[0105] Please see Figure 12 , Figure 12 This is a protection timing diagram for a three-level ANPC circuit when a fault occurs during the transition of the target phase from 0-level to N-level, using the blocking control method provided in this invention to control the blocking of the three-level ANPC circuit. Figure 12 middle, Figure 12 The various parameters and Figure 3 and Figure 4The parameters are kept consistent. Enable indicates the drive signal received by the three-level ANPC circuit, Fault indicates that the three-level ANPC circuit has received a fault signal, t0 indicates the time when the second external transistor Q4 receives the turn-off signal, t1 indicates the time when the fault occurs, and t2 indicates the time when the first internal transistor Q2 is in the turn-off state.

[0106] As a preferred embodiment, the above steps, based on the principle of sequentially turning off the outer transistor, inner transistor, and clamping transistor of the three-level ANPC circuit, and the process of controlling the three-level ANPC circuit by blocking the signal according to the driving signal level state and duration corresponding to the fault of the three-level ANPC circuit, include:

[0107] When a fault occurs in the three-level ANPC circuit during the switching of the target phase from 0+ level to 0- level, the first and second inner tubes of the target phase are turned off at the moment the fault occurs, and the first and second clamping tubes of the target phase are turned off when the first and second inner tubes of the target phase are in the off state.

[0108] When a fault occurs in the three-level ANPC circuit during the transition of the target phase from 0- level to 0+ level, the first and second inner tubes of the target phase are turned off at the moment the fault occurs. And when the first and second inner tubes of the target phase are in the off state, the first and second clamping tubes of the target phase are turned off.

[0109] Please see Figures 13 to 16 , Figure 13 This is the normal timing diagram of a three-level ANPC circuit switching from 0+ level to 0- level in the target phase; Figure 14 This is the normal timing diagram for a three-level ANPC circuit switching from 0- level to 0+ level in the target phase; Figure 13 In the diagram, t1 represents the turn-on time of the second inner tube Q3, and t2 represents the turn-off time of the first inner tube Q2. Figure 14 In the diagram, t1 represents the turn-on time of the first inner tube Q2, and t2 represents the turn-off time of the second inner tube Q3. Figure 15 This is the timing diagram for transient protection of a three-level ANPC circuit when the target phase switches from 0+ level to 0- level. Figure 16 This is the timing diagram for transient protection of a three-level ANPC circuit when the target phase switches from 0- level to 0+ level. Figure 15 and Figure 16 In the diagram, t1 represents the time when the fault occurs, and t2 represents the time when the first clamping transistor Q5 and the second clamping transistor Q6 are turned off.

[0110] As a preferred embodiment, the above steps, based on the principle of sequentially turning off the outer transistor, inner transistor, and clamping transistor of the three-level ANPC circuit, and the process of controlling the three-level ANPC circuit by blocking the signal according to the driving signal level state and duration corresponding to the fault of the three-level ANPC circuit, include:

[0111] When a fault occurs in the three-level ANPC circuit during the transition of the target phase from 0+ level to P level, the first internal transistor of the target phase is turned off at the moment of the fault, and the second clamping transistor of the target phase is turned off when the first internal transistor of the target phase is in the off state.

[0112] When a fault occurs in the three-level ANPC circuit during the transition of the target phase from 0-level to N-level, the second inner transistor of the target phase is turned off at the moment of the fault, and the first clamping transistor of the target phase is turned off when the second inner transistor of the target phase is in the off state.

[0113] When a fault occurs during the transition of the three-level ANPC circuit from 0+ level to P level in the target phase, before it has entered the P level, as shown in Table 1, the drive signals received by each switch in the three-level ANPC circuit indicate that the first external transistor Q1 and the second external transistor Q4 in the target phase are in the off state. Under these circumstances, the first internal transistor Q2 in the target phase of the three-level ANPC circuit can be turned off at the moment the fault occurs, and when the first internal transistor Q2 in the target phase is in the off state, the second clamping transistor Q6 in the target phase is turned off.

[0114] Please see Figure 17 , Figure 17 This is a timing diagram illustrating the protection mechanism for a three-level ANPC circuit when a fault occurs during the transition of the target phase from 0+ level to P level. The protection mechanism utilizes the blocking control method provided in this invention to control the blocking of the three-level ANPC circuit. Figure 17 middle, Figure 17 The various parameters and Figure 3 and Figure 4 The parameters are kept consistent. Enable indicates the drive signal received by the three-level ANPC circuit, Fault indicates that the three-level ANPC circuit received a fault signal, t1 indicates the time when the fault occurred, and t2 indicates the time when the first internal transistor Q2 was in the off state.

[0115] When the three-level ANPC circuit is switching from 0-level to N-level in the target phase, and a fault occurs before entering the N-level, as shown in Table 1, the drive signals received by each switch in the three-level ANPC circuit indicate that the first external transistor Q1 of the target phase is in the off state. In this case, the second internal transistor Q3 of the target phase can be turned off directly at the moment of the fault, and the first clamping transistor Q5 of the target phase can be turned off when the second internal transistor Q3 of the target phase is in the off state.

[0116] Please see Figure 18 , Figure 18 This is a timing diagram illustrating the protection mechanism used in this invention to control the blocking of a three-level ANPC circuit during the transition from 0-level to N-level when a fault occurs. Figure 18 middle, Figure 18 The various parameters and Figure 3 and Figure 4 The parameters are kept consistent. Enable indicates the drive signal received by the three-level ANPC circuit, Fault indicates the fault signal received by the three-level ANPC circuit, t1 indicates the time when the fault occurs, and t2 indicates the time when the second inner transistor Q3 is in the off state.

[0117] In addition, the method provided in this application can also be applied to the waveform control logic of a three-level ANPC circuit. That is, when starting the three-level ANPC circuit, the clamping transistors Q5 and Q6 in the three-level ANPC circuit can be turned on first, then the corresponding internal transistors Q2 and Q3 can be turned on, and finally the corresponding external transistors Q1 and Q4 can be turned on. This can solve the problem of voltage equalization of external transistors when PWM controls the waveform of a three-level ANPC circuit.

[0118] Please see Figure 19 and Figure 20 , Figure 19 This is a schematic diagram of a three-level ANPC circuit during level switching. Figure 20 This is a transient freewheeling current path diagram for a three-level ANPC circuit when switching from 0+ to 0- level. From... Figure 19 and Figure 20 It can be seen that the wave blocking control method of the three-level ANPC circuit provided in this application can effectively solve the problem of long commutation paths that occur during the switching of each level.

[0119] Clearly, the wave-blocking control method for the three-level ANPC circuit provided in this application offers fault protection timing strategies for the switching process between P-level and 0+ level when the modulation wave is positive, as well as for the switching process between N-level and 0- level when the modulation wave is negative, and also includes fault protection timing strategies for the switching process between 0+ level and 0- level. Furthermore, a start / stop switching timing logic scheme for the three-level ANPC circuit based on this fault protection strategy is proposed. According to the wave-blocking control method for the three-level ANPC circuit provided in this application, because the turn-off process of the switching transistors already in the off state in the three-level ANPC circuit can be eliminated during wave-blocking control, the protection action time of the three-level ANPC circuit when encountering a fault can be further shortened.

[0120] Please see Figure 21 , Figure 21 This is a structural diagram of a three-level ANPC circuit blocking control device provided in an embodiment of the present invention. The device includes:

[0121] The status monitoring module 21 is used to monitor the level status and duration of the drive signal of the three-level ANPC circuit in real time.

[0122] The level determination module 22 is used to determine the driving signal level state corresponding to the fault of the three-level ANPC circuit when the three-level ANPC circuit fails.

[0123] The blocking control module 23 is used to block the three-level ANPC circuit based on the principle of sequentially turning off the outer tube, inner tube and clamping tube of the three-level ANPC circuit, and according to the driving signal level state and duration corresponding to the fault of the three-level ANPC circuit.

[0124] The wave blocking control device for a three-level ANPC circuit provided in this embodiment of the invention has the beneficial effects of the wave blocking control method for a three-level ANPC circuit disclosed above.

[0125] Please see Figure 22 , Figure 22 This is a structural diagram of a three-level ANPC circuit blocking control device provided in an embodiment of the present invention. The device includes:

[0126] Memory 31 is used to store computer programs;

[0127] The processor 32 is used to implement the steps of a blocking control method for a three-level ANPC circuit as disclosed above when executing a computer program.

[0128] The wave blocking control device for a three-level ANPC circuit provided in this embodiment of the invention has the beneficial effects of the wave blocking control method for a three-level ANPC circuit disclosed above.

[0129] Accordingly, embodiments of the present invention also disclose a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of a blocking control method for a three-level ANPC circuit as disclosed above.

[0130] The computer-readable storage medium provided in this embodiment of the invention has the beneficial effects of the aforementioned three-level ANPC circuit blocking control method.

[0131] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section.

[0132] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0133] The above provides a detailed description of the blocking control method, apparatus, device, and medium for a three-level ANPC circuit provided by the present invention. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A method for blocking waveform control of a three-level ANPC circuit, characterized in that, include: Real-time monitoring of the driving signal level and duration of the three-level ANPC circuit; When the three-level ANPC circuit fails, the driving signal level state corresponding to the failure of the three-level ANPC circuit is determined; wherein, the driving signal level state is based on the 0+ level and 0- level among the P level, N level and 0 level output by the three-level ANPC circuit, and the switching state of the corresponding switching transistor of the three-level ANPC circuit in various level states and level switching states; Based on the principle of sequentially turning off the outer tube, inner tube, and clamping tube of the three-level ANPC circuit, and according to the driving signal level state and duration corresponding to the fault of the three-level ANPC circuit, the three-level ANPC circuit is subjected to wave blocking control, so as to avoid the turn-off process of the switching tube that is already in the off state in the three-level ANPC circuit, and shorten the protection action time of the three-level ANPC circuit when encountering a fault. Correspondingly, the three-level ANPC circuit includes: three bridge arm circuits with the same structure, each bridge arm circuit being provided with a first outer tube, a second outer tube, a first inner tube, a second inner tube, a first clamping tube, and a second clamping tube; Correspondingly, the process of controlling the three-level ANPC circuit by sequentially turning off the outer transistor, inner transistor, and clamping transistor in the three-level ANPC circuit, and by controlling the three-level ANPC circuit to block out signals according to the driving signal level state and duration corresponding to the fault in the three-level ANPC circuit, includes: When the three-level ANPC circuit malfunctions during the process of the target phase switching from P level to 0+ level, the first inner tube of the target phase is turned off when the first outer tube of the target phase reaches the first preset threshold, and the second clamping tube of the target phase is turned off when the first inner tube of the target phase is in the off state. When the three-level ANPC circuit malfunctions during the process of the target phase switching from 0+ level to P level, the first inner transistor of the target phase is turned off at the moment of the malfunction, and the second clamping transistor of the target phase is turned off when the first inner transistor of the target phase is in the off state. When the three-level ANPC circuit malfunctions during the process of the target phase switching from N level to 0- level, the second inner tube of the target phase is turned off when the second outer tube of the target phase reaches the second preset threshold, and the first clamping tube of the target phase is turned off when the second inner tube of the target phase is in the off state. When the three-level ANPC circuit malfunctions during the transition of the target phase from 0-level to N-level, the first inner transistor of the target phase is turned off at the moment of the malfunction, and the second clamping transistor of the target phase is turned off when the first inner transistor of the target phase is in the off state.

2. The wave blocking control method according to claim 1, characterized in that, The first end of the first outer tube is connected to the positive terminal of the busbar, the second end of the first outer tube is connected to the first end of the first inner tube, the second end of the first inner tube is connected to the first end of the second inner tube, the second end of the second inner tube is connected to the first end of the second outer tube, the second end of the second outer tube is connected to the negative terminal of the busbar, the first end of the first clamping tube is connected to the second end of the first outer tube, the second end of the first clamping tube is connected to the first end of the second clamping tube, and the second end of the second clamping tube is connected to the second end of the second inner tube. Correspondingly, the second end of the first clamping tube is connected to the midpoint of the busbar, and the second end of the first inner tube is the output terminal of the bridge arm circuit.

3. The wave blocking control method according to claim 2, characterized in that, The process of controlling the three-level ANPC circuit by sequentially turning off the outer transistor, inner transistor, and clamping transistor in the three-level ANPC circuit, and by controlling the circuit based on the driving signal level state and duration corresponding to the fault in the three-level ANPC circuit, includes: When the three-level ANPC circuit malfunctions in the P-level state of the target phase, the first external transistor of the target phase is turned off at the moment of the malfunction. When the first external transistor of the target phase is in the off state, the first internal transistor of the target phase is turned off. And when the first internal transistor of the target phase is in the off state, the second clamping transistor of the target phase is turned off. When the three-level ANPC circuit fails in the N-level state of the target phase, the second external transistor of the target phase is turned off at the moment of the fault. When the second external transistor of the target phase is in the off state, the second internal transistor of the target phase is turned off. And when the second internal transistor of the target phase is in the off state, the first clamping transistor of the target phase is turned off. When the three-level ANPC circuit fails in the 0+ level state of the target phase, the first inner tube of the target phase is turned off at the moment of the fault, and when the first inner tube of the target phase is in the off state, the first clamping tube and the second clamping tube of the target phase are turned off. When the three-level ANPC circuit fails in the 0-level state of the target phase, the second inner tube of the target phase is turned off at the moment of the fault, and when the second inner tube of the target phase is in the off state, the first clamping tube and the second clamping tube of the target phase are turned off.

4. The wave blocking control method according to claim 2, characterized in that, The process of controlling the three-level ANPC circuit by sequentially turning off the outer transistor, inner transistor, and clamping transistor in the three-level ANPC circuit, and by controlling the circuit based on the driving signal level state and duration corresponding to the fault in the three-level ANPC circuit, includes: When the three-level ANPC circuit malfunctions during the process of the target phase switching from 0+ level to 0- level, the first inner tube and the second inner tube of the target phase are turned off at the moment of the malfunction, and when the first inner tube and the second inner tube of the target phase are in the off state, the first clamping tube and the second clamping tube of the target phase are turned off. When the three-level ANPC circuit malfunctions during the transition of the target phase from 0- level to 0+ level, the first and second inner tubes of the target phase are turned off at the moment of the malfunction, and the first and second clamping tubes of the target phase are turned off when the first and second inner tubes of the target phase are in the off state.

5. The wave blocking control method according to claim 2, characterized in that, The process of controlling the three-level ANPC circuit by sequentially turning off the outer transistor, inner transistor, and clamping transistor in the three-level ANPC circuit, and by controlling the circuit based on the driving signal level state and duration corresponding to the fault in the three-level ANPC circuit, includes: When the three-level ANPC circuit malfunctions during the process of the target phase switching from 0+ level to P level, the first inner transistor of the target phase is turned off at the moment of the malfunction, and the second clamping transistor of the target phase is turned off when the first inner transistor of the target phase is in the off state. When the three-level ANPC circuit malfunctions during the transition of the target phase from 0-level to N-level, the second inner transistor of the target phase is turned off at the moment of the malfunction, and the first clamping transistor of the target phase is turned off when the second inner transistor of the target phase is in the off state.

6. A wave blocking control device for a three-level ANPC circuit, characterized in that, include: The status monitoring module is used to monitor the level status and duration of the drive signal of the three-level ANPC circuit in real time. The level determination module is used to determine the driving signal level state corresponding to the fault of the three-level ANPC circuit when the three-level ANPC circuit fails; wherein the driving signal level state is based on the 0+ level and 0- level among the P level, N level and 0 level output by the three-level ANPC circuit, and the switching state of the corresponding switching transistor of the three-level ANPC circuit in various level states and level switching states; The blocking control module is used to block the three-level ANPC circuit based on the principle of sequentially turning off the outer tube, inner tube and clamping tube of the three-level ANPC circuit, and according to the driving signal level state and duration corresponding to the fault of the three-level ANPC circuit, so as to avoid the turn-off process of the switching tube that is already in the off state in the three-level ANPC circuit, and shorten the protection action time of the three-level ANPC circuit when encountering a fault. Correspondingly, the three-level ANPC circuit includes: three bridge arm circuits with the same structure, each bridge arm circuit being provided with a first outer tube, a second outer tube, a first inner tube, a second inner tube, a first clamping tube, and a second clamping tube; Correspondingly, the process of controlling the three-level ANPC circuit by sequentially turning off the outer transistor, inner transistor, and clamping transistor in the three-level ANPC circuit, and by controlling the three-level ANPC circuit to block out signals according to the driving signal level state and duration corresponding to the fault in the three-level ANPC circuit, includes: When the three-level ANPC circuit malfunctions during the process of the target phase switching from P level to 0+ level, the first inner tube of the target phase is turned off when the first outer tube of the target phase reaches the first preset threshold, and the second clamping tube of the target phase is turned off when the first inner tube of the target phase is in the off state. When the three-level ANPC circuit malfunctions during the process of the target phase switching from 0+ level to P level, the first inner transistor of the target phase is turned off at the moment of the malfunction, and the second clamping transistor of the target phase is turned off when the first inner transistor of the target phase is in the off state. When the three-level ANPC circuit malfunctions during the process of the target phase switching from N level to 0- level, the second inner tube of the target phase is turned off when the second outer tube of the target phase reaches the second preset threshold, and the first clamping tube of the target phase is turned off when the second inner tube of the target phase is in the off state. When the three-level ANPC circuit malfunctions during the transition of the target phase from 0-level to N-level, the first inner transistor of the target phase is turned off at the moment of the malfunction, and the second clamping transistor of the target phase is turned off when the first inner transistor of the target phase is in the off state.

7. A wave blocking control device for a three-level ANPC circuit, characterized in that, include: Memory, used to store computer programs; A processor, configured to implement the steps of a blocking control method for a three-level ANPC circuit as described in any one of claims 1 to 5 when executing the computer program.

8. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the steps of a blocking control method for a three-level ANPC circuit as described in any one of claims 1 to 5.

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