Encoding and decoding method, encoding and decoding device, medium and equipment of polar code

Abstract

The present disclosure relates to the technical field of coding and decoding, and provides a polar code encoding method, a polar code decoding method, a polar code encoding device, a polar code decoding device, a computer storage medium and an electronic device, wherein the polar code decoding method comprises: dividing a to-be-decoded log-likelihood ratio sequence to obtain a plurality of to-be-decoded subsegments; performing non-successive cancellation list (nonSCL) decoding on the plurality of to-be-decoded subsegments to obtain a plurality of first decoded subsegments; performing subsegment transformation on the plurality of first decoded subsegments to obtain a plurality of second decoded subsegments; and merging the plurality of second decoded subsegments to obtain a decoded bit sequence. The present disclosure can shorten the decoding time.

Description

Technical Field

[0001] This disclosure relates to the field of encoding and decoding technology, and in particular to an encoding method for polar codes, a decoding method for polar codes, an encoding device for polar codes, a decoding device for polar codes, a computer storage medium, and an electronic device. Background Technology

[0002] Polar codes are a coding scheme based on channel polarization. Polar codes are constructed by introducing the concept of channel polarization. Channel polarization consists of two stages: channel joining and channel splitting. Through channel joining and splitting, the symmetrical capacity of each sub-channel exhibits a bipolar trend: as the code length N increases, the capacity of some sub-channels tends to 1, while the capacity of the remaining sub-channels tends to 0. Polar codes utilize this channel polarization phenomenon, transmitting message bits on K sub-channels with a capacity tending to 1, and transmitting frozen bits (i.e., fixed bits known to both the sender and receiver, usually set to all zeros) on the remaining sub-channels. The resulting code is called a Polar code, with a code rate of K / N.

[0003] In related technologies, SCL decoding of each segment to be decoded is generally performed independently. However, the above decoding scheme has the following shortcomings: when selecting alternative paths, it is based on the path with the highest probability value in a single decoded segment, rather than the path with the highest probability value in the entire decoded segment. Therefore, the path with the highest probability in the entire decoded segment may be deleted, resulting in poor decoding performance.

[0004] Therefore, there is an urgent need in this field to develop a new method and apparatus for decoding polar codes.

[0005] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure. Summary of the Invention

[0006] The purpose of this disclosure is to provide a polar code encoding method, a polar code decoding method, a polar code encoding device, a polar code decoding device, a computer storage medium, and an electronic device, thereby overcoming, at least to some extent, the technical problem of poor decoding performance caused by limitations in related technologies.

[0007] Other features and advantages of this disclosure will become apparent from the following detailed description, or may be learned in part from practice of this disclosure.

[0008] According to a first aspect of this disclosure, a polar code encoding method is provided, comprising: dividing a bit sequence to be encoded to obtain a plurality of first segments to be encoded; performing segment transformation on the plurality of first segments to be encoded to obtain a plurality of second segments to be encoded; performing a check code generation operation on the plurality of second segments to be encoded to obtain a plurality of third segments to be encoded; and encoding the plurality of third segments to be encoded to obtain an encoded bit sequence.

[0009] In an exemplary embodiment of this disclosure, the step of dividing the bit sequence to be encoded into multiple first segments to be encoded includes: dividing the bit sequence to be encoded of length N into m first segments to be encoded of length n.

[0010] In an exemplary embodiment of this disclosure, the step of performing segment transformation on the plurality of first segments to be encoded to obtain a plurality of second segments to be encoded includes: performing segment transformation on the m first segments to be encoded of length n to obtain m second segments to be encoded of length n; wherein N and m are both integer powers of 2, and N is the product of m and n.

[0011] In an exemplary embodiment of this disclosure, the step of performing segment transformation on the m first segments to be encoded of length n to obtain m second segments to be encoded of length n includes: determining a specific set of bits from each of the first segments to be encoded according to a first segment transformation rule for generating each second segment to be encoded; performing an XOR operation within the set on at least one specific set of bits to obtain the m second segments to be encoded of length n; wherein, the first segment transformation rule is used to limit the XOR operation involving only frozen bits to obtain constant 0 bits, the XOR operation involving only information bits to obtain pure information bits, and the XOR operation involving both frozen bits and information bits to obtain mixed bits.

[0012] In an exemplary embodiment of this disclosure, the step of performing a checksum generation operation on a plurality of second sub-segments to be encoded to obtain a plurality of third sub-segments to be encoded includes: performing a checksum generation operation on the plurality of second sub-segments to be encoded to obtain a checksum; and adding the checksum to a reserved checksum position in the plurality of second sub-segments to be encoded to obtain a plurality of third sub-segments to be encoded.

[0013] In an exemplary embodiment of this disclosure, performing a checksum generation operation on the plurality of second sub-segments to be encoded to obtain a checksum includes: merging the plurality of second sub-segments to be encoded to obtain a merged sequence; and performing a checksum generation operation on the merged sequence to obtain the checksum.

[0014] In an exemplary embodiment of this disclosure, performing a check code generation operation on the plurality of second sub-segments to be encoded to obtain a check code further includes: dividing the plurality of second sub-segments to be encoded into a plurality of sub-segment groups, each sub-segment group containing at least one second sub-segment to be encoded; and performing a check code generation operation on each sub-segment group to obtain a plurality of check codes.

[0015] In an exemplary embodiment of this disclosure, the step of adding the check code to the reserved check code position in the plurality of second sub-segments to be encoded to obtain a plurality of third sub-segments to be encoded includes: adding the check code to the pure information bits and / or information bits in the plurality of second sub-segments to be encoded to obtain the plurality of third sub-segments to be encoded; wherein, the pure information bits and / or information bits are the bits corresponding to the pure information bits and / or information bits obtained by XORing only the information bits in the second sub-segments to be encoded.

[0016] In an exemplary embodiment of this disclosure, encoding the plurality of third segments to be encoded to obtain an encoded bit sequence includes: polar coding the plurality of third segments to be encoded to obtain a plurality of encoded bit segments; and merging the plurality of encoded bit segments to obtain the encoded bit sequence.

[0017] In an exemplary embodiment of this disclosure, encoding the plurality of third segments to be encoded to obtain an encoded bit sequence includes: performing a bit-reversal transformation on the plurality of third segments to be encoded to obtain a plurality of transformed third segments to be encoded; performing polar code encoding on the transformed plurality of third segments to be encoded to obtain a plurality of encoded bit segments; and merging the plurality of encoded bit segments to obtain the encoded bit sequence.

[0018] In an exemplary embodiment of this disclosure, encoding the plurality of third segments to be encoded to obtain an encoded bit sequence includes: performing an r-order Kronecker operation on the plurality of third segments to be encoded to obtain a plurality of encoded bit segments, where r is a positive integer; and merging the plurality of encoded bit segments to obtain the encoded bit sequence.

[0019] According to a second aspect of this disclosure, a method for decoding polar codes is provided, comprising: dividing a sequence of log-likelihood ratios to be decoded to obtain multiple segments to be decoded; performing non-contiguous deletion list (nonSCL) decoding on the multiple segments to be decoded to obtain multiple first decoded segments; performing segment transformation on the multiple first decoded segments to obtain multiple second decoded segments; and merging the multiple second decoded segments to obtain a decoded bit sequence.

[0020] In an exemplary embodiment of this disclosure, the step of dividing the log-likelihood ratio sequence to be decoded into multiple segments to be decoded includes: dividing the log-likelihood ratio sequence to be decoded into m segments to be decoded of length n; wherein N and m are both integer powers of 2, and N is the product of m and n.

[0021] In an exemplary embodiment of this disclosure, the step of dividing the log-likelihood ratio sequence to be decoded into multiple segments to be decoded includes: dividing the log-likelihood ratio sequence to be decoded into multiple initial segments to be decoded; and performing a bit-reversal transformation on the multiple initial segments to be decoded to obtain the multiple segments to be decoded.

[0022] In an exemplary embodiment of this disclosure, the step of performing non-contiguous deletion list (nonSCL) decoding on the plurality of segments to be decoded to obtain a plurality of first decoded segments includes: performing non-contiguous deletion list (nonSCL) decoding on the plurality of segments to be decoded to obtain a plurality of merge paths; and determining the plurality of first decoded segments based on the plurality of merge paths.

[0023] In an exemplary embodiment of this disclosure, the step of performing non-contiguous deletion list (nonSCL) decoding on the plurality of segments to be decoded to obtain a plurality of merged paths includes: performing contiguous deletion list (SCL) decoding on each of the segments to be decoded to obtain an incomplete first decoding path for each segment; performing segment-based path splitting on each of the first decoding paths to obtain a plurality of incomplete second decoding paths; performing a frozen bit constraint condition check on each of the second decoding paths and determining the paths that pass the check as third decoding paths; arranging each of the third decoding paths in descending order of path probability values ​​to obtain a first decoding path queue; determining candidate decoding paths based on each of the first decoding path queues; continuing to perform non-contiguous deletion list (nonSCL) decoding on each segment to be decoded based on the candidate decoding paths; and determining the merged path based on each candidate decoding path when the length of the second decoding path is N.

[0024] In an exemplary embodiment of this disclosure, determining candidate decoding paths based on each of the first decoding path queues includes: dividing the first decoding path queues based on sub-segments while maintaining the queue order to obtain second decoding path queues for each of the sub-segments to be decoded; when the number of paths with different probability values ​​in the second decoding path queues is less than or equal to a first preset threshold, selecting the paths with different probability values ​​in the second decoding path queues as candidate decoding paths; when the number of paths with different probability values ​​in the second decoding path queues is greater than the first preset threshold, selecting the first preset threshold number of paths with different probability values ​​as candidate decoding paths.

[0025] In an exemplary embodiment of this disclosure, determining candidate decoding paths based on each of the first decoding path queues includes: selecting the first second preset threshold number of paths from the first decoding path queues as a third decoding path queue; dividing the third decoding path queue based on sub-segments while maintaining the queue order to obtain a fourth decoding path queue for each of the sub-segments to be decoded; when the number of paths with different probability values ​​in the fourth decoding path queue is less than or equal to a first preset threshold, selecting the paths with different probability values ​​in the fourth decoding path queue as candidate decoding paths; when the number of paths with different probability values ​​in the fourth decoding path queue is greater than the first preset threshold, selecting the first first preset threshold number of paths with different probability values ​​as candidate decoding paths.

[0026] In an exemplary embodiment of this disclosure, determining the plurality of first decoding segments based on the plurality of merging paths includes: verifying each of the merging paths based on a preset verification method, determining the merging path that passes the verification and has the highest probability as the final decoding path; and dividing the final decoding path based on segments to obtain the plurality of first decoding segments.

[0027] In an exemplary embodiment of this disclosure, the step of performing segment transformation on the plurality of first decoded segments to obtain a plurality of second decoded segments includes: determining an initial bit set from each of the first decoded segments for generating each of the second decoded segments according to a second segment transformation rule; wherein the second segment transformation rule is the inverse transformation of the first segment transformation rule on the encoding side; and performing an intra-set XOR operation on at least one initial bit set to obtain a plurality of second decoded segments.

[0028] In an exemplary embodiment of this disclosure, merging the plurality of second decoded segments to obtain a decoded bit sequence includes: merging m second decoded segments of length n to obtain the decoded bit sequence of length N.

[0029] According to a third aspect of this disclosure, an encoding apparatus for polar codes is provided, characterized in that it comprises: a partitioning module for partitioning a bit sequence to be encoded to obtain a plurality of first segments to be encoded; a segment transformation module for performing segment transformation on the plurality of first segments to be encoded to obtain a plurality of second segments to be encoded; a check code generation module for performing check code generation operations on the plurality of second segments to be encoded to obtain a plurality of third segments to be encoded; and an encoding module for encoding the plurality of third segments to be encoded to obtain an encoded bit sequence.

[0030] According to a fourth aspect of this disclosure, a polar code decoding apparatus is provided, comprising: a partitioning module for partitioning a log-likelihood ratio sequence to be decoded to obtain multiple segments to be decoded; a decoding module for performing non-contiguous deletion list (nonSCL) decoding on the multiple segments to be decoded to obtain multiple first decoded segments; a segment transformation module for performing segment transformation on the multiple first decoded segments to obtain multiple second decoded segments; and a merging module for merging the multiple second decoded segments to obtain a decoded bit sequence.

[0031] According to a third aspect of this disclosure, a computer storage medium is provided, on which a computer program is stored, wherein when the computer program is executed by a processor, it implements the polar code encoding method described in the first aspect and the polar code decoding method described in the second aspect.

[0032] According to a fourth aspect of this disclosure, an electronic device is provided, comprising: a processor; and a memory for storing executable instructions of the processor; wherein the processor is configured to execute the polar code encoding method of the first aspect and the polar code decoding method of the second aspect by executing the executable instructions.

[0033] As can be seen from the above technical solutions, the polar code encoding method, polar code decoding method, polar code encoding apparatus, polar code decoding apparatus, computer storage medium, and electronic device in the exemplary embodiments of this disclosure have at least the following advantages and positive effects:

[0034] In the polar code encoding method provided in an exemplary embodiment of this disclosure, the bit sequence to be encoded is divided to obtain multiple first segments to be encoded, the multiple first segments to be encoded are transformed to obtain multiple second segments to be encoded, the multiple second segments to be encoded are subjected to check code generation operation to obtain multiple third segments to be encoded, and the multiple third segments to be encoded are encoded to obtain an encoded bit sequence. Thus, compared with traditional encoding schemes, this disclosure can achieve flexible encoding and ensure decoding performance.

[0035] In a polar code decoding method provided by an exemplary embodiment of this disclosure, multiple segments to be decoded are obtained by dividing the log-likelihood ratio sequence to be decoded. Non-contiguous deletion list (nonSCL) decoding is then performed on these segments to obtain multiple first decoded segments. Segment transformation is then performed on these first decoded segments to obtain multiple second decoded segments. Finally, these second decoded segments are merged to obtain a decoded bit sequence. This disclosure can select the globally optimal candidate path at each decoding node, using this candidate path as the basis for splitting to finally determine the decoded bit sequence. Therefore, compared with traditional decoding schemes, this disclosure can improve decoding performance while shortening decoding time.

[0036] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0037] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0038] Figure 1 A flowchart illustrating the encoding method of polar codes in an embodiment of this disclosure is shown.

[0039] Figure 2 This illustration shows a flowchart of a process in which multiple first segments to be encoded are transformed to obtain multiple second segments to be encoded in an embodiment of this disclosure.

[0040] Figure 3 This illustration shows a flowchart of a process for generating check codes from multiple second segments to be encoded to obtain multiple third segments to be encoded, as shown in an embodiment of this disclosure.

[0041] Figure 4 A flowchart illustrating the decoding method of polar codes in an embodiment of this disclosure is shown.

[0042] Figure 5 This diagram illustrates the process of obtaining multiple first decoded segments in an embodiment of the present disclosure.

[0043] Figure 6 This diagram illustrates how multiple merge paths are obtained in an embodiment of the present disclosure.

[0044] Figure 7 This illustration shows a flowchart of a process in which multiple first decoding segments are transformed to obtain multiple second decoding segments in an embodiment of this disclosure.

[0045] Figure 8 A flowchart illustrating the overall process of decoding polar codes in an embodiment of this disclosure is shown.

[0046] Figure 9 A schematic diagram of the structure of a polar code encoding apparatus in an exemplary embodiment of this disclosure is shown;

[0047] Figure 10 A schematic diagram of the structure of a polar code decoding apparatus in an exemplary embodiment of this disclosure is shown;

[0048] Figure 11 A schematic diagram of the structure of an electronic device in an exemplary embodiment of this disclosure is shown. Detailed Implementation

[0049] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this disclosure more comprehensive and complete, and to fully convey the concept of the example embodiments to those skilled in the art. The described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a full understanding of embodiments of this disclosure. However, those skilled in the art will recognize that the technical solutions of this disclosure can be practiced with one or more of the specific details omitted, or other methods, components, apparatus, steps, etc., can be employed. In other instances, well-known technical solutions are not shown or described in detail to avoid obscuring various aspects of this disclosure.

[0050] The terms “a,” “an,” “the,” and “the” are used in this specification to indicate the presence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first” and “second” are used only as markings and are not a limitation on the number of objects.

[0051] Furthermore, the accompanying drawings are merely illustrative of this disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities.

[0052] Polar codes are a forward error correction coding method used for signal transmission. The core of their construction is channel polarization, which employs methods on the coding side to make each sub-channel exhibit different reliability. As the code length continues to increase, some channels will tend towards a perfect channel (error-free) with a capacity close to 1, while other channels will tend towards a pure noise channel with a capacity close to 0. Directly transmitting information on channels with a capacity close to 1 to approximate the channel capacity is the only method that can be rigorously proven to reach the Shannon limit.

[0053] Among related technologies, a method based on parallel SCL decoding of a-bit space segments is provided, in which m segments to be decoded are decoded completely independently, and after the entire segment to be decoded is decoded, a decoding path selection with check code assistance is performed on the m segments to be decoded.

[0054] However, this scheme has the following shortcomings: each sub-segment SCL decoding independently completes the decoding of the entire sub-segment. When selecting alternative paths, it is based on the path with the highest path probability value in each decoded sub-segment, rather than the path with the highest path probability value in the entire decoded sub-segment sequence. Therefore, the path with the highest probability value in the entire decoded sub-segment that is contained in the decoded sub-segment may be deleted, resulting in poor decoding performance.

[0055] In the embodiments of this disclosure, a polar code encoding method is first provided, which at least to some extent overcomes the defects of poor decoding performance caused by related encoding methods.

[0056] Figure 1 The diagram shows a flowchart of a polar code encoding method in an embodiment of this disclosure. The execution entity of the polar code encoding method can be a server that encodes polar codes.

[0057] refer to Figure 1 The polar code encoding method according to an embodiment of the present disclosure includes the following steps:

[0058] Step S110: Divide the bit sequence to be encoded into multiple first segments to be encoded;

[0059] Step S120: Perform segment transformation on multiple first segments to be encoded to obtain multiple second segments to be encoded;

[0060] Step S130: Perform check code generation operation on multiple second sub-segments to be encoded to obtain multiple third sub-segments to be encoded;

[0061] Step S140: Encode multiple third segments to be encoded to obtain an encoded bit sequence.

[0062] exist Figure 1 In the technical solution provided by the embodiment shown, on the one hand, the bit sequence to be encoded is divided to obtain multiple first segments to be encoded, the multiple first segments to be encoded are transformed to obtain multiple second segments to be encoded, the multiple second segments to be encoded are subjected to check code generation operation to obtain multiple third segments to be encoded, and the multiple third segments to be encoded are encoded to obtain an encoded bit sequence. Thus, compared with traditional encoding schemes, this disclosure can achieve flexible encoding and ensure decoding performance.

[0063] The following are Figure 1 The specific implementation process of each step in the process will be explained in detail:

[0064] In step S110, the bit sequence to be encoded is divided to obtain multiple first segments to be encoded.

[0065] In this step, the bit sequence to be encoded can contain multiple bits corresponding to a length N, where N is an integer power of 2, for example, 1024 bits.

[0066] For example, the above-mentioned bit sequence of length N can be divided into m first segments of length n to be encoded. Here, N and m are both integer powers of 2, and N is the product of m and n.

[0067] For example, taking m=2 as an example, then Therefore, the above bit sequence to be encoded can be divided into two first segments of length 512.

[0068] For example, the above m first segments to be encoded can be represented as follows:

[0069] v1 = [v 11 v 12 v 13 …v 1n-1 v 1n ]

[0070] v2 = [v 21 v 22 v 23 …v 2n-1 v 2n ]

[0071] ...

[0072] v m =[v m1 v m2 v m3 …v mn-1 v mn ]

[0073] In step S120, multiple first segments to be encoded are transformed to obtain multiple second segments to be encoded.

[0074] In this step, the above m first segments of length n to be encoded can be transformed to obtain m second segments of length n to be encoded.

[0075] For details, please refer to Figure 2 , Figure 2 This illustration shows a flowchart of a process in which multiple first segments to be encoded are transformed to obtain multiple second segments to be encoded, as described in an embodiment of this disclosure. The process includes steps S201-S202.

[0076] In step S201, a specific set of bits for generating each second segment to be encoded is determined from each first segment to be encoded according to the first segment transformation rule.

[0077] In this step, the above-mentioned first segment transformation rule is used to limit the XOR operation involving only frozen bits to obtain constant 0 bits, the XOR operation involving only information bits to obtain pure information bits, and the XOR operation involving both frozen bits and information bits to obtain mixed bits.

[0078] Specifically, based on the first segment transformation rule, a specific set of bits can be determined for generating each of the second segments to be encoded. For example, the set of bits used to generate a... 1j The specific set of bits includes [v 1j v 2j v 3j , ..., v (m-2)j v (m-1)j v mj ], used to generate a 2j The specific set of bits includes [v 2j v 4j v 6j , ..., v (m-4)j v (m-2)j v mj ].

[0079] In step S202, an XOR operation is performed on at least one specific set of bits to obtain m second segments to be encoded, each of length n.

[0080] In this step, after determining the specific bit set mentioned above, an XOR operation within the set can be performed on at least one specific bit set based on the following expression to obtain m second sub-segments of length n to be encoded; wherein, the frozen bit v mj What is obtained directly is the frozen bit a mj , by information bits v mj What is obtained directly is information bit a mj .

[0081]

[0082] It should be noted that in the above expression, j = 1, 2, 3, ..., n.

[0083] Based on the above expression, the five bit types of the second coded segment can be obtained:

[0084] (1) Constant 0 bit: If the bits with the same sequence number in the m first segments to be encoded are all frozen bits, then the corresponding bits in the resulting second segments to be encoded must be 0, hence they are called constant 0 bits;

[0085] (2) Pure information bits: If the bits with the same sequence number in the m first segments to be encoded are all information bits, then the corresponding bits in the obtained second segments to be encoded are pure information bits, and pure information bits contain information bits;

[0086] (3) Mixed bits: If the bits with the same sequence number in the m first segments to be encoded are frozen bits or information bits, then the corresponding bits in the resulting second segments to be encoded are mixed bits;

[0087] (4) Information bits: If the first segment to be encoded is itself the second segment to be encoded, and the bits in the first segment to be encoded are information bits, then the corresponding bits of the second segment to be encoded are information bits.

[0088] (5) Frozen bits: If the first segment to be encoded is itself the second segment to be encoded, and the bits in the first segment to be encoded are frozen bits, then the corresponding bits of the second segment to be encoded are frozen bits.

[0089] For example, the above m second segments to be encoded, each of length n, can be represented as follows:

[0090] a1=[a 11 a 12 a 13 …a 1n-1 a 1n ]

[0091] a2=[a 21 a 22 a 23 …a 2n-1 a 2n ]

[0092] ...

[0093] a m =[a m1 a m2 a m3 …a mn-1 a mn ]

[0094] In step S130, a checksum generation operation is performed on multiple second sub-segments to be encoded to obtain multiple third sub-segments to be encoded.

[0095] In this step, refer to Figure 3 , Figure 3 This diagram illustrates the process of generating checksums from multiple second segments to be encoded to obtain multiple third segments to be encoded, as shown in this embodiment of the present disclosure. The process includes steps S301-S302.

[0096] In step S301, a check code generation operation is performed on multiple second sub-segments to be encoded to obtain a check code.

[0097] In this step, the above check code may include any one or more combinations of the following: cyclic redundancy check code, parity check code.

[0098] In one optional implementation, the number of the above-mentioned check codes can be one. Thus, the above-mentioned multiple second segments to be encoded can be merged to obtain a merged sequence. For example, the above-mentioned multiple second segments to be encoded can be concatenated end to end to obtain the above-mentioned merged sequence. Then, a check code generation operation can be performed on the merged sequence to generate a check code.

[0099] In another optional implementation, the number of check codes can be multiple. Therefore, the multiple second segments to be encoded can be divided into multiple segment groups, each containing at least one second segment to be encoded. Then, check code generation operations are performed on each segment group to obtain multiple check codes. For example, taking the division of the multiple second segments to be encoded into two segment groups (hereinafter referred to as segment group 1 and segment group 2) as an example, each segment group can contain one second segment to be encoded. Therefore, check code generation operations can be performed on segment group 1 and segment group 2 respectively to obtain two check codes.

[0100] In step S302, the check code is added to the reserved check code position in multiple second sub-segments to be encoded, resulting in multiple third sub-segments to be encoded.

[0101] In this step, after generating the check code, the check code can be added to the pure information bits and / or information bits of multiple second segments to be encoded to obtain multiple third segments to be encoded. The pure information bits and / or information bits are the bits corresponding to the pure information bits and / or information bits obtained by XORing the information bits in the second segments to be encoded.

[0102] In step S140, multiple third segments to be encoded are encoded to obtain an encoded bit sequence.

[0103] In this step, after obtaining the third segment to be encoded, the third segment to be encoded can be encoded to obtain the encoded bit sequence.

[0104] In one optional implementation, the aforementioned plurality of third segments to be encoded can be polar-coded to obtain a plurality of encoded bit segments, and then the plurality of encoded bit segments can be merged to obtain an encoded bit sequence.

[0105] Specifically, multiple third segments to be encoded can be polarized to obtain multiple polar codes, which can then be used as the aforementioned multiple encoded bit segments.

[0106] Given that the first segment to be encoded is a polar code containing information bits and frozen bits, the second segment to be encoded contains at least one of the following: frozen bits and information bits. Therefore, the third segment to be encoded is a polar code containing information bits and frozen bits. Thus, any third segment to be encoded can be... Perform polar code encoding to obtain the corresponding encoded bit segments. n is the length of the first segment to be encoded, G i,n Let be the polar code generation matrix corresponding to the i-th third segment to be encoded, i = 1, 2, 3, ..., m.

[0107] In another optional implementation, the plurality of third sub-segments to be encoded can be reversed to obtain the plurality of transformed third sub-segments to be encoded. Then, the plurality of transformed third sub-segments to be encoded can be polarized to obtain the plurality of encoded bit segments. The plurality of encoded bit segments can be merged to obtain the aforementioned encoded bit sequence.

[0108] For example, if the third sub-segment to be encoded is “1010”, then the third sub-segment to be encoded after the bit reversal transformation can be “0101”.

[0109] In another alternative implementation, an r-order (r is a positive integer, and the specific value of r can be set according to the actual situation, and this disclosure does not make any special limitation) Kronecker operation can be performed on the above-mentioned multiple third segments to be encoded to obtain multiple encoded bit segments. Then, the above-mentioned multiple encoded bit segments can be merged to obtain an encoded bit sequence.

[0110] Specifically, the i-th third segment to be encoded can be... Performing an r-order Kronecker operation yields the corresponding encoded bit segment. n is the length of the third segment to be encoded, and F is the second-order Kronecker kernel. n=2 r , i = 1, 2, 3, ..., m, r is a positive integer.

[0111] This disclosure achieves flexible encoding and ensures decoding performance by dividing the bit sequence to be encoded into multiple first segments to be encoded, and then encoding the multiple segments in parallel.

[0112] In the embodiments of this disclosure, a polar code decoding method is also provided, which at least to some extent overcomes the shortcomings of poor decoding performance in related technologies.

[0113] Figure 4 The diagram shows a flowchart of a polar code decoding method in an embodiment of this disclosure. The execution entity of the polar code decoding method can be a server that decodes polar codes.

[0114] refer to Figure 4 A polar code decoding method according to an embodiment of the present disclosure includes the following steps:

[0115] Step S410: Divide the log-likelihood ratio sequence to be decoded to obtain multiple segments to be decoded;

[0116] Step S420: Perform non-contiguous deletion list (nonSCL) decoding on multiple segments to be decoded to obtain multiple first decoded segments;

[0117] Step S430: Perform segment transformation on multiple first decoding segments to obtain multiple second decoding segments;

[0118] Step S440: Merge multiple second decoding segments to obtain a decoded bit sequence.

[0119] exist Figure 4 In the technical solution provided by the embodiment shown, multiple segments to be decoded are obtained by dividing the log-likelihood ratio sequence to be decoded. Non-contiguous deletion list (nonSCL) decoding is performed on the multiple segments to be decoded to obtain multiple first decoded segments. Segment transformation is performed on the multiple first decoded segments to obtain multiple second decoded segments. The multiple second decoded segments are merged to obtain the decoded bit sequence. This disclosure can select the globally optimal candidate path in each decoding node. The candidate path is used as the basis for splitting to finally determine the decoded bit sequence. Therefore, compared with the traditional decoding scheme, this disclosure can improve the decoding performance while shortening the decoding time.

[0120] The following are Figure 4 The specific implementation process of each step in the process will be explained in detail:

[0121] In step S410, the log-likelihood ratio sequence to be decoded is divided to obtain multiple segments to be decoded.

[0122] In this step, the length N corresponding to the likelihood ratio sequence to be decoded is an integer power of 2.

[0123] In one optional implementation, the aforementioned log-likelihood ratio sequence to be decoded, which has a length of N, can be divided into m segments to be decoded, each of length n; where N and m are both integer powers of 2, and N is the product of m and n. For example, assuming N is 1024 and m is 2, then... Therefore, the log-likelihood ratio sequence to be decoded can be divided into two segments of length 512.

[0124] Specifically, each code segment to be decoded can be represented as follows: Code segment 1 to be decoded can be represented as [y 11 y 12 y13 , ..., y 1n The undecoded segment 2 is represented as [y]. 21 y 22 y 23 , ..., y 2n The segment m to be decoded can be represented as [y]. m1 y m2 y m3 , ..., y mn ], i = 1, 2, ..., m; n is the length of the segment to be decoded. Adjacent segments to be decoded are connected in series, for example, it can be represented as segment to be decoded 1 - segment to be decoded 2 - ... - segment to be decoded m.

[0125] In another alternative implementation, the above-mentioned log-likelihood ratio sequence of length N to be decoded can be divided into multiple initial segments to be decoded, and the multiple initial segments to be decoded can be subjected to bit-reversal transformation to obtain the multiple segments to be decoded.

[0126] For example, if the initial code segment to be decoded is "1010", then the code segment to be decoded after the bit reversal transformation can be "0101".

[0127] In step S420, multiple segments to be decoded are decoded using a non-contiguous deletion list (nonSCL) to obtain multiple first decoded segments.

[0128] In this step, refer to Figure 5 , Figure 5 This diagram illustrates the process of obtaining multiple first decoded segments in an embodiment of the present disclosure, including steps S501-S502:

[0129] In step S501, multiple segments to be decoded are decoded using a non-contiguous deletion list (nonSCL) to obtain multiple merged paths.

[0130] In this step, you can refer to Figure 6 , Figure 6 This diagram illustrates the process of obtaining multiple merged paths in an embodiment of the present disclosure, including steps S601-S607:

[0131] In step S601, each segment to be decoded is decoded using the continuous deletion list SCL decoding to obtain an incomplete first decoding path for each segment to be decoded.

[0132] In this step, the SCL decoding of each segment to be decoded (1, 2, ..., m) can be performed to obtain the incomplete first decoding path of each segment to be decoded. Different segments to be decoded correspond to different first path probability sets.

[0133] For example, the probability of the j-th bit and path splitting can be performed on each of the above m segments to be decoded. When j equals 1, two first decoding paths and their respective path probabilities can be obtained; when j is greater than 1, the 2l-bit path of length j corresponding to the j-th bit can be obtained. ij The first decoding path and the 2l ij The path probabilities corresponding to each of the first decoding paths, where i = 1, 2, ..., m; j = 2, ..., n.

[0134] The first decoding path can be understood as a path corresponding to a portion of the bits in the segment to be decoded. The probability set of the first path can include multiple path probability values. For example, if the segment to be decoded 1 is represented as [bit a, bit b, bit c], and the probability of bit a being 1 is calculated to be 0.8, and the probability of bit a being 0 is calculated to be 0.2, then the probability set corresponding to bit a is: bit a - [0.8, 0.2]. Similarly, the probability set corresponding to bit b is: bit b - [0.2, 0.8]. Following the order of [bit a, bit b, bit c], before calculating the probability corresponding to bit c, the incomplete first decoding path corresponding to the segment to be decoded 1 can be determined. That is, 0.8 in bit a - [0.8, 0.2] can be considered as the first probability of path 1, and 0.2 in bit b - [0.2, 0.8] can be considered as the second probability of path 1. Path 1: 0.8 - 0.2, thus the path probability value of path 1 can be determined to be 0.16. Similarly, we can obtain path 2: 0.8 - 0.8 (path probability value of path 2 is 0.64), path 3: 0.2 - 0.2 (path probability value of path 3 is 0.04), and path 4: 0.2 - 0.8 (path probability value of path 4 is 0.16). Paths 1, 2, 3, and 4 can be understood as the incomplete first decoding paths corresponding to the segment to be decoded 1, and the path probability values ​​of each path constitute the first path probability set corresponding to the segment to be decoded.

[0135] In step S602, each first decoding path is split based on sub-segments to obtain multiple incomplete second decoding paths.

[0136] In this step, path splitting between segments can be performed on each first decoding path to obtain multiple incomplete second decoding paths. Specifically, path splitting between segments can be performed on the first decoding paths of each segment to be decoded. 1j , 2l 2j ,…,2l mj The barcode decoding path is split into paths to obtain a 2l path of length m*j. 1j *2l 2j *…2l mjA non-complete second decoding path.

[0137] For example, if the segment to be decoded 1 corresponds to path 1.1 and path 1.2, and the segment to be decoded 2 corresponds to path 2.1 and path 2.2, then the second decoding path obtained after splitting the segments can be: [path 1.1-path 2.1], [path 1.1-path 2.2], [path 1.2-path 2.1], [path 1.2-path 2.2].

[0138] In step S603, the frozen bit constraint condition is checked for each second decoding path, and the path that passes the check is determined as the third decoding path.

[0139] In this step, the frozen bit constraint condition can be checked for each second decoding path, and the path that passes the check is determined as the third decoding path, such as [path 1.1-path 2.1], [path 1.1-path 2.2], [path 1.2-path 2.1], [path 1.2-path 2.2].

[0140] The process of checking the frozen bit constraint condition of the second decoding path includes: when the final bit is a frozen bit, verifying whether the XOR operation result of the corresponding bits in multiple second decoding paths is consistent with the frozen bit based on the second segment transformation rule. This can improve decoding performance.

[0141] It should be noted that the frozen bit can be represented as any set value (such as 0, 1, etc.) or an identifier, etc., and this disclosure does not impose any special restrictions on it.

[0142] For example, if the first preset quantity is 2, the first bit of the first segment in the [path 1.1-path 2.1] of the decoded segment is 'a'. 11 The first bit of the second sub-segment is a 21 If v 11 For frozen bits (frozen bits are preset to 0), since a 11 and a 21 The result of the XOR operation is equal to v 11 Therefore, when a 11 and a 21 The XOR operation result of a is equal to 0, which satisfies the frozen bit constraint condition, that is, when a 11 and a 21 When the XOR operation result is 0, [path 1.1 - path 2.1] satisfies the frozen bit constraint condition. Conversely, if a 11 and a 21 When the result of the XOR operation is not equal to 0, [path 1.1-path 2.1] does not meet the frozen bit constraint condition. In this case, [path 1.1-path 2.1] will be deleted and cannot be retained as the third decoding path.

[0143] In step S604, each third decoding path is arranged in descending order of path probability value to obtain the first decoding path queue.

[0144] In this step, the third decoding paths can be sorted from largest to smallest according to their path probability values ​​to obtain the first decoding path queue.

[0145] For example, taking the third decoding path as containing [path 1.1-path 2.1], [path 1.1-path 2.2], [path 1.2-path 2.1], [path 1.2-path 2.2] as an example, the first decoding path queue obtained by sorting the third decoding path according to the path probability value from largest to smallest can be {[path 1.2-path 2.1], [path 1.2-path 2.2], [path 1.1-path 2.1], [path 1.1-path 2.2]}.

[0146] In step S605, candidate decoding paths are determined based on each first decoding path queue.

[0147] In this step, after determining the first decoding path queue, alternative decoding paths can be determined based on each first decoding path queue.

[0148] In one optional implementation, the first decoding path queue can be divided based on sub-segments while maintaining the queue order to obtain the second decoding path queues for each sub-segment to be decoded. For example, the second decoding path queue for sub-segment 1 to be decoded is {path 1.2, path 1.2, path 1.1, path 1.1}, and the second decoding path queue for sub-segment 2 to be decoded is {path 2.1, path 2.2, path 2.1, path 2.2}.

[0149] Furthermore, taking the second decoding path queue {path 1.2, path 1.2, path 1.1, path 1.1} as an example, on the one hand, if the number of paths with different probability values ​​detected in the second decoding path queue (e.g., 2, which can be set according to the actual situation, and this disclosure does not make any special limitation) is less than or equal to the first preset threshold (e.g., 3, which can be set according to the actual situation, and this disclosure does not make any special limitation), the paths with different probability values ​​in the second decoding path queue can be used as candidate decoding paths. For example, {path 1.2, path 1.1} can be determined as candidate decoding paths.

[0150] On the other hand, taking the second decoding path queue {path 1.2, path 1.2, path 1.1, path 1.1, path 1.3, path 1.4} as an example, when the number of paths with different probability values ​​detected in the second decoding path queue is greater than the first preset threshold (e.g., 3), the first preset threshold number (e.g., 3) of paths with different probability values ​​can be selected as the above-mentioned candidate decoding paths. For example, {path 1.2, path 1.1, path 1.3} can be determined as candidate decoding paths.

[0151] In another optional implementation, the first second preset threshold number of paths (e.g., 8, which can be set according to actual conditions, and this disclosure does not make any special limitation) can be selected from the first decoding path queue as the third decoding path queue, for example: {[path1.2-path2.1], [path1.1-path2.1], [path1.2-path2.2], [path1.1-path2.3], [path1.2-path2.2], [path1.1-path2.3], [path1.2-path2.4], [path1.1-path2.4]}.

[0152] After determining the third decoding path queue, the third decoding path queue can be divided based on the sub-segments while maintaining the queue order, to obtain the fourth decoding path queue for each sub-segment to be decoded. For example, the fourth decoding path queue for sub-segment 1 to be decoded is {path 1.2, path 1.1, path 1.2, path 1.1, path 1.2, path 1.1, path 1.2, path 1.1}, and the fourth decoding path queue for sub-segment 2 to be decoded is {path 2.1, path 2.1, path 2.2, path 2.3, path 2.2, path 2.3, path 2.4, path 2.4}.

[0153] Therefore, referring to the relevant explanations of the above steps, taking the fourth decoding path queue {path 1.2, path 1.1, path 1.2, path 1.1, path 1.2, path 1.1} as an example, on the one hand, if the number of paths with different probability values ​​detected in the fourth decoding path queue (e.g., 2, which can be set according to the actual situation, and this disclosure does not make any special limitation) is less than or equal to the first preset threshold (e.g., 3, which can be set according to the actual situation, and this disclosure does not make any special limitation), the paths with different probability values ​​in the fourth decoding path queue can be used as candidate decoding paths. For example, {path 1.2, path 1.1} can be determined as candidate decoding paths.

[0154] On the other hand, taking the fourth decoding path queue {path 2.1, path 2.1, path 2.2, path 2.3, path 2.2, path 2.3, path 2.4, path 2.4]} as an example, when the number of paths with different probability values ​​detected in the fourth decoding path queue is greater than the first preset threshold (e.g., 3), the first preset threshold number (e.g., 3) of paths with different probability values ​​can be selected as the above-mentioned candidate decoding paths. For example, {path 2.1, path 2.2, path 2.3} can be determined as candidate decoding paths.

[0155] In step S606, non-contiguous deletion list (nonSCL) decoding is performed on each segment to be decoded based on the alternative decoding paths.

[0156] In this step, after selecting candidate decoding paths, non-contiguous deletion list (nonSCL) decoding can be performed on each segment to be decoded based on the candidate decoding paths. Specifically, based on the candidate decoding paths, continuous deletion list (nonSCL) decoding of the next bit can be performed on each segment to be decoded to obtain an incomplete first decoding path for each segment. Then, the first decoding paths are split based on segments to obtain multiple incomplete second decoding paths. The frozen bit constraint condition is checked on each of the second decoding paths, and the paths that pass the check are determined as third decoding paths. The third decoding paths are arranged in descending order of path probability value to obtain a first decoding path queue. Candidate decoding paths are determined based on the queue of first decoding paths. Non-contiguous deletion list (nonSCL) decoding is performed on each segment to be decoded based on the candidate decoding paths. This step S606 is repeated continuously until the non-contiguous deletion list decoding of the last bit of each segment to be decoded is completed.

[0157] In step S607, when the length of the second decoding path is N, a merging path is determined based on each candidate decoding path.

[0158] In this step, when the second decoding path of length N is obtained, it can be determined that the non-contiguous deletion list decoding of the last bit of each segment to be decoded has been completed. Based on this, multiple merging paths can be determined according to each alternative decoding path.

[0159] Next, refer to Figure 5 In step S502, multiple first decoding segments are determined based on multiple merging paths.

[0160] In this step, after determining the merging path, each merging path can be verified based on a preset verification method. The merging path that passes the verification and has the highest probability is determined as the final decoding path. Then, the final decoding path can be divided based on sub-segments to obtain multiple first decoding sub-segments corresponding to multiple sub-segments to be decoded.

[0161] Specifically, the aforementioned preset verification methods may include, but are not limited to, cyclic redundancy check (CRC) and parity check. The CRC code is generated based on the mixed bits and pure information bits / information bits in the segment to be encoded, and the check code can be set in the pure information bits / information bit positions of the segment to be encoded. If multiple check code schemes are used, multiple check codes can be generated based on the corresponding mixed bits and pure information bits / information bits in the segment to be encoded, and the bits of the multiple check codes can be set in the pure information bit positions / information bit positions of the segment to be encoded.

[0162] Next, refer to Figure 4 In step S430, multiple first decoding segments are transformed to obtain multiple second decoding segments.

[0163] In this step, the multiple first decoded segments can be transformed to obtain multiple transformed second decoded segments. The multiple first decoded segments can be represented as follows:

[0164]

[0165] The aforementioned multiple second decoding segments can be represented as follows:

[0166]

[0167] For details, please refer to Figure 7 , Figure 7 This illustration shows a flowchart of a process in which multiple first decoding segments are transformed to obtain multiple second decoding segments in an embodiment of this disclosure, including steps S701-S702:

[0168] In step S701, the initial bit set for generating each second decoding segment is determined from each first decoding segment according to the second segment transformation rule.

[0169] In this step, the above-mentioned second sub-segment transformation rule is the inverse transformation of the first sub-segment transformation rule on the encoding side. The second sub-segment transformation rule can be understood as follows: based on the constant 0 bits, it can be determined that it is obtained by the XOR operation of the frozen bits; based on the pure information bits, it can be determined that it is obtained by the XOR operation of the information bits; based on the mixed bits, it can be determined that it is obtained by the XOR operation of the frozen bits and the information bits. The frozen bits are obtained directly from the frozen bits, and the information bits are obtained directly from the information bits.

[0170] Specifically, the initial bit set used to generate each second decoded segment can be determined according to the second transformation rule. For example, the set of bits used to generate... The initial bit set includes Used to generate The initial bit set includes

[0171] In step S702, an XOR operation is performed on at least one initial bit set to obtain multiple second decoded segments.

[0172] In this step, after determining the initial bit set, an XOR operation can be performed on at least one initial bit set based on the following expression to obtain m second decoding segments of length n.

[0173]

[0174] It should be noted that in the above expression, j = 1, 2, 3, ..., n.

[0175] In step S440, multiple second decoding segments are merged to obtain a decoded bit sequence.

[0176] In this step, the above-mentioned multiple second decoding segments of length n can be merged to obtain a decoding bit sequence of length N as the decoding result.

[0177] Therefore, this disclosure can divide the sequence to be decoded into multiple segments to be decoded and decode them in a manner corresponding to the encoding side. Then, multiple first decoded segments are determined according to each decoded segment. By performing segment transformation and segment merging on the first decoded segments, the decoded bit sequence is obtained. Since multiple segments to be decoded can be decoded by multiple segment decoders according to the encoding rules, the decoding flexibility and decoding performance are improved on the decoding side.

[0178] refer to Figure 8 , Figure 8 This diagram illustrates the overall flowchart of the polar code decoding method in an embodiment of this disclosure, as follows: Figure 8 As shown:

[0179] The likelihood ratio sequence to be decoded can be divided into m segments to be decoded. Then, the segment SCL decoder 801, segment SCL decoder 802, ..., segment SCL decoder 803 can be used to perform continuous deletion list SCL decoding on each segment to be decoded to obtain the first path probability set of the incomplete first decoding path of each segment to be decoded.

[0180] The segment concatenation / L alternative path selection module 804 can be used to split the path between segments of each first decoding path to obtain multiple incomplete second decoding paths; perform frozen bit constraint condition checks on the second decoding paths, and determine the paths that pass the check as third decoding paths; arrange each third decoding path in descending order of path probability value to obtain a first decoding path queue; and determine alternative decoding paths based on each first decoding path queue.

[0181] In addition, the sub-segment SCL decoder 801, sub-segment SCL decoder 802, ..., sub-segment SCL decoder 803 can also be used to continue non-continuous deletion list nonSCL decoding of each sub-segment to be decoded based on the alternative decoding path.

[0182] In addition, the segment concatenation / L alternative path selection 804 can be used to determine multiple merging paths based on each alternative decoding path when the length of the second decoding path is N.

[0183] The verification module 805 can be used to verify each merging path based on a preset verification method, and determine the merging path that passes the verification and has the highest probability as the final decoding path; the final decoding path is divided based on sub-segments to obtain multiple first decoding sub-segments;

[0184] The segment transformation module and the merging module 806 can be used to determine the initial bit set for generating the second decoding segment from each of the first decoding segments according to the second segment transformation rule, and perform an XOR operation within at least one initial bit set to obtain multiple second decoding segments. Then, the multiple obtained second decoding segments can be merged to obtain a decoding bit sequence (i.e., the decoding result) of length N.

[0185] As can be seen, the polar code decoding method in this disclosure can be implemented by dividing the likelihood ratio sequence to be decoded into multiple segments to be decoded and decoding them, corresponding to the encoding side. Then, multiple first decoding segments are determined based on each segment, and the decoded bit sequence is obtained through segment transformation and segment merging. Furthermore, since multiple segment decoders can decode the multiple segments to be decoded according to the encoding rules, this improves both encoding flexibility and decoding performance on the decoding side, while also enhancing decoding flexibility and performance.

[0186] This disclosure also provides an encoding device for polar codes. Figure 9 This diagram illustrates the structure of a polar code encoding apparatus in an exemplary embodiment of this disclosure; as shown below. Figure 9 As shown, the polar code encoding device 900 may include a segmentation module 910, a segment transformation module 920, a check code generation module 930, and an encoding module 940. Wherein:

[0187] The segmentation module 910 is used to segment the bit sequence to be encoded to obtain multiple first segments to be encoded;

[0188] The segment transformation module 920 is used to perform segment transformation on the plurality of first segments to be encoded to obtain a plurality of second segments to be encoded.

[0189] The check code generation module 930 is used to perform check code generation operations on multiple second sub-segments to be encoded to obtain multiple third sub-segments to be encoded.

[0190] The encoding module 940 is used to encode the plurality of third segments to be encoded to obtain an encoded bit sequence.

[0191] In an exemplary embodiment of this disclosure, the partitioning module 910 partitions the bit sequence to be encoded to obtain a plurality of first sub-segments to be encoded, including: partitioning the bit sequence to be encoded of length N to obtain m first sub-segments to be encoded of length n.

[0192] In an exemplary embodiment of this disclosure, the segmentation module 910 performs segment transformation on the plurality of first segments to be encoded to obtain a plurality of second segments to be encoded, including: performing segment transformation on the m first segments to be encoded of length n to obtain m second segments to be encoded of length n; wherein N and m are both integer powers of 2, and N is the product of m and n.

[0193] In an exemplary embodiment of this disclosure, the segment transformation module 920 performs segment transformation on the m first segments to be encoded of length n to obtain m second segments to be encoded of length n, including: determining a specific set of bits from each of the first segments to be encoded according to a first segment transformation rule for generating each second segment to be encoded; performing an XOR operation within the set on at least one specific set of bits to obtain the m second segments to be encoded of length n; wherein, the first segment transformation rule is used to limit the XOR operation involving only frozen bits to obtain constant 0 bits, the XOR operation involving only information bits to obtain pure information bits, and the XOR operation involving both frozen bits and information bits to obtain mixed bits.

[0194] In an exemplary embodiment of this disclosure, the check code generation module 930 performs check code generation operations on multiple second sub-segments to be encoded to obtain multiple third sub-segments to be encoded, including: performing check code generation operations on the multiple second sub-segments to be encoded to obtain check codes; and adding the check codes to reserved check code positions in the multiple second sub-segments to be encoded to obtain multiple third sub-segments to be encoded.

[0195] In an exemplary embodiment of this disclosure, the check code generation module 930 performs check code generation operations on the plurality of second sub-segments to be encoded to obtain a check code, including: merging the plurality of second sub-segments to be encoded to obtain a merged sequence; and performing check code generation operations on the merged sequence to obtain the check code.

[0196] In an exemplary embodiment of this disclosure, the check code generation module 930 performs check code generation operations on the plurality of second sub-segments to be encoded to obtain check codes, and further includes: dividing the plurality of second sub-segments to be encoded into a plurality of sub-segment groups, each sub-segment group containing at least one second sub-segment to be encoded; and performing check code generation operations on each of the sub-segment groups to obtain a plurality of check codes.

[0197] In an exemplary embodiment of this disclosure, the check code generation module 930 adds the check code to a reserved check code position in the plurality of second sub-segments to be encoded to obtain a plurality of third sub-segments to be encoded, including: adding the check code to the pure information bits and / or information bits in the plurality of second sub-segments to be encoded to obtain the plurality of third sub-segments to be encoded; wherein, the pure information bits and / or information bits are the bits corresponding to the pure information bits and / or information bits obtained by XOR operation only on the information bits in the second sub-segments to be encoded.

[0198] In an exemplary embodiment of this disclosure, the encoding module 940 encodes the plurality of third segments to be encoded to obtain an encoded bit sequence, including: performing polar code encoding on the plurality of third segments to be encoded to obtain a plurality of encoded bit segments; and merging the plurality of encoded bit segments to obtain the encoded bit sequence.

[0199] In an exemplary embodiment of this disclosure, the encoding module 940 encodes the plurality of third segments to be encoded to obtain an encoded bit sequence, including: performing a bit-reversal transformation on the plurality of third segments to be encoded to obtain a plurality of transformed third segments to be encoded; performing polar code encoding on the transformed plurality of third segments to be encoded to obtain a plurality of encoded bit segments; and merging the plurality of encoded bit segments to obtain the encoded bit sequence.

[0200] In an exemplary embodiment of this disclosure, the encoding module 940 encodes the plurality of third segments to be encoded to obtain an encoded bit sequence, including: performing an r-order Kronecker operation on the plurality of third segments to be encoded to obtain a plurality of encoded bit segments, where r is a positive integer; and merging the plurality of encoded bit segments to obtain the encoded bit sequence.

[0201] The specific details of each module in the above-mentioned polar code encoding device have been described in detail in the corresponding polar code encoding method, so they will not be repeated here.

[0202] This disclosure also provides a polar code decoding apparatus. Figure 10 This diagram illustrates the structure of a polar code decoding apparatus in an exemplary embodiment of this disclosure; as shown... Figure 10As shown, the polar code decoding device 1000 may include a segmentation module 1010, a decoding module 1020, a segment transformation module 1030, and a merging module 1040. Wherein:

[0203] The partitioning module 1010 is used to partition the log-likelihood ratio sequence to be decoded into multiple segments to be decoded.

[0204] Decoding module 1020 is used to perform non-contiguous deletion list (nonSCL) decoding on the plurality of segments to be decoded to obtain a plurality of first decoded segments;

[0205] The segment transformation module 1030 is used to perform segment transformation on the plurality of first decoded segments to obtain a plurality of second decoded segments;

[0206] The merging module 1040 is used to merge the multiple second decoding segments to obtain a decoded bit sequence.

[0207] In an exemplary embodiment of this disclosure, the partitioning module 1010 partitions the log-likelihood ratio sequence to be decoded to obtain multiple segments to be decoded, including: partitioning the log-likelihood ratio sequence to be decoded of length N to obtain m segments to be decoded of length n; wherein N and m are both integer powers of 2, and N is the product of m and n.

[0208] In an exemplary embodiment of this disclosure, the partitioning module 1010 partitions the log-likelihood ratio sequence to be decoded to obtain multiple segments to be decoded, including: partitioning the log-likelihood ratio sequence to be decoded of length N to obtain multiple initial segments to be decoded; and performing a bit-reversal transformation on the multiple initial segments to be decoded to obtain the multiple segments to be decoded.

[0209] In an exemplary embodiment of this disclosure, the decoding module 1020 performs non-contiguous deletion list (nonSCL) decoding on the plurality of segments to be decoded to obtain a plurality of first decoded segments, including: performing non-contiguous deletion list (nonSCL) decoding on the plurality of segments to be decoded to obtain a plurality of merged paths; and determining the plurality of first decoded segments based on the plurality of merged paths.

[0210] In an exemplary embodiment of this disclosure, the decoding module 1020 performs non-contiguous deletion list (nonSCL) decoding on the plurality of segments to be decoded to obtain a plurality of merged paths, including: performing continuous deletion list (SCL) decoding on each of the segments to be decoded to obtain an incomplete first decoding path for each segment; performing segment-based path splitting on each of the first decoding paths to obtain a plurality of incomplete second decoding paths; performing a frozen bit constraint condition check on each of the second decoding paths and determining the paths that pass the check as third decoding paths; arranging each of the third decoding paths in descending order of path probability value to obtain a first decoding path queue; determining candidate decoding paths based on each of the first decoding path queues; continuing to perform non-contiguous deletion list (nonSCL) decoding on each segment to be decoded based on the candidate decoding paths; and determining the merged path based on each candidate decoding path when the length of the second decoding path is N.

[0211] In an exemplary embodiment of this disclosure, the decoding module 1020 determines candidate decoding paths based on each of the first decoding path queues, including: dividing the first decoding path queues based on sub-segments while maintaining the queue order to obtain second decoding path queues for each of the sub-segments to be decoded; when the number of paths with different probability values ​​in the second decoding path queues is less than or equal to a first preset threshold, the paths with different probability values ​​in the second decoding path queues are selected as candidate decoding paths; when the number of paths with different probability values ​​in the second decoding path queues is greater than the first preset threshold, the first preset threshold number of paths with different probability values ​​are selected as candidate decoding paths.

[0212] In an exemplary embodiment of this disclosure, the decoding module 1020 determines candidate decoding paths for each of the first decoding path queues, including: selecting a second preset threshold number of paths from the first decoding path queue as a third decoding path queue; dividing the third decoding path queue based on sub-segments while maintaining the queue order to obtain a fourth decoding path queue for each of the sub-segments to be decoded; when the number of paths with different probability values ​​in the fourth decoding path queue is less than or equal to a first preset threshold, selecting the paths with different probability values ​​in the fourth decoding path queue as candidate decoding paths; when the number of paths with different probability values ​​in the fourth decoding path queue is greater than the first preset threshold, selecting a first preset threshold number of paths with different probability values ​​as candidate decoding paths.

[0213] In an exemplary embodiment of this disclosure, the decoding module 1020 determines the plurality of first decoding segments based on the plurality of merging paths, including: verifying each of the merging paths based on a preset verification method, determining the merging path that passes the verification and has the highest probability as the final decoding path; and dividing the final decoding path based on segments to obtain the plurality of first decoding segments.

[0214] In an exemplary embodiment of this disclosure, the sub-segment transformation module 1030 performs sub-segment transformation on the plurality of first decoded sub-segments to obtain a plurality of second decoded sub-segments, including: determining an initial bit set from each of the first decoded sub-segments for generating each of the second decoded sub-segments according to a second sub-segment transformation rule; wherein the second sub-segment transformation rule is the inverse transformation of the first sub-segment transformation rule on the encoding side; and performing an XOR operation within the set on at least one initial bit set to obtain a plurality of second decoded sub-segments.

[0215] In an exemplary embodiment of this disclosure, the merging module 1040 merges the plurality of second decoded segments to obtain a decoded bit sequence, including: merging m second decoded segments of length n to obtain the decoded bit sequence of length N.

[0216] The specific details of each module in the above-mentioned polar code decoding device have been described in detail in the corresponding polar code decoding method, so they will not be repeated here.

[0217] It should be noted that although several modules or units for the device used to perform actions have been mentioned in the detailed description above, this division is not mandatory. In fact, according to embodiments of this disclosure, the features and functions of two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided and embodied by multiple modules or units.

[0218] Furthermore, although the steps of the method in this disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or a step may be broken down into multiple steps.

[0219] From the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein can be implemented by software or by combining software with necessary hardware. Therefore, the technical solutions according to the embodiments of this disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as a CD-ROM, USB flash drive, external hard drive, etc.) or on a network, including several instructions to cause a computing device (such as a personal computer, server, mobile terminal, or network device, etc.) to execute the methods according to the embodiments of this disclosure.

[0220] This application also provides a computer-readable storage medium, which may be included in the electronic device described in the above embodiments; or it may exist independently and not assembled into the electronic device.

[0221] Computer-readable storage media can be, for example—but not limited to—electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatuses, or devices, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to: electrical connections having one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In this disclosure, a computer-readable storage medium can be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, apparatus, or device.

[0222] Computer-readable storage media can be sent, propagated, or transmitted for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on a computer-readable storage medium can be transmitted using any suitable medium, including but not limited to: wireless, wireline, optical fiber, RF, etc., or any suitable combination thereof.

[0223] A computer-readable storage medium carries one or more programs that, when executed by an electronic device, cause the electronic device to perform the methods described in the above embodiments.

[0224] Furthermore, this disclosure also provides an electronic device capable of implementing the above-described method.

[0225] Those skilled in the art will understand that various aspects of this disclosure can be implemented as a system, method, or program product. Therefore, various aspects of this disclosure can be specifically implemented in the following forms: a completely hardware implementation, a completely software implementation (including firmware, microcode, etc.), or a combination of hardware and software aspects, collectively referred to herein as a "circuit," "module," or "system."

[0226] The following reference Figure 11 To describe an electronic device 1100 according to such an embodiment of the present disclosure. Figure 11 The electronic device 1100 shown is merely an example and should not impose any limitation on the functionality and scope of use of the embodiments disclosed herein.

[0227] like Figure 11 As shown, the electronic device 1100 is manifested in the form of a general-purpose computing device. The components of the electronic device 1100 may include, but are not limited to: at least one processing unit 1110, at least one storage unit 1120, a bus 1130 connecting different system components (including storage unit 1120 and processing unit 1110), and a display unit 1140.

[0228] The storage unit stores program code that can be executed by the processing unit 1110, causing the processing unit 1110 to perform the steps described in the "Exemplary Methods" section of this specification according to various exemplary embodiments of this disclosure. For example, the processing unit 1110 can perform actions such as... Figure 1 As shown: Step S110, divide the bit sequence to be encoded into multiple first segments to be encoded; Step S120, perform segment transformation on the multiple first segments to be encoded into multiple second segments to be encoded; Step S130, perform checksum generation operation on the multiple second segments to be encoded into multiple third segments to be encoded; Step S140, encode the multiple third segments to be encoded into an encoded bit sequence. Alternatively, the processing unit 1110 can perform the following steps: Figure 4 As shown: Step S410, the log-likelihood ratio sequence to be decoded is divided to obtain multiple segments to be decoded; Step S420, the multiple segments to be decoded are subjected to non-contiguous deletion list (nonSCL) decoding to obtain multiple first decoded segments; Step S430, the multiple first decoded segments are subjected to segment transformation to obtain multiple second decoded segments; Step S440, the multiple second decoded segments are merged to obtain a decoded bit sequence.

[0229] Storage unit 1120 may include a readable medium in the form of a volatile storage unit, such as random access memory (RAM) 11201 and / or cache memory 11202, and may further include a read-only memory (ROM) 11203.

[0230] Storage unit 1120 may also include a program / utility 11204 having a set (at least one) of program modules 11205, such program modules 11205 including but not limited to: operating system, one or more application programs, other program modules and program data, each or some combination of these examples may include an implementation of a network environment.

[0231] Bus 1130 can represent one or more of several types of bus structures, including a memory cell bus or memory cell controller, a peripheral bus, a graphics acceleration port, a processing unit, or a local bus using any of the various bus structures.

[0232] Electronic device 1100 can also communicate with one or more external devices 1200 (e.g., keyboard, pointing device, Bluetooth device, etc.), one or more devices that enable a user to interact with electronic device 1100, and / or any device that enables electronic device 1100 to communicate with one or more other computing devices (e.g., router, modem, etc.). This communication can be performed via input / output (I / O) interface 1150. Furthermore, electronic device 1100 can also communicate with one or more networks (e.g., local area network (LAN), wide area network (WAN), and / or public networks, such as the Internet) via network adapter 1160. As shown, network adapter 1160 communicates with other modules of electronic device 1100 via bus 1130. It should be understood that, although not shown in the figures, other hardware and / or software modules can be used in conjunction with electronic device 1100, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0233] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.

Claims

1. A polar code encoding method, comprising: The bit sequence to be encoded is divided into multiple first segments to be encoded; The plurality of first sub-segments to be encoded are subjected to sub-segment transformation to obtain a plurality of second sub-segments to be encoded. Perform checksum generation operations on multiple second sub-segments to be encoded to obtain multiple third sub-segments to be encoded. The step of performing checksum generation operations on multiple second sub-segments to be encoded to obtain multiple third sub-segments to be encoded includes: Perform a check code generation operation on the plurality of second sub-segments to be encoded to obtain a check code; The check code is added to the reserved check code position in the plurality of second sub-segments to be encoded to obtain a plurality of third sub-segments to be encoded; Performing a checksum generation operation on the plurality of second segments to be encoded to obtain a checksum, further comprising: The plurality of second segments to be encoded are divided into a plurality of segments groups, and each segment group contains at least one second segment to be encoded. Perform check code generation operations on each of the sub-segments to obtain multiple check codes; The plurality of third segments to be encoded are encoded to obtain an encoded bit sequence.

2. The method according to claim 1, characterized in that, The bit sequence to be encoded is divided into multiple first segments to be encoded, including: The bit sequence to be encoded, which has a length of N, is divided into m first sub-segments of length n to be encoded. Wherein, N is the bit length of the bit sequence to be encoded, and N and m are both integer powers of 2, with N being the product of m and n.

3. The method according to claim 2, characterized in that, The step of performing segment transformation on the plurality of first segments to be encoded to obtain a plurality of second segments to be encoded includes: The m first segments to be encoded, each with a length of n, are transformed to obtain m second segments to be encoded, each with a length of n.

4. The method according to claim 3, characterized in that, The step of performing segment transformation on the m first segments to be encoded of length n to obtain m second segments to be encoded of length n includes: According to the first segment transformation rule, a specific set of bits for generating each second segment to be encoded is determined from each of the first segments to be encoded; Perform an XOR operation on at least one specific set of bits to obtain the m second sub-segments of length n to be encoded. The first sub-segment transformation rule is used to limit the XOR operation involving only frozen bits to obtain constant 0 bits, the XOR operation involving only information bits to obtain pure information bits, and the XOR operation involving both frozen bits and information bits to obtain mixed bits.

5. The method according to claim 1, characterized in that, Perform checksum generation operations on the plurality of second segments to be encoded to obtain checksums, including: The multiple second segments to be encoded are merged to obtain a merged sequence; The merged sequence is subjected to a checksum generation operation to obtain the checksum.

6. The method according to claim 1, characterized in that, The step of adding the check code to the reserved check code position in the plurality of second sub-segments to be encoded to obtain a plurality of third sub-segments to be encoded includes: The check code is added to the information bits of the plurality of second sub-segments to be encoded to obtain the plurality of third sub-segments to be encoded. The information bit is the bit corresponding to the information bit obtained by XORing only the information bits in the second segment to be encoded.

7. The method according to any one of claims 1 to 6, characterized in that, The process of encoding the plurality of third segments to be encoded to obtain an encoded bit sequence includes: Polar code encoding is performed on the plurality of third sub-segments to be encoded to obtain a plurality of encoded bit sub-segments; The multiple coded bit segments are merged to obtain the coded bit sequence.

8. The method according to any one of claims 1 to 6, characterized in that, The process of encoding the plurality of third segments to be encoded to obtain an encoded bit sequence includes: The multiple third sub-segments to be encoded are subjected to a bit-reversal transformation to obtain multiple transformed third sub-segments to be encoded. The transformed third sub-segments to be encoded are polarized to obtain multiple encoded bit segments; The multiple coded bit segments are merged to obtain the coded bit sequence.

9. The method according to any one of claims 1 to 5, characterized in that, The process of encoding the plurality of third segments to be encoded to obtain an encoded bit sequence includes: Perform an r-order Kronecker operation on the plurality of third sub-segments to be encoded to obtain a plurality of encoded bit sub-segments, where r is a positive integer; The multiple coded bit segments are merged to obtain the coded bit sequence.

10. A method for decoding polar codes, characterized in that, include: The sequence of log-likelihood ratios to be decoded is divided into multiple segments to be decoded; The multiple segments to be decoded are subjected to non-contiguous deletion list (nonSCL) decoding to obtain multiple first decoded segments. The step of performing non-contiguous deletion list (nonSCL) decoding on the plurality of segments to be decoded to obtain a plurality of first decoded segments includes: performing non-contiguous deletion list (nonSCL) decoding on the plurality of segments to be decoded to obtain a plurality of merge paths; and determining the plurality of first decoded segments based on the plurality of merge paths. The process of performing non-contiguous deletion list (nonSCL) decoding on the plurality of segments to be decoded to obtain multiple merged paths includes: performing continuous deletion list (SCL) decoding on each of the segments to be decoded to obtain an incomplete first decoding path for each segment; performing segment-based path splitting on each of the first decoding paths to obtain multiple incomplete second decoding paths; performing a frozen bit constraint test on each of the second decoding paths and determining the paths that pass the test as third decoding paths; arranging each of the third decoding paths in descending order of path probability values ​​to obtain a first decoding path queue; determining candidate decoding paths based on each of the first decoding path queues; continuing to perform non-contiguous deletion list (nonSCL) decoding on each segment to be decoded based on the candidate decoding paths; and determining the merged path based on each candidate decoding path when the length of the second decoding path is equal to N; wherein N is the bit length of the log-likelihood ratio sequence to be decoded, and N is an integer power of 2. Sub-segment transformation is performed on the plurality of first decoded sub-segments to obtain a plurality of second decoded sub-segments; The multiple second decoding segments are combined to obtain a decoded bit sequence.

11. The method according to claim 10, characterized in that, The sequence of log-likelihood ratios to be decoded is divided into multiple segments to be decoded, including: The sequence of log-likelihood ratios to be decoded, which is of length N, is divided into m segments of length n to be decoded. Where m is an integer power of 2, and N is the product of m and n.

12. The method according to claim 10, characterized in that, The sequence of log-likelihood ratios to be decoded is divided into multiple segments to be decoded, including: The sequence of log-likelihood ratios to be decoded, which has a length of N, is divided to obtain multiple initial segments to be decoded; The multiple initial code segments to be decoded are subjected to a bit-reversal transformation to obtain the multiple code segments to be decoded.

13. The method according to claim 10, characterized in that, The step of determining candidate decoding paths based on each of the first decoding path queues includes: The first decoding path queue is divided based on sub-segments while maintaining the queue order, to obtain the second decoding path queue for each of the sub-segments to be decoded; When the number of paths with different probability values ​​in the second decoding path queue is less than or equal to the first preset threshold, the paths with different probability values ​​in the second decoding path queue are used as the candidate decoding paths. When the number of paths with different probability values ​​in the second decoding path queue is greater than the first preset threshold, the first preset threshold number of paths with different probability values ​​are selected as the candidate decoding paths.

14. The method according to claim 10, characterized in that, The step of determining candidate decoding paths based on each of the first decoding path queues includes: Select the first second preset threshold number of paths from the first decoding path queue as the third decoding path queue; The third decoding path queue is divided based on sub-segments while maintaining the queue order, to obtain the fourth decoding path queue for each of the sub-segments to be decoded. When the number of paths with different probability values ​​in the fourth decoding path queue is less than or equal to the first preset threshold, the paths with different probability values ​​in the fourth decoding path queue are used as the candidate decoding paths. When the number of paths with different probability values ​​in the fourth decoding path queue is greater than the first preset threshold, the first preset threshold number of paths with different probability values ​​are selected as the candidate decoding paths.

15. The method according to claim 10, characterized in that, Determining the plurality of first decoded segments based on the plurality of merging paths includes: Each of the merging paths is verified based on a preset verification method, and the merging path that passes the verification and has the highest probability is determined as the final decoding path. The final decoding path is divided into segments to obtain the plurality of first decoding segments.

16. The method according to any one of claims 10 to 15, characterized in that, The step of performing segment transformation on the plurality of first decoded segments to obtain a plurality of second decoded segments includes: The initial bit set for generating each second decoded segment is determined from each of the first decoded segments according to the second segment transformation rule; wherein the second segment transformation rule is the inverse transformation of the first segment transformation rule on the encoding side; Perform an XOR operation on at least one initial set of bits to obtain multiple second decoded segments.

17. The method according to any one of claims 10 to 15, characterized in that, The merging of the multiple second decoded segments to obtain a decoded bit sequence includes: Merge m second decoded segments of length n to obtain the decoded bit sequence of length N.

18. A polar code encoding device, characterized in that, include: The partitioning module is used to partition the bit sequence to be encoded into multiple first segments to be encoded. The segment transformation module is used to perform segment transformation on the plurality of first segments to be encoded to obtain a plurality of second segments to be encoded. The check code generation module is used to perform check code generation operations on multiple second sub-segments to be encoded, thereby obtaining multiple third sub-segments to be encoded. The check code generation module is used to perform check code generation operations on the plurality of second sub-segments to be encoded to obtain a check code; The check code is added to the reserved check code position in the plurality of second sub-segments to be encoded to obtain a plurality of third sub-segments to be encoded; The check code generation module is used to divide the plurality of second sub-segments to be encoded into a plurality of sub-segment groups, each sub-segment group containing at least one second sub-segment to be encoded. Perform check code generation operations on each of the sub-segments to obtain multiple check codes; The encoding module is used to encode the plurality of third segments to be encoded to obtain an encoded bit sequence.

19. A polar code decoding device, characterized in that, include: The partitioning module is used to partition the log-likelihood ratio sequence to be decoded into multiple segments to be decoded. The decoding module is used to perform non-contiguous deletion list (nonSCL) decoding on the plurality of segments to be decoded to obtain a plurality of first decoded segments; The decoding module is used to perform non-contiguous deletion list (nonSCL) decoding on the multiple segments to be decoded, resulting in multiple merged paths; The plurality of first decoded segments are determined based on the plurality of merging paths; The decoding module is used to perform continuous deletion list SCL decoding on each of the segments to be decoded to obtain an incomplete first decoding path for each segment to be decoded. Each of the first decoding paths is split based on sub-segments to obtain multiple incomplete second decoding paths; Each of the second decoding paths is subjected to a frozen bit constraint test, and the path that passes the test is determined as the third decoding path; The third decoding paths are arranged in descending order of their path probability values ​​to obtain the first decoding path queue; Candidate decoding paths are determined based on each of the first decoding path queues; Based on the alternative decoding paths, continue to perform non-contiguous deletion list (nonSCL) decoding on each segment to be decoded. When the length of the second decoding path is equal to N, the merging path is determined based on each candidate decoding path; where N is the bit length of the log-likelihood ratio sequence to be decoded, and N is an integer power of 2; The segment transformation module is used to perform segment transformation on the plurality of first decoded segments to obtain a plurality of second decoded segments; The merging module is used to merge the multiple second decoding segments to obtain a decoded bit sequence.

20. A computer storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the encoding method of the polar code according to any one of claims 1 to 9 or the decoding method of the polar code according to any one of claims 10 to 17.

21. An electronic device, characterized in that, include: processor; as well as Memory for storing the executable instructions of the processor; The processor is configured to execute the encoding method of the polar code according to any one of claims 1 to 9 or the decoding method of the polar code according to any one of claims 10 to 17 by executing the executable instructions.

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