Method of power management, memory device and controller thereof, and electronic device

Abstract

A method for power management in a memory device, a related memory device and controller thereof, and a related electronic device are disclosed. The memory device includes a non-volatile memory, and the non-volatile memory includes at least one non-volatile memory component. The method can include, during an initialization phase of the memory device, detecting whether a host device supports communication corresponding to a first communication protocol; and controlling a physical layer circuit in the memory device to remain in a power-off state to conserve power, before detecting that the host device supports communication corresponding to the first communication protocol, wherein the physical layer circuit supports communication corresponding to the first communication protocol. By the present invention, the controller (e.g., a power-on control circuit therein) can selectively turn on or off one or more corresponding power switches in the controller, so that there is no unnecessary power consumption problem.

Description

[0001] The original application's application date, application number, and invention title are as follows:

[0002] Application date: 2019 / 04 / 03;

[0003] Application number: 201910267002.X; and

[0004] Invention title: Method for power management, memory device and its controller, and electronic device. Technical Field

[0005] This invention relates to memory control, and more particularly to a method for power management in a memory device, the associated memory device and its controller, and the associated electronic device. Background Technology

[0006] In recent years, due to the continuous development of memory technology, various portable or non-portable memory devices (such as memory cards conforming to SD / MMC, CF, MS, and XD standards respectively; and embedded memory devices conforming to UFS and eMMC standards respectively) have been widely implemented in many applications. Therefore, the access control of the memory in these memory devices has become a very popular topic.

[0007] Commonly used NAND flash memory can be mainly divided into two categories: single-level cell (SLC) and multiple-level cell (MLC). In single-level cell flash memory, each transistor acting as a memory cell has only two charge values, representing logic 0 and logic 1 respectively. In contrast, in multiple-level cell flash memory, the storage capacity of each transistor acting as a memory cell can be fully utilized. It is driven by a higher voltage to record at least two sets of bit information (such as 00, 01, 11, 10) within a single transistor at different voltage levels. Theoretically, the recording density of multiple-level cell flash memory can be at least twice that of single-level cell flash memory, which is very good news for the NAND flash memory industry.

[0008] Compared to single-cell flash memory, multi-cell flash memory quickly became the mainstream choice for memory devices due to its lower cost and ability to provide larger capacity within a limited space. However, problems caused by the instability of multi-cell flash memory also emerged. To ensure that the memory device's access control to flash memory complies with relevant specifications, the flash memory controller usually has certain management mechanisms to properly manage data access.

[0009] Even with these management mechanisms, existing memory devices still have shortcomings. For example, memory devices such as memory cards compliant with the Secure Digital (SD) standard, known as "SD memory cards," have a maximum transfer efficiency of 104 MB / s (megabytes per second) based on a six-bit SD interface. However, as storage capacity increases with advancements in memory technology, this transfer efficiency seems insufficient. While existing technologies attempt to address this issue, such as through different interfaces, they also introduce other problems. Therefore, a novel approach and related architecture are needed to solve the problems of existing technologies without or with minimal side effects. Summary of the Invention

[0010] One object of the present invention is to disclose a method and apparatus for power management in a memory device (e.g., a SD Express (or simply "SD") memory card), for example, by means of relevant detection during an initialization phase, in order to solve the aforementioned problems.

[0011] At least one embodiment of the present invention discloses a method for power management in a memory device. The memory device may include a non-volatile memory (NV memory), and the NV memory may include at least one NV memory component (e.g., one or more NV memory components). The method may include: during an initialization phase of the memory device, detecting whether a host device supports communication corresponding to a first communication protocol; and before detecting that the host device supports communication corresponding to the first communication protocol, controlling a physical layer (PHY) circuit in the memory device to remain in a power-off state to save power, wherein the physical layer circuit supports communication corresponding to the first communication protocol.

[0012] In addition to the methods described above, this invention also discloses a memory device, which includes a non-volatile memory and a controller. The non-volatile memory is used to store information and may include at least one non-volatile memory component (e.g., one or more non-volatile memory components). The controller is coupled to the non-volatile memory and is used to control the operation of the memory device. Furthermore, the controller includes a processing circuitry configured to control the controller according to multiple master device instructions from a master device, allowing the master device to access the non-volatile memory through the controller. The controller also includes a transmission interface circuitry coupled to the processing circuitry and used to facilitate communication between the memory device and the master device. For example, during an initialization phase of the memory device, the controller detects whether the master device supports communication corresponding to a first communication protocol. Before detecting that the master device supports communication corresponding to the first communication protocol, the controller controls a physical layer circuitry in the transmission interface circuitry to remain in a power-off state to save power, wherein the physical layer circuitry supports communication corresponding to the first communication protocol.

[0013] According to certain embodiments, the present invention also discloses related electronic devices. The electronic device may include the aforementioned memory device, and may further include: the main device coupled to the memory device. The main device may include: at least one processor for controlling the operation of the main device; and a power supply circuit coupled to the at least one processor for providing power to the at least one processor and the memory device. Additionally, the memory device may provide storage space for the main device.

[0014] In addition to the methods described above, this invention also discloses a controller for a memory device, wherein the memory device includes the controller and a non-volatile memory. The non-volatile memory may include at least one non-volatile memory component (e.g., one or more non-volatile memory components). Furthermore, the controller includes a processing circuitry configured to control the controller according to a plurality of master device instructions from a master device, allowing the master device to access the non-volatile memory through the controller. The controller also includes a transmission interface circuitry coupled to the processing circuitry and used to enable communication between the memory device and the master device. For example, during an initialization phase of the memory device, the controller detects whether the master device supports communication corresponding to a first communication protocol. Before detecting that the master device supports communication corresponding to the first communication protocol, the controller controls a physical layer (PHY) circuitry in the transmission interface circuitry to remain in a power-off state to save power, wherein the physical layer circuitry supports communication corresponding to the first communication protocol.

[0015] The method and related equipment proposed in this invention ensure that the memory device operates properly under various conditions. For example, the method provides multiple control schemes for power management; the related equipment includes, for example, the controller, the memory device, and the electronic device. Furthermore, during an initialization phase, aided by relevant detection, the controller (e.g., its power-on control circuitry) can selectively turn one or more corresponding power switches on or off, and the electronic device and the memory device do not incur unnecessary power consumption. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of a main device and a memory device according to an embodiment of the present invention.

[0017] Figure 2 According to an embodiment of the present invention, a method for use in a memory device such as Figure 1 A schematic diagram of a power management device in a memory device is shown.

[0018] Figure 3 This is a workflow of a method for power management in a memory device according to an embodiment of the present invention.

[0019] Figure 4 Draw Figure 2 The illustrated device is shown in certain implementation details of one embodiment of the present invention.

[0020] Figure 5The diagram illustrates a first control scheme of the method in one embodiment of the present invention.

[0021] Figure 6 A second control scheme of the method in one embodiment of the present invention is illustrated.

[0022] Figure 7 Here is an example of a state diagram.

[0023] Figure 8 This diagram illustrates an example of a quick SD initialization sequence that begins with the issuance of an SD command.

[0024] Figure 9 This illustrates an example where the quick SD initialization sequence does not begin with issuing an SD command.

[0025] The reference numerals in the attached figures are explained as follows:

[0026] 10 Electronic devices

[0027] 50 Main Unit

[0028] 52 processor

[0029] 54 Power Supply Circuit

[0030] 100, 200 memory devices

[0031] 110, 210 Memory Controller

[0032] 112 microprocessor

[0033] 112M Read-Only Memory

[0034] 112C program code

[0035] 114 Control Logic Circuit

[0036] 116 Random Access Memory

[0037] 118, 218 transmission interface circuits

[0038] 118Y physical layer circuit

[0039] 118M and 218M power management circuits

[0040] 120 Non-volatile memory

[0041] 122-1, 122-2 …122-N Non-volatile memory components

[0042] 212 Core Processing Unit

[0043] 214 Non-volatile memory controller

[0044] 216 Static Random Access Memory

[0045] Regulators 221 and 222

[0046] 223 Power Switch Circuit

[0047] 224 PCIe physical layer circuits

[0048] 225 Voltage Detection Circuit

[0049] 226 Power-on control circuit

[0050] 227 PCIe and NVMe Controllers

[0051] 228 SD Interface Logic Circuit

[0052] 405 Conversion Circuit

[0053] 410 Inverter

[0054] 420 flip-flop

[0055] 501, 502 Power Switches

[0056] VDD1, VDD2, VDD3 drive voltage input terminals

[0057] {DAT0(REFCLK+),DAT1(REFCLK-),DAT2(CLKREQ#),DAT3(PERST#),CLK,CMD,…}communication terminals

[0058] CTRL power control signal

[0059] RESET signal

[0060] VDD1, VDD2, VDD3, VDDx driving voltages

[0061] CLK, CMD, DAT3 (PERST#),

[0062] DAT0 / REFCLK+, DAT1 / REFCLK-, DAT2 / CLKREQ#, DAT3 / PERST# signals

[0063] CMD0 and CMD8 commands

[0064] R7 Reply

[0065] 300 Workflow

[0066] Steps S10, S12, S14, S16, S18 Detailed Implementation

[0067] Figure 1 This is a schematic diagram of an electronic device 10 according to an embodiment of the present invention, wherein the electronic device 10 may include a main device 50 and a memory device 100. The main device 50 may include at least one processor (e.g., one or more processors), collectively referred to as processor 52, and may also include a power supply circuit 54 coupled to processor 52. Processor 52 is used to control the operation of the main device 50, and power supply circuit 54 is used to provide power to processor 52 and memory device 100, and output one or more drive voltages to memory device 100. Memory device 100 can be used to provide storage space to main device 50, and obtain the one or more drive voltages from main device 50 as power for memory device 100. Examples of main device 50 may include (but are not limited to): multifunctional mobile phone, wearable device, tablet computer, and personal computer such as desktop computer and laptop computer. Examples of memory device 100 may include (but are not limited to): portable memory devices (such as a memory card conforming to SD / MMC, CF, MS, XD, or UFS standards), solid-state drives (SSDs), and various embedded memory devices conforming to UFS and eMMC standards, respectively. According to this embodiment, memory device 100 may include a controller such as a memory controller 110, and may also include a non-volatile memory (NVmemory) 120, wherein the controller is used to access the NVmemory 120, and the NVmemory 120 is used to store information. The NVmemory 120 may include at least one NVmemory element (e.g., one or more NVmemory elements), such as multiple NVmemory elements 122-1, 122-2, ..., and 122-N, where the symbol "N" may represent a positive integer greater than one. For example, the non-volatile memory 120 may be a flash memory, and the non-volatile memory components 122-1, 122-2, ... and 122-N may be multiple flash memory chips or multiple flash memory dies, but the present invention is not limited thereto.

[0068] like Figure 1As shown, the memory controller 110 may include a processing circuit such as a microprocessor 112, a storage unit such as a read-only memory (ROM) 112M, a control logic circuit 114, a random access memory (RAM) 116, and a transmission interface circuit 118, wherein the above components are interconnected via a bus. The random access memory 116 may be implemented as static random access memory (SRAM), but the present invention is not limited thereto. The random access memory 116 can be used to provide internal storage space to the memory controller 110; for example, the random access memory 116 can be used as a buffer memory to buffer data. In addition, in this embodiment, the read-only memory 112M is used to store a program code 112C, and the microprocessor 112 is used to execute the program code 112C to control access to the non-volatile memory 120. Note that in some examples, the program code 112C may be stored in the random access memory 116 or any type of memory. Additionally, a data protection circuit (not shown) in the control logic circuit 114 can protect data and / or perform error correction, while the transmission interface circuit 118 can conform to a specific communication standard (such as Serial Advanced Technology Attachment (SATA), Universal Serial Bus (USB), Peripheral Component Interconnect Express (PCIe), embedded Multi Media Card (eMMC), or Universal Flash Storage (UFS)), and can communicate according to the specific communication standard, for example, for the memory device 100 to communicate with the host device 50.

[0069] Specifically, the transmission interface circuit 118 may conform to a newer communication standard (such as the SD 7.0 standard), which may focus on higher-speed communication and be compatible with multiple communication standards (such as the PCIe standard and the SD 6.0 standard), meaning that the transmission interface circuit 118 is compatible with these communication standards. The transmission interface circuit 118 may include a physical layer (PHY) circuit 118Y (e.g., a PCIe physical layer circuit) supporting communication corresponding to a first communication protocol (e.g., the PCIe communication protocol), and may also include a power management (PM) circuit 118M to perform power management and control the power supply of the physical layer circuit 118Y. For example, the host device 50 may support communication corresponding to the first communication protocol, and the transmission interface circuit 118 may communicate with the host device 50 through the physical layer circuit 118Y. For example, the host device 50 may support communication corresponding to a second communication protocol (instead of the first communication protocol), and the transmission interface circuit 118 may communicate with the host device 50 without using the physical layer circuit 118Y. Additionally, the power management circuit 118M performs power management; specifically, during an initialization phase of the memory device 100, it detects at least one drive voltage of the memory device 100 at the corresponding drive voltage input terminal to selectively turn one or more power switches in the memory controller 110 on or off. For example, the memory controller 110 may turn the power to the physical layer circuit 118Y on or off via the one or more power switches under different conditions. In this way, unnecessary power consumption can be avoided.

[0070] In this embodiment, the master device 50 can transmit master device instructions and corresponding logical addresses to the memory controller 110 to access the memory device 100. The memory controller 110 receives the plurality of master device instructions and the plurality of logical addresses, and translates the plurality of master device instructions into memory operation instructions (hereinafter referred to as operation instructions), and uses the plurality of operation instructions to control the non-volatile memory 120 to read, write / program, etc., memory cells (e.g., data pages) with physical addresses in the non-volatile memory 120, wherein the plurality of physical addresses correspond to the plurality of logical addresses. When the memory controller 110 performs an erase operation on any one of the plurality of non-volatile memory components 122-1, 122-2, ... and 122-N, 122-n ("n" can be any positive integer in the interval [1, N]), at least one block of the plurality of blocks of the non-volatile memory component 122-n will be erased, wherein each of the plurality of blocks may include a plurality of pages (e.g., data pages), and an access operation (e.g., read or write) may be performed on one or more pages.

[0071] Figure 2 This is a schematic diagram of a device for power management in a memory device (such as the memory device described above) according to an embodiment of the present invention. The memory device 200 (e.g., a Quick SD memory card), memory controller 210 (e.g., a Quick SD memory card controller), core processing unit 212 (e.g., core processing circuitry), non-volatile memory controller 214, static random access memory 216, transfer interface circuitry 218, and power management circuitry 218M can be examples of the memory device 100, memory controller 110, microprocessor 112, control logic circuitry 114, random access memory 116, transfer interface circuitry 118, and power management circuitry 118M, respectively, but the present invention is not limited thereto. The memory controller 210 may include related circuitry such as a direct memory access (DMA) controller, analog circuitry, etc. The transmission interface circuit 218 may include multiple sub-circuits such as regulators 221 and 222, a power switch circuit 223 (which may include the one or more power switches), a PCIe physical layer circuit 224, a voltage detection circuit 225, a power-on control circuit 226, a PCIe and NVMe controller 227, and an SD interface logic circuit 228, and may enable the memory device 200 to interact with the host device 50 through at least a portion of the terminals of the memory device 200. The transmission interface circuit 218 (e.g., the multiple sub-circuits therein) may be coupled to certain interface terminals of the memory device 200, wherein the transmission interface circuit 218 and the associated terminals may conform to multiple standards such as different generations of standards (e.g., SD 6.0 and SD 7.0 standards). For example, the plurality of terminals of the memory device 200 may include drive voltage input terminals {VDD1, VDD2, VDD3} and communication terminals {DAT0(REFCLK+), DAT1(REFCLK-), DAT2(CLKREQ#), DAT3(PERST#), CLK, CMD, …} corresponding to newer communication standards (e.g., SD 7.0 standard). Since the transmission interface circuit 218 and the aforementioned terminals may conform to multiple standards, such as standards of different generations, the first four communication terminals may have their own primary and secondary names, which can be used to refer to the terminal names corresponding to a certain generation of the standard when needed. For ease of understanding, the signals on the plurality of terminals of the memory device 200 may be indicated using italicized words with the same names as these terminals. For example, the drive voltage input terminals {VDD1, VDD2, VDD3} may be used to receive a set of drive voltages {VDD1, VDD2, VDD3} from the main device 50. VDD1, VDD2, VDD3Such as {3.3V, 1.8V, 1.2V}. Additionally, the primary names of the first four communication terminals {DAT0, DAT1, DAT2, DAT3} and the drive voltage input terminals {VDD1, VDD2, VDD3} indicate that these terminals are compatible with the SD standard, while the secondary names of the first four communication terminals {REFCLK+, REFCLK-, CLKREQ#, PERST#} indicate their respective uses corresponding to the PCIe communication protocol (e.g., a reference clock differential pair {REFCLK+, REFCLK-} for synchronizing the PCIe interface of the memory device 200, a reference clock request CLKREQ# for requesting a reference clock, and a reset signal PERST# for resetting the memory device 200), but the invention is not limited thereto. According to this embodiment, a set of regulators such as regulators 221 and 222 can regulate the set of drive voltages { VDD1, VDD2, VDD3 One or more of these circuits generate power to one or more other circuits (e.g., PCIe physical layer circuitry 224), such as power supplies for the digital power domain and analog power domain of PCIe physical layer circuitry 224 (e.g., "digital power" and "analog power"). Power switch circuitry 223 can control the power supply to PCIe physical layer circuitry 224 via the one or more power switches, wherein after the power supply is turned on by power switch circuitry 223, PCIe physical layer circuitry 224 can perform physical layer operations corresponding to the PCIe communication protocol. With the aid of voltage detection circuitry 225, power-on control circuitry 226 can automatically control the power supply to PCIe physical layer circuitry 224 via power switch circuitry 223, for example, without relying on an internal clock source of memory controller 210, which can be preset to remain off without hindering the automatic control mechanism in this architecture for automatically controlling the power supply to PCIe physical layer circuitry 224. The PCIe and NVMe controller 227 can communicate with either the PCIe or NVMe communication protocol as needed, and the SD interface logic circuit 228 can communicate and / or interface with any version of the SD standard as needed. Figure 2 The architecture shown allows the memory controller 210 (e.g., the transmission interface circuit 218) to communicate according to any of the plurality of communication standards, in particular, to communicate according to the SD 6.0 standard when needed and to communicate according to the SD 7.0 standard when needed.

[0072] According to some embodiments, since the power required to drive the PCIe physical layer circuitry 224 may vary,Figure 2 The related architecture and wiring can be varied. The power switch circuit 223 can be directly or indirectly (e.g., via one or more regulators) coupled to at least a portion (e.g., some or all) of the drive voltage input terminals {VDD1, VDD2, VDD3}, and the number of regulators between the power switch circuit 223 and the aforementioned at least a portion of the drive voltage input terminals {VDD1, VDD2, VDD3} can be varied. For example, regulator 221 can adjust the drive voltage. VDD1 (e.g., 3.3 V) to generate a power supply as a power source for the digital power domain (e.g., "digital power"), and regulator 222 can adjust the drive voltage. VDD2 (e.g., 1.8 V) to generate a power supply as a power source for the analog power domain (e.g., "analog power supply"). According to some embodiments, the voltage detection circuit 225 may be coupled to one or more of the drive voltage input terminals {VDD2, VDD3}. For example, the voltage detection circuit 225 may detect a predetermined drive voltage corresponding to a predetermined drive voltage input terminal VDDx (e.g., VDD2 or VDD3) among the drive voltage input terminals {VDD2, VDD3}. VDDx (For example VDD2 or VDD3 Voltage detection is performed, wherein the voltage detection circuit 225 can be coupled to a predetermined drive voltage input terminal VDDx (e.g., VDD2 or VDD3).

[0073] Figure 3 This is a workflow 300 of a method for power management in a memory device according to an embodiment of the present invention, wherein the method can be applied to the controller (e.g., memory controllers 110 and 210), the memory device (e.g., memory devices 100 and 200), and an electronic device (e.g., electronic device 10) provided with the memory device.

[0074] In step S10, during the initialization phase of memory device 100 (e.g., memory device 200), memory controller 110 (e.g., memory controller 210) may detect whether host device 50 supports communication corresponding to the first communication protocol (e.g., PCIe communication protocol).

[0075] In step S12, before detecting that the host device 50 supports communication corresponding to the first communication protocol, the memory controller 110 (e.g., memory controller 210) may control the physical layer circuit 118Y (e.g., PCIe physical layer circuit 224) to remain in a power-off state to save power, wherein the physical layer circuit 118Y supports communication corresponding to the first communication protocol.

[0076] In step S14, the memory controller 110 (e.g., memory controller 210) checks whether the host device 50 supports communication corresponding to the first communication protocol. If the host device 50 supports communication corresponding to the first communication protocol, proceed to step S16; otherwise, proceed to step S18.

[0077] In step S16, when it is detected that the host device 50 supports communication corresponding to the first communication protocol, the memory controller 110 (e.g., memory controller 210) can control the physical layer circuit 118Y (e.g., PCIe physical layer circuit 224) to enter a power-on state so that communication corresponding to the first communication protocol can be performed through the physical layer circuit 118Y, thereby allowing the host device 50 to access the memory device 100 (e.g., memory device 200).

[0078] In step S18, when it is detected that the host device 50 does not support communication corresponding to the first communication protocol, the memory controller 110 (e.g., memory controller 210) can perform communication corresponding to another communication protocol without using the physical layer circuit 118Y (e.g., PCIe physical layer circuit 224) to allow the host device 50 to access the memory device 100 (e.g., memory device 200).

[0079] For ease of understanding, the method can be described using workflow 300, but the invention is not limited thereto. According to some embodiments, one or more steps in workflow 300 may be added, deleted, or modified.

[0080] According to this embodiment, the power management circuit 118M (e.g., power management circuit 218M) can perform power management according to the described method. The main device 50 can output the group drive voltage { VDD1, VDD2, VDD3 {3.3V, 1.8V, 1.2V} to memory device 100 (e.g., memory device 200). Specifically, power switch circuit 223 may be coupled between at least one drive voltage (e.g., one or more drive voltages) of the group of drive voltages and physical layer circuit 118Y (such as PCIe physical layer circuit 224), wherein controlling physical layer circuit 118Y to remain in a power-off state can be performed by power switch circuit 223. For example, the aforementioned at least one drive voltage may include one or more drive voltages, such as... VDD1 (e.g., 3.3 V) or { VDD1, VDD2 (e.g., {3.3V, 1.8V}), the power switch circuit 223 may include a plurality of power switches coupled to the one or more drive voltages, and the plurality of power switches may respectively control the power supply of the digital power domain and the analog power domain of the physical layer circuit 118Y (such as PCIe physical layer circuit 224).

[0081] During the initialization phase, a first driving voltage in the group of driving voltages, such as a driving voltage... VDD1 Typically, a predetermined drive voltage can be achieved. VDDx (For example VDD2 or VDD3 Before being pulled from a ground voltage level (e.g., 0 V) ​​to a second voltage level (e.g., 1.8 V or 1.2 V), it is pulled from the ground voltage level (e.g., 0 V) ​​to a first voltage level (e.g., 3.3 V). This is based on a predetermined drive voltage. VDDx The memory controller 110 (e.g., memory controller 210) can detect whether the host device 50 supports communication corresponding to the first communication protocol. In particular, the voltage detection circuit 225 can detect a predetermined drive voltage. VDDx Voltage detection is performed to generate a detection signal, and the power-on control circuit 226 can monitor a first signal (e.g., ...) from the main device 50 based on the detection signal. DAT3 (PERST#) A first signal is generated by a logic state of the memory device 200 to control the power supply of a physical layer circuit 118Y, such as a PCIe physical layer circuit 224. The first signal can be received by the memory device 200 via a corresponding communication terminal DAT3 (PERST#), and the power control signal CTRL indicates whether the host device 50 supports communication corresponding to the first communication protocol. Additionally, the power-on circuit 226 may include a one-bit storage circuit (e.g., a buffer or a flip-flop) to store one-bit information corresponding to the logic state. The power-on control circuit 226 can store the one-bit information in the one-bit storage circuit based on the detection signal to generate the power control signal CTRL. For example, the detection signal can be input to a clock terminal CK of the one-bit storage circuit (e.g., the detection signal can be used as a clock signal for the one-bit storage circuit), and the power control signal CTRL can be an output signal of the one-bit storage circuit. Furthermore, the power-on control circuit 226 can invert the first signal to generate an inverted signal of the first signal, and monitor the logic state of the first signal by monitoring a corresponding logic state of the inverted signal, wherein the corresponding logic state can be stored as the single bit information. For example, an edge of the detection signal can indicate the predetermined drive voltage. VDDx The transition. In some embodiments, due to the predetermined drive voltage during a normal operation phase. VDDxThere may be no further transformation, so the detection signal may not have subsequent edges appearing during the normal operation phase of the memory device 100 (e.g., memory device 200).

[0082] According to some embodiments, the power supply to be controlled (e.g., selectively turned on or off) by the power switch circuit 223 can be varied based on different control schemes of the method, for example, depending on the power demand to be supplied to the PCIe physical layer circuit 224. Figure 2 The illustrated architecture allows this power-saving design to be applied during the initialization phase of the fast SD memory card, which can be a memory card based on the SD 7.0 standard (e.g., a tiny memory card). Note that an SD card with a six-bit SD interface can achieve a maximum transfer rate of 104 MB / s. In contrast, the transmission interface circuit 118 (e.g., transmission interface circuit 218) can be designed to perform communication corresponding to the PCIe communication protocol, allowing the memory device 100 (e.g., memory device 200) to achieve a maximum transfer rate of 985 MB / s while maintaining compatibility with the SD interface. Thus, regardless of whether a host device (e.g., host device 50) supports the newer communication standard (e.g., the SD 7.0 standard), the method and related devices of the present invention (e.g., the controllers such as memory controllers 110 and 210) can ensure that the memory devices (e.g., memory devices 100 and 200) operate properly under various conditions.

[0083] Regarding the implementation of a new generation of SD cards, Figures 1-2 The architectures shown in any of the examples are suitable for power management to achieve energy savings. In particular, the PCIe physical layer circuitry 224 can perform PCIe communication operations according to the needs of the PCIe physical layer, but it can be quite power-intensive. The power switch circuitry 223 (e.g., the plurality of power switches) can be preset to remain off; when the memory device 200 operates in SD interface mode, the PCIe physical layer circuitry 224 does not consume power. Furthermore, the voltage level of the power supply required by the PCIe physical layer circuitry 224 can depend on the manufacturing process of the memory controller and / or various conditions of the related intellectual property modules. Regardless of the manufacturing process used and regardless of whether the conditions of the plurality of related intellectual property modules change, the method and related apparatus of the present invention can achieve extremely low power consumption.

[0084] According to some embodiments, when the SD memory card is inserted into the wrong slot, such as the slot corresponding to an SD 4.0 (UHS2) host, although this SD 4.0 host can supply drive voltage by default... VDD2The power switch circuit 223 (e.g., a power switch coupled to the drive voltage input terminal VDD2) can, under default conditions, prevent the PCIe physical layer circuit 224 from being powered by the drive voltage. VDD2 Power is applied because the power switch circuit 223 (e.g., the plurality of power switches) is preset to remain off.

[0085] Figure 4 Draw Figure 2 The illustrated device is described in certain implementation details of one embodiment of the invention. For example, the power-on control circuit 226 may include a buffer or a flip-flop 420 (having an input terminal D, an output terminal Q, a clock terminal CK, and a reset terminal R), and may include an inverter 410 coupled between terminal DAT3 (PERST#) and input terminal D to convert the signal... DAT3 (PERST#) Reverse or invert, and may also include a conversion circuit 405 (which may be referred to as a power-on reset circuit in this embodiment), wherein the output terminal Q is coupled to at least one control terminal of the power-on circuit 223 (e.g., the control terminal of the plurality of power switches therein). When the memory device 200 initially uses a drive voltage VDD1 Power on (e.g., 3.3 V), drive voltage VDD1 It can be used to reset the flip-flop 420, for example, by corresponding to the drive voltage. VDD1 A reset signal RESET is provided to ensure that there is no unknown state in the flip-flop 420. Specifically, the conversion circuit 405 can be used to convert the drive voltage... VDD1 Converted to a reset signal RESET, so that the reset signal RESET is driven by a voltage... VDD1 The instant when the ground voltage level (e.g., 0 V) ​​is pulled to the first voltage level (e.g., 3.3 V) has a corresponding driving voltage. VDD1 A pulse of transition (e.g., a rising edge) is used, and this pulse can be used as a reset pulse to reset the flip-flop 420 so that the power switching circuit 223 (e.g., the plurality of power switches therein) is initially in the off state. In this way, the power-on control circuit 226 can perform a "power-on reset" of the flip-flop 420 using the reset signal RESET. Figure 4 In the architecture shown, the power switch ground circuit 223 (e.g., the plurality of power switches therein) can be preset to remain off.

[0086] According to this embodiment, the voltage detection circuit 225 may include a voltage detector, for example, the voltage detector may be implemented by a comparator, but the invention is not limited thereto. The comparator may receive a predetermined drive voltage. VDDx (For example VDD2 or VDD3For example, the memory device 200 can be designed to avoid using a driving voltage. VDD3 When memory device 200 does not support the use of drive voltage VDD3 At that time, the predetermined driving voltage VDDx Can represent VDD2 (e.g., 1.8 V). Alternatively, the memory device 200 may be designed to use a driving voltage. VDD3 When the memory device 200 supports the use of drive voltage VDD3 At that time, the predetermined driving voltage VDDx Can represent VDD3 (e.g., 1.2 V). Additionally, the comparator can determine the predetermined drive voltage. VDDx (For example VDD2 or VDD3 The signal is compared with a predetermined threshold voltage to generate a comparison result signal, which can be used as the detection signal and can be input to the clock terminal CK. For example, the predetermined drive voltage... VDDx The voltage level can be pulled up at a specific point in time (e.g., from 0 V to 1.8 V, or from 0 V to 1.2 V). When the predetermined drive voltage... VDDx The voltage level reaches (e.g., greater than or equal to) the predetermined threshold voltage, which indicates the predetermined drive voltage. VDDx If the voltage level falls within an effective range, the comparator can change the voltage level of the comparison result signal, for example, from a low voltage level to a high voltage level; otherwise, the comparator can maintain the voltage level of the comparison result signal unchanged. For ease of understanding, the transition in the voltage level of the comparison result signal can be considered as a rising edge of a "pulse" carried by the comparison result signal, such as the edge from the low voltage level to the high voltage level, where the pulse width of this pulse may be long and may remain at the high voltage level until a predetermined drive voltage is reached. VDDx The voltage is pulled down (e.g., from 1.8 V to 0 V, or from 1.2 V to 0 V). Because the pulse width of this pulse is typically not as short as that of a normal pulse (such as a clock signal), this pulse can be referred to as a dummy pulse. The power-on control circuit 226 can utilize this dummy pulse as a clock source for the flip-flop 420. For example, the flip-flop 420 can temporarily store a signal based on the clock source, such as the dummy pulse. DAT3 (PERST#) The data of the inverse signal (e.g., high / low states such as logic high / low).

[0087] Since the output terminal Q is coupled to at least one control terminal of the power switch circuit 223 (e.g., the control terminals of the plurality of power switches therein), the power-on control circuit 226 can use the output signal of the flip-flop 420 at the output terminal Q as the power control signal CTRL (which can be regarded as a switching control signal of the plurality of power switches). The power control signal CTRL may have a logic value of 0 or a logic value of 1, in particular, it may be at a low level corresponding to a logic value of 0 or at a high level corresponding to a logic value of 1, but the invention is not limited thereto. When the power control signal CTRL has a logic value of 1 (e.g., at the high level), the plurality of power switches are turned on to supply power from regulators 221 and 222 to the PCIe physical layer circuit 224 respectively as power for the digital power domain (e.g., "digital power") and power for the analog power domain (e.g., "analog power"); otherwise, the plurality of power switches remain off. According to this embodiment, the signal DAT3 (PERST#) The signal can be a low-active signal, and the inverted signal output from inverter 410 to input terminal D can be a high-active signal. When the signal... DAT3 (PERST#) The inverting signal is at its low level (e.g., pulled down from a high level such as 3.3 V to a low level such as 0 V, and / or held at the low level), and at its high level (e.g., pulled up from a low level such as 0 V to a high level such as 3.3 V, and / or held at the high level). In response to the triggering of the clock source such as the virtual pulse, the flip-flop 420 can latch the data of the inverting signal (e.g., the logic high state), and the power control signal CTRL can have a logic value of 1 (e.g., at the high level). Thus, when a predetermined drive voltage is applied... VDDx The voltage level reaches (e.g., greater than or equal to) the predetermined threshold voltage, which indicates the predetermined drive voltage. VDDx When the voltage level falls within the effective range, the power-on control circuit 226 turns on the plurality of power switches to supply power from regulators 221 and 222 to the PCIe physical layer circuit 224.

[0088] According to some embodiments, due to the supply of driving voltage VDD1 Timing and supply drive voltage VDD3 The time interval between the points in time can be varied. When no SD instruction is detected during the initialization phase, the core processing unit 212 can shut down an internal clock source in the memory controller 210 to save power. In this situation, the method and apparatus of the present invention can use the voltage detector to detect a predetermined drive voltage. VDDxThe voltage level is adjusted to generate the virtual pulse, and the virtual pulse (instead of the internal clock source) can be used as the clock source to trigger the flip-flop 420 to turn on the plurality of power switches. For ease of understanding, assume that the internal clock source is a clock with a frequency of 20 MHz (megahertz) based on some circuit design, wherein: when the internal clock source is turned off, the memory device 200 consumes approximately one hundred microamperes (mA) at the group drive voltage; and when a free-run clock such as the internal clock source is turned on, the memory device 200 consumes approximately five hundred microamperes at the group drive voltage; however, the invention is not limited thereto. In this way, the memory controller 210 can properly manage the power of the PCIe physical layer circuitry 224 without turning on the internal clock source. Therefore, the method of the present invention can achieve the goal of saving power without side effects.

[0089] According to some embodiments, at the beginning of activating the memory device 200, the main device 50 first applies a drive voltage. VDD1 (instead of other drive voltages) VDD2 and VDD3 (any one of them) is supplied to memory device 200. Based on Figure 2 The architecture shown (in particular, Figure 4 As shown in the architecture, when the host device 50 enters PCIe mode, the memory controller 210 (e.g., power-on circuit 226) can promptly turn on the plurality of power switches to supply power from regulators 221 and 222 to the PCIe physical layer circuit 224.

[0090] Figure 5 The diagram illustrates a first control scheme of the described method in one embodiment of the present invention. When the PCIe physical layer circuit 224 is implemented using a 40 nanometer (nm) process, the PCIe physical layer circuit 224 may require a voltage of 2.5 V, which can be obtained from the drive voltage. VDD1 (For example, 3.3 V) is converted; and the PCIe physical layer circuit 224 may require a voltage of 1.1 V, which can be obtained from the drive voltage. VDD1 (For example, 3.3 V) is obtained through conversion. Regulators 221 and 222 can adjust the drive voltage. VDD1 Perform adjustment operation to adjust the drive voltage VDD1These are respectively converted to power supplies for the digital power domain (e.g., "digital power," such as a regulated drive voltage of 1.1 V) and power supplies for the analog power domain (e.g., "analog power," such as a regulated drive voltage of 2.5 V). When the power-on control circuit 226 activates the power switch circuit 223, the power switch circuit 223 (e.g., power switches 501 and 502) can respectively turn on the digital power supply, such as the regulated drive voltage of 1.1 V, and the analog power supply, such as the regulated drive voltage of 2.5 V, to the PCIe physical layer circuit 224; otherwise, the power switch circuit 223 (e.g., power switches 501 and 502) can prevent the digital power supply, such as the regulated drive voltage of 1.1 V, and the analog power supply, such as the regulated drive voltage of 2.5 V, from being turned on to the PCIe physical layer circuit 224.

[0091] Figure 6 The diagram illustrates a second control scheme of the described method in one embodiment of the present invention. When the PCIe physical layer circuit 224 is implemented using a 28-nanometer process, the PCIe physical layer circuit 224 may require a voltage of 1.8 V, which can be obtained from the drive voltage. VDD2 (For example, 1.8 V) is converted; and the PCIe physical layer circuit 224 may require a voltage of 0.9 V, which can be obtained from the drive voltage. VDD1 (For example, 3.3 V) is obtained through conversion. Regulators 221 and 222 can respectively adjust the drive voltage. VDD1 (e.g., 3.3 V) and drive voltage VDD2 (e.g., 1.8 V) is regulated to adjust the drive voltage. VDD1 and VDD2 These are respectively converted to power supplies for the digital power domain (e.g., "digital power," such as a regulated drive voltage of 0.9 V) and power supplies for the analog power domain (e.g., "analog power," such as a regulated drive voltage of 1.8 V). When the power-on control circuit 226 activates the power switch circuit 223, the power switch circuit 223 (e.g., power switches 501 and 502) can respectively turn on the digital power supply, such as the regulated drive voltage of 0.9 V, and the analog power supply, such as the regulated drive voltage of 1.8 V, to the PCIe physical layer circuit 224; otherwise, the power switch circuit 223 (e.g., power switches 501 and 502) can prevent the digital power supply, such as the regulated drive voltage of 0.9 V, and the analog power supply, such as the regulated drive voltage of 1.8 V, from being turned on to the PCIe physical layer circuit 224.

[0092] Figure 7An example of a state diagram is shown. The memory controller 110 (e.g., memory controller 210) can operate properly during the initialization phase under various conditions. For example, at the beginning of starting the memory device 200, the master device 50 will drive a voltage... VDD1 Supply to memory controller 210 (for ease of understanding, in) Figure 7 The winning bid is indicated as " VDD1 (Pulled up), and the power-on control circuit 226 by default keeps the power switch circuit 223 (e.g., power switches 501 and 502) in the off state (labeled "power switch off"). For example, when the main device 50 is in signal... DAT3 (PERST#) When it is at its low level, the predetermined drive voltage will be applied. VDDx (For example VDD2 or VDD3 ) supplied to memory controller 210 (for ease of understanding, in Figure 7 The winning bid is indicated as " VDDx Pulled up and PERST# = 0”), the power-on control circuit 226 turns on the power switch circuit 223 (e.g., power switches 501 and 502) to enter its on state (marked as “power switch on”). Additionally, whether or not a drive voltage is used... VDD2 or driving voltage VDD3 As a predetermined driving voltage VDDx The ability to perform voltage detection may vary depending on the design. For example, when the memory device 200 (e.g., the memory card such as the SD memory card) does not support the use of drive voltage... VDD3 Predetermined drive voltage VDDx Can represent driving voltage VDD2 (e.g., 1.8 V). For example, when the memory device 200 (e.g., the memory card) supports the use of a driving voltage... VDD3 Predetermined drive voltage VDDx Can represent driving voltage VDD3 (e.g., 1.2V).

[0093] Figure 8 This illustrates an example of a quick SD initialization sequence that begins with the issuance of an SD command. Figure 9 This illustrates an example where the quick SD initialization sequence does not begin with the issuance of an SD command. Signal { CLK, CMD, DAT3 (PERST#), DAT0 (REFCLK+), DAT1 (REFCLK-), DAT2 (CLKREQ#) (The primary and secondary names of the four signals that follow can also be separated by the symbol " / "; in) Figures 8-9 They are marked as " DAT3 / PERST# "", DAT0 / REFCLK+ "", DAT1 / REFCLK- "", DAT2 / CLKREQ#The memory controller 210 can receive signals at the corresponding terminals {CLK, CMD, DAT3(PERST#), DAT0(REFCLK+), DAT1(REFCLK-), DAT2(CLKREQ#)} of the memory device 200, respectively. The internal state of the memory device 200 during the initialization phase can include certain predetermined states such as virtual initialization, SD mode, PCIe linkup, and / or PCIe mode. During the initialization phase, the memory controller 210 can disable a pull-up resistor coupled to terminal DAT3(PERST#) to allow the host device 50 to freely drive signals as needed. DAT3 (PERST#) (such as) DAT3 / PERST# In particular, in Figure 8 In the example shown, the host device 50 can transmit instructions CMD0 and CMD8, and the memory controller 210 can respond with R7. Certain fields of instruction CMD8, such as the fields {“PCIe Availability”, “PCIe 1.2V Support”}, can include bits {1, 1} to indicate that the host device 50 supports PCIe communication and the PCIe 1.2V drive voltage. Similarly, certain fields of response R7, such as the fields {“PCIe Response”, “PCIe 1.2V Support”}, can include bits {1, 0} to indicate that the memory device 200 supports PCIe communication but not the PCIe 1.2V drive voltage. However, the invention is not limited to these examples. Based on these examples, the transmission interface circuit 218 can conform to the SD 7.0 standard. Additionally, during the initialization phase, the memory controller 210 can control the interaction between the memory device 200 (e.g., the memory card such as the SD memory card) and the host device 50 to enter PCIe interface mode, for example, when the host device 50 supports the drive voltage, based on any of these examples. VDD3 However, this invention is not limited to situations where the memory card does not support it. Based on Figure 2 The architecture shown (especially) Figure 4 As shown in the architecture, when needed, the memory controller 210 (e.g., power-on control circuit 226) can promptly turn on power switches 510 and 520 to supply power from regulators 221 and 222 to the PCIe physical layer circuit 224. When the PCIe physical layer circuit 224 is not needed, the memory controller 210 (e.g., power-on control circuit 226) can default to leaving power switches 510 and 520 in their off state to save power to the memory device 200.

[0094] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for power management in a memory device, characterized in that, The memory device includes a non-volatile memory, the non-volatile memory including at least one non-volatile memory component, and the method includes: During an initialization phase of the memory device, it is detected whether a master device supports communication corresponding to a first communication protocol, wherein detecting whether the master device supports communication corresponding to the first communication protocol includes: A voltage detection is performed on a predetermined drive voltage from the main device to generate a detection signal; and Based on the detection signal, monitoring a logic state of a first signal from the master device to generate a power control signal corresponding to the logic state for controlling the power supply of a physical layer circuit in the memory device, wherein monitoring the logic state of the first signal from the master device to generate the power control signal corresponding to the logic state includes: Based on the detection signal, a single bit of information corresponding to the logic state is stored in a single-bit storage circuit to generate the power control signal, wherein the detection signal is input to a clock terminal of the single-bit storage circuit, and the power control signal is an output signal of the single-bit storage circuit; and Before detecting that the master device supports communication corresponding to the first communication protocol, the physical layer circuit in the memory device is kept in a power-off state to save power, wherein the physical layer circuit supports communication corresponding to the first communication protocol.

2. The method as described in claim 1, characterized in that, The main device outputs a set of driving voltages to the memory device, wherein the set of driving voltages includes the predetermined driving voltage; a power switch circuit in the memory device is coupled between at least one of the driving voltages in the set of driving voltages and the physical layer circuit; and controlling the physical layer circuit to remain in the power-off state is performed by the power switch circuit.

3. The method as described in claim 2, characterized in that, The at least one driving voltage includes one or more driving voltages; and the power switching circuit includes a plurality of power switches coupled to the one or more driving voltages, and the plurality of power switches are respectively used to control the digital power domain and the analog power domain of the physical layer circuit.

4. The method as described in claim 1, characterized in that, The master device outputs a set of driving voltages to the memory device, wherein the set of driving voltages includes the predetermined driving voltage; and during the initialization phase, before the predetermined driving voltage in the set of driving voltages is pulled from a ground voltage level to a second voltage level, a first driving voltage in the set of driving voltages is pulled from the ground voltage level to a first voltage level.

5. The method as described in claim 1, characterized in that, The single-bit storage circuit is a buffer or a flip-flop.

6. The method as described in claim 1, characterized in that, Monitoring the logic state of the first signal from the master device based on the detection signal to generate the power control signal corresponding to the logic state further includes: Invert the first signal to generate an inverse signal of the first signal; and The logic state of the first signal is monitored by monitoring a corresponding logic state of the reverse signal, wherein the corresponding logic state is stored as the single bit information.

7. The method as described in claim 1, characterized in that, The detection signal is used as a clock signal for the single-bit storage circuit.

8. The method as described in claim 1, characterized in that, One edge of the detection signal indicates the change in the predetermined drive voltage.

9. The method as described in claim 8, characterized in that, No subsequent edge appears during a normal operating phase of the memory device, as indicated by the detection signal.

10. The method as described in claim 1, characterized in that, Also includes: When it is detected that the master device does not support communication corresponding to the first communication protocol, communication corresponding to another communication protocol is performed without using the physical layer circuit, so as to allow the master device to access the memory device.

11. The method as described in claim 1, characterized in that, Also includes: When the host device is detected to support communication corresponding to the first communication protocol, the physical layer circuit is controlled to enter a power-on state so that communication corresponding to the first communication protocol can be performed through the physical layer circuit, thereby allowing the host device to access the memory device.

12. A memory device, characterized in that, include: A non-volatile memory for storing information, wherein the non-volatile memory includes at least one non-volatile memory component; as well as A controller, coupled to the non-volatile memory, is used to control the operation of the memory device, wherein the controller includes: A processing circuit is configured to control the controller based on a plurality of master device instructions from a master device, thereby allowing the master device to access the non-volatile memory through the controller; and A transmission interface circuit, coupled to the processing circuit, is used to enable the memory device to communicate with the host device, wherein the transmission interface circuit includes: A voltage detection circuit; and A power-on control circuit is coupled to the voltage detection circuit, wherein the power-on control circuit includes: A single-bit storage circuit; in: During an initialization phase of the memory device, the controller detects whether the master device supports communication corresponding to a first communication protocol, wherein: The voltage detection circuit is used to detect a predetermined drive voltage from the main device to generate a detection signal; and The power-on control circuit is used to monitor a logic state of a first signal from the host device based on the detection signal to generate a power control signal corresponding to the logic state, so as to control the power supply of a physical layer circuit in the transmission interface circuit, wherein: The single-bit storage circuit is used to store single-bit information corresponding to the logic state. The power-on control circuit stores the single-bit information corresponding to the logic state into the single-bit storage circuit based on the detection signal to generate the power control signal. The detection signal is input to a clock terminal of the single-bit storage circuit, and the power control signal is an output signal of the single-bit storage circuit. Before detecting that the master device supports communication corresponding to the first communication protocol, the controller controls the physical layer circuit in the transmission interface circuit to remain in a power-off state to save power, wherein the physical layer circuit supports communication corresponding to the first communication protocol.

13. The memory device as claimed in claim 12, characterized in that, The main device outputs a set of driving voltages to the memory device, wherein the set of driving voltages includes the predetermined driving voltage; The transmission interface circuit also includes: A power switch circuit is coupled between at least one of the group of drive voltages and the physical layer circuit, wherein the controller controls the physical layer circuit to remain in the power-off state via the power switch circuit.

14. The memory device as claimed in claim 12, characterized in that, The master device outputs a set of driving voltages to the memory device, wherein the set of driving voltages includes the predetermined driving voltage; and during the initialization phase, before the predetermined driving voltage in the set of driving voltages is pulled from a ground voltage level to a second voltage level, a first driving voltage in the set of driving voltages is pulled from the ground voltage level to a first voltage level.

15. An electronic device comprising a memory device as claimed in claim 12, characterized in that, Also includes: The main device is coupled to the memory device, wherein the main device includes: At least one processor is used to control the operation of the main device; and A power supply circuit, coupled to the at least one processor, is used to provide power to the at least one processor and the memory device; The memory device provides storage space to the main device.

16. A controller for a memory device, characterized in that, The memory device includes the controller and a non-volatile memory, the non-volatile memory including at least one non-volatile memory component, and the controller including: A processing circuit is configured to control the controller based on a plurality of master device instructions from a master device, thereby allowing the master device to access the non-volatile memory through the controller; and A transmission interface circuit, coupled to the processing circuit, is used to enable the memory device to communicate with the host device, wherein the transmission interface circuit includes: A voltage detection circuit; and A power-on control circuit is coupled to the voltage detection circuit, wherein the power-on control circuit includes: A single-bit storage circuit; in: During an initialization phase of the memory device, the controller detects whether the master device supports communication corresponding to a first communication protocol, wherein: The voltage detection circuit is used to detect a predetermined drive voltage from the main device to generate a detection signal; and The power-on control circuit is used to monitor a logic state of a first signal from the host device based on the detection signal to generate a power control signal corresponding to the logic state, so as to control the power supply of a physical layer circuit in the transmission interface circuit, wherein: The single-bit storage circuit is used to store single-bit information corresponding to the logic state. The power-on control circuit stores the single-bit information corresponding to the logic state into the single-bit storage circuit based on the detection signal to generate the power control signal. The detection signal is input to a clock terminal of the single-bit storage circuit, and the power control signal is an output signal of the single-bit storage circuit. Before detecting that the master device supports communication corresponding to the first communication protocol, the controller controls the physical layer circuit in the transmission interface circuit to remain in a power-off state to save power, wherein the physical layer circuit supports communication corresponding to the first communication protocol.

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