I2C bus communication method, device, equipment and readable medium

Abstract

The present invention provides a method, device, equipment and readable medium for I2C bus communication, the method comprising: connecting an I2C controller to the outside of a processor chip via a GPIO pin, and connecting a slave device to the I2C controller so that the slave device communicates with the processor chip via the I2C controller; dividing the communication channel of the I2C bus link into a plurality of sub-channels, and allowing the slave device to communicate in different sub-channels, and setting a channel frequency for each sub-channel; creating a configuration table in the I2C controller, and recording the information of the communication channel in the configuration table; and according to the information of the communication channel recorded in the configuration table, the communication information of the slave device is collected into the sub-channel with the highest channel frequency. By using the scheme of the present invention, it is possible to achieve refined control of the I2C link, reduce the pin power consumption and link load of the processor itself, and improve system stability.

Description

Technical Field

[0001] The present invention relates to the field of computers, and more particularly to an I2C bus communication method, device, equipment and readable medium. Background Art

[0002] I2C (Inter-Integrated Circuit) bus is a two-wire serial bus developed by PHILIPS, used to connect microcontrollers and their peripherals. It is a bus standard widely used in the field of microelectronic communication control. It is a special form of synchronous communication with the advantages of fewer interface lines, simple control method, small device package, and higher communication rate.

[0003] I2C transfers information between devices connected to the bus through the serial data (SDA) line and the serial clock (SCL) line. Each device is identified by a unique address and can act as a transmitter or receiver (depending on the function of the device). The host is the device that initializes the data transfer on the bus and generates the clock signal that allows the transfer. At this time, any addressed device is considered a slave.

[0004] Normally, the I2C link is relatively simple, with one master and multiple slaves. When servers form a data center and the I2C links are interconnected, the I2C devices will form a multi-master and multi-slave mesh architecture. A large number of I2C devices occupy a large amount of link resources. At the same time, more I2C links occupy a large amount of chip pin resources, resulting in higher chip maintenance costs. The previous I2C control strategy becomes bloated and slow. Summary of the invention

[0005] In view of this, the purpose of the embodiments of the present invention is to propose a method, device, equipment and readable medium for I2C bus communication. By using the technical solution of the present invention, it is possible to achieve refined control of the I2C link, reduce the pin power consumption and link load of the processor itself, and improve system stability.

[0006] Based on the above purpose, one aspect of an embodiment of the present invention provides an I2C bus communication method, comprising the following steps:

[0007] Connect the I2C controller to the outside of the processor chip through the GPIO pin, and connect the slave device to the I2C controller so that the slave device communicates with the processor chip through the I2C controller;

[0008] Divide the communication channel of the I2C bus link into several sub-channels, and make the slave devices communicate in different sub-channels, and set the channel frequency for each sub-channel;

[0009] Create a configuration table in the I2C controller and record the information of the communication channel in the configuration table;

[0010] According to the information of the communication channel recorded in the configuration table, the communication information of the slave device is gathered into the sub-channel with the highest channel frequency.

[0011] According to one embodiment of the present invention, setting a channel frequency for each sub-channel includes:

[0012] In response to manually setting a channel frequency for each sub-channel, setting a sub-channel for the I2C controller to communicate with the slave device to a fixed frequency;

[0013] Setting a subchannel for communication between the I2C controller and the processor chip to a first fixed frequency, wherein the first fixed frequency is greater than a fixed frequency for communication with the slave device;

[0014] In response to automatically setting the channel frequency for each sub-channel, a highest frequency among data packets in the sub-channel is set as the frequency of the sub-channel.

[0015] According to one embodiment of the present invention, the configuration table includes a channel number, a channel frequency, a slave device address and a channel status information, wherein the channel number is used to label each sub-channel with a 4-bit binary number, the channel frequency is the frequency of the sub-channel set automatically or manually, and the channel status is represented by a four-bit binary number to indicate the condition of the sub-channel, wherein the first bit indicates whether the sub-channel is normal, the second bit indicates whether the link has a short circuit fault, the third bit indicates whether the link is abnormally broken, and the fourth bit indicates whether the slave device is abnormal.

[0016] According to one embodiment of the present invention, it also includes:

[0017] Read the configuration table every time a threshold time passes, and determine whether the data in the configuration table is abnormal;

[0018] In response to data anomalies in the configuration table, a corresponding alarm is issued to the administrator.

[0019] Another aspect of the embodiments of the present invention further provides an I2C bus communication device, the device comprising:

[0020] A connection module, the connection module is configured to connect the I2C controller to the outside of the processor chip through the GPIO pin, and connect the slave device to the I2C controller so that the slave device communicates with the processor chip through the I2C controller;

[0021] A division module, the division module is configured to divide the communication channel of the I2C bus link into a plurality of sub-channels, and enable the slave devices to communicate in different sub-channels, and set a channel frequency for each sub-channel;

[0022] Create a module, and configure the module to create a configuration table in the I2C controller and record the information of the communication channel in the configuration table;

[0023] The communication module is configured to collect the communication information of the slave device into the sub-channel with the highest channel frequency according to the information of the communication channel recorded in the configuration table.

[0024] According to one embodiment of the present invention, the partitioning module is further configured as follows:

[0025] In response to manually setting a channel frequency for each sub-channel, setting a sub-channel for the I2C controller to communicate with the slave device to a fixed frequency;

[0026] Setting a subchannel for communication between the I2C controller and the processor chip to a first fixed frequency, wherein the first fixed frequency is greater than a fixed frequency for communication with the slave device;

[0027] In response to automatically setting the channel frequency for each sub-channel, a highest frequency among data packets in the sub-channel is set as the frequency of the sub-channel.

[0028] According to one embodiment of the present invention, the configuration table includes a channel number, a channel frequency, a slave device address and a channel status information, wherein the channel number is used to label each sub-channel with a 4-bit binary number, the channel frequency is the frequency of the sub-channel set automatically or manually, and the channel status is represented by a four-bit binary number to indicate the condition of the sub-channel, wherein the first bit indicates whether the sub-channel is normal, the second bit indicates whether the link has a short circuit fault, the third bit indicates whether the link is abnormally broken, and the fourth bit indicates whether the slave device is abnormal.

[0029] According to one embodiment of the present invention, an alarm module is further included, and the alarm module is configured as follows:

[0030] Read the configuration table every time a threshold time passes, and determine whether the data in the configuration table is abnormal;

[0031] In response to data anomalies in the configuration table, a corresponding alarm is issued to the administrator.

[0032] Another aspect of the embodiments of the present invention further provides a computer device, the computer device comprising:

[0033] at least one processor; and

[0034] The memory stores computer instructions executable on the processor, and the instructions implement the steps of any one of the above methods when executed by the processor.

[0035] According to another aspect of the embodiments of the present invention, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of any one of the above methods are implemented.

[0036] The present invention has the following beneficial technical effects: the I2C bus communication method provided by the embodiment of the present invention connects the I2C controller to the outside of the processor chip through the GPIO pin, and connects the slave device to the I2C controller so that the slave device communicates with the processor chip through the I2C controller; divides the communication channel of the I2C bus link into a plurality of sub-channels, and enables the slave device to communicate in different sub-channels, and sets a channel frequency for each sub-channel; creates a configuration table in the I2C controller, and records the information of the communication channel in the configuration table; and according to the information of the communication channel recorded in the configuration table, the communication information of the slave device is gathered into the sub-channel with the highest channel frequency. The technical solution can realize the refined control of the I2C link, reduce the pin power consumption and link load of the processor itself, and improve the system stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other embodiments can be obtained based on these drawings without paying creative work.

[0038] Figure 1 is a schematic flow chart of an I2C bus communication method according to an embodiment of the present invention;

[0039] Figure 2 A schematic diagram of an I2C bus communication architecture according to an embodiment of the present invention;

[0040] Figure 3 is a schematic diagram of a time division multiplexing diagram according to an embodiment of the present invention;

[0041] Figure 4 A schematic diagram of an I2C bus communication device according to an embodiment of the present invention;

[0042] Figure 5 is a schematic diagram of a computer device according to an embodiment of the present invention;

[0043] Figure 6 FIG. 1 is a schematic diagram of a computer-readable storage medium according to an embodiment of the present invention. DETAILED DESCRIPTION

[0044] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the embodiments of the present invention are further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0045] Based on the above purpose, a first aspect of an embodiment of the present invention provides an embodiment of an I2C bus communication method. Figure 1 Shown is a schematic flow chart of the method.

[0046] like Figure 1 As shown in , the method may include the following steps:

[0047] S1 connects the I2C controller to the outside of the processor chip through the GPIO pin, and connects the slave device to the I2C controller so that the slave device can communicate with the processor chip through the I2C controller. The present invention is aimed at the I2C management scenario in the server cluster environment, and proposes an I2C bus cascade controller to achieve low-overhead control of the I2C bus network. The I2C controller is independent of the outside of the processor chip and connected to the processor chip through the GPIO pin or other link. In this way, its pins are no longer limited by the processor chip, and GPIO pin multiplexing is not required. In addition, multiple chips can be cascaded to achieve exponential link expansion, such as Figure 2 As shown, slave devices or other I2C controllers can be mounted on any pin of the I2C controller, arranged in a two-dimensional plane, and connected to each other using the I2C bus. In the initialization state, the I2C controller can be manually configured. If there is no automatic configuration, the superior-subordinate relationship will be automatically formed by analyzing the link communication and recorded in the configuration table.

[0048] S2 divides the communication channel of the I2C bus link into several sub-channels, and enables the slave devices to communicate in different sub-channels, and sets the channel frequency for each sub-channel. At the same time, in order to solve the problem of link congestion, the present invention uses the method of upper frequency increase and time division multiplexing to divide the link channel into several sub-channels, and the division rules can be adaptively adjusted according to the clock frequency. The channel frequency represents the initial frequency of the channel. This part can be manually configured, or the monitoring module can automatically generate a matching frequency by reading the data packet of the channel and analyzing the clock-related information.

[0049] S3 creates a configuration table in the I2C controller and records the information of the communication channel in the configuration table. The present invention includes a configuration table, which is stored in the I2C controller and can be obtained by other master devices. The upper layer application can access the table using other high-speed interfaces and can write and read information in the table.

[0050] S4 collects the communication information of the slave device to the sub-channel with the highest channel frequency according to the information of the communication channel recorded in the configuration table. Regardless of whether the channel frequency of the sub-channel is set manually or automatically, it is necessary to ensure that the channel frequency of the master device is greater than the channel frequency of the slave device. When information is transmitted, the channel with low frequency summarizes information to the channel with high frequency. In the present invention, the I2C controller may also include a monitoring module responsible for monitoring link communication, a flow control matrix responsible for collecting multi-channel communication to the upper channel, a configuration module responsible for configuring link information according to the link situation, and a configuration table responsible for storing relevant information.

[0051] By using the technical solution of the present invention, refined control of the I2C link can be achieved, the pin power consumption and link load of the processor itself are reduced, and the system stability is improved.

[0052] In a preferred embodiment of the present invention, setting the channel frequency for each sub-channel includes:

[0053] In response to manually setting a channel frequency for each sub-channel, setting a sub-channel for the I2C controller to communicate with the slave device to a fixed frequency;

[0054] Setting a subchannel for communication between the I2C controller and the processor chip to a first fixed frequency, wherein the first fixed frequency is greater than a fixed frequency for communication with the slave device;

[0055] In response to automatically setting the channel frequency for each sub-channel, the highest frequency in the data packet in the sub-channel is set as the frequency of the sub-channel. Regardless of whether the channel frequency of the sub-channel is set manually or automatically, it is necessary to ensure that the channel frequency of the master device is greater than the channel frequency of the slave device, and when information is transmitted, the channel with a low frequency aggregates information to the channel with a high frequency.

[0056] In a preferred embodiment of the present invention, the configuration table includes a channel number, a channel frequency, a slave device address and a channel status information, wherein the channel number is a 4-bit binary number for labeling each subchannel, the channel frequency is the frequency of the subchannel set automatically or manually, and the channel status is represented by a 4-bit binary number to represent the status of the subchannel, wherein the first bit represents whether the subchannel is normal, the second bit represents whether the link is short-circuited, the third bit represents whether the link is abnormally disconnected, and the fourth bit represents whether the slave device is abnormal. The channel number represents the subchannel sequence number of the I2C master controller, which is distinguished by a 4-bit binary number, with an upper limit of 16. If there are more requirements, it can be expanded by increasing the number of bits. The channel frequency represents the initial frequency of the channel, which can be manually configured or the monitoring module can automatically generate a matching frequency by reading the data packet of the channel and analyzing the clock-related information. The device status represents the current status of the channel, which is represented by a 4-bit binary number, wherein the first bit represents whether it is normal, the second bit represents whether the link is short-circuited, that is, a continuous low level, the third bit represents whether the link is abnormally disconnected, that is, a continuous high level without signal, and the fourth bit represents whether the device is abnormal, such as initiating a communication request from the device.

[0057] In a preferred embodiment of the present invention, it also includes:

[0058] Read the configuration table every time a threshold time passes, and determine whether the data in the configuration table is abnormal;

[0059] In response to data anomalies in the configuration table, a corresponding alarm is issued to the administrator.

[0060] Figure 3 The figure below is the time division multiplexing diagram of the upper link and each channel. The controller aggregates the data of channels 1, 2, and 3, and through time division multiplexing, it becomes channel 0. The frequency of channel 0 is three times that of channels 1, 2, and 3, and is transmitted to the upper link. The data transmitted by the upper layer will also be distributed to each channel in this way, and the time division multiplexing function of the link is realized by spreading the clock, which can ensure that there is no delay in the communication between the master and slave devices. Figure 2 , I2C controller 2 combines the data of slave devices C, D, and E through time division multiplexing technology and transmits it to I2C controller 1. The channel frequency is three times the frequency of C, D, and E. I2C controller 1 summarizes the data of I2C controller 2 and the data of slave devices A\B and sends them to the processor chip together. The channel frequency is 5 times that of slave devices C\D\E. According to this architecture design, the original 5 slave devices occupied 10 I2C links and 10 pins, but now only two links, two pins and two controllers are used to achieve it, which greatly saves the number of system pins.

[0061] By using the technical solution of the present invention, refined control of the I2C link can be achieved, the pin power consumption and link load of the processor itself are reduced, and the system stability is improved.

[0062] It should be noted that a person of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment method can be implemented by instructing the relevant hardware through a computer program, and the above-mentioned program can be stored in a computer-readable storage medium, and when the program is executed, it can include the processes of the embodiments of the above-mentioned methods. The storage medium can be a disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM), etc. The above-mentioned computer program embodiment can achieve the same or similar effect as any of the above-mentioned method embodiments corresponding thereto.

[0063] In addition, the method disclosed in the embodiment of the present invention can also be implemented as a computer program executed by a CPU, and the computer program can be stored in a computer-readable storage medium. When the computer program is executed by the CPU, the above functions defined in the method disclosed in the embodiment of the present invention are performed.

[0064] Based on the above purpose, a second aspect of the embodiment of the present invention provides an I2C bus communication device, such as Figure 4 As shown, the device 200 includes:

[0065] A connection module, the connection module is configured to connect the I2C controller to the outside of the processor chip through the GPIO pin, and connect the slave device to the I2C controller so that the slave device communicates with the processor chip through the I2C controller;

[0066] A division module, the division module is configured to divide the communication channel of the I2C bus link into a plurality of sub-channels, and enable the slave devices to communicate in different sub-channels, and set a channel frequency for each sub-channel;

[0067] Create a module, and configure the module to create a configuration table in the I2C controller and record the information of the communication channel in the configuration table;

[0068] The communication module is configured to collect the communication information of the slave device into the sub-channel with the highest channel frequency according to the information of the communication channel recorded in the configuration table.

[0069] In a preferred embodiment of the present invention, the partitioning module is further configured as follows:

[0070] In response to manually setting a channel frequency for each sub-channel, setting a sub-channel for the I2C controller to communicate with the slave device to a fixed frequency;

[0071] Setting a subchannel for communication between the I2C controller and the processor chip to a first fixed frequency, wherein the first fixed frequency is greater than a fixed frequency for communication with the slave device;

[0072] In response to automatically setting the channel frequency for each sub-channel, a highest frequency among data packets in the sub-channel is set as the frequency of the sub-channel.

[0073] In a preferred embodiment of the present invention, the configuration table includes a channel number, a channel frequency, a slave device address and a channel status information, wherein the channel number is used to label each sub-channel with a 4-bit binary number, the channel frequency is the frequency of the sub-channel set automatically or manually, and the channel status is represented by a four-bit binary number to indicate the condition of the sub-channel, wherein the first bit indicates whether the sub-channel is normal, the second bit indicates whether the link has a short circuit fault, the third bit indicates whether the link is abnormally broken, and the fourth bit indicates whether the slave device is abnormal.

[0074] In a preferred embodiment of the present invention, an alarm module is further included, and the alarm module is configured as follows:

[0075] Read the configuration table every time a threshold time passes, and determine whether the data in the configuration table is abnormal;

[0076] In response to data anomalies in the configuration table, a corresponding alarm is issued to the administrator.

[0077] Based on the above purpose, a third aspect of an embodiment of the present invention provides a computer device. Figure 5 FIG. 2 is a schematic diagram of an embodiment of a computer device provided by the present invention. Figure 5 As shown, the embodiment of the present invention includes the following apparatus: at least one processor 21; and a memory 22, the memory 22 stores computer instructions 23 that can be run on the processor, and when the instructions are executed by the processor, the following method is implemented:

[0078] Connect the I2C controller to the outside of the processor chip through the GPIO pin, and connect the slave device to the I2C controller so that the slave device communicates with the processor chip through the I2C controller;

[0079] Divide the communication channel of the I2C bus link into several sub-channels, and make the slave devices communicate in different sub-channels, and set the channel frequency for each sub-channel;

[0080] Create a configuration table in the I2C controller and record the information of the communication channel in the configuration table;

[0081] According to the information of the communication channel recorded in the configuration table, the communication information of the slave device is gathered into the sub-channel with the highest channel frequency.

[0082] In a preferred embodiment of the present invention, setting the channel frequency for each sub-channel includes:

[0083] In response to manually setting a channel frequency for each sub-channel, setting a sub-channel for the I2C controller to communicate with the slave device to a fixed frequency;

[0084] Setting a subchannel for communication between the I2C controller and the processor chip to a first fixed frequency, wherein the first fixed frequency is greater than a fixed frequency for communication with the slave device;

[0085] In response to automatically setting the channel frequency for each sub-channel, a highest frequency among data packets in the sub-channel is set as the frequency of the sub-channel.

[0086] In a preferred embodiment of the present invention, the configuration table includes a channel number, a channel frequency, a slave device address and a channel status information, wherein the channel number is used to label each sub-channel with a 4-bit binary number, the channel frequency is the frequency of the sub-channel set automatically or manually, and the channel status is represented by a four-bit binary number to indicate the condition of the sub-channel, wherein the first bit indicates whether the sub-channel is normal, the second bit indicates whether the link has a short circuit fault, the third bit indicates whether the link is abnormally broken, and the fourth bit indicates whether the slave device is abnormal.

[0087] In a preferred embodiment of the present invention, it also includes:

[0088] Read the configuration table every time a threshold time passes, and determine whether the data in the configuration table is abnormal;

[0089] In response to data anomalies in the configuration table, a corresponding alarm is issued to the administrator.

[0090] Based on the above purpose, a fourth aspect of an embodiment of the present invention provides a computer-readable storage medium. Figure 6 FIG. 2 is a schematic diagram of an embodiment of a computer-readable storage medium provided by the present invention. Figure 6 As shown, the computer readable storage medium 31 stores a computer program 32 that performs the following method when executed by a processor:

[0091] Connect the I2C controller to the outside of the processor chip through the GPIO pin, and connect the slave device to the I2C controller so that the slave device communicates with the processor chip through the I2C controller;

[0092] Divide the communication channel of the I2C bus link into several sub-channels, and make the slave devices communicate in different sub-channels, and set the channel frequency for each sub-channel;

[0093] Create a configuration table in the I2C controller and record the information of the communication channel in the configuration table;

[0094] According to the information of the communication channel recorded in the configuration table, the communication information of the slave device is gathered into the sub-channel with the highest channel frequency.

[0095] In a preferred embodiment of the present invention, setting the channel frequency for each sub-channel includes:

[0096] In response to manually setting a channel frequency for each sub-channel, setting a sub-channel for the I2C controller to communicate with the slave device to a fixed frequency;

[0097] Setting a subchannel for communication between the I2C controller and the processor chip to a first fixed frequency, wherein the first fixed frequency is greater than a fixed frequency for communication with the slave device;

[0098] In response to automatically setting the channel frequency for each sub-channel, a highest frequency among data packets in the sub-channel is set as the frequency of the sub-channel.

[0099] In a preferred embodiment of the present invention, the configuration table includes a channel number, a channel frequency, a slave device address and a channel status information, wherein the channel number is used to label each sub-channel with a 4-bit binary number, the channel frequency is the frequency of the sub-channel set automatically or manually, and the channel status is represented by a four-bit binary number to indicate the condition of the sub-channel, wherein the first bit indicates whether the sub-channel is normal, the second bit indicates whether the link has a short circuit fault, the third bit indicates whether the link is abnormally broken, and the fourth bit indicates whether the slave device is abnormal.

[0100] In a preferred embodiment of the present invention, it also includes:

[0101] Read the configuration table every time a threshold time passes, and determine whether the data in the configuration table is abnormal;

[0102] In response to data anomalies in the configuration table, a corresponding alarm is issued to the administrator.

[0103] In addition, the method disclosed in the embodiment of the present invention can also be implemented as a computer program executed by a processor, and the computer program can be stored in a computer-readable storage medium. When the computer program is executed by the processor, the above functions defined in the method disclosed in the embodiment of the present invention are performed.

[0104] In addition, the above method steps and system units may also be implemented using a controller and a computer-readable storage medium for storing a computer program that enables the controller to implement the above steps or unit functions.

[0105] It will also be appreciated by those skilled in the art that various exemplary logic blocks, modules, circuits and algorithm steps described in conjunction with the disclosure herein can be implemented as electronic hardware, computer software or a combination of the two. In order to clearly illustrate this interchangeability of hardware and software, a general description has been given to the functions of various schematic components, blocks, modules, circuits and steps. Whether this function is implemented as software or hardware depends on specific applications and the design constraints imposed on the entire system. Those skilled in the art can implement the function in various ways for each specific application, but this implementation decision should not be interpreted as causing a departure from the disclosed scope of the embodiments of the present invention.

[0106] In one or more exemplary designs, the function can be implemented in hardware, software, firmware or any combination thereof. If implemented in software, the function can be stored on a computer-readable medium or transmitted by a computer-readable medium as one or more instructions or codes. Computer-readable media include computer storage media and communication media, and the communication media include any media that helps to transfer a computer program from one location to another. The storage medium can be any available medium that can be accessed by a general or special computer. As an example and not limiting, the computer-readable medium may include RAM, ROM, EEPROM, CD-ROM or other optical disk storage devices, disk storage devices or other magnetic storage devices, or any other medium that can be used to carry or store the required program code in the form of an instruction or data structure and can be accessed by a general or special computer or a general or special processor. In addition, any connection can be appropriately referred to as a computer-readable medium. For example, if a coaxial cable, optical fiber cable, twisted pair, digital subscriber line (DSL) or wireless technologies such as infrared, radio and microwaves are used to send software from a website, server or other remote source, the above-mentioned coaxial cable, optical fiber cable, twisted pair, DSL or wireless technologies such as infrared, radio and microwaves are all included in the definition of the medium. As used herein, disk and disc include compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk, Blu-ray disc, wherein disks usually reproduce data magnetically, while optical discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.

[0107] The above are exemplary embodiments disclosed in the present invention, but it should be noted that various changes and modifications may be made without departing from the scope disclosed in the embodiments of the present invention as defined in the claims. The functions, steps and / or actions of the method claims according to the disclosed embodiments described herein do not need to be performed in any particular order. In addition, although the elements disclosed in the embodiments of the present invention may be described or required in individual form, they may also be understood as multiple unless explicitly limited to the singular.

[0108] It should be understood that, as used herein, the singular forms "a", "an" are intended to include the plural forms as well, unless the context clearly supports an exception. It should also be understood that, as used herein, "and / or" refers to any and all possible combinations including one or more of the associated listed items.

[0109] The serial numbers of the embodiments disclosed in the above embodiments of the present invention are only for description and do not represent the advantages or disadvantages of the embodiments.

[0110] A person skilled in the art will understand that all or part of the steps to implement the above embodiments may be accomplished by hardware or by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a disk or an optical disk, etc.

[0111] A person skilled in the art should understand that the discussion of any of the above embodiments is only exemplary and is not intended to imply that the scope of the disclosure of the embodiments of the present invention (including the claims) is limited to these examples; under the concept of the embodiments of the present invention, the technical features in the above embodiments or different embodiments can also be combined, and there are many other changes in different aspects of the embodiments of the present invention as above, which are not provided in detail for the sake of simplicity. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present invention should be included in the protection scope of the embodiments of the present invention.

Claims

1. A method for I2C bus communication, characterized in that: The following steps are involved: Connect the I2C controller to the outside of the processor chip through the GPIO pin, and connect the slave device to the I2C controller so that the slave device communicates with the processor chip through the I2C controller; Divide the communication channel of the I2C bus link into a plurality of sub-channels, and enable the slave devices to communicate in different sub-channels, and set a channel frequency for each sub-channel so that the frequency of the sub-channel for the I2C controller to communicate with the processor chip is greater than the frequency of the sub-channel for the I2C controller to communicate with the slave device; Create a configuration table in the I2C controller and record the information of the communication channel in the configuration table; The communication information from the device is collected into the I2C controller according to the communication channel information recorded in the configuration table.

2. The method according to claim 1, characterized in that Setting the channel frequency for each subchannel involves: In response to manually setting a channel frequency for each sub-channel, setting a sub-channel for the I2C controller to communicate with the slave device to a fixed frequency; Setting a subchannel for communication between the I2C controller and the processor chip to a first fixed frequency, wherein the first fixed frequency is greater than a fixed frequency for communication with the slave device; In response to automatically setting the channel frequency for each sub-channel, a highest frequency among data packets in the sub-channel is set as the frequency of the sub-channel.

3. The method according to claim 1, characterized in that The configuration table includes the channel number, channel frequency, slave device address and channel status information, where the channel number uses a 4-bit binary number to label each sub-channel, the channel frequency is the frequency of the sub-channel set automatically or manually, and the channel status is represented by a four-bit binary number to indicate the status of the sub-channel, where the first bit indicates whether the sub-channel is normal, the second bit indicates whether the link is short-circuited, the third bit indicates whether the link is abnormally broken, and the fourth bit indicates whether the slave device is abnormal.

4. The method according to claim 1, characterized in that: Also includes: Read the configuration table every time a threshold time passes, and determine whether the data in the configuration table is abnormal; In response to data anomalies in the configuration table, a corresponding alarm is issued to the administrator.

5. An I2C bus communication device, characterized in that: The device comprises: A connection module, wherein the connection module is configured to connect the I2C controller to the outside of the processor chip through the GPIO pin, and connect the slave device to the I2C controller so that the slave device communicates with the processor chip through the I2C controller; A division module, wherein the division module is configured to divide the communication channel of the I2C bus link into a plurality of sub-channels, and enable the slave devices to communicate in different sub-channels, and set a channel frequency for each sub-channel so that the frequency of the sub-channel for the I2C controller to communicate with the processor chip is greater than the frequency of the sub-channel for the I2C controller to communicate with the slave device; A creation module, wherein the creation module is configured to create a configuration table in the I2C controller and record information of the communication channel in the configuration table; The communication module is configured to collect the communication information of the slave device into the I2C controller according to the information of the communication channel recorded in the configuration table.

6. The device according to claim 5, characterized in that The partition module is also configured as: In response to manually setting a channel frequency for each sub-channel, setting a sub-channel for the I2C controller to communicate with the slave device to a fixed frequency; Setting a subchannel for communication between the I2C controller and the processor chip to a first fixed frequency, wherein the first fixed frequency is greater than a fixed frequency for communication with the slave device; In response to automatically setting the channel frequency for each sub-channel, a highest frequency among data packets in the sub-channel is set as the frequency of the sub-channel.

7. The device according to claim 5, characterized in that The configuration table includes the channel number, channel frequency, slave device address and channel status information, where the channel number uses a 4-bit binary number to label each sub-channel, the channel frequency is the frequency of the sub-channel set automatically or manually, and the channel status is represented by a four-bit binary number to indicate the status of the sub-channel, where the first bit indicates whether the sub-channel is normal, the second bit indicates whether the link is short-circuited, the third bit indicates whether the link is abnormally broken, and the fourth bit indicates whether the slave device is abnormal.

8. The device according to claim 5, characterized in that It also includes an alarm module, wherein the alarm module is configured as follows: Read the configuration table every time a threshold time passes, and determine whether the data in the configuration table is abnormal; In response to data anomalies in the configuration table, a corresponding alarm is issued to the administrator.

9. A computer device, characterized in that: include: at least one processor; as well as A memory storing computer instructions executable on the processor, wherein the instructions, when executed by the processor, implement the steps of the method according to any one of claims 1 to 4.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 4 are implemented.

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