Lamoeba chip architecture and runtime reconfiguration mechanism method based on asynchronous mechanism

Abstract

The application discloses a Lamoeba chip architecture and a runtime reconstruction mechanism method based on an asynchronous mechanism, which combines an asynchronous reconfigurable Lamoeba chip and a reconstruction algorithm mechanism with time as a cost. The asynchronous mechanism provides a hardware basis for reconfigurable computing. The Lamoeba chip adopts a communication architecture of an on-chip mesh NoC to perform data transmission and communication on a network. The network adopts a 2D-mesh topology structure. Different types of computing modules are mounted in the network. In combination with a microprocessor in a single-chip microcomputer, software programming and routing address configuration are performed to complete the calculation of corresponding algorithms. The reconstruction algorithm calculates the data operation time, routing time and arbitration time of different paths in the network to find the shortest time allocation mode for algorithm mapping and change the deployment of the computing modules in the algorithm to the hardware resources. The application has the advantages of flexible general computing, high special computing, low power consumption without a clock and the ability to avoid various problems caused by the clock in the synchronous circuit.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of computer information processing, integrated circuit design and reconfigurable computing, and particularly relates to a Lamoeba chip architecture and runtime reconfiguration mechanism method based on an asynchronous mechanism. BACKGROUND

[0002] In the field of reconfigurable computing, there are two traditional computing methods:

[0003] One is to use application-specific integrated circuits (ASICs). ASICs are designed specifically to perform a given computation, so they are very fast and efficient when performing the exact computation for which they were designed. If any part of the circuit needs to be modified, this forces the chip to be redesigned and remanufactured, which is a very high-cost process;

[0004] The second method is to use software-programmed microprocessors, which is a more flexible solution. Processors perform computations by executing a set of instructions, and the implementation of different functions of the system can change the way the software instructions are executed without changing the hardware. However, a processor generally has four instruction cycles when completing a set of operations, including fetching instructions, decoding, executing, and writing back, so it is affected in terms of performance and is much slower than ASICs in terms of working rate.

[0005] In addition, the existing methods also have the following problems:

[0006] (1) High unit cost, long cycle, and poor flexibility of special-purpose chips

[0007] For the computing method of application-specific integrated circuits, i.e., special-purpose chips, ICs tailored for specific applications cannot be applied to other application scenarios, so the flexibility of this method is very low. If a function in the circuit is modified, it must be fundamentally redesigned, and the unit cost of the chip itself is very high, so the cost of this method is relatively high.

[0008] (2) Low efficiency and poor performance of microprocessor software programming implementation

[0009] Microprocessors generally have corresponding instruction sets, and different computations are implemented through programming. However, due to memory access, long instruction cycle time, and the limitations of fixed control architecture, the highest efficiency and fastest speed cannot be achieved.

[0010] (3) Performance of synchronous circuits is limited

[0011] In the design of integrated circuits, most designs adopt synchronous circuit design. The current mainstream CMOS process is 45nm to 14nm, and the latest process can reach 3nm. With the improvement of CMOS process, not only the integration of transistors will increase, but also the complexity of the circuit on the fixed area will increase, and the time delay sensitivity of the circuit will also increase, making the clock circuit design and implementation more difficult. Therefore, synchronous design will face challenges such as clock skew, power management of clock tree, and clock distribution.

[0012] (4) Synchronous design also has problems such as excessive power consumption and electromagnetic radiation

[0013] Through investigation, it is found that in the design of synchronous circuit, the power consumption of clock tree accounts for a high proportion in the power consumption of the entire circuit, for example: the power consumption of Alpha21164 microprocessor [1] circuit under the classic 0.18um process of DEC company accounts for 40% of the entire circuit power consumption. In many high-performance processors, the proportion of power consumption of clock circuit is about 35% to 40%. SUMMARY

[0014] In order to solve the defects and deficiencies existing in the prior art, the purpose of the present application is to provide a Lamoeba chip architecture and runtime reconstruction mechanism method based on asynchronous mechanism.

[0015] The present application is implemented as follows: a Lamoeba chip architecture and runtime reconstruction mechanism method based on asynchronous mechanism, which combines an asynchronous reconfigurable Lamoeba chip with a time-consuming reconstruction algorithm mechanism. The asynchronous mechanism Lamoeba chip provides a hardware basis for reconfigurable computing. In the Lamoeba chip architecture, the Lamoeba chip uses the communication architecture of on-chip mesh NoC for network data transmission and communication. The network uses a 2D-mesh topology, and different types of computing modules are mounted in the network. Combined with the microprocessor in the single-chip microcomputer, software programming and routing address configuration are performed to complete the calculation of the corresponding algorithm. The reconstruction algorithm calculates the data operation time, routing time and arbitration time in the network to find the shortest time allocation mode for algorithm mapping and change the deployment of the computing module in the algorithm to the hardware resource.

[0016] Preferably, the Lamoeba chip architecture based on asynchronous mechanism is composed of chip software and hardware interface, mesh NoC and PE resource. The mesh NoC provides high-performance PE interconnection, and its configuration is realized by software of the main processor. The software transmits data packets and target PE address coordinate information, and then the Lamoeba chip performs high-speed online reconfigurable computing.

[0017] Preferably, the operation process of the shortest time allocation mode in the reconstruction algorithm comprises the following steps:

[0018] (1) Calculate whether there is a request from other directions to the node in the next time period; if yes, judge that the routing node needs to be arbitrated and calculate the arbitration time, otherwise the routing node directly outputs;

[0019] (2) Calculate the total time T of different paths according to the following formula:

[0020] T=(m+n)t jump +t e +Δt

[0021]

[0022] t i，j =nt jump , n∈{0,1,…,4}

[0023] Wherein, T is the total time from the input network to the output network, the network size is m rows and n columns, t jump is the time of routing each hop, t e is the time of the corresponding calculation unit, t i，j is the arbitration time of the routing node under different coordinates, t i，j is an integer multiple of t jump , Δt is the sum of the arbitration time of each routing node in a complete path;

[0024] (3) Calculate the corresponding T for different paths, and select the path with the smallest T as the target path.

[0025] Preferably, the specific process of step (1) is:

[0026] Assuming that the coordinates of the routing nodes passed by the selected path are (i, j), t0 represents the current time point, t s，i，j represents the time point of arriving at the routing node (i, j), t f，i，j represents the time point of output from the routing node (i, j), when (i, j) does not pass through the routing node before the calculation node, α is 1, and when (i, j) passes through the routing node after the calculation node, α is 0; The time point of arriving at (i, j) routing node is calculated according to the following formula:

[0027] t s，i，j =t0+(i+j)t jump +(1-α)(t jump +t e ), α∈{0,1}

[0028] t f，i，j= t0 + (i + j + 1) t jump + (1 - a) (t jump - t e ), a e {0, 1}

[0029] Assuming the coordinates of the computing node or routing node occupied by the current time in the network is (x, y), the next node to be passed through is (i, j), and the time point of reaching the (i, j) node is t' s，x，y , and the time point of output from the routing node is t' f，x，y . When (x, y) is the coordinates of the routing node, μ is 1, and when it is the coordinates of the computing node, μ is 0. The time point formula of node (x, y) reaching the routing node (i, j) is as follows:

[0030] t' s，x，y = t0 + (i - x + j - y) t jump + (1 - μ) (t e - t r ), μ e {0, 1}

[0031] t' f，x，y = t0 + (i - x + j - y + 1) t jump + (1 - μ) (t e - t r ), μ e {0, 1}

[0032] In the time period of (t' s，x，y , t' f，x，y ), the (i, j) routing node is occupied, and when data packets come again from other directions, they cannot be directly transmitted out, but have to wait until the first data packet is transmitted out before the transmission of the next data packet can be performed. Whether arbitration or direct transmission is performed when the selected path reaches the (i, j) routing node is determined by the following formula:

[0033] t' s，x，y < t s，i，j < t' f，x，y

[0034] When the time point of the next selected path reaching (i, j) is between the time point of the node (x, y) already occupied in the network reaching (i, j) and the end time point, and data packets are transmitted in the same direction, it indicates that arbitration will occur at the node, t i，j = t jump , that is, when t' s，x，y < t s，i，j < t' f，x，y , it indicates that (i, j) is occupied in the current time period, and arbitration will occur at the routing node, and at this time Δt = t jump .

[0035] Preferably, in the deployment, the algorithm is deployed onto the hardware resources by scheduling, allocating, binding and routing reconfiguration methods.

[0036] Reconfigurable computing aims to fill the gap between hardware and software, which is to configure hardware resources by software to adapt to the processing of different algorithms, so it has the flexibility of software and the high speed of ASIC hardware. The reconfigurable system is usually composed of reconfigurable logic and general-purpose microprocessors. The processor performs operations that cannot be completed in the reconfigurable logic, and the computing core is mapped to the reconfigurable hardware. Reconfigurable computing provides a new means to improve the flexibility, adaptability and scalability of the system. The existing reconfigurable devices are field programmable gate arrays (FPGA), which contain an array of computing elements, the functions of which are determined by a plurality of programmable configuration bits. FPGA and reconfigurable computing have been proved to be able to accelerate various applications. For example, data encryption can utilize parallelism and fine-grained data operations simultaneously. The routing between logic blocks in reconfigurable hardware has an important contribution to the overall area of the reconfigurable hardware. Good routing structure is crucial to ensure that the design can be successfully placed and routed to the reconfigurable hardware.

[0037] The present application overcomes the deficiencies of the prior art, and provides a Lamoeba chip architecture and runtime reconfiguration mechanism method based on an asynchronous mechanism. The present application studies the Lamoeba chip implemented by the asynchronous mechanism in combination with the reconfiguration algorithm mechanism at the cost of time. The present chip is implemented in an event-triggered manner without a global clock, avoiding the influence of the global clock circuit in the synchronous circuit. The present chip adopts a network on chip (NoC) communication architecture to complete the transmission and communication of data on the network. The network adopts a 2D-mesh topology, mounts different computing modules thereon, and completes the calculation of the corresponding algorithm. The present chip provides a hardware basis for reconfigurable computing. The present patent proposes a reconfigurable algorithm in combination with the mesh NoC. The algorithm changes the deployment of the computing modules to the hardware resources in runtime in combination with the influence of the congestion condition in the chip network on the entire algorithm at the cost of time, mainly calculates the total time under different paths, and thus finds the time shortest allocation mode to realize the mapping of the algorithm, improving the overall implementation efficiency of the algorithm. Through the reconfigurable algorithm, the algorithm in different application scenarios is mapped to the network, the node with the smallest conflict probability in the network is found, the cost is reduced, the operation efficiency of the algorithm implemented on the network is higher, and the area utilization rate is smaller.

[0038] Compared with the disadvantages and deficiencies of the prior art, the present application has the following beneficial effects:

[0039] (1) The application adopts reconfigurable computing mode, considering the flexibility of general computing and the high efficiency of special computing. Reconfigurable computing fills the gap between hardware and software. This computing mode is through software configuration of hardware resources to adapt to the processing of different algorithms, so it has the flexibility of software and the high speed of ASIC hardware. The reconfigurable system is usually composed of reconfigurable logic and general microprocessor. The processor performs operations that cannot be completed in the reconfigurable logic, and the computing core is mapped to the reconfigurable hardware. Reconfigurable computing provides a new means to improve the flexibility, adaptability and scalability of the system.

[0040] (2) The application adopts asynchronous mechanism chip to realize reconfigurable computing mode, avoiding various problems caused by clock in synchronous circuit. The asynchronous controller is adopted to replace the clock circuit in the synchronous circuit. Compared with the synchronous clock scheme, the asynchronous circuit does not need a large clock distribution network, but realizes local communication by adopting an asynchronous controller. The asynchronous controllers complete asynchronous control through a handshake protocol, so that the challenges of clock skew, clock tree power management and clock distribution in the design of large-scale integrated circuit can be well avoided.

[0041] (3) The asynchronous circuit adopted by the application has the advantages of no clock and low power consumption. The reconfigurable chip in the application adopts the no-clock event trigger mode. Only when the event comes, the current trigger is driven to be used. When other triggers have no event driving, they will not work, so the power consumption is very low in the whole working process. This working mode has good application scenarios for military and wearable devices. In addition, the asynchronous circuit has the characteristics of low system integration complexity, high running speed, strong electromagnetic interference and network interface specification, and has strong competitiveness in low power design. Moreover, the asynchronous design also has the advantages of high throughput, no electromagnetic pollution, better robustness to power, temperature and manufacturing parameters, and good modularity.

[0042] (4) The asynchronous mesh NoC in the application has good routing performance. Different types of computing modules are mounted in the routing network, combined with the microprocessor in the single-chip microcomputer, software programming and routing address configuration are carried out to realize different computing, which provides a basis for reconfigurable computing. Therefore, it is very meaningful to study the architecture and runtime reconfiguration mechanism of the chip. BRIEF DESCRIPTION OF DRAWINGS

[0043] Figure 1 is a click controller and BBD protocol;

[0044] Figure 2 is a micro-pipeline diagram of the application;

[0045] Figure 3is the asynchronous reconfigurable hardware architecture of the present application;

[0046] Figure 4 is the reconfigurable mechanism of the present application. DETAILED DESCRIPTION

[0047] In order to make the objects, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in combination with the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and do not limit the present application.

[0048] 1. Asynchronous circuit

[0049] 1.1. BBD handshake protocol

[0050] Asynchronous mechanism is a kind of clockless circuit, as shown in Figure 1 , wherein the BBD type asynchronous circuit is a method for locally solving timing problems, which effectively distinguishes the data module and the control module of the circuit. It should be noted that the matching delay of two adjacent asynchronous controllers in the control path must be greater than the time required for the corresponding data path calculation, otherwise it will lead to incorrect behavior and output violation behavior. The control of the whole design is guaranteed by the "request-response" mechanism, and the adjacent controllers are synchronized through handshaking. Figure 1 The left half is the structure diagram of the Click asynchronous controller unit, which is composed of an exclusive OR gate, an exclusive NOR gate, an AND gate, a NOT gate, a latch and a plurality of buffer units. Unlike CElement, the Click controller adopts a 2-phase non-return-to-zero "constrained bundled data" handshake protocol. The asynchronous controller has two input terminals (in_R and out_A) and three output terminals (in_A, out_R and Fire), wherein the ports (in_R and in_A) on the left side of the controller are used for communication with the Click controller of the previous stage timing, and the ports (out_R and out_A) on the right side of the controller are used for communication with the Click controller of the next stage timing. The Fire signal is used for data processing.

[0051] 1.2. Micro-pipeline

[0052] The micro-pipeline structure was proposed by Ivan Sutherland at the 1988 Turing Award ceremony, which usually contains two paths: control path and data path, as shown in Figure 2The control path is composed of asynchronous controller and delay unit; the data path is composed of data, register and combinational logic circuit. Assuming that during initialization, the input data and the binding of req / ack pair arrive, at the same time, the local control signal fire is generated and the register is flipped, then the current stage of the data path starts to calculate with data and combinational logic. After the calculation is completed, the updated data is bound with a new event, and then enters the next stage.

[0053] 2. Asynchronous reconfigurable chip

[0054] 2.1 Chip architecture

[0055] The reconfigurable system provided by the application is composed of two parts, i.e. a microprocessor and an asynchronous reconfigurable Laoema chip, wherein the chip is mainly composed of a software and hardware interface, a mesh NoC and a PE resource, as shown in the figure. Figure 3 They are all implemented through an asynchronous mechanism, so the work of the chip is completely asynchronous.

[0056] The application uses 180nm process to manufacture a full-asynchronous mesh NoC, and the chip has passed the test, wherein the overall power supply of the chip is 3.3V, the core voltage is 1.8V, and the pins are in_data, sfr_rd, in_valid, west_in_R_00, out_data, out_valid, North_click_out_A_33, clk and rst. When in_valid is high, in_data is valid and starts to transmit data into the chip through a serial port; when out_valid is high, out_data outputs data and completes the calculation.

[0057] The NoC provides the interconnection of high-performance PEs, and its configuration is realized by the host processor through software. The software transmits data packets and address coordinate information of target PEs, and then the reconfigurable chip performs high-speed online reconfigurable calculation.

[0058] 2.2 Network on chip

[0059] The asynchronous reconfigurable chip adopts a network on chip (NoC) communication architecture, adopts a 4*4 2D-mesh as its topological structure, and can complete data communication and interaction through the network. The entire network contains two types of nodes, i.e. resource nodes and routing nodes, and the architecture diagram is as shown in the figure. Figure 3The network shown in the figure has a total of 16 routing nodes, which are network transfer nodes established to solve the communication problem between functional modules, and the main function is to realize the communication between functional modules. The resource node is a module that realizes the required function of the system, which contains 16 resource nodes. The network interacts with the outside data through a serial-parallel conversion interface and a parallel-serial conversion interface, which processes the bit width of the data. Through the network, the on-chip resources are interconnected, and the data is encapsulated and packaged for transmission, realizing efficient interaction between modules. The combination of the on-chip routing mechanism of NoC and the Mesh network structure improves the communication efficiency between the resource nodes. In the design of the entire mesh structure of NoC, a clockless asynchronous design idea is adopted, and the data is bound by an event-driven handshake mechanism, which has the characteristics of low power consumption, easy integration of modules, and high security.

[0060] Each routing node in the network has routing function in five directions, east, west, south, north and local. The first four directions are used to connect with adjacent nodes to realize the communication ability with other routing nodes around. The local input and output ports are used to communicate with the processing unit in the node to realize the data operation. The core of the network mainly includes two aspects, one is routing algorithm and the other is arbitration mechanism. The routing algorithm between nodes adopts X-Y routing algorithm, which belongs to deterministic dimension-order routing algorithm. The routing path is only related to the start address and the end address. When the routing node address and the target routing node address are determined, the routing path is unique. The routing mode of X-Y routing algorithm is to analyze the address data in the data packet first, then to route the X direction data, and then to route the Y direction data. Finally, the target node is found and the routing process is completed. In order to prevent the conflict of two or more than two requests in the routing network, arbitration mechanism is used to realize the request signal distribution, buffer and waiting functions. The arbitrator realizes the fair distribution of the request signal in the whole routing node, maintains the fairness of the arbitration result and maintains the routing health of the whole network. Each routing node in the network is connected with a processing unit. The whole network mainly includes two operation modes, fixed point and floating point, which include three 16-bit asynchronous fixed point adders, five 16-bit asynchronous floating point adders, four 16-bit asynchronous fixed point multipliers and four 16-bit asynchronous floating point multipliers. The processing unit is an important part of the processor structure, and the operation speed directly affects the efficiency of the whole chip. The fixed point multiplier is realized based on the asynchronous circuit design methodology. It adopts micro-pipeline to control the timing of each module and Booth algorithm to realize 16-bit multiplier. The core idea is to shift first (to generate multiple partial products), then to compress and finally to sum, which reduces the coupling between modules and ensures the operation speed. The floating point multiplication includes three operations, sign bit addition, exponent bit addition and mantissa multiplication. The routing mechanism of the network and the different types of operation units provide a hardware basis for the reconfigurability of the algorithm.

[0061] 3. Run-time reconfiguration

[0062] 3.1. Deterministic time cost

[0063] The main idea of the reconfigurable routing algorithm is to find a path with the least arbitration times for a complete calculation, so as to improve the operation efficiency of the whole algorithm. Through a reconfigurable algorithm, the time of data operation in different paths in the network is calculated, and the path with the shortest calculation time is found to transmit and operate the data packet.

[0064] Assuming that the network size is m rows and n columns, T is the total time from the input network to the output network, tjump t is the time for each hop of routing e t is the time for each hop of routing i，j t is the arbitration time of the routing node in different coordinates i，j t is an integer multiple of t jump A routing node receives data packets from at most 5 directions, so the maximum arbitration time of a routing node is 4 times the time of each hop, and the minimum case is that arbitration cannot occur, i.e., n is 0. The Δt time is the sum of the arbitration times of each routing node in a complete path. By calculating the total time T of different paths, the smallest T value is selected to determine the path to be taken.

[0065] T = (m + n) t jump + t e + Δt

[0066]

[0067] t i，j = nt jump , n ∈ {0, 1, …, 4}

[0068] To calculate the arbitration time, first determine whether the routing node will produce arbitration, so the calculation of the judgment is also a very important step. To determine whether the next selected path passes through a routing node that will produce arbitration, it is necessary to calculate whether the routing node will have data packets from other directions to send data packets in the same direction within the next time period. If so, the routing node will perform arbitration, and the arbitration time will be calculated. If not, the routing node will directly output.

[0069] Assume that the coordinates of the routing node passed by the selected path are (i, j), t0 represents the current time point, t s，i，j represents the time point of arrival at the routing node (i, j), t f，i，j represents the time point of output from the routing node (i, j), and α is 1 when (i, j) does not pass through a routing node before the calculation node, and α is 0 when (i, j) passes through a routing node after the calculation node. The calculation formula for the time point of arrival at (i, j) is as follows:

[0070] t s，i，j = t0 + (i + j) t jump + (1 - α) (t jump + t e ), α ∈ {0, 1}

[0071] t f，i，j = t0 + (i + j + 1) t jump + (1 - α) (t jump + t e ), α ∈ {0, 1}

[0072] Assume that the coordinates of the computing node or routing node currently occupied in the network are (x, y), and the next node to pass through is (i, j). The time point of reaching the node (i, j) is t′ s，x，y , the time point of output from this routing node is t′ f，x，y When (x, y) is the coordinate of the routing node, μ is 1, and when it is the coordinate of the calculation node, μ is 0. The time point when the node (x, y) reaches the routing node (i, j) is calculated as follows:

[0073] t′ s，x，y =t0+(i-x+jy)t jump +(1-μ)(t e -t r ), μ∈{0,1}

[0074] t′ f，x，y =t0+(i-x+j-y+1)t jump +(1-μ)(t e -t r ), μ∈{0,1}

[0075] In (t′ s，x，y , t' f，x，y ) time period, the (i, j) routing node is occupied. When a data packet is received from another direction, it cannot be directly transmitted. It must wait until the first data packet is transmitted before the next data packet can be transmitted. When the selected path reaches the (i, j) routing node, whether to arbitrate or transmit directly is determined by the following formula:

[0076] t′ s，x，y <t s，i，j <t′ f，x，y

[0077] When the time point at which the next selected path reaches (i, j) is between the time point at which the occupied node (x, y) in the network reaches (i, j) and the time point at which it ends, and the data packet is transmitted in the same direction, it indicates that the node will arbitrate, t i，j =t jump , that is, when t′ s，x，y <t s，i，j <t′ f，x，y When (i, j) is occupied in the current time period, the routing node will arbitrate, and Δt = t jump ; Calculate Δt using this method and ultimately get the total time T.

[0078] 3.2 Runtime Reconfiguration Strategy

[0079] Reconfigurability mainly includes algorithm and resource reconfigurability. The algorithm is deployed on the hardware resource through scheduling, allocation, binding and routing reconfiguration method. The reconfigurable system is usually composed of the combination of reconfigurable logic and general microprocessor. The implementation architecture of the corresponding software and hardware interaction processing mechanism is the combination of software processor and Lamoeba chip.

[0080] For Figure 4 For the overall mechanism of the reconfigurable system shown, firstly, the application of a specific scenario is divided into multiple tasks by the main CPU, wherein the task contains corresponding operation and scheduled data. The scheduling strategy is to allocate the task to the corresponding software cluster or hardware cluster according to the potential parallelism at the operation level. After the task is allocated to the hardware, the chip is configured according to the time cost evaluation method. The reconfigurable chip receives the data packet through the hardware-software interface, configures the resource, completes the software-hardware mapping, and performs time calculation.

[0081] The above only describes the preferred embodiments of the present application and is not used to limit the present application. Any modification, equivalent replacement and improvement made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A Lamoeba chip architecture and runtime reconstruction mechanism method based on asynchronous mechanism, characterized in that: The method combines an asynchronously reconfigurable Lamoeba chip with a time-costly reconstruction algorithm mechanism. The asynchronous Lamoeba chip provides a hardware foundation for reconfigurable computing. In the Lamoeba chip architecture, the Lamoeba chip uses an on-chip mesh NoC communication architecture to transmit and communicate data on the network. The network adopts a 2D-mesh topology structure. Different types of computing modules are mounted in the network. In combination with the microprocessor in the single-chip microcomputer, software programming and routing address configuration are performed to complete the calculation of the corresponding algorithm. The reconstruction algorithm calculates the data operation time, routing time and arbitration time under different paths in the network to find the shortest allocation method to map the algorithm and change the deployment of the computing modules in the algorithm to the hardware resources. The calculation process of the allocation method with the shortest time in the reconstruction algorithm includes the following steps: (1) Calculate whether there is a request from a data packet from another direction to the routing node in the next time period; if so, determine whether the routing node needs to arbitrate and calculate the arbitration time; otherwise, the routing node directly outputs; (2) Calculate the total time T of different paths according to the following formula: T=(m+n)t jump +t e +Δt t i，j =nt jump ,n∈{0,1,…,4} Among them, T is the total time from entering the network to leaving the network, the network size is m rows and n columns, t jump is the time for each hop of routing, t e is the execution time of the corresponding computing unit, t i，j is the arbitration time of routing nodes at different coordinates, t i，j It is t jump An integer multiple of Δt, which is the sum of the arbitration times of nodes in each route in a complete path; (3) Calculate the corresponding T for different paths and select the path with the shortest time T as the target path; The specific process of step (1) is as follows: Assume that the coordinates of the routing node passed by the selected path are (i, j), t0 represents the current time point, t s，i，j Indicates the time point of arrival at routing node (i, j), t f，i，j It represents the time point when the routing node (i, j) is output. When (i, j) has not passed the routing node before the calculation node, α is 1. When it passes the routing node after the calculation node, α is 0. The time point when it reaches the routing node (i, j) is calculated as follows: t s，i，j =t0+(i+j)t jump +(1-α)(t jump +t e ),α∈{0,1} t f，i，j =t0+(i+j+1)t jump +(1-α)(t jump +t e ),α∈{0,1} Assume that the coordinates of the computing node or routing node currently occupied in the network are (x, y), and the next node to pass through is (i, j). The time point of reaching the node (i, j) is t′ s，x，y , the time point of output from this routing node is t′ f，x，y When (x, y) is the coordinate of the routing node, μ is 1, and when it is the coordinate of the calculation node, μ is 0. The calculation formula for the time point when the node (x, y) reaches the routing node (i, j) is as follows: t′ s，x，y =t0+(i-x+j-y)t jump +(1-μ)(t e -t r ),μ∈{0,1} t′ f,x,y =t0+(i-x+j-y+1)t jump +(1-μ)(t e -t r ),μ∈{0,1} In (t′ s,x,y ,t′ f,x,y ) time period, the (i, j) routing node is occupied. When transmitting data packets in other directions again, they cannot be transmitted directly. They have to wait until the first data packet is transmitted before the next data packet can be transmitted. When the selected path reaches the (i, j) routing node, whether arbitration or direct transmission is determined is determined by the following formula: t′ s,x,y <t s,i,j <t′ f,x,y When the time point at which the next selected path reaches (i, j) is between the time point at which the occupied node (x, y) in the network reaches (i, j) and the time point at which it ends, and the data packet is transmitted in the same direction, it indicates that the node will arbitrate, t i，j =t jump , that is, when t′ s，x，y <t s，i，j <t′ f，x，y When (i, j) is occupied in the current time period, the routing node will arbitrate, and Δt = t jump .

2. The method according to claim 1, wherein The asynchronous Lamoeba chip architecture consists of chip hardware and software interfaces, a mesh NoC (Not Controlled Component) and PE resources. The mesh NoC provides high-performance PE interconnection, and its configuration is implemented by the main processor using software. The software transmits data packets and the address coordinate information of the target PE, and then the Lamoeba chip performs high-speed online reconfigurable computing.

3. The method according to claim 1, wherein In the deployment, the algorithm is deployed on hardware resources through scheduling, allocation, binding and routing reconstruction methods.

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