Receiving Circuit, Source Driver Chip, Display Device, and Data Channel Selection Method

Abstract

Embodiments of the present application provide a receiving circuit, a source driver chip, a display device, and a data channel selection method. The receiving circuit includes a first receiving module, a second receiving module, a detection circuit, and a selection circuit; the first receiving module corresponds to a first data channel; the second receiving module corresponds to a second data channel; the first receiving module includes a first analog front end and a first clock data recovery circuit connected electrically; the second receiving module includes a second analog front end and a second clock data recovery circuit connected electrically; the detection circuit is connected to the first analog front end, the second analog front end, and the first clock data recovery circuit respectively, and is configured to output a channel selection signal based on the received first signal, second signal, and frequency lock signal. By adopting the embodiments of the present application, automatic detection and control of the data channel can be performed without consuming additional chip pins, thereby reducing the number of chip pins and reducing the dependence on the timing control chip.

Description

Technical Field

[0001] The present application relates to the field of display technologies. Specifically, the present application relates to a receiving circuit, a source driver chip, a display device, and a data channel selection method. Background Art

[0002] With the continuous increase in the size and resolution of display panels, more and more display data needs to be transmitted from a Timing Controller (TCON) chip to a Source Driver (SD) chip. Increasing the data channels can significantly increase the amount of transmitted data. More and more point-to-point interface protocols in display panels can support the multi-data channel mode, and one data channel corresponds to one receiving module.

[0003] In a receiving module, it includes an analog front-end (AFE) and a Clock Data Recovery (CDR) circuit. The analog front-end receives small signals from the channel, amplifies the small signals, and transmits the amplified signals to the clock data recovery circuit. The source driver chip can receive signals from the timing control chip through one data channel or two data channels.

[0004] Generally, there are two common ways to control the data channel mode (i.e., select one data channel or two data channels). One is to control through the pins of the source driver chip. The other is to control through the information package sent by the Timing Controller (TCON) chip to the source driver chip.

[0005] However, the pin control method consumes additional chip pins, and the information package control method depends on the TCON chip. Summary of the Invention

[0006] Aiming at the disadvantages of the existing methods, the present application proposes a receiving circuit, a source driver chip, a display device, and a data channel selection method.

[0007] In a first aspect, an embodiment of the present application provides a receiving circuit, including: a first receiving module, a second receiving module, a detection circuit, and a selection circuit; the first receiving module corresponds to a first data channel; the second receiving module corresponds to a second data channel;

[0008] The first receiving module includes an electrically connected first analog front-end and a first clock data recovery circuit; the first analog front-end is used to output a first signal; the first clock data recovery circuit is used to output a frequency locked signal and a first locked signal based on the first signal;

[0009] The second receiving module includes an electrically connected second analog front end and a second clock data recovery circuit; the second analog front end is used to output a second signal; the second clock data recovery circuit is used to output a second locking signal based on the second signal;

[0010] The detection circuit is respectively connected to the first analog front end, the second analog front end and the first clock data recovery circuit, and is used to output a channel selection signal based on the received first signal, second signal and frequency locking signal;

[0011] The selection circuit is respectively connected to the first clock data recovery circuit, the second clock data recovery circuit and the detection circuit, and is used to generate a third locking signal from the received first locking signal and second locking signal, and output the first locking signal or the third locking signal based on the received channel selection signal.

[0012] In a possible implementation, the selection circuit includes a first logic gate circuit and a selector;

[0013] The first logic gate circuit is respectively connected to the first clock data recovery circuit and the second clock data recovery circuit, and is used to output a third locking signal based on the first locking signal and the second locking signal;

[0014] The selector is respectively connected to the first logic gate circuit, the first clock data recovery circuit and the detection circuit, and is used to select and output the first locking signal or the third locking signal based on the channel selection signal;

[0015] The detection circuit is further used to output the channel selection signal to the second analog front end and the second clock data recovery circuit to control the working states of the second analog front end and the second clock data recovery circuit.

[0016] In a possible implementation, the detection circuit includes:

[0017] The second logic gate circuit is connected to the first clock data recovery circuit and is used to output a third signal based on the frequency locking signal;

[0018] The trigger circuit is respectively connected to the second logic gate circuit and the first signal terminal, and is used to be reset based on the third signal and output a fourth signal;

[0019] The first counting module is respectively connected to the first analog front end, the second logic gate circuit and the trigger circuit, and is used to be reset based on the third signal and output a fifth signal to the trigger circuit and the third logic gate circuit based on the first signal and the fourth signal;

[0020] The third logic gate circuit is respectively connected to the trigger circuit and the first counting module, and is used to output a sixth signal based on the fourth signal and the fifth signal;

[0021] The second counting module is respectively connected to the second analog front end, the third logic gate circuit and the second logic gate circuit, and is used for resetting based on the third signal, and outputting a seventh signal based on the second signal and the sixth signal; the seventh signal is used to obtain a channel selection signal through a look-up table.

[0022] In a possible implementation manner, the second logic gate circuit includes: an inverter group and a first NAND gate;

[0023] The inverter group includes n inverters connected in sequence, where n is an odd number;

[0024] The first input end of the first NAND gate is connected to one end of the inverter group and the first clock data recovery circuit, and is used for receiving the frequency locking signal;

[0025] The second input end of the first NAND gate is connected to the other end of the inverter group;

[0026] The output end of the first NAND gate is used for outputting a third signal. In a possible implementation manner, the trigger circuit includes: a first flip-flop, a first inverter, a second flip-flop and a second inverter;

[0027] The output end of the first counting module is connected to the clock end of the first flip-flop, the input end of the first flip-flop is connected to the first signal end, the reset end of the first flip-flop is connected to the second logic gate circuit, and the output end of the first flip-flop is connected to the input end of the second flip-flop;

[0028] The output end of the first counting module is connected to the clock end of the second flip-flop via the first inverter, and the reset end of the second flip-flop is connected to the second logic gate circuit;

[0029] The second flip-flop outputs a fourth signal via the second inverter.

[0030] In a possible implementation manner, the third logic gate circuit includes: a second NAND gate and a third inverter;

[0031] The first input end of the second NAND gate is connected to the trigger circuit for receiving the fourth signal;

[0032] The second input end of the second NAND gate is connected to the first counting module for receiving the fifth signal;

[0033] The output end of the second NAND gate outputs a sixth signal via the third inverter.

[0034] In a possible implementation manner, the first counting module includes a first counter;

[0035] The enable end of the first counter is connected to the trigger circuit for receiving the fourth signal;

[0036] The clock terminal of the first counter is connected to the first analog front end and is used to receive a first signal;

[0037] The reset terminal of the first counter is connected to the second logic gate circuit and is used to receive a third signal;

[0038] The output terminal of the first counter is respectively connected to the trigger circuit and the third logic gate circuit and is used to output a fifth signal.

[0039] In a possible implementation manner, the second counting module includes a second counter;

[0040] The enable terminal of the second counter is connected to the third logic gate circuit and is used to receive a sixth signal;

[0041] The clock terminal of the second counter is connected to the second analog front end and is used to receive a second signal;

[0042] The reset terminal of the second counter is connected to the second logic gate circuit and is used to receive a third signal;

[0043] The output terminal of the second counter is used to output a seventh signal.

[0044] In a second aspect, an embodiment of the present application provides a source driver chip, including the receiving circuit as in the first aspect.

[0045] In a third aspect, an embodiment of the present application provides a display device, including a timing control chip and the source driver chip as in the second aspect;

[0046] The receiving circuit is connected to the timing control chip and is used to output a first lock signal or a third lock signal to the timing control chip.

[0047] In a fourth aspect, an embodiment of the present application provides a method for selecting a data channel by the receiving circuit as in the first aspect, including:

[0048] Outputting a frequency lock signal and a first lock signal based on the received first signal, and outputting a second lock signal based on the received second signal;

[0049] Outputting a channel selection signal based on the first signal, the second signal and the frequency lock signal;

[0050] Outputting a first lock signal or a third lock signal based on the channel selection signal to select a data channel; wherein, the first lock signal is used to control the selection of a first data channel, and the third lock signal is generated from the first lock signal and the second lock signal and is used to control the selection of the first data channel and the second data channel.

[0051] The beneficial technical effects brought by the technical solutions provided by the embodiments of the present application include:

[0052] The receiving circuit provided by the embodiment of the present application passes through a detection circuit. The detection circuit is respectively connected to a first analog front end, a second analog front end, and a first clock data recovery circuit, and is used to output a channel selection signal based on the received first signal, second signal, and frequency lock signal. Through a selection circuit, the first lock signal or the third lock signal is selected and output to automatically detect and control the data channel, without consuming additional chip pins, thereby being able to reduce the number of chip pins and reduce the dependence on the timing control chip.

[0053] Additional aspects and advantages of the present application will be given in part in the following description, which will become apparent from the following description, or will be understood through the practice of the present application. Description of the Drawings

[0054] The above and / or additional aspects and advantages of the present application will become apparent and easy to understand from the following description of the embodiments in conjunction with the drawings, where:

[0055] Figure 1 is a schematic structural diagram of a receiving circuit provided by an embodiment of the present application;

[0056] Figure 2 is a schematic circuit principle diagram of a receiving circuit provided by an embodiment of the present application;

[0057] Figure 3 is a schematic structural diagram of a detection circuit provided by an embodiment of the present application;

[0058] Figure 4 is a schematic circuit principle diagram of a detection circuit provided by an embodiment of the present application;

[0059] Figure 5 is a schematic timing diagram of a detection circuit provided by an embodiment of the present application;

[0060] Figure 6 is a schematic timing diagram of a single-channel data channel mode operation provided by an embodiment of the present application;

[0061] Figure 7 is a schematic timing diagram of a two-channel data channel mode operation provided by an embodiment of the present application;

[0062] Figure 8 is a schematic structural diagram of a display device provided by an embodiment of the present application;

[0063] Figure 9 is a schematic flowchart of a method for a receiving circuit to select a data channel provided by an embodiment of the present application.

[0064] Reference Numerals:

[0065] 1 - Source driver chip, 10 - Receiving circuit, 11 - First receiving module, 111 - First analog front end, 112 - First clock data recovery circuit, 12 - Second receiving module, 121 - Second analog front end, 122 - Second clock data recovery circuit, 13 - Detection circuit, 131 - Second logic gate circuit, 132 - Trigger circuit, 133 - First counting module, 134 - Third logic gate circuit, 135 - Second counting module, 14 - Selection circuit, 141 - First logic gate circuit, 142 - Selector; 20 - Third receiving module;

[0066] 2 - Timing control chip. Detailed implementation manners

[0067] The present application will be described in detail below. Examples of embodiments of the present application are shown in the drawings, where the same or similar reference numerals denote the same or similar components or components having the same or similar functions throughout. In addition, if the detailed description of the known technology is unnecessary for showing the features of the present application, it will be omitted. The embodiments described below with reference to the drawings are exemplary and are only used to explain the present application and should not be construed as a limitation of the present application.

[0068] Those skilled in the art of the present technology can understand that, unless otherwise defined, all terms (including technical terms and scientific terms) used herein have the same meaning as the general understanding of those of ordinary skill in the technical field to which the present application belongs. It should also be understood that terms such as those defined in a general dictionary should be understood to have a meaning consistent with the meaning in the context of the prior art, and will not be interpreted in an idealized or overly formal sense unless specifically defined as here.

[0069] Those skilled in the art of the present technology can understand that, unless specifically stated, the singular forms "a", "an", "the" and "said" used herein may also include the plural forms. It should be further understood that the phrase "comprising" used in the specification of the present application means the presence of the stated features, integers, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or their groups. It should be understood that when we say that an element is "connected" or "coupled" to another element, it can be directly connected or coupled to other elements, or there may also be intermediate elements. In addition, the "connection" or "coupling" used herein may include wireless connection or wireless coupling. The phrase "and / or" used herein includes all or any unit and all combinations of one or more related listed items.

[0070] The technical solutions of the present application and how the technical solutions of the present application solve the above technical problems will be described in detail below with specific embodiments.

[0071] An embodiment of the present application provides a receiving circuit 10, as Figure 1 shown. The receiving circuit 10 includes: a first receiving module 11, a second receiving module 12, a detection circuit 13, and a selection circuit 14; the first receiving module 11 corresponds to a first data channel; the second receiving module 12 corresponds to a second data channel.

[0072] The first receiving module 11 includes an electrically connected first analog front end 111 and a first clock data recovery circuit 112; the first analog front end 111 is configured to amplify a received small signal and then output a first signal DIN0; the first clock data recovery circuit 112 is configured to output a frequency lock signal FLOCK0 and a first lock signal LOCK0 based on the first signal DIN0; wherein, the frequency lock signal FLOCK0 is used to represent the locked frequency of the first signal DIN0, and the first lock signal LOCK0 is used to represent the locked frequency and phase of the first signal D1N0.

[0073] The second receiving module 12 includes an electrically connected second analog front end 121 and a second clock data recovery circuit 122; the second analog front end 121 is configured to amplify a received small signal and then output a second signal DIN1; the second clock data recovery circuit 122 is configured to output a second lock signal LOCK1 based on the second signal DIN1, and the second lock signal LOCK1 is used to represent the locked frequency and phase of the second signal DIN1.

[0074] The detection circuit 13 is respectively connected to the first analog front end 111, the second analog front end 121, and the first clock data recovery circuit 112, and is configured to output a channel selection signal EN1 based on the received first signal DIN0, second signal DIN1, and frequency lock signal FLOCK0;

[0075] The selection circuit 14 is respectively connected to the first clock data recovery circuit 112, the second clock data recovery circuit 122, and the detection circuit 13, and is configured to generate a third lock signal from the received first lock signal LOCK0 and second lock signal LOCK1, and output the first lock signal LOCK0 or the third lock signal based on the received channel selection signal EN1.

[0076] It should be noted that the first lock signal LOCK0 corresponds to the first data channel, and the second lock signal LOCK1 corresponds to the second data channel. Since the third lock signal is generated based on the first lock signal LOCK0 and the second lock signal LOCK1, the third lock signal corresponds to both the first data channel and the second data channel at the same time. When the selection circuit 14 outputs the first lock signal LOCK0, it means that the selection circuit 14 selects the first data channel. When the selection circuit 14 outputs the third lock signal, it means that the selection circuit 14 selects both the first data channel and the second data channel at the same time.

[0077] The receiving circuit 10 provided by the embodiment of the present application passes through the detection circuit 13. The detection circuit 13 is respectively connected to the first analog front end 111, the second analog front end 121 and the first clock data recovery circuit 112, and is used for outputting a channel selection signal based on the received first signal DIN0, second signal DIN1 and frequency lock signal FLOCK0. Through the selection circuit 14, the first lock signal LOCK1 or the third lock signal is selected and output. Since the first lock signal LOCK1 corresponds to the first data channel and the third lock signal corresponds to the first data channel and the second data channel, automatic detection and control of the data channel can be realized without consuming additional chip pins, thereby reducing the number of chip pins and reducing the dependence on the timing control chip.

[0078] In some embodiments, as Figure 1 shown, the selection circuit 14 includes a first logic gate circuit 141 and a selector 142;

[0079] The first logic gate circuit 141 is respectively connected to the first clock data recovery circuit 112 and the second clock data recovery circuit 122, and is used for outputting a third lock signal based on the first lock signal LOCK0 and the second lock signal LOCK1;

[0080] The selector 142 is respectively connected to the first logic gate circuit 141, the first clock data recovery circuit 112 and the detection circuit 13, and is used for selecting and outputting the first lock signal LOCK0 or the third lock signal based on the channel selection signal EN1;

[0081] The detection circuit 13 is further used for outputting the channel selection signal EN1 to the second analog front end 121 and the second clock data recovery circuit 122 to control the working states of the second analog front end 121 and the second clock data recovery circuit 122.

[0082] Exemplarily, as Figure 2As shown, the first logic gate circuit 141 includes a second NAND gate and a fourth inverter. The first input terminal of the second NAND gate is connected to the first clock data recovery circuit 112 for receiving the first lock signal LOCK0. The second input terminal of the second NAND gate is connected to the second clock data recovery circuit 122 for receiving the second lock signal LOCK1. The output terminal of the second NAND gate outputs a third lock signal LOCK2 via the fourth inverter. One input terminal of the selector 142 is connected to the inverter for receiving the third lock signal LOCK2, and the other input terminal of the selector 142 is connected to the first clock data recovery circuit 112 for receiving the first lock signal LOCK0. The lock signal LOCK output by the output terminal of the selector 142 includes the first lock signal LOCK0 or the third lock signal LOCK2. The selector 142 determines whether to output the first lock signal LOCK0 or the third lock signal LOCK2 based on the channel selection signal EN1. The specific selection method will be introduced below and will not be elaborated here.

[0083] Please refer to Figure 2 、 Figure 6 and Figure 7 As shown, the channel selection signal EN0 is used to control whether the first analog front end 111 and the first clock data recovery circuit 112 work. If the channel selection signal EN0 is at a high level (H), both the first analog front end 111 and the first clock data recovery circuit 112 are in an operating state. If the channel selection signal EN0 is at a low level (L), both the first analog front end 111 and the first clock data recovery circuit 112 are in a non-operating state. In this application, as Figure 6 and Figure 7 shown, the channel selection signal EN0 is at a high level (H), and the channel selection signal EN0 controls the operation of the first analog front end 111 and the first clock data recovery circuit 112, that is, the first data channel in this application is always operating. Specifically, in implementation, the channel selection signal EN0 is controlled by the chip power supply, that is, after the chip is powered on and stabilized, the channel selection signal EN0 becomes high level. As Figures 6 - 7 shown, the channel selection signal EN0 and the channel selection signal EN1 being at a high level (H) are both power-on initial settings.

[0084] Figure 2 In it, AFE0 represents the first analog front end, AFE1 represents the second analog front end, CDR0 represents the first clock data recovery circuit, CDR1 represents the second clock data recovery circuit, and LDD (Lane Data Detection) represents the detection circuit.

[0085] In some embodiments, as Figure 3As shown, the detection circuit 13 includes: a second logic gate circuit 131, a trigger circuit 132, a first counting module 133, a third logic gate circuit 134, and a second counting module 135.

[0086] The second logic gate circuit 131 is connected to the first clock data recovery circuit 112 and is configured to output a third signal RSB based on the frequency lock signal FLOCK.

[0087] The trigger circuit 132 is respectively connected to the second logic gate circuit and the first signal terminal VDD, and is configured to be reset based on the third signal RSB and output a fourth signal EN_LD.

[0088] The first counting module 133 is respectively connected to the first analog front end 111, the second logic gate circuit, and the trigger circuit 132, and is configured to be reset based on the third signal RSB and output a fifth signal Q0<7> to the trigger circuit 132 and the third logic gate circuit 134 based on the first signal DIN0 and the fourth signal EN_LD.

[0089] The third logic gate circuit 134 is respectively connected to the trigger circuit 132 and the first counting module 133, and is configured to output a sixth signal EN1_LD based on the fourth signal EN_LD and the fifth signal Q0<7>.

[0090] The second counting module 135 is respectively connected to the second analog front end 121, the third logic gate circuit 143, and the second logic gate circuit 131, and is configured to be reset based on the third signal RSB and output a seventh signal Q1<7:0> based on the second signal D1N1 and the sixth signal EN1_LD; the seventh signal Q1<7:0> is used to obtain a channel selection signal through a look-up table. The method of obtaining the channel selection signal through the look-up table will be introduced below and will not be elaborated here.

[0091] In some embodiments, as Figure 4 shown, the second logic gate circuit 131 includes: an inverter group and a first NAND gate.

[0092] The inverter group includes n inverters connected in sequence, where n is an odd number. Figure 4 In which n = 3. Of course, the value of n can be set according to actual situations and is not limited in this application.

[0093] Setting n inverters (n being an odd number) is used to first reset the first counter CNT0, the second counter CNT1, and two D flip-flops (the third signal RSB is at a low level), and then resume operation (the third signal RSB is at a high level). It can be understood that as Figure 4 and Figure 5As shown, after the frequency-locked signal FLOCK0 passes through n inverters, there is a delay, and the delay time is the time when the third signal RSB is at a low level (L).

[0094] The first input terminal of the first NAND gate is connected to one end of the inverter group and the first clock data recovery circuit 112, and is used to receive the frequency-locked signal FLOCK0; the second input terminal of the first NAND gate is connected to the other end of the inverter group; the output terminal of the first NAND gate is used to output the third signal RSB.

[0095] In some embodiments, as Figure 4 shown, the trigger circuit 132 includes: a first flip-flop, a first inverter, a second flip-flop, and a second inverter; both the first flip-flop and the second flip-flop are D flip-flops.

[0096] The output terminal of the first counting module is connected to the clock terminal of the first flip-flop, the input terminal (D) of the first flip-flop is connected to the first signal terminal VDD, the reset terminal Rb of the first flip-flop is connected to the second logic gate circuit, and the output terminal Q of the first flip-flop is connected to the input terminal D of the second flip-flop;

[0097] The output terminal of the first counting module 133 is connected to the clock terminal of the second flip-flop via the first inverter, and the reset terminal Rb of the second flip-flop is connected to the second logic gate circuit 131; the second flip-flop outputs the fourth signal EN_LD via the second inverter.

[0098] In some embodiments, as Figure 4 shown, the third logic gate circuit 134 includes: a second NAND gate and a third inverter;

[0099] The first input terminal of the second NAND gate is connected to the trigger circuit and is used to receive the fourth signal EN_LD; the second input terminal of the second NAND gate is connected to the first counting module 133 and is used to receive the fifth signal Q0<7>; the output terminal of the second NAND gate outputs the sixth signal EN1_LD via the third inverter.

[0100] In some embodiments, as Figure 4 shown, the first counting module 133 includes a first counter CNT0.

[0101] The enable terminal of the first counter CNT0 is connected to the trigger circuit 132 and is used to receive the fourth signal EN_LD; the clock terminal of the first counter CNT0 is connected to the first analog front end 111 and is used to receive the first signal D1N0; the reset terminal of the first counter CNT0 is connected to the second logic gate circuit 131 and is used to receive the third signal RSB; the output terminal of the first counter CNT0 is respectively connected to the trigger circuit 132 and the third logic gate circuit 134 and is used to output the fifth signal Q0<7>.

[0102] In some embodiments, as Figure 4 shown, the second counting module 135 includes a second counter CNT1.

[0103] The enable terminal of the second counter CNT1 is connected to the third logic gate circuit 134 for receiving the sixth signal EN1_LD; the clock terminal of the second counter CNT1 is connected to the second analog front end 121 for receiving the second signal D1N1; the reset terminal of the second counter CNT1 is connected to the second logic gate circuit for receiving the third signal RSB; the output terminal of the second counter CNT1 is used for outputting the seventh signal Q1<7:0>.

[0104] Please refer to Figure 2 , Figure 4 , Figure 5 , Figure 6 and Figure 7 , and the working principle of the receiving circuit 10 provided in the embodiments of the present application will be described below. The receiving circuit 10 provided in the present application automatically detects and controls the received signal during the training phase to achieve automatic control of the data channel mode. The circuit is simple and convenient, without consuming additional chip pins, thereby being able to reduce the number of chip pins and also being able to reduce the dependence on the timing control chip.

[0105] As Figure 6 and Figure 7 shown, during the training phase, the receiving circuit 10 of the source driver chip 1 will track the frequency and phase of the training data, where the training data is the low-frequency clock signal included in the first signal DIN0 and the low-frequency clock signal included in the second signal DIN1. After locking the frequency and phase of the training data, a lock signal will be output and the lock signal (such as Figure 6 and Figure 7 LOCK) will be fed back to the timing control chip, and the timing control chip will send display data to the source driver chip 1 based on the lock signal (such as Figure 6 and Figure 7 LOCK), and enter the data phase. As Figure 2 , Figure 6 and Figure 7 shown, LOCK represents the lock signal output by the selector 142, that is, LOCK is the first lock signal LOCK0 or the third lock signal LOCK2. The third lock signal LOCK2 is obtained by the first lock signal LOCK0 and the second lock signal LOCK1 through a NAND gate and an inverter.

[0106] Optionally, the first clock data recovery circuit 112 is connected to the third receiving module 20 for outputting the first data signal DOUT0 <n:0>to the third receiving module 20; the second clock data recovery circuit 122 is connected to the third receiving module 20 for outputting a second data signal DOUT1 <n:0>to the third receiving module 20; the third receiving module 20 is configured to receive the first data signal DOUT0 <n:0>, and / or, the second data signal DOUT1 <n:0>Perform encoding and decoding processing; the specific setting method and working principle of the third receiving module 20 are similar to those of the prior art and will not be elaborated here.

[0107] See Figure 2 , Figure 6 and Figure 7 As shown, the working principle of the receiving circuit is as follows:

[0108] In the training stage, when the frequency lock signal FLOCK0 changes from low level to high level, the detection circuit 13 starts to operate, that is, starts to compare the frequencies of the first signal DIN0 and the second signal DIN1, as in the frequency comparison stage T1 in Figure 6 and Figure 7 . Figure 6 and Figure 7 EN0 in

[0109] is always at high level, that is, the first data channel Lane0 in this application always works. Figure 6 As shown in Figure 6 , when the chip is powered on, the initial setting of the channel selection signal EN1 is high level (H). When the frequency lock signal FLOCK0 changes from low level to high level, it enters the frequency comparison stage T1, and the detection circuit 13 starts to work. If in this stage, the detection circuit 13 detects that the frequencies of the first signal D1N0 and the second signal D1N1 are basically not equal (when the range of the following K value is other), then after the frequency comparison stage T1, the output channel selection signal EN1 jumps from high level to low level (L). When the channel selection signal EN1 output by the detection circuit 13 is at low level, it means that only the first data channel works. The selector 142 selects the output lock signal LOCK as the first lock signal LOCK0 based on the low-level channel selection signal EN1, as shown by the two arrow directions in

[0110] As shown in Figure 7 , if in the frequency comparison stage T1, the detection circuit 13 detects that the frequencies of the first signal D1N0 and the second signal D1N1 are basically equal (when the range of the following K value is between 120 and 136), then after the frequency comparison stage T1, the level of the output channel selection signal EN1 does not change and still outputs high level (H). When the channel selection signal EN1 output by the detection circuit 13 is at high level, it means that two data channels work. The selector 142 selects the output lock signal LOCK as the lock signal obtained from the first lock signal LOCK0 and the second lock signal LOCK1 through a NAND gate and an inverter based on the channel selection signal EN1, that is, the lock signal LOCK is the signal output when both the first lock signal LOCK0 and the second lock signal LOCK1 are at high level, as shown by the two arrow directions in Figure 7 .

[0111] See Figure 4 and Figure 5 , the working principle of the detection circuit 13 is as follows:

[0112] Taking the first counter CNT0 and the second counter CNT1 both being 8-bit counters as an example for illustration. Of course, the first counter CNT0 and the second counter CNT1 can also be set to other types of counters, which is not limited in this application.

[0113] The first counter CNT0 is configured to only count the highest bit, that is, when the first counter CNT0 counts up to 128 times, the level of the fifth signal Q0<7> output by the first counter CNT0 is inverted once. The second counter CNT1 is configured to start counting from 0, that is, the second counter CNT1 counts 0, 1, 2,..., K - 1, K. When the level of the fifth signal Q0<7> output by the first counter CNT0 is inverted, the counting of the second counter CNT1 is completed, and the seventh signal Q1<7:0> output by the second counter CNT1 is a value (K value).

[0114] As shown in Table 1, when the range of the K value is between 120 and 136 (including the two end values 120 and 136), EN1 is 1, as Figure 7 shown, the lock signal LOCK is the signal after the NAND operation of the first lock signal LOCK0 and the second lock signal LOCK1 and then passing through an inverter, that is, when it is detected that the frequencies of the signals of the two data channels are basically equal (the range of the K value is 120 - 136), the first data channel and the second data channel are both controlled to work, that is, the two-channel data channel mode is selected. When the range of the K value is other (Else), EN1 is 0, as Figure 6 shown, the lock signal LOCK is the first lock signal LOCK0, that is, the frequency of the signal of the second data channel is not detected, that is, the first data channel works and the second data channel is controlled not to work, that is, the one-channel data channel mode is selected.

[0115] The range of the K value being between 120 and 136 (including the two end values 120 and 136) is only an example, and it can also be set to other ranges, which is not limited in this application.

[0116] Table 1: Example of LUT (look-up table)

[0117]

[0118] such as Figure 4 and Figure 5 As shown, when the frequency lock signal FLOCK0 changes from low level to high level, a third signal RSB is generated through the second logic gate circuit 131. This third signal RSB is first low level for a first duration and then becomes high level. The second logic gate circuit 131 is used to first change the third signal RSB generated by the frequency lock signal FLOCK0 to low level, so as to reset the first counter CNT0, the second counter CNT1, and two D flip - flops. Thus, the fifth signal Q0<7> and the seventh signal Q1<7:0> are reset by the first counter CNT0 and the second counter CNT1 and become low level; after the fourth signal EN_LD is reset by the two D flip - flops and then passes through an inverter, it becomes high level. After the two D flip - flops are reset, the output Q of the two D flip - flops outputs low level, and the second D flip - flop outputs high level after passing through an inverter, that is, the fourth signal EN_LD becomes high level.

[0119] When the fourth signal EN_LD becomes high level, the first counter CNT0 starts to count the number of rising edges of the first signal DIN0. When it counts 128 times, the fifth signal Q0<7> changes from low level to high level. The first D flip - flop outputs high level, and the second D flip - flop outputs low level. After passing through an inverter, the fourth signal EN_LD is still high level. The high - level fourth signal EN_LD and the high - level fifth signal Q0<7> pass through the third logic gate circuit 134 and then output a high - level sixth signal EN1_LD.

[0120] When the sixth signal EN1_LD becomes high level, the second counter CNT1 starts to count the number of rising edges of the second signal DIN1 until the fifth signal Q0<7> is pulled low. Specifically, when the first counter CNT0 counts 128 times, the level of the fifth signal Q0<7> is inverted once. The output Q of the first D flip - flop outputs high level, and the output Q of the second D flip - flop outputs high level. The fourth signal EN_LD output after passing through an inverter becomes low level. Since the fourth signal EN_LD is output to the enable terminal of the first counter CNT0, the first counter CNT0 stops working, that is, the fifth signal Q0<7> is pulled low and becomes low level. The low - level fifth signal Q0<7> and the low - level fourth signal EN_LD pass through the third logic gate circuit 134 and then output a low - level sixth signal EN1_LD, causing the second counter CNT1 to stop working.

[0121] The seventh signal Q1<7:0> output by the second counter CNT1 is a value (K value) determined by the input frequency of the second signal DIN1. According to the established corresponding information table (such as Table 1), it can be determined whether the input frequency of the second signal DIN1 is equal to the input frequency of the first signal DIN0, so as to determine the value of the channel selection signal EN1.

[0122] The detection circuit 13 provided in the embodiment of the present application, in addition to the two data channel applications described above, any other multi-data channels can control the automation of the data channel mode through the above detection circuit 13, and all are within the protection scope of the present application. For example, if there are three data channels, according to the principle of the above two data channels, one data channel can be set to work all the time, and the other two data channels are sequentially detected. By respectively comparing the frequencies of the other two data channels with that of this one data channel, the detection of the other two data channels can be realized.

[0123] Based on the same inventive concept, as Figure 8 shown, the embodiment of the present application provides a source driver chip 1, including the receiving circuit 10 provided in any of the above embodiments.

[0124] The source driver chip 1 provided in the embodiment of the present application has the same inventive concept and the same beneficial effects as the previous embodiments. The content not shown in detail in the source driver chip 1 can be referred to the previous embodiments, and will not be elaborated here.

[0125] Based on the same inventive concept, as Figure 8 shown, the embodiment of the present application provides a display device, including a timing control chip 2 and the source driver chip 1 provided in any of the above embodiments;

[0126] The receiving circuit 10 is connected to the timing control chip 2 and is used to output a first lock signal or a third lock signal to the timing control chip 2.

[0127] The display device provided in the embodiment of the present application has the same inventive concept and the same beneficial effects as the previous embodiments. The content not shown in detail in the display device can be referred to the previous embodiments, and will not be elaborated here.

[0128] Specifically, as Figure 8 shown, the first lock signal LOCK0 or the third lock signal is used to be transmitted to the timing control chip 2. In the display device, in the point-to-point interface protocol between the timing control chip 2 and the source driver chip 1, the data transmission between the timing control chip 2 and the source driver chip 1 includes a training stage and a data stage.

[0129] Based on the same inventive concept, the embodiment of the present application provides a method for selecting a data channel by the receiving circuit provided in any of the above embodiments, as Figure 9 shown, the selection method includes:

[0130] S1: Output a frequency lock signal and a first lock signal based on the received first signal, and output a second lock signal based on the received second signal;

[0131] S2: Output a channel selection signal based on the first signal, the second signal, and the frequency lock signal;

[0132] S3: Output a first lock signal or a third lock signal based on the channel selection signal to select a data channel; wherein, the first lock signal is used to control the selection of the first data channel, and the third lock signal is generated from the first lock signal and the second lock signal and is used to control the selection of the first data channel and the second data channel.

[0133] The method for selecting a data channel provided by the embodiment of the present application has the same inventive concept and the same beneficial effects as the previous embodiments. For the content not shown in detail in the method for selecting a data channel of the receiving circuit, reference may be made to the previous embodiments and will not be elaborated herein.

[0134] Applying the embodiment of the present application can at least achieve the following beneficial effects:

[0135] The receiving circuit 10 provided by the embodiment of the present application passes through the detection circuit 13, which is respectively connected to the first analog front end 111, the second analog front end 121, and the first clock data recovery circuit 112, and is used to output a channel selection signal based on the received first signal DIN0, second signal DIN1, and frequency lock signal FLOCK0. Through the selection circuit 14, the first lock signal LOCK1 or the third lock signal is selected and output to automatically detect and control the data channel, without consuming additional chip pins, thereby reducing the number of chip pins and reducing the dependence on the timing control chip.

[0136] Those skilled in the art of the present technology can understand that the various operations, methods, steps, measures, and solutions in the processes discussed in the present application can be alternated, changed, combined, or deleted. Further, other steps, measures, and solutions in the various operations, methods, and processes discussed in the present application can also be alternated, changed, rearranged, decomposed, combined, or deleted. Further, those in the prior art having steps, measures, and solutions in the various operations, methods, and processes disclosed in the present application can also be alternated, changed, rearranged, decomposed, combined, or deleted.

[0137] In the description of the present application, it should be understood that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present application.

[0138] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of this application, unless otherwise specified, the meaning of "a plurality" is two or more.

[0139] In the description of this application, it should be noted that unless otherwise clearly specified and defined, the terms "mounted", "connected" and "coupled" should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral connection; it may be directly connected, or indirectly connected through an intermediate medium, and it may be the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0140] In the description of this specification, specific features, structures, materials or characteristics may be combined in any one or more embodiments or examples in a suitable manner.

[0141] It should be understood that although each step in the flowchart of the drawings is shown in sequence as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise clearly stated in this document, the execution of these steps is not strictly limited in order and they may be executed in other orders. Moreover, at least a part of the steps in the flowchart of the drawings may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same moment, but may be executed at different moments, and their execution order is not necessarily sequential, but may be executed alternately or in turn with at least a part of other steps or sub-steps or stages of other steps.

[0142] The above are only some embodiments of this application. It should be pointed out that for those of ordinary skill in the art, without departing from the principle of this application, several improvements and refinements can still be made, and these improvements and refinements should also be regarded as the protection scope of this application.

Claims

1. A receiving circuit, characterized in that, Including: A first receiving module, a second receiving module, a detection circuit, and a selection circuit; The first receiving module corresponds to a first data channel; The second receiving module corresponds to a second data channel; The first receiving module includes an electrically connected first analog front end and a first clock data recovery circuit; the first analog front end is used to output a first signal; The first clock data recovery circuit is used to output a frequency locked signal and a first locked signal based on the first signal; The second receiving module includes an electrically connected second analog front end and a second clock data recovery circuit; the second analog front end is used to output a second signal; The second clock data recovery circuit is used to output a second locked signal based on the second signal; The detection circuit, which is respectively connected to the first analog front end, the second analog front end, and the first clock data recovery circuit, is used to output a channel selection signal based on the received first signal, second signal, and frequency locked signal; The selection circuit, which is respectively connected to the first clock data recovery circuit, the second clock data recovery circuit, and the detection circuit, is used to generate a third locked signal from the received first locked signal and second locked signal, and output the first locked signal or the third locked signal based on the received channel selection signal.

2. The receiving circuit according to claim 1, wherein The selection circuit includes a first logic gate circuit and a selector; The first logic gate circuit, which is respectively connected to the first clock data recovery circuit and the second clock data recovery circuit, is used to output the third locked signal based on the first locked signal and the second locked signal; The selector, which is respectively connected to the first logic gate circuit, the first clock data recovery circuit, and the detection circuit, is used to selectively output the first locked signal or the third locked signal based on the channel selection signal; The detection circuit is further used to output the channel selection signal to the second analog front end and the second clock data recovery circuit to control the operating states of the second analog front end and the second clock data recovery circuit.

3. The receiving circuit according to claim 1, characterized in that, The detection circuit includes: A second logic gate circuit, connected to the first clock data recovery circuit, for outputting a third signal based on the frequency locked signal; A trigger circuit, respectively connected to the second logic gate circuit and a first signal terminal, for resetting based on the third signal and outputting a fourth signal; A first counting module, respectively connected to the first analog front end, the second logic gate circuit, and the trigger circuit, for resetting based on the third signal and outputting a fifth signal to the trigger circuit and a third logic gate circuit based on the first signal and the fourth signal; The third logic gate circuit, respectively connected to the trigger circuit and the first counting module, for outputting a sixth signal based on the fourth signal and the fifth signal; The second counting module is respectively connected to the second analog front end, the third logic gate circuit and the second logic gate circuit, and is configured to be reset based on the third signal, and output a seventh signal based on the second signal and the sixth signal; the seventh signal is used to obtain the channel selection signal through a look-up table.

4. The receiving circuit according to claim 3, characterized in that, The second logic gate circuit includes: an inverter group and a first NAND gate; The inverter group includes n inverters connected in sequence, where n is an odd number; The first input terminal of the first NAND gate is connected to one end of the inverter group and the first clock data recovery circuit, and is configured to receive the frequency lock signal; The second input terminal of the first NAND gate is connected to the other end of the inverter group; The output terminal of the first NAND gate is configured to output the third signal.

5. The receiving circuit according to claim 3, characterized in that The trigger circuit includes: a first flip-flop, a first inverter, a second flip-flop and a second inverter; The output terminal of the first counting module is connected to the clock terminal of the first flip-flop, the input terminal of the first flip-flop is connected to the first signal terminal, the reset terminal of the first flip-flop is connected to the second logic gate circuit, and the output terminal of the first flip-flop is connected to the input terminal of the second flip-flop; The output terminal of the first counting module is connected to the clock terminal of the second flip-flop via the first inverter, and the reset terminal of the second flip-flop is connected to the second logic gate circuit; The second flip-flop outputs the fourth signal via the second inverter.

6. The receiving circuit according to claim 3, wherein The third logic gate circuit includes: a second NAND gate and a third inverter; The first input terminal of the second NAND gate is connected to the trigger circuit and is configured to receive the fourth signal; The second input terminal of the second NAND gate is connected to the first counting module and is configured to receive the fifth signal; The output terminal of the second NAND gate outputs the sixth signal via the third inverter.

7. The receiving circuit according to claim 3, wherein The first counting module includes a first counter; the second counting module includes a second counter; The enable terminal of the first counter is connected to the trigger circuit and is configured to receive the fourth signal; The clock terminal of the first counter is connected to the first analog front end and is configured to receive the first signal; The reset terminal of the first counter is connected to the second logic gate circuit and is configured to receive the third signal; The output terminal of the first counter is respectively connected to the trigger circuit and the third logic gate circuit and is configured to output the fifth signal; The enable terminal of the second counter is connected to the third logic gate circuit and is configured to receive the sixth signal; The clock terminal of the second counter is connected to the second analog front end and is configured to receive the second signal; The reset terminal of the second counter is connected to the second logic gate circuit and is configured to receive the third signal; The output terminal of the second counter is configured to output the seventh signal.

8. The receiving circuit according to claim 2, wherein The first logic gate circuit includes: a second NAND gate and a fourth inverter; The first input terminal of the second NAND gate is connected to the first clock data recovery circuit and is configured to receive the first lock signal; The second input terminal of the second NAND gate is connected to the second clock data recovery circuit for receiving a second locking signal; The output terminal of the second NAND gate is connected to the fourth inverter for outputting a third locking signal.

9. A source driver chip, characterized in that, Comprising the receiving circuit according to any one of claims 1 to 8.

10. A display device, characterized in that, Comprising a timing control chip and the source driver chip according to claim 9; The receiving circuit is connected to the timing control chip for outputting the first locking signal or the third locking signal to the timing control chip.

11. A method for selecting a data channel using the receiving circuit according to any one of claims 1 to 8, characterized in that, Comprising: Outputting a frequency locking signal and a first locking signal based on the received first signal, and outputting a second locking signal based on the received second signal; Outputting a channel selection signal based on the first signal, the second signal and the frequency locking signal; Outputting the first locking signal or the third locking signal based on the channel selection signal to select a data channel; wherein, the first locking signal is used to control the selection of a first data channel, and the third locking signal is generated from the first locking signal and the second locking signal and is used to control the selection of the first data channel and a second data channel.

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