A partition backlight data processing method and device

Abstract

The present invention provides a partitioned backlight data processing method and apparatus, applicable to a backlight display device, wherein the backlight frame of the backlight display device has at least one backlight partition. The method comprises utilizing the backlight power of at least one backlight frame to reduce the partitioned backlight data value of at least one backlight partition in the at least one backlight frame, thereby obtaining adjusted partitioned backlight data; and utilizing the adjusted partitioned backlight data of two preceding and succeeding backlight frames to perform interpolation processing on the two backlight frames, thereby obtaining the interpolated partitioned backlight data. The present invention has the advantage of resolving the problem of significant backlight trailing caused by a low backlight frame rate displayed by the backlight display device, thereby improving the user's viewing experience.

Description

Technical Field

[0001] The present invention relates to the technical field of backlight display and the technical field, and in particular to a partitioned backlight data processing method and device. Background Art

[0002] Existing backlight display devices, such as Mini-LED, have poor technical versatility. Replacing a backlight display driver solution requires redeveloping a partitioned backlight display control system, which not only increases product development costs but also delays technology research and development progress.

[0003] Furthermore, existing backlight display devices lack measures to limit backlight power consumption, requiring a high-power backlight power supply to ensure device operation. Furthermore, the backlight frame rate of backlight display devices often matches or is slightly lower than the display frame rate, which can easily cause backlight streaking and affect the user's viewing experience. These issues have hindered the development and promotion of backlight display devices. Summary of the Invention

[0004] In order to solve the above technical problems, the present invention provides a partitioned backlight data processing method and device to solve the existing problems.

[0005] In one aspect of the present invention, a method for processing partitioned backlight data is provided, which is applied to a backlight display device, wherein a backlight frame of the backlight display device has at least one backlight partition. The method comprises:

[0006] Using the backlight power of at least one backlight frame, reducing the subarea backlight data value of at least one backlight subarea in the at least one backlight frame to obtain adjusted subarea backlight data;

[0007] Using the adjusted subarea backlight data of the two preceding and succeeding backlight frames, interpolation processing is performed on the two backlight frames to obtain subarea backlight data after the interpolation processing.

[0008] Another aspect of the present invention provides a partitioned backlight data processing device, which is applied to a backlight display device, wherein the backlight frame of the backlight display device has at least one backlight partition, and the device includes an adjustment module and a processing module:

[0009] The adjustment module is configured to reduce the partition backlight data value of at least one backlight partition in the at least one backlight frame by using the backlight power of the at least one backlight frame to obtain adjusted partition backlight data;

[0010] The processing module is used to use the adjusted subarea backlight data of the two previous and next backlight frames to perform interpolation processing on the two backlight frames to obtain the subarea backlight data after the interpolation processing.

[0011] Another aspect of the present invention provides an electronic device, comprising:

[0012] at least one processor;

[0013] a memory communicatively coupled to at least one of the processors;

[0014] and a computer program stored on the memory and executable on the processor, wherein the method is implemented when the processor executes the computer program.

[0015] Another aspect of the present invention provides a non-volatile computer-readable storage medium having a computer program stored thereon, wherein the computer program is configured to cause the computer to execute the method.

[0016] One or more technical solutions provided in the embodiments of the present invention have at least the following technical effects or advantages:

[0017] By adopting the technical solution of the present invention, the problem of obvious backlight tailing caused by the low backlight frame rate of the backlight display device can be solved, thereby improving the user's viewing experience. In addition, the technical solution of the present invention enhances the versatility of backlight display technology as a whole and reduces backlight display power consumption.

[0018] The above brief description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are described in detail below by way of example. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Further details, features and advantages of the invention are disclosed in the following description of exemplary embodiments with reference to the accompanying drawings, in which:

[0020] Figure 1 A flow chart of the partition backlight data processing method provided by the present invention is shown;

[0021] Figure 2 The structure diagram of the partitioned backlight data processing device provided by the present invention is shown;

[0022] Figure 3 Shows a flow chart of the partition backlight control in the present invention;

[0023] Figure 4 shows a schematic structural diagram of a backlight display device in the present invention;

[0024] Figure 5 It shows a structural diagram of the data processing module in the present invention. DETAILED DESCRIPTION

[0025] Embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although certain embodiments of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be construed as limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the present invention. It should be understood that the drawings and embodiments of the present invention are for illustrative purposes only and are not intended to limit the scope of protection of the present invention.

[0026] It should be understood that the various steps described in the method embodiments of the present invention may be performed in different orders and / or in parallel. In addition, the method embodiments may include additional steps and / or omit the steps shown. The scope of the present invention is not limited in this respect.

[0027] The term "including" and its variations used in this document are open inclusions, that is, "including but not limited to". The term "based on" means "based at least in part on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one other embodiment"; the term "some embodiments" means "at least some embodiments". The relevant definitions of other terms will be given in the following description. It should be noted that the concepts of "first", "second", etc. mentioned in the present invention are only used to distinguish different devices, modules or units, and are not used to limit the order or interdependence of the functions performed by these devices, modules or units.

[0028] The names of the messages or information exchanged between multiple devices in the embodiments of the present invention are only used for illustrative purposes and are not used to limit the scope of these messages or information.

[0029] Description of the existing technology

[0030] Before introducing the technical solution of the present invention, the prior art related to the present invention is described as follows:

[0031] LDM: Local dimming (local backlight adjustment);

[0032] LDM data: refers to the grayscale data within each backlight partition obtained by dividing the graphic data of the backlight image into multiple backlight partitions. It is generally 8 / 10 / 12 / 16 bits wide. The larger the bit width, the larger the backlight grayscale value, the finer the backlight adjustment, and the smoother the backlight image displayed;

[0033] SPI: Serial Peripheral Interface (Serial Peripheral Interface);

[0034] QSPI: Quad SPI (four-wire SPI bus);

[0035] LVDS: Low Voltage Differential Signaling;

[0036] eDP: eDisplayPort (built-in video interface);

[0037] A high-definition display protocol interface;

[0038] SOC: System on Chip;

[0039] FPGA: Field Programmable Gate Array (field programmable gate array);

[0040] TCON: Timing Controller (timing controller or timing control circuit);

[0041] DDR: Double Data Rate Synchronous Dynamic Random Access Memory.

[0042] Example 1

[0043] In this embodiment, a partitioned backlight data processing method is provided, which is applied to a backlight display device capable of playing pictures based on backlight frames, such as Figure 4 As shown, the backlight display device includes a SOC, an FPGA algorithm board, a TCON board, a backlight display glass panel, a backlight control and drive board, and a backlight array.

[0044] like Figure 1 As shown, the method includes:

[0045] Step S101: using the FPGA algorithm board to adjust the partition backlight data of at least one backlight partition;

[0046] Step S102: performing frame insertion processing on the adjusted partition backlight data in the FPGA algorithm board.

[0047] Step S101 further includes:

[0048] The FPGA algorithm board has an FPGA module and a high-bandwidth DDR4, and a bidirectional communication connection between the two. The FPGA module includes a high-speed transceiver, a data selection channel and a data processing module. Figure 5As shown, the data processing module includes a graphics processing module, a backlight power processing module, and a backlight frame rate multiplication module, which are bidirectionally connected to the high-bandwidth DDR4. The graphics processing module includes a dual-port RAM and a DDR read / write control-1 section, the backlight power processing module includes a dual-port RAM and a DDR read / write control-2 section, and the backlight frame rate multiplication module includes a dual-port RAM and a DDR read / write control-3 section.

[0049] The backlight power processing module is provided with an adjustment coefficient a, whose numerical range is set to 0 to 1, and whose step value is set to 0.1; and a power threshold is pre-set, the upper limit of which is the maximum power consumption of the backlight of the backlight display device, so that the sum of the power consumption of components such as the backlight array, TCON board, and display screen of the backlight display device and the power consumption of core boards such as the SOC and FPGA algorithm board is not greater than the rated power of the power supply of the backlight display device.

[0050] The backlight power processing module adjusts the partitioned backlight data of at least one backlight partition of the backlight frame using the adjustment coefficient a, including:

[0051] Obtaining a frame backlight power consumption value of the backlight frame based on a backlight power consumption value of one backlight partition or combining backlight power consumption values ​​of multiple backlight partitions;

[0052] At the beginning of the adjustment, the default value of the adjustment coefficient a is set to 1, and the weighted frame backlight power consumption value is obtained by multiplying the adjustment coefficient a by the frame backlight power consumption value;

[0053] If the weighted frame backlight power consumption value is higher than the power threshold, the adjustment coefficient a is gradually reduced according to a step value of one unit (equivalent to reducing the frame backlight power consumption value by 0.1 times) until the weighted frame backlight power consumption value obtained after the multiplication is no higher than the power threshold, and the value of the adjustment coefficient a at this time is determined;

[0054] The determined value of the adjustment coefficient a is multiplied by the value of the grayscale of each pixel in at least one backlight subarea to obtain adjusted subarea backlight data of the at least one backlight subarea.

[0055] Step S102 further includes:

[0056] The DDR read / write control-2 portion of the backlight power processing module outputs the adjusted partitioned backlight data of at least one backlight partition to the DDR read / write control-3 portion of the backlight frame rate multiplication module. The backlight frame rate multiplication module performs interpolation processing based on the adjusted partitioned backlight data of at least one backlight partition in two consecutive backlight frames at the same backlight partition position. The module then interpolates the two frames to obtain the interpolated partitioned backlight data. The backlight frame rate multiplication module then multiplies the frame rate of the backlight frames, caches the interpolated partitioned backlight data, and outputs the interpolated partitioned backlight data to the dual-port RAM of the backlight power processing module. The interpolated partitioned backlight data is cached by the DDR read / write control-3 portion of the backlight frame rate multiplication module in the high-bandwidth DDR4.

[0057] In an optional manner of this embodiment, as Figure 3 and Figure 4 As shown, the second dual-port RAM of the graphics processing module outputs the graphic data of the screen to the TCON board. After the TCON board processes the graphic data of the screen, the screen content is displayed on the glass panel. The dual-port RAM of the backlight frame rate multiplication module outputs the partitioned backlight data after the interpolation process to the backlight control and driver board. The backlight control and driver board receives the partitioned backlight data of each backlight partition, parses it, and distributes it to each drive channel. Each drive channel corresponds to a backlight partition, thereby realizing the partitioned control display of the backlight array. The number of lamp beads in a backlight partition is 1, 2, 4, 6, 9, 30, etc.

[0058] By controlling the timing of the graphic data of the picture and / or the partitioned backlight data, the partitioned control display of the picture content and / or the backlight array on the glass panel is adjusted.

[0059] In another optional embodiment of this embodiment, Figure 3 and Figure 4 As shown, the multiple high-speed transceivers in the FPGA module receive signals from the SOC via LVDS, eDP, The graphic data of the complete picture transmitted by the high-definition display protocol interface or the partition backlight data transmitted by the communication protocol such as SPI and QSPI is connected to the data selection channel.

[0060] The data selection channel selects the input mode according to the input data. If the input data is partition backlight data transmitted through SPI, QSPI and other communication protocols, it enters the partition backlight data input mode and sends the partition backlight data to the data processing module; if the input data is transmitted through LVDS, eDP, When the graphic data of the complete picture is transmitted by the high-definition display protocol interface, the graphics data input mode is entered, and the graphic data of the picture is sent to the data processing module.

[0061] When the input data is graphic data for the screen, the graphic data is sequentially input to the first dual-port RAM and DDR read / write control-1 portion of the graphics processing module, the graphic data is cached, and partitioned backlight data is generated. The graphic data is then output to the second dual-port RAM of the graphics processing module, and the partitioned backlight data is output from the DDR read / write control-1 portion of the graphics processing module to the DDR read / write control-2 portion of the backlight power processing module. The caching of the graphic data involves the DDR read / write control-1 portion of the graphics processing module caching the graphic data to the high-bandwidth DDR4; and the generation of the partitioned backlight data involves dividing the screen into at least one backlight partition based on a preset number of backlight partitions, and calculating the average grayscale value of each pixel within the at least one backlight partition.

[0062] When the input data is partitioned backlight data, the partitioned backlight data is sequentially input to the dual-port RAM and DDR read / write control-2 portion of the backlight power processing module and / or input from the DDR read / write control-1 portion of the graphics processing module, and the partitioned backlight data is cached. The DDR read / write control-2 portion of the backlight power processing module caches the partitioned backlight data to the high-bandwidth DDR4.

[0063] In this embodiment, since the FPGA module integrates a backlight power control algorithm, it can support a SOC that is not provided with a local backlight adjustment algorithm to implement multi-zone backlight control.

[0064] Based on the same inventive concept, the present invention also provides a device embodiment corresponding to the method of embodiment 1, see embodiment 2 for details.

[0065] Example 2

[0066] In this embodiment, a partitioned backlight data processing device is provided, which is applied to a backlight display device capable of playing pictures based on backlight frames, such as Figure 4As shown, the backlight display device includes a SOC, an FPGA algorithm board, a TCON board, a backlight display glass panel, a backlight control and drive board, and a backlight array.

[0067] like Figure 2 As shown, the device includes an adjustment module 201 and a processing module 202:

[0068] The adjustment module 201 is configured to adjust the partition backlight data of at least one backlight partition;

[0069] The processing module 202 is configured to perform frame insertion processing on the adjusted partition backlight data.

[0070] Among them, the adjustment module 201 is provided with an adjustment coefficient a, whose numerical range is set to 0 to 1, and whose step value is set to 0.1; and a power threshold is pre-set, and the upper limit of the power threshold is the maximum power consumption of the backlight of the backlight display device, so that the sum of the power consumption of the backlight array, TCON board, display screen and other components of the backlight display device and the power consumption of the core boards such as SOC and FPGA algorithm board is not greater than the rated power of the power supply of the backlight display device.

[0071] The adjusting module 201 adjusts the partitioned backlight data of at least one backlight partition of the backlight frame using the adjustment coefficient a, including:

[0072] Obtaining a frame backlight power consumption value of the backlight frame based on a backlight power consumption value of one backlight partition or combining backlight power consumption values ​​of multiple backlight partitions;

[0073] At the beginning of the adjustment, the default value of the adjustment coefficient a is set to 1, and the weighted frame backlight power consumption value is obtained by multiplying the adjustment coefficient a by the frame backlight power consumption value;

[0074] If the weighted frame backlight power consumption value is higher than the power threshold, the adjustment coefficient a is gradually reduced according to a step value of one unit (equivalent to reducing the frame backlight power consumption value by 0.1 times) until the weighted frame backlight power consumption value obtained after the multiplication is no higher than the power threshold, and the value of the adjustment coefficient a at this time is determined;

[0075] The determined value of the adjustment coefficient a is multiplied by the value of the grayscale of each pixel in at least one backlight subarea to obtain adjusted subarea backlight data of the at least one backlight subarea.

[0076] The processing module 202 performs interpolation processing based on the adjusted partitioned backlight data of at least one backlight partition. Based on the adjusted partitioned backlight data of at least one backlight partition in two consecutive backlight frames at the same backlight partition position, the processing module 202 calculates an average value of the adjusted partitioned backlight data, interpolates the two frames, and obtains the partitioned backlight data after the interpolation processing. The processing module 202 then multiplies the frame rate of the backlight frame, caches the partitioned backlight data after the interpolation processing, and outputs the partitioned backlight data after the interpolation processing.

[0077] In an optional manner of this embodiment, the device further includes a transmission module 203, which outputs the graphic data of the picture to display the picture content, and outputs the partitioned backlight data after the interpolation processing to realize the partitioned control display of the backlight array.

[0078] In another optional embodiment of the present invention, the device further includes a selection module 204, which enters a partition backlight data input mode if the input data is partition backlight data transmitted via a communication protocol such as SPI or QSPI, and sends the partition backlight data to the adjustment module 201; if the input data is partition backlight data transmitted via a communication protocol such as LVDS, eDP, When the graphic data of the complete screen is transmitted by the high-definition display protocol interface, the graphics data input mode is entered, and the graphic data of the screen is sent to the adjustment module 201.

[0079] When the input data is graphic data of the picture, the picture is divided into at least one backlight partition based on a preset number of backlight partitions, and the average grayscale of each pixel in the at least one backlight partition is calculated to generate the partition backlight data.

[0080] In this embodiment, since the FPGA module integrates a backlight power control algorithm, it can support a SOC that is not provided with a local backlight adjustment algorithm to implement multi-zone backlight control.

[0081] Since the device described in this embodiment is used to implement the method of Example 1 of the present invention, those skilled in the art will be able to understand the specific structure and variations of the device based on the method described in Example 1 of the present invention, and therefore will not be described in detail here. All devices used to implement the method of Example 1 of the present invention are within the scope of protection of the present invention.

[0082] Based on the same inventive concept, the present invention also provides an electronic device embodiment corresponding to the method of embodiment 1, see embodiment 3 for details.

[0083] Example 3

[0084] In this embodiment, an electronic device is provided, comprising:

[0085] at least one processor;

[0086] a memory communicatively coupled to at least one of the processors;

[0087] And a computer program stored in the memory and executable on the processor, wherein the processor implements the method of the first embodiment of the present invention when executing the computer program.

[0088] Since the electronic device described in this embodiment is a device used to implement the method of Example 1 of the present invention, those skilled in the art will be able to understand the specific implementation and various variations of the electronic device based on the method described in Example 1 of the present invention. Therefore, how the electronic device implements the method of Example 1 of the present invention will not be described in detail here. As long as a device used by those skilled in the art to implement the method of Example 1 of the present invention falls within the scope of protection of the present invention.

[0089] Based on the same inventive concept, the present invention also provides a non-volatile computer-readable storage medium embodiment corresponding to the method of embodiment one, see embodiment four for details.

[0090] Example 4

[0091] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, apparatuses, or computer program products. The present invention may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware. Therefore, as described below, the present invention may take the form of a computer program product implemented on one or more computer-readable storage media (including but not limited to optical storage, magnetic storage, and non-volatile semiconductor storage) containing computer-usable program code.

[0092] In this embodiment, a non-volatile computer-readable storage medium is provided. The non-volatile computer-readable storage medium stores a computer program. The computer program is used to enable the computer to execute the method of the first embodiment of the present invention.

[0093] Although the specific embodiments of the present invention are described above, those skilled in the art should understand that the specific embodiments described in the present invention are only illustrative and are not intended to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be included in the scope of protection of the claims of the present invention.

Claims

1. A partitioned backlight data processing method, applied to a backlight display device, wherein the backlight frame of the backlight display device has at least one backlight partition, characterized in that: The method comprises: Using the backlight power of at least one backlight frame, reducing the subarea backlight data value of at least one backlight subarea in the at least one backlight frame to obtain adjusted subarea backlight data; Using the adjusted subarea backlight data of the two preceding and succeeding backlight frames, interpolation processing is performed on the two backlight frames to obtain subarea backlight data after the interpolation processing; The step of reducing the partition backlight data value of at least one backlight partition in the at least one backlight frame further comprises: determining a coefficient so that the backlight power of the at least one backlight frame weighted by the coefficient is not higher than a predetermined power threshold; The partitioned backlight data of the at least one backlight frame is weighted and adjusted using the determined coefficients.

2. The method according to claim 1, wherein determining a coefficient further comprises: The coefficient is gradually reduced according to a set step value until the backlight power of the at least one backlight frame weighted by the coefficient is not higher than the predetermined power threshold, and the reduced coefficient value is determined.

3. The method according to claim 1, wherein the interpolating the two backlight frames further comprises: Interpolation processing is performed on the two backlight frames in the same backlight subarea according to the adjusted subarea backlight data values ​​of the two backlight frames.

4. The method according to claim 3, wherein the interpolating the two backlight frames further comprises: A backlight frame is inserted between the two backlight frames according to an average value of the adjusted partition backlight data of the two backlight frames in the same backlight partition.

5. The method according to claim 1 , further comprising: before reducing the subarea backlight data value of at least one backlight subarea in the at least one backlight frame by using the backlight power of the at least one backlight frame; In the case that the subarea backlight data of the at least one backlight frame is not received, the subarea backlight data of the at least one backlight frame is obtained by calculation.

6. A partitioned backlight data processing device, applied to a backlight display device, wherein the backlight frame of the backlight display device has at least one backlight partition, characterized in that: The device includes an adjustment module and a processing module; The adjustment module is configured to reduce the partition backlight data value of at least one backlight partition in the at least one backlight frame by using the backlight power of the at least one backlight frame to obtain adjusted partition backlight data; The processing module is configured to perform interpolation processing on the two backlight frames using the adjusted subarea backlight data of the two backlight frames to obtain the subarea backlight data after the interpolation processing; The step of reducing the partition backlight data value of at least one backlight partition in the at least one backlight frame further comprises: determining a coefficient so that the backlight power of the at least one backlight frame weighted by the coefficient is not higher than a predetermined power threshold; The determined coefficients are used to weight and adjust the partitioned backlight data of the at least one backlight frame. 7 . The apparatus according to claim 6 , further comprising a selection module configured to calculate and obtain the subarea backlight data of the frame when the subarea backlight data of the at least one backlight frame is not received.

8. An electronic device comprising: at least one processor; a memory communicatively coupled to at least one of the processors; as well as A computer program stored in the memory and executable on the processor, wherein the processor implements the method according to any one of claims 1 to 5 when executing the computer program.

9. A non-volatile computer-readable storage medium having a computer program stored thereon, characterized in that: The computer program is used to cause the computer to execute the method according to any one of claims 1 to 5.

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