A HDLC-TRDP real-time conversion gateway

Abstract

The present application provides a HDLC-TRDP real-time conversion gateway, including: an FPGA module, receiving and parsing pre-processed HDLC protocol type messages and / or TRDP protocol type messages, and performing protocol type conversion on the parsing results according to preset environment configuration information to complete the gateway exchange of messages; wherein, the protocol type conversion is implemented by an on-chip paging mapping method; a power conversion module, converting the original input voltage output by the DC power supply on the rail vehicle into a module power supply voltage, and transmitting the module power supply voltage to the FPGA module. The present application can realize the conversion and reception between HDLC protocol type messages and TRDP protocol type messages, thereby completing the gateway exchange of messages.

Description

Technical Field

[0001] The present application relates to the field of rail transit vehicle network control, and specifically to a HDLC-TRDP real-time conversion gateway. Background Art

[0002] In the early days of train monitoring and control networks, due to the lack of a unified standard, some network systems in rail transit trains used a bus with HDLC as the link layer and RS485 as the physical layer. With the promotion and application of the IEC61375 international standard for train communication networks, TCN buses and Ethernet buses have been widely adopted.

[0003] However, there are still a large number of network systems using HDLC+RS485 bus on existing old trains. With the continuous upgrading and development of technology, many existing old trains have begun to be upgraded and renovated. In the upgrade and renovation, in order to reduce the renovation cost, it is often necessary to retain the communication interface form of some subsystems, such as signal systems, doors, air conditioners, etc. At present, the latest communication technology is Ethernet communication, which can meet the development requirements of high bandwidth and intelligence, and has become the first choice for the renovation of old vehicles. Therefore, in the renovation of old trains, the subsystems that retain the original communication interface need to have a conversion gateway from HDLC protocol to Ethernet to realize the interaction between subsystem data and Ethernet network.

[0004] In current engineering applications, a common solution is to implement protocol conversion through the existing HDLC protocol controller and the TRDP protocol stack running on the CPU. This design is relatively simple in technical implementation, but has the following shortcomings:

[0005] (1) In terms of hardware design, multiple chips are required for construction, which makes the hardware structure more complex and increases the risk of failure.

[0006] (2) Since the HDLC protocol data and TRDP protocol data are ultimately converted through software, the delay caused by data forwarding is relatively large, affecting the train control accuracy. Summary of the invention

[0007] In response to the problems in the prior art, the present application provides a HDLC-TRDP real-time conversion gateway that can realize the conversion and reception between HDLC protocol type messages and TRDP protocol type messages, thereby completing the gateway exchange of messages.

[0008] In order to solve the above technical problems, this application provides the following technical solutions:

[0009] In a first aspect, the present application provides a HDLC-TRDP real-time conversion gateway, comprising:

[0010] The FPGA module receives and parses the pre-processed HDLC protocol type message and / or TRDP protocol type message, and performs protocol type conversion on the parsing result according to the preset environment configuration information to complete the gateway exchange of the message; wherein the protocol type conversion is implemented by an on-chip paging mapping method;

[0011] The power conversion module converts the original input voltage output by the DC power supply on the rail vehicle into a module power supply voltage, and connects the module power supply voltage to the FPGA module.

[0012] Furthermore, the HDLC-TRDP real-time conversion gateway also includes an RS485 interface circuit for pre-processing the received HDLC protocol type message and sending it to the FPGA module.

[0013] Furthermore, the HDLC-TRDP real-time conversion gateway also includes an Ethernet interface circuit for pre-processing the received TRDP protocol type message and sending it to the FPGA module.

[0014] Furthermore, the HDLC-TRDP real-time conversion gateway also includes a CPU module for receiving the environmental configuration information from the central control unit of the rail vehicle and loading the environmental configuration information into the FPGA module.

[0015] Furthermore, the FPGA module includes an HDLC protocol control module, a TRDP transceiver control module, a data exchange management module and a dual-port RAM storage area;

[0016] Wherein, the HDLC protocol control module is used to receive and parse the HDLC protocol type message from the RS485 interface circuit, and send the corresponding HDLC protocol type data to the data exchange management module after obtaining it, or receive and process the HDLC protocol type data from the data exchange management module and send it to the RS485 interface circuit after processing it;

[0017] The TRDP transceiver control module is used to receive the TRDP protocol type message from the Ethernet interface circuit and parse it, and send it to the data exchange management module after obtaining the corresponding TRDP protocol type data, or receive and process the TRDP protocol type data from the data exchange management module and send it to the Ethernet interface circuit;

[0018] The data exchange management module is used to receive the HDLC protocol type data from the HDLC protocol control module and / or receive the TRDP protocol type data from the TRDP transceiver control module, and perform protocol conversion processing on the HDLC protocol type data and / or the TRDP protocol type data in a paging mapping manner according to the environmental configuration information, and forward the data after the protocol conversion processing to the corresponding interface circuit via the corresponding transceiver control module;

[0019] The dual-port RAM storage area is used to temporarily store the HDLC protocol type data and / or the TRDP protocol type data in a page mapping manner according to the environmental configuration information.

[0020] Further, the HDLC protocol control module includes a Manchester codec, a receiving buffer, a sending buffer, a transmitter, a receiver, a verification module and a main control module;

[0021] Wherein, the Manchester codec receives and decodes the HDLC protocol type message from the RS485 interface circuit or encodes the HDLC protocol type data returned by the main control module;

[0022] The receiver sends the HDLC protocol type message decoded by the Manchester codec to the main control module;

[0023] The transmitter sends the HDLC protocol type data returned by the main control module to the Manchester codec;

[0024] The receiving buffer is connected to the receiver and temporarily stores the decoded HDLC protocol type message;

[0025] The sending buffer is connected to the transmitter to temporarily store the returned HDLC protocol type data;

[0026] The verification module is connected to the transmitter and the receiver respectively, and is used to verify the decoded HDLC protocol type message and / or the returned HDLC protocol type data;

[0027] The main control module uses a state machine to control the Manchester codec, receiving buffer, sending buffer, transmitter, receiver and verification module actions respectively.

[0028] Furthermore, the TRDP transceiver control module includes a MAC layer control module, an IP layer control module, a UDP layer control module and a TRDP message processing module;

[0029] Wherein, the MAC layer control module converts the data processed by the IP layer control module and sends it to the Ethernet interface circuit or receives and parses the TRDP protocol type message from the Ethernet interface circuit;

[0030] The IP layer control module receives the processing result of the UDP layer control module and then performs IP packetization or receives and analyzes the processing result of the MAC layer control module;

[0031] The UDP layer control module is used to perform UDP packetization or receive and parse the processing result of the IP layer control module after receiving the processing result of the TRDP message processing module;

[0032] The TRDP message processing module is used to receive the TRDP protocol type data sent by the data exchange management module and then perform TRDP packaging or receive and parse the processing result of the UDP layer control module.

[0033] Furthermore, the data exchange management module includes a configuration register, an addressing management module and a data access module;

[0034] Wherein, the addressing management module communicates with the configuration register, and addresses the HDLC protocol type message and / or the TRDP protocol type message according to the environment configuration information stored in the configuration register;

[0035] The data access module is connected to the addressing management module and the dual-port RAM storage area respectively, and is used to complete the access operation of the HDLC protocol type message and / or TRDP protocol type message in the dual-port RAM storage area according to the addressing result.

[0036] Further, the dual-port RAM storage area includes a first HDLC storage area, a second HDLC storage area, a first TRDP storage area, and a second TRDP storage area;

[0037] Wherein, the first HDLC storage area and the second HDLC storage area are used to store the HDLC protocol type message in a HDLC mapping message format according to the environment configuration information in a rolling alternating manner;

[0038] The first TRDP storage area and the second TRDP storage area are used to store the TRDP protocol type message in a TRDP mapping message format in accordance with the environmental configuration information in a rolling alternating manner.

[0039] Furthermore, the power conversion module comprises:

[0040] A power supply short-circuit protection circuit is connected to the original input voltage and performs short-circuit protection processing on the original input voltage;

[0041] A power reverse protection circuit, connected to the power short circuit protection circuit, to perform reverse protection on the voltage output by the power short circuit protection circuit;

[0042] A power surge protection circuit, connected to the power reverse protection circuit, and performing surge protection processing on the voltage output by the power reverse protection circuit;

[0043] A power pulse protection circuit, connected to the power surge protection circuit, performs pulse protection processing on the voltage output by the power reverse protection circuit;

[0044] A power supply filter circuit, connected to the power supply pulse protection circuit, and filtering the voltage output by the power supply pulse protection circuit;

[0045] A voltage conversion circuit, connected to the power filter circuit, performs voltage reduction processing on the filtered voltage;

[0046] A low voltage drop linear regulator is connected to the voltage conversion circuit and performs linear voltage regulation on the voltage after the voltage reduction process to obtain the module supply voltage.

[0047] In response to the problems in the prior art, the HDLC-TRDP real-time conversion gateway provided in the present application can integrate the gateway function into the same chip based on the field programmable gate array (FPGA) technology, realize the conversion and reception between HDLC protocol type messages and TRDP protocol type messages, complete the gateway exchange of messages, simplify the hardware design, reduce the production cost, and improve the product reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0049] Figure 1 The structural diagram of the HDLC-TRDP real-time conversion gateway in the embodiment of the present application;

[0050] Figure 2 A structural diagram of the FPGA module in the embodiment of the present application;

[0051] Figure 3 A structural diagram of the HDLC protocol control module in an embodiment of the present application;

[0052] Figure 4 A structural diagram of the TRDP transceiver control module in an embodiment of the present application;

[0053] Figure 5 A structural diagram of a data exchange management module in an embodiment of the present application;

[0054] Figure 6 One of the structural diagrams of the dual-port RAM storage area in the embodiment of the present application;

[0055] Figure 7 The second structural diagram of the dual-port RAM storage area in the embodiment of the present application;

[0056] Figure 8 Schematic diagram of HDLC-TRDP real-time conversion gateway application and configuration update in the embodiment of the present application;

[0057] Fig. 9 Schematic diagram of HDLC-TRDP real-time conversion gateway application and configuration update in an embodiment of the present application. DETAILED DESCRIPTION

[0058] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0059] In one embodiment, see Figure 1 In order to realize the conversion and reception between HDLC protocol type messages and TRDP protocol type messages, thereby completing the gateway exchange of messages, the present application provides a HDLC-TRDP real-time conversion gateway, including: an FPGA module and a power conversion module.

[0060] The FPGA module receives and parses the pre-processed HDLC protocol type message and / or TRDP protocol type message, and performs protocol type conversion on the parsing result according to the preset environment configuration information to complete the gateway exchange of the message; wherein the protocol type conversion is implemented by an on-chip paging mapping method;

[0061] The power conversion module converts the original input voltage output by the DC power supply on the rail vehicle into a module power supply voltage, and connects the module power supply voltage to the FPGA module.

[0062] It is understandable that the present application embodiment is applied to the train communication network. In the development process of the train communication network, since a unified communication standard was not formed in the early stage, there are various forms of communication technology. With the continuous promotion and development of standards, TCN bus and Ethernet bus have become the current mainstream. Therefore, the existing old projects using other buses are facing upgrading and transformation, such as HDLC bus, which has been facing elimination, and the existing systems are all transformed into new network interface forms, and there are difficulties in the technical difficulty of old equipment transformation and high cost. Therefore, the use of HDLC-TRDP real-time conversion gateway can realize non-transformation system access Ethernet, and the transformation scheme is simple, low cost, and meets the real-time requirements of the control network.

[0063] The HDLC-TRDP real-time conversion gateway is mainly composed of five parts: RS485 interface circuit, FPGA module, CPU processing module, Ethernet interface circuit, and power conversion circuit. The gateway has redundant TRDP Ethernet ports and 485 interfaces, and can update and maintain application software and configuration files through the Ethernet port. The gateway adopts a miniaturized and modular design and is powered by DC110V, which is easy to install.

[0064] The HDLC-TRDP real-time conversion gateway provided in this application can complete the communication conversion between HDLC protocol data and TRDP protocol data, and realize real-time data interaction between the two protocol interface devices.

[0065] The working principle of HDLC-TRDP real-time conversion gateway is:HDLC protocol control function is realized by FPGA, data interaction with HDLC protocol interface device is realized, and the interactive data is distributed in the dual-port RAM storage area built inside FPGA by address;TRDP protocol type message transceiver is realized by FPGA, data interaction with Ethernet network equipment is realized, and the interactive data is distributed in the dual-port RAM storage area built inside FPGA by address;The mapping addressing relationship of HDLC protocol type message and TRDP protocol type message is constructed by FPGA, after mapping relationship configuration (also referred to as environment configuration information) is read by CPU module, FPGA reads the TRDP data packet mapped by the HDLC protocol type message that needs to be forwarded to Ethernet by corresponding mapping addressing relationship, and is sent to Ethernet network on time;Similarly, FPGA reads the HDLC data packet mapped by the TRDP protocol type message that needs to be forwarded to HDLC bus, and is sent to HDLC bus on time.Thus, gateway exchange (data conversion) function described in the application is realized.

[0066] Specifically, the HDLC-TRDP real-time conversion gateway in the embodiment of the present application includes five modules: RS485 interface circuit, Ethernet interface circuit, FPGA module, CPU module and power conversion module.

[0067] Among them, the RS485 interface circuit is used to realize the receiving and sending functions of the physical layer of the HDLC communication of the equipment. The RS485 interface circuit includes the RS485 standard interface subcircuit, RS485 protection filter circuit, RS485 bus isolation power supply and RS485 transceiver circuit, etc. The HDLC protocol control physical layer is realized by the RS485 bus circuit, including the standard connector, the necessary filtering protection circuit and the bus signal isolation and differential conversion function circuit.

[0068] FPGA module is the core part of this application, which includes HDLC protocol control module, TRDP transceiver control module, dual-port RAM storage area and data exchange management module. HDLC protocol control module mainly realizes the transmission, analysis and link layer message control of HDLC data. TRDP transceiver control module mainly realizes the reception and transmission of TRDP message. Dual-port RAM storage area is mainly used to store HDLC data and TRDP data. Data exchange management module is used to store the received HDLC data and TRDP data in the specified area according to the corresponding addressing mapping relationship, and the received HDLC data is mapped to the TRDP protocol type message according to the specified addressing mapping relationship, and is transferred to the TRDP transceiver control module for transmission, and the received TRDP protocol type message is also mapped to the HDLC protocol type message according to the specified addressing mapping relationship, and is transferred to the HDLC protocol control module for transmission.

[0069] The main function of the CPU module is to receive and parse the corresponding environmental configuration information, which includes: the addressing mapping relationship between HDLC data packets and TRDP data packets, the source address, destination address, message length and other configuration information of HDLC data packets, the addressing configuration of HDLC data packets in the storage area, the IP address, multicast address, ComID and addressing configuration of TRDP data packets in the storage area, etc.

[0070] The Ethernet interface circuit realizes the functions of the 3-way Ethernet interface communication physical layer, of which 2-way realizes the external real-time TRDP Ethernet communication function, and the other 1-way realizes the Ethernet debugging, log download and system maintenance functions inside the device. The Ethernet interface circuit is composed of a PHY chip, a network transformer and necessary protection and filtering circuits.

[0071] The power conversion module provides power input for the other modules mentioned above. The core of the power conversion circuit is the DC / DC power conversion module; the power conversion module realizes the conversion of DC 110V to 5V voltage and ensures that the output voltage and current are stable and not affected by the external 110V power supply.

[0072] The workflow of the HDLC-TRDP real-time conversion gateway provided by this application is as follows:

[0073] (1) During the initialization configuration process, the CPU module reads the corresponding environment configuration information from the environment configuration file and carries out the initialization configuration, that is, loading the environment configuration information into the FPGA module. Parse the corresponding environment configuration information sent by HDLC and write it into the corresponding configuration register, including source address, destination address, frame length, etc.; parse the corresponding configuration information sent by TRDP and write it into the corresponding configuration register, including IP address, multicast address, ComID, etc.; the mapping relationship between TRDP protocol type messages and HDLC protocol type messages; TRDP data storage addressing method and HDLC data storage addressing method. After initialization is completed, the HDLC-TRDP real-time conversion gateway can realize data interaction with the HDLC bus and Ethernet network respectively, and can also realize real-time conversion of HDLC messages and TRDP messages.

[0074] (2) During normal operation, the HDLC protocol control module obtains environmental configuration information; in the HDLC protocol, the device that dominates the transmission and reception process is the master node. When this node is the HDLC master node, it sends an HDLC request message according to the source address and receives the corresponding HDLC response message according to the destination address; in the HDLC protocol, the node that is requested by the master node to send response data during the transmission and reception process is the slave node. When this node is the HDLC slave node, it receives the corresponding HDLC request message and sends the HDLC response message.

[0075] (3) During normal operation, the TRDP transceiver control module obtains Ethernet data packets through the Ethernet interface circuit. The TRDP transceiver control module determines whether the received data packet IP, address, length and other information meet the receiving requirements through the environment configuration information, and transmits the received data packet that meets the requirements to the data exchange management module, which stores it. The TRDP transceiver control module periodically sends TRDP data to the Ethernet network through the environment configuration information. The TRDP data is read from the specified area by the data exchange management module and packaged for transmission. During the transmission process, the TRDP transceiver control module fills in the source IP, destination IP, multicast address, frame length and other information of the data packet to be sent.

[0076] (4) During normal operation, the data exchange management module stores the received HDLC protocol type message and TRDP protocol type message in the designated area of ​​the dual-port RAM storage area by reading the addressing offset in the environmental configuration information; the data exchange management module reads the addressing offset in the environmental configuration information, and reads the data to be sent to the HDLC bus or TRDP network from the dual-port RAM storage area, and sends it to the HDLC and TRDP sending buffers to be sent to the corresponding network. Generally, the sending of data is performed periodically according to the settings in the environmental configuration information.

[0077] (5) During normal operation, the dual-port RAM storage area is divided into an HDLC storage area and a TRDP storage area, and each storage area has two different pages (the first HDLC storage area and the second HDLC storage area, the first TRDP storage area and the second TRDP storage area); when the HDLC protocol type message needs to be stored in the first page of the designated area during the receiving process, the data that needs to be forwarded to the TRDP network at the same time is read from the second page, and the paging is managed by the data exchange management module. Similarly, when the TRDP protocol type message needs to be stored in the first page of the designated area during the receiving process, the data that needs to be forwarded to the HDLC bus at the same time is read from the second page, thereby realizing rolling alternation, read-write separation, and ensuring data consistency; the paging is managed by the data exchange management module.

[0078] (6) During the software maintenance phase, the application program and environment configuration file can be downloaded to the CPU module through the service port.

[0079] The difference between the HDLC-TRDP real-time conversion gateway provided by the present application and the prior art is at least that: in the design of the conversion gateway from HDLC to other buses, it can be seen that most of the implementations are based on the mode of protocol controller+CPU processor, and most of the processing work needs to be implemented by the software in the CPU processor. Using the HDLC-TRDP real-time conversion gateway provided by the present application, the forwarding function of the gateway can be realized by FPGA, and the main work of the CPU processor is only to perform the initialization configuration of the environment in the initial stage. Specifically, first, the embodiment of the present application carries out the design of the gateway function with FPGA as the core, and the HDLC dedicated protocol control chip can no longer be used; second, the embodiment of the present application realizes the transceiver function of the TRDP data packet by FPGA, without using the TRDP protocol stack transfer piece; third, the core function of the embodiment of the present application is mainly realized by FPGA, and a more efficient and real-time conversion function can be realized. The HDLC-TRDP real-time conversion gateway provided by the present application has been designed more optimally for the application characteristics of the gateway exchange of HDLC data and TRDP data.

[0080] In one embodiment, see Figure 1 The HDLC-TRDP real-time conversion gateway also includes an RS485 interface circuit for pre-processing the received HDLC protocol type message and sending it to the FPGA module.

[0081] It is understandable that the HDLC-TRDP real-time conversion gateway requires an HDLC physical layer interface circuit, which is generally implemented using an RS485 transceiver circuit that can implement RS485 differential signal transceiver.

[0082] The RS485 (standard) interface circuit is implemented using a standard D-Sub9 connector and is equipped with bus terminal matching resistors and bus power pull-up and pull-down resistors. The RS485 protection filter circuit consists of an industrial mode interference filter and a high-performance TVS protection diode to filter bus interference and reduce the impact of large pulse shocks. The RS485 isolated power supply and RS485 transceiver both use a transformer coil electrical isolation solution to achieve electrical isolation between the RS4854 transceiver and the external bus. The bus power supply is isolated from the device board power supply. The RS485 transceiver is implemented using a communication rate control and low bit error rate mode solution, and the RS485 transceiver implements the bus differential signal conversion function.

[0083] In one embodiment, see Figure 1 The HDLC-TRDP real-time conversion gateway also includes an Ethernet interface circuit for pre-processing the received TRDP protocol type message and sending it to the FPGA module.

[0084] It is understandable that the HDLC-TRDP real-time conversion gateway needs a TRDP physical layer interface circuit, which is implemented using an Ethernet PHY chip. Since the TRDP network generally uses redundant channels, this interface circuit is also set redundantly.

[0085] The Ethernet interface circuit realizes the functions of the physical layer of two-way Ethernet interface communication, and conducts real-time TRDP Ethernet communication with the outside. At the same time, each channel realizes the Ethernet debugging, log download and system maintenance functions inside the device. The core of the Ethernet interface circuit is a high-performance 802.3 standard Gigabit physical layer PHY chip. The physical layer PHY chip is connected to the FPGA module MII interface. The PHY chip has link detection, rate detection, communication status output, communication independent clock, and communication self-negotiation functions. The Ethernet interface circuit adopts a network transformer, an industrial-grade M12 metal shielded connector and a low EMI circuit design.

[0086] In one embodiment, see Figure 1The HDLC-TRDP real-time conversion gateway also includes a CPU module for receiving the environmental configuration information from the central control unit of the rail vehicle and loading the environmental configuration information into the FPGA module.

[0087] It is understandable that the CPU module mainly implements the conversion gateway initialization software configuration (environmental configuration information) function. During the initialization process, the CPU module reads the environmental configuration file and parses the following information from the environmental configuration file: HDLC configuration information, TRDP configuration information, addressing mapping relationship between HDLC packets and TRDP packets, and addressing offset, etc.

[0088] Write HDLC configuration information, such as source address, destination address, data packet length, sending cycle, etc., into the corresponding registers in the FPGA module; write TRDP configuration information, such as source IP, multicast IP, ComID, data packet length, sending cycle, etc., into the corresponding registers in the FPGA module; write the addressing mapping relationship between HDLC data packets and TRDP data packets (i.e. which TRDP data packet corresponds to the data packet forwarded to HDLC and which HDLC data packets correspond to the data packet forwarded to TRDP) into the registers in the FPGA module so that the FPGA module knows the correspondence between the forwarded data packet and the forwarded data packet; write the addressing offset into the registers in the FPGA module so that the FPGA module knows the address corresponding to the data access.

[0089] It should be noted that the FPGA module and the CPU module can be implemented by different chip combinations or by the same SOC system-on-chip, thereby making the design more concise and compact. Since the implementation function of the CPU module is relatively simple, it can also be implemented by using an FPGA chip and generating a CPU soft core in the FPGA. This application is not limited to this.

[0090] In one embodiment, see Figure 2 , the HDLC-TRDP real-time conversion gateway, the FPGA module includes an HDLC protocol control module, a TRDP transceiver control module, a data exchange management module and a dual-port RAM storage area;

[0091] Wherein, the HDLC protocol control module is used to receive and parse the HDLC protocol type message from the RS485 interface circuit, and send the corresponding HDLC protocol type data to the data exchange management module after obtaining it, or receive and process the HDLC protocol type data from the data exchange management module and send it to the RS485 interface circuit after processing it;

[0092] The TRDP transceiver control module is used to receive the TRDP protocol type message from the Ethernet interface circuit and parse it, and send it to the data exchange management module after obtaining the corresponding TRDP protocol type data, or receive and process the TRDP protocol type data from the data exchange management module and send it to the Ethernet interface circuit;

[0093] The data exchange management module is used to receive the HDLC protocol type data from the HDLC protocol control module and / or receive the TRDP protocol type data from the TRDP transceiver control module, and perform protocol conversion processing on the HDLC protocol type data and / or the TRDP protocol type data in a paging mapping manner according to the environmental configuration information, and forward the data after the protocol conversion processing to the corresponding interface circuit via the corresponding transceiver control module;

[0094] The dual-port RAM storage area is used to temporarily store the HDLC protocol type data and / or the TRDP protocol type data in a page mapping manner according to the environmental configuration information.

[0095] It is understandable that the core part of the HDLC-TRDP real-time conversion gateway is the FPGA module, which implements the function of the conversion gateway. In the FPGA module, the HDLC protocol control function is implemented to realize the transmission and reception of HDLC protocol data. Using FPGA to implement this function can reduce the use of protocol controller chips, reduce the overall hardware quantity, and improve the design integration.

[0096] In the FPGA module, the TRDP data receiving and sending function is implemented, and the data link layer data parsing is realized through the MAC layer control module. After the IP layer control module, UDP control module, and TRDP message processing module, the verification or filling of the data messages of each layer is realized. The IP, ComID, multicast address, message length, etc. of the TRDP data are verified or filled, and the periodic sending of data is controlled by the timing module.

[0097] In the FPGA module, the storage and reading management of HDLC data and TRDP data is realized through the data exchange management module. The data exchange management module calculates the corresponding addresses for receiving and reading HDLC data and TRDP data through the addressing management module through the configuration register information given by the initialization, and performs data access management through the corresponding addresses.

[0098] In the FPGA module, a dual-port RAM storage area is implemented to define a receiving storage area for HDLC data and TRDP data, and through a paging mechanism, different page storage areas are used to read, send and receive storage respectively.

[0099] The most critical aspect of the HDLC-TRDP real-time conversion gateway is the design of data conversion. The embodiment of the present application designs a dual-port RAM storage area in the FPGA to store the data received on the HDLC side and the data received on the TRDP side respectively. Since the main purpose of the gateway device is to realize data forwarding, the data received on the HDLC side needs to be forwarded to the TRDP side; similarly, the data received on the TRDP side needs to be forwarded to the HDLC side. Therefore, a corresponding storage area is planned for the data received on each side, and the storage area is mapped to the "shadow storage area" on the other side. See Figure 7 As shown, for the TRDP protocol type messages stored on the TRDP side, they are arranged according to the addressing mapping relationship, divided into corresponding HDLC protocol type messages, and the corresponding information is written into the configuration register as the environment configuration information. Similarly, for the HDLC protocol type messages stored on the HDLC side, they are also arranged according to the addressing mapping relationship, and can be combined into corresponding TRDP protocol type messages, and the corresponding information is written into the configuration register as the configuration information. For the conversion gateway, the reasonable planning of the storage area simplifies the data processing process and improves the conversion efficiency.

[0100] In one embodiment, see Figure 3 , the HDLC protocol control module includes a Manchester codec, a receiving buffer, a sending buffer, a transmitter, a receiver, a verification module and a main control module;

[0101] Wherein, the Manchester codec receives and decodes the HDLC protocol type message from the RS485 interface circuit or encodes the HDLC protocol type data returned by the main control module;

[0102] The receiver sends the HDLC protocol type message decoded by the Manchester codec to the main control module;

[0103] The transmitter sends the HDLC protocol type data returned by the main control module to the Manchester codec;

[0104] The receiving buffer is connected to the receiver and temporarily stores the decoded HDLC protocol type message;

[0105] The sending buffer is connected to the transmitter to temporarily store the returned HDLC protocol type data;

[0106] The verification module is connected to the transmitter and the receiver respectively, and is used to verify the decoded HDLC protocol type message and / or the returned HDLC protocol type data;

[0107] The main control module uses a state machine to control the Manchester codec, receiving buffer, sending buffer, transmitter, receiver and verification module actions respectively.

[0108] In specific implementation, the data processing process is divided into two directions:

[0109] ① During the data reception process, the physical waveform of the data frame is decoded by the Manchester codec, converted into a binary bit stream, converted into message data by the receiver, and CRC check is performed by the check module. After the check, the main control module determines whether the received frame is the data to be received, and puts the data to be received into the receiving buffer.

[0110] ② During the data transmission process, the main control module obtains the data to be sent, then writes the data to be sent into the transmission buffer, gives a transmission start signal, starts the transmitter, converts the data in the transmission buffer into a binary bit stream, encodes it through the Manchester codec, and sends it to the HDLC bus.

[0111] In one embodiment, see Figure 4 , the TRDP transceiver control module includes a MAC layer control module, an IP layer control module, a UDP layer control module and a TRDP message processing module;

[0112] Wherein, the MAC layer control module converts the data processed by the IP layer control module and sends it to the Ethernet interface circuit or receives and parses the TRDP protocol type message from the Ethernet interface circuit;

[0113] The IP layer control module receives the processing result of the UDP layer control module and then performs IP packetization or receives and analyzes the processing result of the MAC layer control module;

[0114] The UDP layer control module is used to perform UDP packetization or receive and parse the processing result of the IP layer control module after receiving the processing result of the TRDP message processing module;

[0115] The TRDP message processing module is used to receive the TRDP protocol type data sent by the data exchange management module and then perform TRDP packaging or receive and parse the processing result of the UDP layer control module.

[0116] In specific implementation, the data processing process is divided into two directions:

[0117] ① In the process of data reception, Ethernet network data is converted into binary bit streams through the physical layer Ethernet interface circuit, and then converted into Ethernet messages through the MAC layer control module. The Ethernet messages are checked by the IP layer control module for IP address, data length, IP layer check value, etc. The messages that pass the inspection are sent to the UDP control module for port address, data length, UDP layer check value, etc. The data that pass the inspection is sent to the TRDP message processing unit for ComID, data length, TRDP layer check value, etc. After passing the inspection, it is provided to the data exchange management unit as received data and stored in the dual-port RAM storage area. If it fails in the intermediate inspection process, the message is discarded.

[0118] ② During the data transmission process, the data exchange management unit reads the data to be sent from the dual-port RAM storage area, passes through the TRDP message processing unit, adds TRDP fields such as ComID, data length, and TRDP layer check value, and then passes through the UDP control module to add UDP fields such as port address, data length, and UDP layer check value, and then passes through the IP layer control module to add IP address, data length, IP layer check value and other IP layer fields. The final Ethernet message data is converted into a binary bit stream by the MAC layer control module, converted into a physical waveform by the Ethernet interface circuit, and sent to the Ethernet.

[0119] In one embodiment, see Figure 5 , the data exchange management module includes a configuration register, an addressing management module and a data access module;

[0120] Wherein, the addressing management module communicates with the configuration register, and addresses the HDLC protocol type message and / or the TRDP protocol type message according to the environment configuration information stored in the configuration register;

[0121] The data access module is connected to the addressing management module and the dual-port RAM storage area respectively, and is used to complete the access operation of the HDLC protocol type message and / or TRDP protocol type message in the dual-port RAM storage area according to the addressing result.

[0122] Understandably, Figure 5 It is a data exchange management module in the FPGA module of the embodiment of the present invention. The data exchange management module is mainly composed of configuration registers, addressing management modules, data access modules and other parts.

[0123] During specific implementation, in the initialization phase, the CPU module writes the pre-uploaded and stored environment configuration information into the configuration register, including the communication source and destination address, message length, storage first address, transceiver cycle and other information on the HDLC side and the TRDP side; In the actual application phase, the addressing management module reads the environment configuration information in the configuration register, especially reads the aforementioned addressing mapping relationship, and manages the addressing mapping process between messages of different protocol types according to the addressing mapping relationship. The data access module stores the received HDLC message and TRDP message in the specified storage area according to the transceiver process requirements of the HDLC protocol control module and the TRDP transceiver control module, reads the data to be sent from the storage area, transmits it to the HDLC protocol control module and the TRDP transceiver control module, and finally sends it to each bus network. The so-called addressing mapping process is as follows: in the TRDP message storage area, the address of the TRDP message to be received is allocated according to the message port address of the Ethernet network, and the HDLC message corresponding to the received TRDP message is arranged in sequence within the address range of the TRDP message according to a pre-established protocol plan, and an address is allocated to each HDLC message according to the first address of the arrangement; in the HDLC message storage area, according to a pre-established protocol plan, multiple HDLC messages corresponding to the TRDP message are arranged in sequence and allocated addresses, and the corresponding first address is allocated to the corresponding TRDP message.

[0124] In one embodiment, see Figure 6 , the dual-port RAM storage area includes a first HDLC storage area, a second HDLC storage area, a first TRDP storage area, and a second TRDP storage area;

[0125] Wherein, the first HDLC storage area and the second HDLC storage area are used to store the HDLC protocol type message in a HDLC mapping message format according to the environment configuration information in a rolling alternating manner;

[0126] The first TRDP storage area and the second TRDP storage area are used to store the TRDP protocol type message in a TRDP mapping message format in accordance with the environmental configuration information in a rolling alternating manner.

[0127] Understandably, Figure 6 It is a dual-port RAM storage area design architecture diagram in the FPGA module of the embodiment of the present application. The dual-port RAM storage area is divided into an HDLC data receiving storage area and a TRDP receiving storage area. To ensure data consistency, the HDLC data receiving storage area and the TRDP receiving storage area are divided into two pages, respectively referred to as the first storage area and the second storage area, to avoid simultaneous read and write operations.

[0128] Figure 7It is the storage distribution of TRDP and HDLC message mapping relationship in the present invention in the storage area and the configuration of the register in the data exchange management module.HDLC messages are stored in the HDLC storage area, and the relevant destination address, message first address, message length and other information are configured in the configuration register, and the HDLC messages stored are arranged by the relationship mapped to the TRDP messages, so that the TRDP mapping messages can correspond to the storage area, and the TRDP mapping messages are also configured in the configuration register area. The relevant ComID address, message first address, message length and other information. Similarly, TRDP messages are stored in the TRDP storage area, and are mapped to HDLC messages.

[0129] For example, the message mapping process is as follows: if the message received on the TRDP side is E2, its message length is 100 bytes, and its first address is assigned to AE2, and its corresponding HDLC messages are four, namely B1, B2, B3, and B4, each message is 20 bytes. Assuming the pre-planned protocol, the four messages correspond to the 0th to 19th bytes, 20th to 39th bytes, 40th to 59th bytes, and 60th to 79th bytes of the TRDP message, respectively. Then the four messages are arranged in sequence in the E2 message storage area, and the addresses assigned to the four messages are AB1, AB2, AB3, and AB4, respectively, where the address value of AB1 is AE2, the address value of AB2 is AE2+20, the address value of AB3 is AE2+40, and the address value of AB4 is AE2+60. The address value is AE2+60; if the messages received on the HDLC side are A1, A2, A3, and A4, each message is 20 bytes, and the messages corresponding to the four HDLCs are the same TRDP message E1. Assuming the pre-planned protocol, the four messages correspond to bytes 0-19, 20-39, 40-59, and 60-79 of the TRDP message, respectively. Then the four messages are arranged in sequence in the E1 message storage area, and the addresses allocated to the four messages are AA1, AA2, AA3, and AA4, respectively. The address value of AA2 is AA1+20, the address value of AA3 is AA1+40, and the address value of AA4 is AA1+60. The address value of address AE1 allocated to TRDP message E1 is AA1.

[0130] In one embodiment, see Figure 1 , the power conversion module comprises:

[0131] A power supply short-circuit protection circuit is connected to the original input voltage and performs short-circuit protection processing on the original input voltage;

[0132] A power reverse protection circuit, connected to the power short circuit protection circuit, to perform reverse protection on the voltage output by the power short circuit protection circuit;

[0133] A power surge protection circuit, connected to the power reverse protection circuit, and performing surge protection processing on the voltage output by the power reverse protection circuit;

[0134] A power supply pulse protection circuit, connected to the power supply surge protection circuit, performs pulse protection processing on the voltage output by the power supply reverse protection circuit;

[0135] A power supply filter circuit, connected to the power supply pulse protection circuit, and filtering the voltage output by the power supply pulse protection circuit;

[0136] A voltage conversion circuit, connected to the power filter circuit, performs voltage reduction processing on the filtered voltage;

[0137] A low voltage difference linear regulator is connected to the voltage conversion circuit, and performs linear voltage regulation on the voltage after the voltage reduction process to obtain the module supply voltage.

[0138] It can be understood that the HDLC-TRDP real-time conversion gateway itself is equipped with a power conversion module to realize the conversion of vehicle-mounted DC110V to board-level 5V and 3V power supplies, providing stable power supply for the entire gateway device.

[0139] The core of the power conversion module is the DC / DC power conversion component. The power conversion realizes the power conversion from DC110V to DC5V. The 110V power input passes through the 2W2 power industrial-grade connector, short-circuit protection circuit, reverse protection circuit, surge protection circuit, pulse protection circuit, and filter circuit to input the DC / DC power module. After the power module outputs a 5V single power supply, the high-precision low-ripple power supply LDO component (low voltage difference linear regulator) outputs the 3.3V voltage required by each functional module.

[0140] It should be noted that Figure 8 It is a schematic diagram of the application program and configuration update of the present invention. The application program and configuration file can be uploaded through any Ethernet port.

[0141] Fig. 9 It is the schematic diagram of the practical application of the present invention in a specific project. In this example, the subsystems such as air conditioning, door, signal, passenger information service without Ethernet interface are converted into gateway in real time by HDLC-TRDP, and the interaction with Ethernet TRDP data is realized.

[0142] In order to better illustrate the present application, taking a door control unit with 4 HDLC interfaces connected to the TRDP Ethernet as an example, the data exchange process of the HDLC-TRDP real-time conversion gateway is described as follows:

[0143] (1) The HDLC-TRDP real-time conversion gateway needs to be configured before it is put into regular work. Before the MVB bus data switch works, it needs to be initialized and configured. The CPU processing module parses the uploaded configuration file, writes the mapping relationship between HDLC data and TRDP data, and the addressing configuration of data storage into the register in the FPGA module, and after entering the regular working state, the corresponding conversion work can be performed. For example, the gate control unit of the 4 HDLC interfaces has source data addresses A1, A2, A3, and A4 (each message length is 20 bytes), which need to be packaged and converted into TRDP data packets E1 (message is 100 bytes), and A1-A4 are arranged in sequence to correspond to the E1 message. The HDLC message addresses from the network system that the gate control unit needs to receive are B1, B2, B3, and B4 (each message length is 20 bytes), respectively. The 4 data packets come from the network system TRDP data packet E2 (message is 100 bytes), and B1-B4 are arranged in sequence to correspond to the E2 message. For each of the received data messages A1-A4 and E2, the addresses stored in the FPGA module are P0A1-P0A4 and P0E2 respectively, because the addresses of the second page in the storage area of ​​the paging mechanism are P1A1-P1A4 and P1E2 respectively. For messages B1-B4 and E1, since they are split or packaged from the forwarding data of the corresponding mapping relationship, there is no need to allocate storage addresses.

[0144] (2) The HDLC-TRDP conversion gateway is initialized after power-on, and the configuration file is read by the CPU processing module to parse out the corresponding HDLC configuration information, TRDP configuration information and addressing information. After the configuration file is parsed, the CPU processing module writes the configuration information into the register in the FPGA module, so that the FPGA module learns the HDLC transceiver information and the TRDP transceiver information, including the corresponding addressing information of HDLC and TRDP. According to the example in step (1), the conversion gateway reads the B1, B2, B3, and B4 messages mapped by the E2 message in the TRDP storage area on the HDLC side, corresponding to 4 gates, and sends them as source messages. The 4 gate controllers respond to A1, A2, A3, and A4 as response messages. After the conversion gateway receives the A1-A4 message, it stores the data in the corresponding storage area. On the TRDP side, the E1 message mapped by the A1-A4 message data is periodically read and sent to the Ethernet network.

[0145] (3) On the HDLC side, the conversion gateway is controlled by the HDLC protocol module, which sends the B1-B4 data converted from the Ethernet network message E2 as a request message, and sends the data to the bus through the 485 transceiver circuit. After receiving the request message, the door controller replies with a response message A1-A4. The conversion gateway converts the message through the 485 transceiver circuit, and the HDLC protocol control module parses the message and receives it.

[0146] (4) On the TRDP side, the conversion gateway sends the gated message A1-A4 data to the Ethernet network through the TRDP transceiver module, and adds the source IP, destination IP, ComID, message length, CRC check and other corresponding configurations to the E1 message through the IP layer control, UDP layer control, and TRDP message processing module. The message is sent to the Ethernet network through the MAC layer control module and the Ethernet transceiver circuit; the conversion gateway receives the Ethernet message from the Ethernet network, and after being parsed by the transceiver circuit and the MAC layer control module, the IP layer control, UDP layer control, and TRDP message processing module proofread the message source IP, destination IP, ComID, message length, CRC check and other fields. The proofread data message is the data message E2 that the conversion gateway needs to receive, and the message is received and stored in the corresponding storage area.

[0147] (5) When the conversion gateway is in normal working state, the data exchange management module in the FPGA module stores the A1-A4 message received by the HDLC side into the P0A1-P0A4 or P1A1-P1A4 address of the dual-port RAM storage area. When writing to the corresponding address, the data exchange management module will maintain the page number identification bit register corresponding to the message. For example, when writing to P0A1-P0A4, the register identification is 0; when writing to P1A1-P1A4, the register identification is 1. When the conversion gateway needs to read the E1 message mapped by the A1-A4 message and send it to the Ethernet, it will first read the corresponding register page number identification. For example, when the page number is 0, it is known that the storage operation is processing the P0 page, and the address area data of the P1 page is read and sent. Similarly, when the page number is 1, it is known that the storage operation is processing the P1 page, and the address area data of the P0 page is read and sent.

[0148] (6) When the conversion gateway is in normal working state, the data exchange management module in the FPGA module stores the E2 message received by the TRDP side in the P0E2 or P1E2 address of the dual-port RAM storage area. When writing to the corresponding address, the data exchange management module will maintain the page number identification register corresponding to the message. For example, when writing to P0E2, the register identification is 0; when writing to P1E2, the register identification is 1. When the conversion gateway needs to read the B1-B4 message mapped by the E2 message and send it to the HDLC side, it will first read the corresponding register page number identification. For example, when the page number is 0, it is known that the storage operation is processing the P0 page, and the address area data of the P1 page is read and sent. Similarly, when the page number is 1, it is known that the storage operation is processing the P1 page, and the address area data of the P0 page is read and sent.

[0149] (7) During the forwarding process, if data reception is abnormal on the HDLC side, such as data packet cycle timeout, message CRC check error, etc., the corresponding error bit field in the data packet sent by the forwarding side, i.e., the TRDP side, will be set, thereby informing the TRDP side of the abnormal communication status on the HDLC side. Similarly, when data reception is abnormal on the TRDP side, corresponding operations are also performed on the HDLC side.

[0150] (8) The above operations are repeated periodically.

[0151] (9) Through the above operations, the HDLC-TRDP real-time conversion gateway realizes the real-time exchange of data between the door controller on the HDLC side and the TRDP side of the Ethernet system.

[0152] Through the above examples, the basic implementation method of HDLC-TRDP real-time conversion gateway is described. By the design method based on FPGA module as the core, by realizing HDLC control and TRDP transceiver control in FPGA, the real-time conversion of two kinds of protocol data can be realized. Since the subsystem data volume that the conversion gateway often converts is relatively small, the conversion gateway configuration can be mostly small-scale, and the FPGA resource demand for the conversion gateway is not high, and the chip with lower cost can be used, and it is designed as a miniaturized, modular device. The present application embodiment can easily realize the data conversion of two kinds of bus networks of HDLC and TRDP, and the software and hardware changes of tasks are not required for both HDLC side and TRDP side equipment, and the requirements of real-time control of network control system can be reached, so it is convenient to compare existing technology, and there are obvious advantages.

[0153] In summary, the method for exchanging data between HDLC and TRDP implemented in the embodiment of the present application has the following characteristics:

[0154] 1. The main functions are realized by FPGA chip, which simplifies the hardware structure. If the CPU+FPGA SOC chip is used, the overall circuit will be more simplified;

[0155] 2. The data forwarding function is realized through FPGA, which greatly improves the real-time performance of forwarding compared with software implementation;

[0156] 3. Using FPGA to send and receive TRDP data greatly simplifies the software processing flow and improves the processing speed of data sending and receiving compared to using the TRDP software protocol stack;

[0157] 4. The embodiments of the present application can realize real-time conversion to TRDP for HDLC devices that do not have a TRDP Ethernet interface. For HDLC devices, no software or hardware changes are required, and real-time transparent transmission can be directly achieved by the conversion gateway according to the original working mode.

[0158] 5. The embodiment of the present application reasonably plans the mechanism of data storage conversion, greatly simplifies the forwarding process, improves the forwarding efficiency, and reduces the delay of the conversion gateway.

[0159] 6. This method can be integrated into a modular, miniaturized device that is easy to install, and is relatively simple to install and implement.

[0160] The various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referenced to each other, and each embodiment focuses on the differences from other embodiments.

[0161] The above is a description of a specific embodiment of the specification. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in an order different from that in the embodiments and still achieve the desired results. In addition, the processes depicted in the drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0162] Each embodiment in this specification is described in a progressive manner, and the same and similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In the description of this specification, the description of reference terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the embodiment of this specification. In this specification, the schematic representation of the above terms does not necessarily target the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples without contradiction.

[0163] The above is only an example of the embodiment of the present specification and is not intended to limit the embodiment of the present specification. For those skilled in the art, the embodiment of the present specification may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the embodiment of the present specification shall be included in the scope of the claims of the embodiment of the present specification.

Claims

1. A HDLC-TRDP real-time conversion gateway, characterized in that, include: The FPGA module receives and parses the pre-processed HDLC protocol type message and / or TRDP protocol type message, and performs protocol type conversion on the parsing result according to the preset environment configuration information to complete the gateway exchange of the message; wherein the protocol type conversion is implemented by an on-chip paging mapping method; A power conversion module, which converts the original input voltage output by the DC power supply on the rail vehicle into a module power supply voltage, and connects the module power supply voltage to the FPGA module; Wherein, the FPGA module includes an HDLC protocol control module, a TRDP transceiver control module, a data exchange management module and a dual-port RAM storage area; The HDLC protocol control module is used to receive and parse the HDLC protocol type message from the RS485 interface circuit, and send the corresponding HDLC protocol type data to the data exchange management module after obtaining it, or receive and process the HDLC protocol type data from the data exchange management module and send it to the RS485 interface circuit after processing it; The TRDP transceiver control module is used to receive the TRDP protocol type message from the Ethernet interface circuit and parse it, and send it to the data exchange management module after obtaining the corresponding TRDP protocol type data, or receive and process the TRDP protocol type data from the data exchange management module and send it to the Ethernet interface circuit; The data exchange management module is used to receive the HDLC protocol type data from the HDLC protocol control module and / or receive the TRDP protocol type data from the TRDP transceiver control module, and perform protocol conversion processing on the HDLC protocol type data and / or the TRDP protocol type data in a paging mapping manner according to the environmental configuration information, and forward the data after the protocol conversion processing to the corresponding interface circuit via the corresponding transceiver control module; The dual-port RAM storage area is used to temporarily store the HDLC protocol type data and / or the TRDP protocol type data in a page mapping manner according to the environmental configuration information.

2. The HDLC-TRDP real-time conversion gateway according to claim 1, characterized in that It also includes an RS485 interface circuit, which is used for pre-processing the received HDLC protocol type message and then sending it to the FPGA module.

3. The HDLC-TRDP real-time conversion gateway according to claim 2, characterized in that It also includes an Ethernet interface circuit for pre-processing the received TRDP protocol type message and sending it to the FPGA module.

4. The HDLC-TRDP real-time conversion gateway according to claim 3, characterized in that It also includes a CPU module, which is used to receive the environmental configuration information from the central control unit of the rail vehicle and load the environmental configuration information into the FPGA module.

5. The HDLC-TRDP real-time conversion gateway according to claim 1, characterized in that The HDLC protocol control module includes a Manchester codec, a receiving buffer, a sending buffer, a transmitter, a receiver, a verification module and a main control module; Wherein, the Manchester codec receives and decodes the HDLC protocol type message from the RS485 interface circuit or encodes the HDLC protocol type data returned by the main control module; The receiver sends the HDLC protocol type message decoded by the Manchester codec to the main control module; The transmitter sends the HDLC protocol type data returned by the main control module to the Manchester codec; The receiving buffer is connected to the receiver and temporarily stores the decoded HDLC protocol type message; The sending buffer is connected to the transmitter to temporarily store the returned HDLC protocol type data; The verification module is connected to the transmitter and the receiver respectively, and is used to verify the decoded HDLC protocol type message and / or the returned HDLC protocol type data; The main control module uses a state machine to control the Manchester codec, receiving buffer, sending buffer, transmitter, receiver and verification module actions respectively.

6. The HDLC-TRDP real-time conversion gateway according to claim 1, characterized in that, The TRDP transceiver control module includes a MAC layer control module, an IP layer control module, a UDP layer control module and a TRDP message processing module; Wherein, the MAC layer control module converts the data processed by the IP layer control module and sends it to the Ethernet interface circuit or receives and parses the TRDP protocol type message from the Ethernet interface circuit; The IP layer control module receives the processing result of the UDP layer control module and then performs IP packetization or receives and analyzes the processing result of the MAC layer control module; The UDP layer control module is used to perform UDP packetization or receive and parse the processing result of the IP layer control module after receiving the processing result of the TRDP message processing module; The TRDP message processing module is used to receive the TRDP protocol type data sent by the data exchange management module and then perform TRDP packaging or receive and parse the processing result of the UDP layer control module.

7. The HDLC-TRDP real-time conversion gateway according to claim 1, characterized in that, The data exchange management module includes a configuration register, an addressing management module and a data access module; Wherein, the addressing management module communicates with the configuration register, and addresses the HDLC protocol type message and / or the TRDP protocol type message according to the environment configuration information stored in the configuration register; The data access module is connected to the addressing management module and the dual-port RAM storage area respectively, and is used to complete the access operation of the HDLC protocol type message and / or TRDP protocol type message in the dual-port RAM storage area according to the addressing result.

8. The HDLC-TRDP real-time conversion gateway according to claim 1, characterized in that The dual-port RAM storage area includes a first HDLC storage area, a second HDLC storage area, a first TRDP storage area, and a second TRDP storage area; Wherein, the first HDLC storage area and the second HDLC storage area are used to store the HDLC protocol type message in a HDLC mapping message format according to the environment configuration information in a rolling alternating manner; The first TRDP storage area and the second TRDP storage area are used to store the TRDP protocol type message in a TRDP mapping message format in accordance with the environmental configuration information in a rolling alternating manner.

9. The HDLC-TRDP real-time conversion gateway according to claim 1, characterized in that, The power conversion module comprises: A power supply short-circuit protection circuit is connected to the original input voltage and performs short-circuit protection processing on the original input voltage; A power reverse protection circuit, connected to the power short circuit protection circuit, to perform reverse protection on the voltage output by the power short circuit protection circuit; A power surge protection circuit, connected to the power reverse protection circuit, and performing surge protection processing on the voltage output by the power reverse protection circuit; A power pulse protection circuit, connected to the power surge protection circuit, performs pulse protection processing on the voltage output by the power reverse protection circuit; A power supply filter circuit, connected to the power supply pulse protection circuit, and filtering the voltage output by the power supply pulse protection circuit; A voltage conversion circuit, connected to the power filter circuit, performs voltage reduction processing on the filtered voltage; A low voltage drop linear regulator is connected to the voltage conversion circuit and performs linear voltage regulation on the voltage after the voltage reduction process to obtain the module supply voltage.

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