Control method for implementing noise consistency of multi-channel digital receiving module

Abstract

The application discloses a control method for realizing noise consistency of a multi-channel digital receiving module, and belongs to the technical field of multi-channel noise consistency, and the specific method comprises the following steps: marking the channel noises of corresponding modules as noise 1 and noise 2 respectively; performing digital down-conversion processing on each channel noise, and converting the data rate of the channel noise into I1, Q1, I2 and Q2 signals with a data rate of 4MSPS; obtaining noise power 1 and noise power 2 through a LABVIEW tool; calculating the difference value between the noise power 1 and the noise power 2, and compensating the difference value back into the channel; and performing digital down-conversion processing on each channel noise, then calculating the noise power difference value in real time through the LABVIEW software, and calculating and generating a noise power compensation value through the MATLAB software. The noise consistency method designed by the application can effectively improve the problems in the background technology, so that the noises among the channels are almost consistent.

Description

Technical Field

[0001] This invention belongs to the field of multi-channel noise consistency technology, specifically a control method for achieving noise consistency in multi-channel digital receiving modules. Background Technology

[0002] With the continuous development of radar digital transceiver technology, in order to improve the dynamic requirements of radar systems, radar analog echo signals are generally sampled and processed by multi-channel digital receiving modules. The most significant characteristic of multi-channel digital receiving modules is the large number of sampling channels; therefore, differences in the operating performance of the devices in each channel are unavoidable, resulting in noise inconsistencies between channels. For multi-channel processing technology, excessive noise differences between channels pose a challenge to the radar channel consistency requirements. Therefore, this invention provides a control method for achieving noise consistency in multi-channel digital receiving modules. Summary of the Invention

[0003] To address the problems of the above solutions, this invention provides a control method for achieving noise consistency in multi-channel digital receiver modules.

[0004] The objective of this invention can be achieved through the following technical solution: a control method for achieving noise consistency in a multi-channel digital receiver module, the specific method comprising:

[0005] Step 1: Label the channel noise of the corresponding module as noise 1 and noise 2 respectively;

[0006] Step 2: Perform digital down-conversion processing on the noise of each channel to convert it into I1, Q1 and I2, Q2 signals with a data rate of 4MSPS;

[0007] Step 3: Obtain noise power 1 and noise power 2 using LabVIEW tools;

[0008] Step 4: Calculate the difference between noise power 1 and noise power 2, and compensate this difference back into the channel.

[0009] Furthermore, the sampling rate of the IQ signal is 4 MSPS, with 2000 IQ sample data in a single repetition period. The IQ data consists of I and Q signals, each with a resolution of 16 bits and a data capacity of 2000*2*16 bits. The data is transmitted optically using optical gigabit Ethernet as the optical protocol. After the IQ signal is sent to the computer terminal, the computer processes the received data.

[0010] Furthermore, for a single sample point, its signal power is:

[0011] G = 10log 10 (I 2 +Q2 );

[0012] For channel 1, its noise IQ signal expression is as follows:

[0013] I1=(I1′,I2′,I3′,…,I n ′), n=2000;

[0014] Q1=(Q1′, Q2′, Q3′,…,Q n ′), n=2000;

[0015] For channel 2, its noise IQ signal expression is as follows:

[0016] I1=(I1″,I2″,I3″,…,I n n = 2000;

[0017] Q1=(Q1″, Q2″, Q3″,…,Q n n = 2000;

[0018] Since the noise is generally Gaussian white noise, the method for calculating the average noise power for an n-point IQ signal is as follows:

[0019]

[0020] For channel 1, the average noise power is as follows:

[0021]

[0022] For channel 2, the average noise power is as follows:

[0023]

[0024] Therefore, the difference in average noise power between channel 1 and channel 2 is shown below:

[0025] G Δ =|G′-G″|.

[0026] Furthermore, after calculating the noise power difference, the Gaussian white noise function is called through the MATLAB scientific computing software, which can generate white noise signals of arbitrary power. The generated white noise sequences are Inoise and Qnoise; Inoise and Qnoise are saved in the FPGA as MIF files.

[0027] To better simulate the characteristics of Gaussian white noise, the length of the white noise sequence generated by MATLAB software was set to 32768, that is, the lengths of Inoise and Qnoise are both 32768, and their depth is much greater than the depth of a single periodic signal.

[0028] I noise = (I1, I2, I3, ..., I n ), n = 32768;

[0029] Q noise = (Q1, Q2, Q3, ..., Q n ), n = 32768.

[0030] Furthermore, the ADC outputs two noise signals, CH1 and CH2, each with a 16-bit width. After digital down-conversion, the width of CH1 and CH2 will be increased to 40 bits. This is because signal filtering is achieved through convolution multiplication, and the filter coefficients have an 18-bit width. To prevent data overflow, the output data width is also 40 bits. Since the digital down-conversion output signal is 40 bits, and the system dynamic range requirement is 90dB, only 16 bits of the IQ data need to be retained. This retention is achieved by truncating the input full-amplitude signal by retaining only one sign bit. The amplitude values ​​of I1 and Q1 are less than those of I2 and Q2, so white noise sequences I3 and Q3 are added to I1 and Q1. Therefore, the lengths of I3 and Q3 are the same as those of I1 and Q1.

[0031] I3=(I1″′, I2″′, I3″′,…,I n "′), n = 2000;

[0032] Q3=(Q1″′, Q2″′, Q3″′,…,Q n ″′), n=2000.

[0033] Furthermore, within a single period, the number of sample points is 2000. When the first sample point is output, the lower 15 bits of the DDC output I signal are 12768. Therefore, the current I3 output value is the 12768th data value in the Inoise sequence.

[0034] I3(1)=I noise (12768);

[0035] When the 1800th sample point is output, the lower 15 bits of the DDC output I signal are 56. Therefore, the current I3 output value is the 56th data value in the Inoise sequence.

[0036] I3(1800)=I noise (56);

[0037] The Q3 operation is similar to the I3 operation.

[0038] Furthermore, when G′>G″, then:

[0039]

[0040] When G″>G′, then:

[0041]

[0042] Compared with the prior art, the beneficial effects of the present invention are:

[0043] By performing digital down-conversion processing on the noise of each channel, and then calculating the noise power difference value in real time using LabVIEW software, and generating the noise power compensation value using MATLAB software, the FPGA adds the compensation value to the channel. The noise consistency method designed in this invention can effectively improve the problems in the background technology, making the noise between channels almost consistent. Therefore, the channel consistency method designed in this invention can greatly improve the problem of noise inconsistency between channels, so that the signal echo channels can be basically kept consistent, thereby improving radar detection performance. Attached Figure Description

[0044] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0045] Figure 1 This is a flowchart illustrating the process of the method of the present invention;

[0046] Figure 2 The original noise maps for both channels;

[0047] Figure 3 The diagram shows the improved noise power for the two channels.

[0048] Figure 4 This is an example diagram of the DDC1 I channel output signal of the present invention. Detailed Implementation

[0049] The technical solution of the present invention will be clearly and completely described below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0050] like Figures 1 to 4 As shown, Figure 2 The diagram shows noise power graphs with varying noise levels. Figure 2 In the diagram, the blue curve represents channel 1, and the red curve represents channel 2. Figure 2It can be seen that there is a noise difference between the channels, that is, the noise power of the two channels is not the same. Figure 3 The image shown is a noise power diagram of a system for achieving noise uniformity in a multi-channel digital receiver module, as described in this invention. Figure 2 The comparison shows that, Figure 3 The noise difference between the involved signals has been greatly improved, and the noise power of the two signals is basically the same. For detection radar, the echo signals of different radar beams are output to the digital receiving module through analog channels. Due to hardware differences and manufacturing inconsistencies, there are often inconsistencies in channel noise, which leads to the problem of channel dynamic inconsistency. This problem will make it difficult for the radar to calibrate the minimum signal.

[0051] A control method for achieving noise consistency in a multi-channel digital receiver module involves an analog-to-digital conversion sampling rate of 200 MSPS, a signal center frequency of 140 MSPS, and channel noises of noise 1 and noise 2. The implementation scheme primarily involves digital down-conversion of each channel noise signal without inputting a valid signal, transforming it into I1, Q1 and I2, Q2 signals with a data rate of 4 MSPS. Noise power 1 and noise power 2 are obtained using LabVIEW, and the difference between them is calculated. This difference is then compensated back into the channel noise, thereby achieving channel noise consistency.

[0052] This design utilizes a combination of a dual-channel analog-to-digital converter (ADC) chip, ADS42LB69, and an FPGA chip, EP4SGX230. Since the radar operates using a pulse signal system, the radar pulse repetition frequency in this invention is 2kHz, i.e., a period of 500µs. The ADS42LB69 ADC chip has a sampling rate of 200MSPS, with two signal channels and an IQ signal sampling rate of 4MSPS. The block diagram is shown below. Figure 1 As shown. Since the sampling rate of the IQ signal is 4 MSPS, there are 2000 IQ sample data points within a single repetition period. The IQ data consists of I and Q signals, each with a resolution of 16 bits. Therefore, the data capacity is 2000 * 2 * 16 bits. The data is transmitted optically using Gigabit Ethernet as the optical protocol. Figure 1 As shown. After the IQ signal is sent to the computer terminal, the computer will process the received data. For a single sample point, its signal power is:

[0053] G = 10log 10 (I 2 +Q 2 );

[0054] For channel 1, its noise IQ signal expression is as follows:

[0055] I1=(I1′,I2′,I3′,…,I n′), n=2000;

[0056] Q1=(Q1′, Q2′, Q3′,…,Q n ′), n=2000;

[0057] For channel 2, its noise IQ signal expression is as follows:

[0058] I1=(I1″,I2″,I3″,…,I n n = 2000;

[0059] Q1=(Q1″, Q2″, Q3″,...,Q n n = 2000;

[0060] Since the noise is generally Gaussian white noise, for an n-point IQ signal, one method for calculating the average noise power is as follows:

[0061]

[0062] For channel 1, the average noise power is as follows:

[0063]

[0064] For channel 2, the average noise power is as follows:

[0065]

[0066] Therefore, the difference in average noise power between channel 1 and channel 2 is shown below:

[0067] G Δ =|G′-G″|;

[0068] After calculating the noise power difference, the Gaussian white noise function is called using the MATLAB scientific computing software. This function can generate white noise signals of arbitrary power, producing Inoise and Qnoise sequences. To better simulate the characteristics of Gaussian white noise, the length of the white noise sequence generated by the MATLAB software is set to 32768, meaning both Inoise and Qnoise are 32768 bytes long, with a depth much greater than that of a single-cycle signal. Inoise and Qnoise are saved as MIF files on the FPGA.

[0069] I noise = (I1, I2, I3, ..., I n ), n = 32768;

[0070] Q noise = (Q1, Q2, Q3, ..., Q n ), n = 32768;

[0071] Figure 1 The specific implementation process is demonstrated. The ADC outputs two noise signals, CH1 and CH2, with a bit width of 16 bits. After digital down-conversion, the bit width of CH1 and CH2 will be widened to 40 bits. This is because signal filtering is achieved through convolution multiplication, and the filter coefficients have a bit width of 18 bits. Furthermore, to prevent data overflow, the output data bit width is 40 bits. Since the digital down-conversion output signal is 40 bits, and the system dynamic range requirement is 90dB, only 16 bits of the IQ data need to be retained. The retention method is to truncate the input full-amplitude signal by retaining one sign bit. The amplitude values ​​of I1 and Q1 are less than those of I2 and Q2, so white noise sequences I3 and Q3 are added to I1 and Q1. Therefore, the lengths of I3 and Q3 are the same as those of I1 and Q1.

[0072] I3=(I1″′, I2″′, I3″′,…,I n "′), n = 2000;

[0073] Q3=(Q1″′, Q2″′, Q3″′,…,Q n "′), n = 2000;

[0074] The defining characteristic of Gaussian white noise is its randomness. Since the white noise sequence is stored in ROM, the ROM read address must also reflect randomness. Because the lengths of Inoise and Qnoise are 32768 (i.e., the address width is 15), and the full width of the signal filtering convolution output is 40, and the signal itself is white noise... Figure 4 The image shows the full-width 40-bit data output from the I channel of DDC1. As can be seen from the figure, the bits below the 22nd bit are all white noise bits, which meet the randomness requirement. Therefore, the lower 15 bits of noise data can be directly extracted as the address of the ROM to meet the randomness requirement.

[0075] Within a single cycle, since the number of sample points is 2000, when the first sample point is output, the lower 15 bits of the DDC output I signal are 12768. Therefore, the current I3 output value is the 12768th data value in the Inoise sequence.

[0076] I3(1)=I noise (12768);

[0077] When the 1800th sample point is output, the lower 15 bits of the DDC output I signal are 56. Therefore, the current I3 output value is the 56th data value in the Inoise sequence.

[0078] I3(1800)=I noise (56);

[0079] The Q3 operation is similar to the I3 operation.

[0080] When G′>G″, then:

[0081]

[0082] When G″>G′, then:

[0083]

[0084] Noise compensation values ​​are generated by calculating the noise difference between channels and then used to compensate the channel with the lower noise value. The random address of the noise ROM is obtained from the original white noise itself. The implementation is simple and straightforward, requiring no complex algorithms to generate random addresses. Furthermore, this method can generate noise of arbitrary power, has wide applications, and can be extended to other fields.

[0085] The above formulas are all numerical calculations after removing dimensions. The formulas are obtained by software simulation based on a large amount of data and are closest to the real situation. The preset parameters and preset thresholds in the formulas are set by those skilled in the art according to the actual situation or obtained by simulation based on a large amount of data.

[0086] The above embodiments are only used to illustrate the technical methods of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical methods of the present invention without departing from the spirit and scope of the technical methods of the present invention.

Claims

1. A control method for achieving noise uniformity in a multi-channel digital receiver module, characterized in that, Specific methods include: Step 1: Label the channel noise of the corresponding module as noise 1 and noise 2 respectively; Step 2: Perform digital down-conversion processing on the noise of each channel to convert it into I1, Q1 and I2, Q2 signals with a data rate of 4MSPS; Step 3: Obtain noise power 1 and noise power 2 using LabVIEW tools; Step 4: Calculate the difference between noise power 1 and noise power 2, and compensate the corresponding difference back into the channel. The noise power compensation value is generated by MATLAB software. The FPGA adds the compensation value to the channel so that the noise between the channels is almost the same.

2. The control method for achieving noise consistency in a multi-channel digital receiver module according to claim 1, characterized in that, The sampling rate of the IQ signal is 4 MSPS, with 2000 IQ sample data in a single repetition period. The IQ data consists of I and Q signals, each with a resolution of 16 bits. The data capacity is 2000*2*16 bits. The data is transmitted optically using Gigabit Ethernet as the optical protocol. After the IQ signal is sent to the computer terminal, the computer processes the received data.

3. The control method for achieving noise consistency in a multi-channel digital receiver module according to claim 2, characterized in that, For a single sample point, its signal power is: ； For channel 1, its noise IQ signal expression is as follows: ； ； For channel 2, its noise IQ signal expression is as follows: ； ； For an n-point IQ signal, the method for calculating the average noise power is as follows: ； For channel 1, the average noise power is as follows: ； For channel 2, the average noise power is as follows: ； Therefore, the difference in average noise power between channel 1 and channel 2 is shown below: 。 4. The control method for achieving noise consistency in a multi-channel digital receiver module according to claim 3, characterized in that, After the noise power difference is calculated, the Gaussian white noise function is called through the MATLAB scientific computing software, which can generate white noise signals of arbitrary power. The generated white noise sequences are Inoise and Qnoise; Inoise and Qnoise are saved in the FPGA as MIF files.

5. The control method for achieving noise consistency in a multi-channel digital receiver module according to claim 4, characterized in that, Set the length of the white noise sequence generated by MATLAB software to 32768, that is: ； 。 6. The control method for achieving noise consistency in a multi-channel digital receiver module according to claim 5, characterized in that, The ADC outputs two noise signals CH1 and CH2, each with a bit width of 16 bits. After digital downconversion, the bit width of CH1 and CH2 will be expanded to 40 bits, resulting in a 40-bit output signal. The IQ data retains 16 bits by truncating the signal by retaining one sign bit from the input full-amplitude signal. Since the amplitude values ​​of I1 and Q1 are less than those of I2 and Q2, white noise sequences I3 and Q3 are added to I1 and Q1, thus making I3 and Q3 the same length as I1 and Q1. ； 。 7. The control method for achieving noise consistency in a multi-channel digital receiver module according to claim 6, characterized in that, Within a single period, the number of sample points is 2000. When the first sample point is output, the lower 15 bits of the DDC output I signal are 12768. Therefore, the current I3 output value is the 12768th data value in the Inoise sequence. ； When the 1800th sample point is output, the lower 15 bits of the DDC output I signal are 56. Therefore, the current I3 output value is the 56th data value in the Inoise sequence. 。 8. The control method for achieving noise consistency in a multi-channel digital receiver module according to claim 7, characterized in that, when Then we have: ； when Then we have: .

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