A heterogeneous platform radar control and signal processing apparatus and radar system
By integrating ZYNQ, FPGA and DSP processors into a heterogeneous platform radar control and signal processing device, the problems of large number of devices, large overall size and heavy weight of traditional radar systems are solved. This achieves high integration and low cost of radar systems, improves signal transmission reliability and timing accuracy, and is suitable for radar miniaturization.
Patent Information
- Application Number
- CN202511249078.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-03
- Publication Date
- 2026-07-14
- Estimated Expiration
- 2045-09-03
AI Technical Summary
Traditional radar systems are characterized by a large number of devices, large overall size and weight, high power consumption and cost, complex inter-module connections, and insufficient signal transmission reliability and timing accuracy.
The radar control and signal processing device adopts a heterogeneous platform, integrating ZYNQ, FPGA and DSP processors. System control, signal generation, signal sampling and processing are realized through a single board, reducing external physical connections. Data exchange is carried out through printed lines and internal interconnection of FPGA chips.
It achieves a high degree of integration of the radar system, reduces costs, improves signal transmission reliability and timing accuracy, reduces failure points, and is suitable for radar miniaturization design.
Smart Images
Figure CN121091210B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of radar system technology, and in particular to a heterogeneous platform radar control and signal processing device and radar system. Background Technology
[0002] Radar systems are relatively complex electronic devices, typically consisting of multiple functionally independent subsystems, including timer modules, AD sampling modules, central control modules, signal processing modules, and beam control modules. Each of these exists as an independent 6U or 3U standard board and is installed in an ATR chassis, exchanging signals and transmitting data through connectors and external cables.
[0003] This type of multi-board discrete architecture is widely used in traditional large radars, but it involves a large number of devices, a large overall size, and a high weight, which also brings significant power consumption and cost issues. In addition, the connection between modules relies on a large number of cables and connectors, which not only increases the complexity and weight of the system, but also introduces risks of delay, interference, and reliability in signal transmission. Summary of the Invention
[0004] This invention provides a heterogeneous platform radar control and signal processing device and radar system, which solves the problem of how to achieve a high degree of integration of radar system while improving signal transmission and processing performance.
[0005] To achieve the above objectives, this application adopts the following technical solution:
[0006] Firstly, a heterogeneous platform radar control and signal processing device is provided, comprising:
[0007] The control and processing unit, signal interface unit, clock management unit, and power management unit are integrated into the single board;
[0008] The control and processing unit includes three heterogeneous processors: ZYNQ, FPGA, and DSP.
[0009] The ZYNQ processor includes a PS terminal and a PL terminal. The PS terminal runs the main control software, which is used for overall system status control, resource scheduling, instruction forwarding, and echo data processing and forwarding. The PL terminal is configured to implement timing, wave control, signal generation, and data interface driving functions.
[0010] The FPGA processor is configured to perform signal acquisition, digital downconversion filtering, digital beamforming, pulse compression, coherent accumulation, and moving target detection functions.
[0011] The DSP processor is configured to implement constant false alarm rate (CFAR) detection and uses a multi-core parallel processing architecture to segment data for different distance ranges.
[0012] The signal interface unit is connected to the control and processing unit and includes a timing interface, a synchronous / asynchronous serial port, a DAC interface, a multi-channel ADC module, and an optical fiber module, used to realize signal and data interaction between the overall device and the external radar subsystem.
[0013] The clock management unit is connected to the control and processing unit and the signal interface unit. It is used to receive an external reference clock and generate the working clock required by each unit in the device. It is also equipped with an on-board crystal oscillator backup function.
[0014] The power management unit is used to convert the input voltage into multiple power supply voltages required by the internal and external subsystems of the device.
[0015] Furthermore, the control and processing unit interacts with external systems for data and commands via Ethernet; within the control and processing unit:
[0016] The ZYNQ processor and the FPGA processor are interconnected via LVDS, GTX and the first GPIO interface; the LVDS interface is used for uplink control command transmission, the GTX interface is used for inter-chip data interaction, and the first GPIO interface is used for inter-chip timing trigger signal transmission.
[0017] The DSP processor and the FPGA processor are interconnected through a second GPIO, a first SRIO, and a first EMIF interface; the second GPIO interface is used for inter-chip timing trigger signal transmission, the first SRIO interface is used for inter-chip data interaction, and the first EMIF interface is used for instruction transmission.
[0018] The DSP processor and the ZYNQ processor are interconnected through a third GPIO, a second SRIO, and a second EMIF interface; the third GPIO is used for inter-chip timing trigger signal transmission, the second SRIO is used for inter-chip data interaction, and the second EMIF is used for instruction transmission.
[0019] Furthermore, the PL terminal includes:
[0020] The timing module is used to generate all the timing signals required for the operation of the entire machine.
[0021] The beam control module is used to control the TR_T, TR_R, Data, and CLK signals required for the operation of all T / R components, and to control the normal transmission and reception of signals by the T / R components of the array system.
[0022] The signal generation module is used to output the intermediate frequency digital baseband signal to the DAC module, so that the DAC interface can generate an intermediate frequency analog signal;
[0023] The data interface driver module is used to generate the interface data required to control the external systems; the external systems include: frequency source, receiver and servo system.
[0024] Furthermore, the FPGA processor includes:
[0025] The signal acquisition module is used to sample intermediate frequency analog signals and convert them into digital signals;
[0026] The digital downconversion filter module is used to perform quadrature digital downconversion on intermediate frequency digital signals, transforming the signals into zero intermediate frequency (IF) IQ signals; and adaptively filtering according to the actual signal bandwidth.
[0027] The digital beamforming module is used to complete digital beamforming, forming sum, azimuth difference, and elevation difference beams from 4-quadrant echo data, or forming multiple receiving beams in the azimuth and elevation dimensions as needed.
[0028] The pulse compression module is used to compress linear frequency modulated signals into pulses.
[0029] The coherent accumulation module is used to coherently accumulate the signal for each repetition cycle.
[0030] The moving target detection module is used to implement MTI and MTD functions and has the ability to filter out stationary ground targets.
[0031] Furthermore, the DSP processor includes:
[0032] The constant false alarm rate (CFAR) detection module is used to perform CFAR detection on targets. When handling long-distance, high-point CFAR processing, the data is segmented by distance, and different distance segments are assigned to different cores for processing, thereby improving processing efficiency.
[0033] Furthermore, the signal interface unit includes:
[0034] At least 5 ADC modules, of which the first 4 are used for radar echo signal sampling and the 5th is used for array calibration signal sampling. The digital signal after sampling by the ADC is transmitted to the FPGA processor.
[0035] The DAC interface is used to receive the digital baseband signal generated by the ZYNQ processor and convert it into an analog baseband signal for output.
[0036] The fiber optic module is connected to the FPGA processor via the Aurora interface and is used to quickly output massive amounts of data from inside the device to an external data storage module.
[0037] In a second aspect, a radar system is provided, including a heterogeneous platform radar control and signal processing device as described in the first aspect.
[0038] The heterogeneous platform radar control and signal processing device of the present invention has the following beneficial effects:
[0039] This design employs an integrated architecture combining a single ZYNQ chip, DSP, FPGA, DAC, and multi-channel ADC to realize system control, signal generation, signal sampling, and signal processing functions within the radar system. The entire radar processing workflow, from command generation, signal generation, transmission control, echo acquisition to signal processing, is implemented on a single board. High integration, small size, and light weight significantly reduce costs. Optimal energy efficiency and processing performance are achieved by rationally allocating resources to the most suitable processor platform based on the characteristics of each processing task. Numerous external physical connections between modules are eliminated, with data exchange via printed circuit lines and internal interconnections within the FPGA chip. This reduces potential failure points caused by connectors and cables, improving signal transmission reliability and timing accuracy. In practical applications, this design features low power consumption and a short production cycle, facilitating radar miniaturization.
[0040] The radar system corresponding to the heterogeneous platform radar control and signal processing device of this invention can achieve the same technical effect, and will not be described in detail here to avoid duplication. Attached Figure Description
[0041] Figure 1 This is a schematic structural diagram of a heterogeneous platform radar control and signal processing device provided in an embodiment of this application. Detailed Implementation
[0042] To further illustrate the technical means and effects adopted by the present invention to achieve its intended purpose, the technical solutions in the embodiments of this application are clearly described. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art are within the scope of protection of this application.
[0043] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such terms can be used interchangeably where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, a first object can be one or more. Furthermore, in the specification, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.
[0044] The steps described in the specification and the flowcharts in the accompanying drawings of this invention are not necessarily strictly executed according to the step numbers; the execution order of the method steps can be changed. Furthermore, certain steps can be omitted, multiple steps can be combined into one step, and / or one step can be broken down into multiple steps.
[0045] This specification provides a heterogeneous platform radar control and signal processing device, and also relates to a radar system. The following detailed description is provided in conjunction with the accompanying drawings and preferred embodiments.
[0046] Please see Figure 1 This application provides a heterogeneous platform radar control and signal processing device, such as... Figure 1 As shown, it includes:
[0047] The control and processing unit, signal interface unit, clock management unit, and power management unit are integrated into the single board;
[0048] The control and processing unit includes three heterogeneous processors: ZYNQ, FPGA, and DSP.
[0049] The ZYNQ processor includes a PS terminal and a PL terminal. The PS terminal runs the main control software, which is used for overall system status control, resource scheduling, instruction forwarding, and echo data processing and forwarding. The PL terminal is configured to implement timing, wave control, signal generation, and data interface driving functions.
[0050] The FPGA processor is configured to perform signal acquisition, digital downconversion filtering, digital beamforming, pulse compression, coherent accumulation, and moving target detection functions.
[0051] The DSP processor is configured to implement constant false alarm rate (CFAR) detection and uses a multi-core parallel processing architecture to segment data for different distance ranges.
[0052] The signal interface unit is connected to the control and processing unit and includes a timing interface, a synchronous / asynchronous serial port, a DAC interface, a multi-channel ADC module, and an optical fiber module, used to realize signal and data interaction between the overall device and the external radar subsystem.
[0053] The clock management unit is connected to the control and processing unit and the signal interface unit. It is used to receive an external reference clock and generate the working clock required by each unit in the device. It is also equipped with an on-board crystal oscillator backup function.
[0054] The power management unit is used to convert the input voltage into multiple power supply voltages required by the internal and external subsystems of the device.
[0055] Furthermore, the control and processing unit interacts with external systems for data and commands via Ethernet; within the control and processing unit:
[0056] The ZYNQ processor and the FPGA processor are interconnected via LVDS, GTX and the first GPIO interface; the LVDS interface is used for uplink control command transmission, the GTX interface is used for inter-chip data interaction, and the first GPIO interface is used for inter-chip timing trigger signal transmission.
[0057] The DSP processor and the FPGA processor are interconnected through a second GPIO, a first SRIO, and a first EMIF interface; the second GPIO interface is used for inter-chip timing trigger signal transmission, the first SRIO interface is used for inter-chip data interaction, and the first EMIF interface is used for instruction transmission.
[0058] The DSP processor and the ZYNQ processor are interconnected through a third GPIO, a second SRIO, and a second EMIF interface; the third GPIO is used for inter-chip timing trigger signal transmission, the second SRIO is used for inter-chip data interaction, and the second EMIF is used for instruction transmission.
[0059] Furthermore, the PL terminal includes:
[0060] The timing module is used to generate all the timing signals required for the operation of the entire machine.
[0061] The beam control module is used to control the TR_T, TR_R, Data, and CLK signals required for the operation of all T / R components, and to control the normal transmission and reception of signals by the T / R components of the array system.
[0062] The signal generation module is used to output the intermediate frequency digital baseband signal to the DAC module, so that the DAC interface can generate an intermediate frequency analog signal;
[0063] The data interface driver module is used to generate the interface data required to control external systems, including frequency sources, receivers, servo systems, etc.
[0064] Furthermore, the FPGA processor includes:
[0065] The signal acquisition module is used to sample intermediate frequency analog signals and convert them into digital signals;
[0066] The digital downconversion filter module is used to perform quadrature digital downconversion on intermediate frequency digital signals, transforming the signals into zero intermediate frequency (IF) IQ signals; and adaptively filtering according to the actual signal bandwidth.
[0067] The digital beamforming module is used to complete digital beamforming, forming sum, azimuth difference, and elevation difference beams from 4-quadrant echo data, or forming multiple receiving beams in the azimuth and elevation dimensions as needed.
[0068] The pulse compression module is used to compress linear frequency modulated signals into pulses.
[0069] The coherent accumulation module is used to coherently accumulate the signal for each repetition cycle.
[0070] The moving target detection module is used to implement MTI and MTD functions and has the ability to filter out stationary ground targets.
[0071] Furthermore, the DSP processor includes:
[0072] The constant false alarm rate (CFAR) detection module is used to perform CFAR detection on targets. When handling long-distance, high-point CFAR processing, the data is segmented by distance, and different distance segments are assigned to different cores for processing, thereby improving processing efficiency.
[0073] Furthermore, the signal interface unit includes:
[0074] At least 5 ADC modules, of which the first 4 are used for radar echo signal sampling and the 5th is used for array calibration signal sampling. The digital signal after sampling by the ADC is transmitted to the FPGA processor.
[0075] The DAC interface is used to receive the digital baseband signal generated by the ZYNQ processor and convert it into an analog baseband signal for output.
[0076] The fiber optic module is connected to the FPGA processor via the Aurora interface and is used to quickly output massive amounts of data from inside the device to an external data storage module.
[0077] In specific implementation, for example:
[0078] ZYNQ uses Fudan Microelectronics' FMQL45T900 processor, JFM7VX690T FPGA, and FT-6678 DSP. The FMQL45T900 processor, JFM7VX690T processor, and FT-6678 processor all have 2GB of external DDR3 SDRAM.
[0079] In the signal interface unit, the timing interface adopts two specifications: a 422 differential interface and an LVDS differential interface. The 422 differential interface is used for external timing interfaces with high anti-interference requirements for long-distance transmission of trigger signals, while the LVDS differential interface is used for external timing interfaces with high accuracy in trigger signal timing.
[0080] The synchronous serial port uses a 422 level, including DATA and CLK signals, for transmitting command data, status feedback, and other information with other external subsystem modules (such as T / R components, frequency sources, and receivers). The asynchronous serial port also uses a 422 level, including DATA and CLK signals, for transmitting command data, status feedback, and other information with other external subsystem modules (such as servo controllers).
[0081] The DAC interface receives the digital baseband signal from the ZYNQ, converts the digital baseband signal into an analog baseband signal, and outputs it to the frequency conversion module of an external system through the SSNMA interface, thereby generating a radio frequency transmission excitation signal.
[0082] The system includes a 5-channel ADC module using the Analog Devices AD9680 chip, capable of sampling 1GSPS, 14-bit signals. The first four channels sample the echo signals during normal radar operation, while the last channel samples the surface calibration signals. The digital signals obtained after ADC sampling are transmitted to the FPGA via the JESD204B interface.
[0083] The fiber optic module connects to the FPGA via the Aurora interface to enable rapid output of massive amounts of data (such as ADC data, DDC data, pulse compression data, etc.). The output peer module is a data storage module (not this module, but an external module).
[0084] The clock management unit receives a reference clock from an external frequency source (not this module, but another external module), and generates a 1GHz sampling clock for the ADC module, a 100MHz operating clock for the FPGA processor, a 1GHz main frequency clock for the DSP, and an 800MHz clock for its DDR through the clock management chip. Simultaneously, an onboard crystal oscillator is provided on this board, connected to the clock management chip as a clock backup, allowing for single-board debugging when external input clocks are unavailable.
[0085] The power management unit input is DC12~36V voltage, with a power of 300W, and performs two functions. (1) Convert the +12V, +3.3V, +1.8V, +1.2V and +1.0V voltages required for the operation of this module; (2) Provide power to the frequency source, receiver and frequency converter module, optimize the external module design interface, integrate power supply and control signals, and optimize the overall circuit design.
[0086] Based on the above technical solution, this application has the following advantages:
[0087] This design employs an integrated architecture combining a single ZYNQ chip, DSP, FPGA, DAC, and multi-channel ADC to implement system control, signal generation, signal sampling, and signal processing functions within the radar system. The entire radar processing workflow, from command generation, signal generation, transmission control, echo acquisition to signal processing, is implemented on a single board. High integration, small size, and light weight significantly reduce costs. Optimal energy efficiency and processing performance are achieved by rationally allocating resources to the most suitable processor platform based on the characteristics of each processing task. Numerous external physical connections between modules are eliminated, with data exchange via printed circuit lines and internal interconnections within the FPGA chip. This reduces potential failure points caused by connectors and cables, improving signal transmission reliability and timing accuracy. Different interfaces are used for different applications, ensuring high speed while improving transmission reliability and the timing accuracy of critical trigger signals. In practical applications, this design features low power consumption and a short production cycle, facilitating radar miniaturization.
[0088] Corresponding to the above-described heterogeneous platform radar control and signal processing device embodiments, this application also provides a radar system, including the radar system described above.
[0089] The radar system described above achieves the same technical effect as the radar system embodiments described above, and will not be repeated here to avoid duplication.
[0090] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of this application is not limited to performing functions in the order shown or discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.
[0091] It is understood that the embodiments of this application have been described above in conjunction with the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. As those skilled in the art will know, various changes or equivalent substitutions can be made to these features and embodiments without departing from the spirit and scope of the invention. Furthermore, those skilled in the art, under the guidance or instruction of this application, can modify these features and embodiments to adapt to specific situations and materials without departing from the spirit and scope of the invention. Therefore, this invention is not limited to the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are within the protection scope of this invention.
Claims
1. A heterogeneous platform radar control and signal processing device, characterized in that, include: The control and processing unit, signal interface unit, clock management unit, and power management unit are integrated into the single board; The control and processing unit includes three heterogeneous processors: ZYNQ, FPGA, and DSP. The ZYNQ processor includes a PS terminal and a PL terminal. The PS terminal runs the main control software, which is used for overall system status control, resource scheduling, instruction forwarding, and echo data processing and forwarding. The PL terminal is configured to implement timing, wave control, signal generation, and data interface driving functions. The FPGA processor is configured to perform signal acquisition, digital downconversion filtering, digital beamforming, pulse compression, coherent accumulation, and moving target detection functions. The DSP processor is configured to implement constant false alarm rate (CFAR) detection and uses a multi-core parallel processing architecture to segment data for different distance ranges. The signal interface unit is connected to the control and processing unit and includes a timing interface, a synchronous / asynchronous serial port, a DAC interface, a multi-channel ADC module, and an optical fiber module, used to realize signal and data interaction between the overall device and the external radar subsystem. The clock management unit is connected to the control and processing unit and the signal interface unit. It is used to receive an external reference clock and generate the working clock required by each unit in the device. It is also equipped with an on-board crystal oscillator backup function. The power management unit is used to convert the input voltage into multiple power supply voltages required by the internal and external subsystems of the device.
2. The heterogeneous platform radar control and signal processing device according to claim 1, characterized in that, The control and processing unit interacts with external systems for data and commands via Ethernet; within the control and processing unit: The ZYNQ processor and the FPGA processor are interconnected via LVDS, GTX and the first GPIO interface; the LVDS interface is used for uplink control command transmission, the GTX interface is used for inter-chip data interaction, and the first GPIO interface is used for inter-chip timing trigger signal transmission. The DSP processor and the FPGA processor are interconnected through a second GPIO, a first SRIO, and a first EMIF interface; the second GPIO interface is used for inter-chip timing trigger signal transmission, the first SRIO interface is used for inter-chip data interaction, and the first EMIF interface is used for instruction transmission. The DSP processor and the ZYNQ processor are interconnected through a third GPIO, a second SRIO, and a second EMIF interface; the third GPIO is used for inter-chip timing trigger signal transmission, the second SRIO is used for inter-chip data interaction, and the second EMIF is used for instruction transmission.
3. The heterogeneous platform radar control and signal processing device according to claim 1, characterized in that, The PL terminal includes: The timing module is used to generate all the timing signals required for the operation of the entire machine. The beam control module is used to control the TR_T, TR_R, Data, and CLK signals required for the operation of all T / R components, and to control the normal transmission and reception of signals by the T / R components of the array system. The signal generation module is used to output the intermediate frequency digital baseband signal to the DAC module, so that the DAC interface can generate an intermediate frequency analog signal; The data interface driver module is used to generate the interface data required to control the external systems; the external systems include: frequency source, receiver and servo system.
4. The heterogeneous platform radar control and signal processing device according to claim 1, characterized in that, The FPGA processor includes: The signal acquisition module is used to sample intermediate frequency analog signals and convert them into digital signals; The digital downconversion filter module is used to perform quadrature digital downconversion on intermediate frequency digital signals, transforming the signals into zero intermediate frequency (IF) IQ signals; and adaptively filtering according to the actual signal bandwidth. The digital beamforming module is used to complete digital beamforming, forming azimuth difference and elevation difference beams from 4-quadrant echo data, or forming multiple receiving beams in the azimuth and elevation dimensions as needed; The pulse compression module is used to compress linear frequency modulated signals into pulses. The coherent accumulation module is used to coherently accumulate the signal for each repetition cycle. The moving target detection module is used to implement MTI and MTD functions and has the ability to filter out stationary ground targets.
5. The heterogeneous platform radar control and signal processing device according to claim 1, characterized in that, The DSP processor includes: The constant false alarm rate (CFAR) detection module is used to perform CFAR detection on targets. When handling long-distance, high-point CFAR processing, the data is segmented by distance, and different distance segments are assigned to different cores for processing, thereby improving processing efficiency.
6. The heterogeneous platform radar control and signal processing device according to claim 1, characterized in that, The signal interface unit includes: At least 5 ADC modules, of which the first 4 are used for radar echo signal sampling and the 5th is used for array calibration signal sampling. The digital signal after sampling by the ADC is transmitted to the FPGA processor. The DAC interface is used to receive the digital baseband signal generated by the ZYNQ processor and convert it into an analog baseband signal for output. The fiber optic module is connected to the FPGA processor via the Aurora interface and is used to quickly output massive amounts of data from inside the device to an external data storage module.
7. A radar system, characterized in that, Includes the heterogeneous platform radar control and signal processing apparatus as described in any one of claims 1-6.
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