A device debugging method, device, equipment and medium

Abstract

The present application discloses a device debugging method, device, equipment and medium, relating to the field of device maintenance. The method is applied to a debugging unit that is connected to a debugging unit through a cable at one end and connected to the universal asynchronous receiver / transmitter (UART) pins of a unit to be debugged at the other end, and includes: respectively determining whether start bit information is contained in a first preset buffer area and a second preset buffer area; determining the signal line corresponding to the buffer area containing the start bit information as the data sending end signal line of the unit to be debugged, and determining the correspondence between each signal and the data sending end signal line and the data receiving end signal line of the unit to be debugged; connecting the unit to be debugged to a preset data conversion device by using the correspondence, and realizing the conversion between the universal asynchronous transceiver signal and the target debugging signal by using the preset data conversion device, so as to enable the debugging unit to debug the unit to be debugged. The present invention realizes the correct connection of the signal lines between the UART pins and the debugging unit, and can realize plug and play.

Description

Technical Field

[0001] The present invention relates to the field of equipment maintenance, and particularly to a method, device, equipment and medium for equipment debugging. Background Art

[0002] During the server design process, debugging interfaces are reserved for monitoring and debugging in aspects such as design, development, and maintenance. Common debugging interfaces on current servers include I2C (Inter-Integrated Circuit), UART (Universal Asynchronous Receiver / Transmitter), JTAG (Joint Test Action Group), USB (Universal Serial Bus), etc. Among them, for the status monitoring of some key devices, one or more UART interfaces are reserved to be respectively connected to the relevant main functional modules inside the device. When in use, the user connects different UART ports to observe the active states of the corresponding functional modules.

[0003] In the prior art, when using a debugger to debug a device through UART, due to the lack of a unified specification in the UART pin design, when using a UART debugger to connect different UART pins, it is necessary to pre-check the data to determine the pin definitions of the UART pins of the device and the signal definitions of each pin of the debugger, and then connect the TXD (Transmit Data) and RXD (Receive Data) of the debugger to the RXD of the UART pins of the device to be debugged. Only after that can the data transmission between the debugger and the device to be debugged be realized. In the actual operation process, when the user connects and debugs UART pins with different pin definitions, it is easy to get confused and it is necessary to adjust the connection position multiple times to achieve the data transmission between the device under test and the debugger, wasting time and energy.

[0004] As can be seen from the above, in the process of using a debugger to debug a device through UART, how to avoid the situation of low pin connection efficiency of UART pins caused by the confusion of UART pins with different pin definitions is a problem to be solved in this field. Summary of the Invention

[0005] In view of this, the purpose of the present invention is to provide a method, device, equipment and medium for equipment debugging, which can realize the correct connection of signal lines between UART pins and a debugging unit, and can achieve plug-and-play when the debugging unit is connected to the UART pins. The specific scheme is as follows:

[0006] In a first aspect, the present application discloses a device debugging method, which is applied to a debugging unit connected to a debugging unit through a cable at one end and connected to the universal asynchronous receiver / transmitter pin of the unit to be debugged at the other end, and includes:

[0007] Determine whether the start bit information is contained in the first preset buffer and the second preset buffer respectively; the first preset buffer and the second preset buffer each store the universal asynchronous transceiver signals sent by the unit to be debugged and received through the preset first signal line and second signal line respectively;

[0008] Determine the signal line corresponding to the buffer containing the start bit information as the data sending end signal line of the unit to be debugged, and determine the correspondence between the first signal line, the second signal line, the data sending end signal line and the data receiving end signal line of the unit to be debugged;

[0009] Use the correspondence to connect the data sending end signal line and the data receiving end signal line of the unit to be debugged to the data receiving end and the data sending end of the preset data conversion device respectively, and use the preset data conversion device to realize the conversion between the universal asynchronous transceiver signal and the target debugging signal, so that the debugging unit can use the target debugging signal to debug the unit to be debugged.

[0010] Optionally, before respectively determining whether the start bit information is contained in the first preset buffer and the second preset buffer, it further includes:

[0011] Receive the universal asynchronous transceiver signal sent by the unit to be debugged through the first signal line and the second signal line;

[0012] Convert the level of the universal asynchronous transceiver signal to a preset debugging level, and store the universal asynchronous transceiver signal after level conversion in the preset buffer corresponding to the corresponding signal line.

[0013] Optionally, the determining the signal line corresponding to the buffer containing the start bit information as the data sending end signal line of the unit to be debugged, and determining the correspondence between the first signal line, the second signal line, the data sending end signal line and the data receiving end signal line of the unit to be debugged includes:

[0014] Determine the signal line corresponding to the buffer containing the start bit information as the data sending end signal line of the unit to be debugged, and determine the other signal line except the data sending end signal line of the unit to be debugged among the first signal line and the second signal line as the data receiving end signal line of the unit to be debugged;

[0015] Determine the correspondence between the first signal line, the second signal line, the data transmission end signal line, and the data reception end signal line of the unit to be debugged.

[0016] Optionally, after respectively determining whether the first preset buffer and the second preset buffer contain start bit information, the method further includes:

[0017] If neither the first preset buffer nor the second preset buffer contains start bit information, send a data request to the unit to be debugged using a third preset buffer based on a first control strategy, and determine whether the first preset buffer receives a universal asynchronous transceiver signal containing start bit information; the third preset buffer is located in the line where the data transmission end of the preset data conversion device is located;

[0018] If the first preset buffer receives a universal asynchronous transceiver signal containing start bit information, determine the first signal line as the data transmission end signal line of the unit to be debugged, and perform the step of determining the correspondence between the first signal line, the second signal line, the data transmission end signal line, and the data reception end signal line of the unit to be debugged;

[0019] If the first preset buffer does not receive a universal asynchronous transceiver signal containing start bit information, send a data request to the unit to be debugged using a third preset buffer based on a second control strategy, and determine whether the second preset buffer receives a universal asynchronous transceiver signal containing start bit information;

[0020] If the second preset buffer receives a universal asynchronous transceiver signal containing start bit information, determine the second signal line as the data transmission end signal line of the unit to be debugged, and perform the step of determining the correspondence between the first signal line, the second signal line, the data transmission end signal line, and the data reception end signal line of the unit to be debugged.

[0021] If the second preset buffer does not receive a universal asynchronous transceiver signal containing start bit information, determine the working state of the unit to be debugged as abnormal, and control a preset flashing light to emit an alarm signal.

[0022] Optionally, the sending a data request to the unit to be debugged using a third preset buffer based on a first control strategy includes:

[0023] Pull the SEL signal low to a low level, and send a data request to the unit to be debugged using a third preset buffer;

[0024] Correspondingly, the sending a data request to the unit to be debugged using a third preset buffer based on a second control strategy includes:

[0025] Pull the SEL signal high to a high level, and send a data request to the unit to be debugged using the third preset buffer.

[0026] Optionally, the conversion of the universal asynchronous transceiver signal and the target debug signal is implemented using the preset data conversion device, so that the debug unit can debug the unit to be debugged using the target debug signal, including:

[0027] Implement the conversion of the universal asynchronous transceiver signal and the universal serial bus signal using the preset data conversion device, so that the debug unit can debug the unit to be debugged using the target debug signal through the universal serial bus interface preset in the debug unit.

[0028] Optionally, the connection of the data sending end signal line and the data receiving end signal line of the unit to be debugged to the data receiving end and the data sending end of the preset data conversion device respectively using the corresponding relationship includes:

[0029] Determine the SEL signal value based on the corresponding relationship;

[0030] Use the preset signal conversion device to connect the data sending end signal line and the data receiving end signal line of the unit to be debugged to the data receiving end and the data sending end of the preset data conversion device respectively based on the line connection method corresponding to the SEL signal value.

[0031] In a second aspect, the present application discloses a device debugging device, which is applied to a debug unit connected to a unit to be debugged through a cable at one end and connected to the universal asynchronous transceiver pin of the unit to be debugged at the other end, including:

[0032] An information determination module, configured to respectively determine whether the start bit information is contained in the first preset buffer and the second preset buffer; the first preset buffer and the second preset buffer each store the universal asynchronous transceiver signals sent by the unit to be debugged and received through the preset first signal line and second signal line respectively;

[0033] A signal line determination module, configured to determine the signal line corresponding to the buffer containing the start bit information as the data sending end signal line of the unit to be debugged, and determine the corresponding relationship between the first signal line, the second signal line, the data sending end signal line, and the data receiving end signal line of the unit to be debugged;

[0034] A signal line connection module is used to connect the data sending end signal line and the data receiving end signal line of the unit to be debugged to the data receiving end and the data sending end of a preset data conversion device respectively according to the corresponding relationship, and use the preset data conversion device to implement the conversion between the universal asynchronous transceiver signal and the target debugging signal, so that the debugging unit can use the target debugging signal to debug the unit to be debugged.

[0035] In a third aspect, the present application discloses an electronic device, including:

[0036] A memory for storing a computer program;

[0037] A processor for executing the computer program to implement the foregoing device debugging method.

[0038] In a fourth aspect, the present application discloses a computer storage medium for storing a computer program; wherein, when the computer program is executed by a processor, the steps of the foregoing disclosed device debugging method are implemented.

[0039] In the present application, one end of the debugging unit is connected to the debugging unit through a cable, and the other end is connected to the universal asynchronous transceiver pin of the unit to be debugged. The debugging unit first determines whether the start bit information is contained in the first preset buffer and the second preset buffer respectively; the first preset buffer and the second preset buffer each store the universal asynchronous transceiver signal sent by the unit to be debugged and received through the preset first signal line and second signal line respectively; determine the signal line corresponding to the buffer containing the start bit information as the data sending end signal line of the unit to be debugged, and determine the corresponding relationship between the first signal line, the second signal line, the data sending end signal line and the data receiving end signal line of the unit to be debugged; connect the data sending end signal line and the data receiving end signal line of the unit to be debugged to the data receiving end and the data sending end of a preset data conversion device respectively according to the corresponding relationship, and use the preset data conversion device to implement the conversion between the universal asynchronous transceiver signal and the target debugging signal, so that the debugging unit can use the target debugging signal to debug the unit to be debugged. In this way, the present application monitors whether the data in the preset buffer contains a start bit to determine whether the corresponding signal line is the data sending end signal line of the unit to be debugged, so as to accurately implement the connection of the signal line between the UART pin and the debugging unit without knowing the different pin definitions of the UART pin of the unit to be debugged, and can achieve plug and play when the debugging unit connects to the UART pin. Description of the Drawings

[0040] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only the embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained according to the provided drawings.

[0041] Figure 1 It is a flowchart of a device debugging method provided by this application;

[0042] Figure 2 It is a schematic diagram of the device connection relationship provided by this application;

[0043] Figure 3 It is a schematic diagram of the overall solution provided by this application;

[0044] Figure 4 It is a flowchart of a specific device debugging method provided by this application;

[0045] Figure 5 It is the first schematic diagram of line connection provided by this application;

[0046] Figure 6 It is the second schematic diagram of line connection provided by this application;

[0047] Figure 7 It is a schematic diagram of the structure of a device debugging device provided by this application;

[0048] Figure 8 It is a structural diagram of an electronic device provided by this application. Detailed implementation manners

[0049] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0050] In the prior art, due to the confusion of UART pin headers with different pin definitions, the pin connection efficiency of the UART pin headers is low. In this application, the correct connection of the signal lines between the UART pin headers and the debugging unit can be achieved, and plug-and-play can be realized when the debugging unit is connected to the UART pins.

[0051] The embodiments of the present invention disclose a device debugging method, which is applied to a debugging unit that is connected to a debugging unit through a cable at one end and connected to the universal asynchronous receiver / transmitter pin header of the unit to be debugged at the other end. See Figure 1 As described, the method includes:

[0052] Step S11: Determine whether the start bit information is contained in the first preset buffer and the second preset buffer respectively; the first preset buffer and the second preset buffer each store the universal asynchronous transceiver signals sent by the unit to be debugged and received through a preset first signal line and a second signal line respectively.

[0053] The present invention is applicable to scenarios where a UART pin is required to connect a debugger for debugging in the motherboard design and debugging of electronic devices such as mobile phones and servers. In this embodiment, the first signal line and the second signal line are connected to the UART signals of the UART pins of the unit to be debugged, and are used to transmit the data sent by the unit to be debugged. It can be understood that in this embodiment, the first preset buffer and the second preset buffer respectively correspond to the first signal line and the second signal line, that is, the data received by the first signal line will be stored in the first preset buffer, and the data received by the second signal line will be stored in the second preset buffer.

[0054] In this embodiment, before determining whether the start bit information is contained in the first preset buffer and the second preset buffer respectively, it further includes: receiving the universal asynchronous transceiver signals sent by the unit to be debugged through the first signal line and the second signal line; converting the level of the universal asynchronous transceiver signals into a preset debugging level, and storing the universal asynchronous transceiver signals after level conversion into the preset buffer corresponding to the respective signal lines.

[0055] In the specific implementation manner of this embodiment, to ensure that the level states of the signal lines are consistent with the level states of the debugging unit, a level conversion unit is added to the input side of the signal lines. After the first signal line and the second signal line receive the UART signals sent by the unit to be debugged, the level conversion unit will perform level conversion on the UART signals and convert the level state of the input signals into the internal working level of the debugging unit. After the level conversion, the UART signals will be stored in the corresponding preset buffers.

[0056] Step S12: Determine the signal line corresponding to the buffer containing the start bit information as the data sending end signal line of the unit to be debugged, and determine the corresponding relationship between the first signal line, the second signal line, the data sending end signal line and the data receiving end signal line of the unit to be debugged.

[0057] In this embodiment, determining the signal line corresponding to the buffer area containing the start bit information as the data transmission end signal line of the unit to be debugged, and determining the corresponding relationships among the first signal line, the second signal line, the data transmission end signal line, and the data reception end signal line of the unit to be debugged includes: determining the signal line corresponding to the buffer area containing the start bit information as the data transmission end signal line of the unit to be debugged, and determining the other signal line except the data transmission end signal line of the unit to be debugged among the first signal line and the second signal line as the data reception end signal line of the unit to be debugged; determining the corresponding relationships among the first signal line, the second signal line, the data transmission end signal line, and the data reception end signal line of the unit to be debugged.

[0058] UART can convert parallel data into serial data for output. It has only two data lines, TXD, and does not require a clock but synchronizes data through a pre-agreed baud rate. In actual use, as Figure 2 shown, it is necessary to connect the TXD of device 1 to the RXD of device 2, and at the same time connect the RXD of device 1 to the TXD of device 2. That is, the data sent by the transmitter of device 1 is received by the receiver of device 2. Similarly, when device 1 receives data, the receiver of device 1 will receive the data sent from the transmitter of device 2.

[0059] In the present invention, the principle of analyzing the information in the first preset buffer and the second preset buffer is mainly based on the UART communication protocol. In the specific implementation process, when the sending end sends data, a start bit, a parity check bit (optional), and a stop bit will be added to the parallel data to be sent. Since the sending end level of the UART will be at a high level all the time when there is no signal transmission, when starting to send data, the sending end will pull down the connected level for one clock cycle, then start to transmit the parallel data to be sent, and finally add the parity check bit (optional) and the stop bit to complete the transmission of a data packet. Therefore, if one preset buffer has a start bit while the other preset buffer does not have a start bit, it can be determined that there is a process of the unit to be debugged transmitting data to the debugging unit in the signal line connected to the preset buffer with the start bit. Therefore, in this embodiment, the signal line corresponding to the buffer containing the start bit information is determined as the data sending end signal line of the unit to be debugged, that is, the signal line connected to the preset buffer containing the start bit information is the TXD of the unit to be debugged, and then the signal line connected to the other preset buffer is the RXD of the unit to be debugged. That is to say, this step can determine the corresponding relationship between the first signal line and the second signal connection line and the TXD and RXD of the unit to be debugged. That is to say, this step can accurately determine which end of the UART pin is the TXD and which end is the RXD without knowing the different pin definitions of the UART pins of the unit to be debugged.

[0060] Step S13: Use the corresponding relationship to connect the data sending end signal line and the data receiving end signal line of the unit to be debugged to the data receiving end and the data sending end of the preset data conversion device respectively, and use the preset data conversion device to implement the conversion between the universal asynchronous transceiver signal and the target debugging signal, so that the debugging unit can use the target debugging signal to debug the unit to be debugged.

[0061] In the specific implementation manner of this embodiment, a signal line connection module can be set. After determining the corresponding relationship between the first signal line and the second signal connection line and the TXD and RXD of the unit to be debugged in step S12, the first signal line and the second signal line can be respectively connected to the data receiving end and the data sending end of the preset data conversion device based on the way that the receiving end of the unit to be debugged is connected to the sending end of the preset data conversion device and the sending end of the unit to be debugged is connected to the receiving end of the preset data conversion device.

[0062] In this embodiment, a preset data conversion device is provided in the debugging unit for converting a universal asynchronous transceiver signal into a target debugging signal, where the target debugging signal is a signal recognizable by the debugging unit. The preset data device can also be connected to a preset debugging interface. By connecting a debugging device to the preset debugging interface, the target debugging signal can be transmitted to the debugging device. In a preferred embodiment, the target debugging signal can be a USB signal, and the preset debugging interface is a USB interface.

[0063] As Figure 3 shown is an overall schematic diagram of a solution proposed in this application. The part within the dashed box in the figure is the debugging unit proposed in the present invention. Taking the computer on the left as an example of the debugging unit in the figure, the UART pins on the right are the UART pins of the unit to be debugged. The overall process of this solution is as follows: After the first signal line and the second signal line receive the UART signals from the UART pins, the UART signals are respectively stored in the first preset buffer and the second preset buffer after level conversion. The IN1 on the first signal line and the IN2 on the second signal line are respectively connected to the RXD and TXD of the USB to UART module through the signal connection module within the small dashed box in the figure. The signal connection module sets the wiring A1 for the RXD of the USB to UART module, and based on the corresponding relationship between the first signal line, the second signal line, the data sending end signal line, and the data receiving end signal line of the unit to be debugged, sets two wirings B1 and B2 for the RXD of the USB to UART module to achieve accurate signal connection. After the signal connection module connects the lines, the RXD of the USB to UART module can receive the UART signal transmitted from the unit to be debugged and convert the UART signal into a USB signal. The USB signal can then be transmitted to the computer through the USB interface provided in the debugging unit via a cable, and the user can use the debugging unit to debug the unit to be debugged. It can be understood that the signal line 1 and the signal line 2 in the figure are respectively the first signal line and the second signal line, and the data buffer 1 and the data buffer 2 are respectively the first preset buffer and the second preset buffer. IN1 is the signal after the first signal line passes through the internal level conversion of the debugging unit, IN2 is the signal after the second signal line passes through the internal level conversion of the debugging unit, and A1 is connected to the TXD of the USB to UART module.

[0064] In this embodiment, one end of the debugging unit is connected to the debugging unit through a cable, and the other end is connected to the pins of the universal asynchronous receiver / transmitter (UART) of the unit to be debugged. The debugging unit first determines whether start bit information is contained in the first preset buffer and the second preset buffer respectively; the first preset buffer and the second preset buffer each store the UART signals sent by the unit to be debugged and received through a preset first signal line and a second signal line respectively; the signal line corresponding to the buffer containing the start bit information is determined as the data transmission end signal line of the unit to be debugged, and the corresponding relationship between the first signal line, the second signal line, the data transmission end signal line and the data reception end signal line of the unit to be debugged is determined; the data transmission end signal line and the data reception end signal line of the unit to be debugged are respectively connected to the data reception end and the data transmission end of a preset data conversion device by using the corresponding relationship, and the preset data conversion device is used to implement the conversion between the UART signal and the target debugging signal, so that the debugging unit can use the target debugging signal to debug the unit to be debugged. In this way, the present application determines whether the start bit is contained in the data in the preset buffer to judge whether the corresponding signal line is the data transmission end signal line of the unit to be debugged, so as to accurately determine which end of the UART pins is the TXD and which end is the RXD without knowing the different pin definitions of the UART pins of the unit to be debugged, so as to realize the correct connection of the signal lines between the UART pins and the debugging unit, and the plug-and-play function can be realized when the debugging unit is connected to the UART pins.

[0065] Figure 4 It is a flowchart of a specific device debugging method provided by an embodiment of the present application. Refer to Figure 4 As shown, the method includes:

[0066] Step S21: Determine whether start bit information is contained in the first preset buffer and the second preset buffer respectively; the first preset buffer and the second preset buffer each store the UART signals sent by the unit to be debugged and received through a preset first signal line and a second signal line respectively.

[0067] Among them, for the more specific processing process of step S21, reference can be made to the corresponding content disclosed in the foregoing embodiment, and details will not be repeated here.

[0068] Step S22: Determine the signal line corresponding to the buffer containing the start bit information as the data transmission end signal line of the unit to be debugged, and determine the corresponding relationship between the first signal line, the second signal line, the data transmission end signal line and the data reception end signal line of the unit to be debugged.

[0069] Among them, for a more specific processing procedure regarding step S22, reference can be made to the corresponding content disclosed in the foregoing embodiments, and details will not be elaborated herein.

[0070] Step S23: Determine the SEL signal value based on the corresponding relationship.

[0071] In this embodiment, the SEL (select) signal value is determined based on the corresponding relationship, and the SEL signal value is used to control the applicable line connection method in the signal line connection module. In a specific implementation process, there are two cases for the corresponding relationship between the first signal line, the second signal line, the data sending end signal line, and the data receiving end signal line of the unit to be debugged. Specifically, when the corresponding relationship is that the first signal line is connected to the TXD of the UART pin header and the second signal line is connected to the RXD of the UART pin header, the SEL level state is controlled to be 0; when the corresponding relationship is that the first signal line is connected to the RXD of the UART pin header and the second signal line is connected to the TXD of the UART pin header, the SEL level state is controlled to be 1.

[0072] Step S24: Use a preset signal conversion device to connect the data sending end signal line and the data receiving end signal line of the unit to be debugged to the data receiving end and the data sending end of the preset data conversion device respectively based on the line connection method corresponding to the SEL signal value.

[0073] The following table is a signal connection relationship table proposed in this application, which shows the connection states of the corresponding IN1 and IN2 when the SEL signal is 0, 1, or HZ (high impedance). It should be noted that the SEL is in a high impedance state by default.

[0074] Table 1

[0075]

[0076]

[0077] In a specific implementation manner, when the SEL level state is 0, as Figure 5 shown, IN1 after level conversion of the first signal line is connected to the RXD of the USB to UART module, and IN2 after level conversion of the second signal line is connected to the TXD of the USB to UART module; when the SEL level state is 1, as Figure 6 shown, IN1 after level conversion of the first signal line is connected to the TXD of the USB to UART module, and IN2 after level conversion of the second signal line is connected to the RXD of the USB to UART module.

[0078] Step S25: Use the preset data conversion device to implement the conversion between the universal asynchronous receiver / transmitter (UART) signal and the universal serial bus (USB) signal, so that the debugging unit can debug the unit to be debugged through the preset USB interface in the debugging unit and by using the target debugging signal.

[0079] In this embodiment, after respectively determining whether the first preset buffer and the second preset buffer contain start bit information, it further includes: If neither the first preset buffer nor the second preset buffer contains start bit information, a data request is sent to the unit to be debugged by using the third preset buffer based on the first control strategy, and it is determined whether the first preset buffer receives a UART signal containing start bit information; the third preset buffer is located in the line where the data sending end of the preset data conversion device is located; If the first preset buffer receives a UART signal containing start bit information, the first signal line is determined as the data sending end signal line of the unit to be debugged, and the step of determining the corresponding relationship between the first signal line, the second signal line, the data sending end signal line and the data receiving end signal line of the unit to be debugged is executed; If the first preset buffer does not receive a UART signal containing start bit information, a data request is sent to the unit to be debugged by using the third preset buffer based on the second control strategy, and it is determined whether the second preset buffer receives a UART signal containing start bit information; If the second preset buffer receives a UART signal containing start bit information, the second signal line is determined as the data sending end signal line of the unit to be debugged, and the step of determining the corresponding relationship between the first signal line, the second signal line, the data sending end signal line and the data receiving end signal line of the unit to be debugged is executed. If the second preset buffer does not receive a UART signal containing start bit information, the working state of the unit to be debugged is determined to be abnormal, and a warning signal is controlled to be emitted by the preset flashing light. It can be understood that Figure 5 and Figure 6 the data cache 4 in

[0080] In this embodiment, the step of sending a data request to the unit to be debugged by using the third preset buffer based on the first control strategy may include: pulling the SEL signal low to a low level, and sending a data request to the unit to be debugged by using the third preset buffer; correspondingly, the step of sending a data request to the unit to be debugged by using the third preset buffer based on the second control strategy includes: pulling the SEL signal high to a high level, and sending a data request to the unit to be debugged by using the third preset buffer.

[0081] In this embodiment, when it is simultaneously monitored that there is no data transmission in both preset buffers, first, as Figure 5As shown, the SEL signal will be pulled low to a low level. IN1 is connected to B1, and IN2 is connected to A1. At this time, the data buffer 4 in the figure can be used as the third preset buffer area to send a data request to the unit to be debugged through the second signal line. The principle is to simulate a debugging device sending data to the unit to be debugged to verify whether the first signal line is connected to the TXD of the UART pin header and whether the second signal line is connected to the RXD of the UART pin header. If the first preset buffer area receives a universal asynchronous transceiver signal containing start bit information, it indicates that the verification is successful, and the corresponding relationship between the first signal line, the second signal line, the data sending end signal line, and the data receiving end signal line of the unit to be debugged can be determined. If the first preset buffer area does not receive a universal asynchronous transceiver signal containing start bit information, it indicates that the verification fails. At this time, as Figure 6 shown, the SEL signal will be pulled high to a high level. IN1 is connected to A1, and IN2 is connected to B2. The data buffer 4 in the figure is used as the third preset buffer area to send a data request to the unit to be debugged through the first signal line, verifying whether the first signal line is connected to the RXD of the UART pin header and whether the second signal line is connected to the TXD of the UART pin header. If the second preset buffer area receives a universal asynchronous transceiver signal containing start bit information, it indicates that the verification is successful, and the corresponding relationship between the first signal line, the second signal line, the data sending end signal line, and the data receiving end signal line of the unit to be debugged can be determined. After the above verification steps, if the second preset buffer area still does not receive a universal asynchronous transceiver signal containing start bit information, it indicates that the working state of the unit to be debugged is abnormal and normal communication cannot be completed. The LED is controlled to flash to emit an alarm signal outward.

[0082] In this embodiment, the SEL signal value is determined through the corresponding relationship between the first signal line, the second signal line, the data sending end signal line, and the data receiving end signal line of the unit to be debugged, and the applicable line connection method in the signal line connection module is controlled based on the SEL signal value. It is also proposed that when neither the first preset buffer area nor the second preset buffer area contains start bit information, a data request is sent to the unit to be debugged using the third preset buffer area to independently detect the TXD and RXD of the UART pin header of the unit to be debugged in the way of simulating a debugging device sending data to the unit to be debugged. In this way, through the debugging unit proposed in the present invention, the correct connection of the UART pin header and the signal lines of the debugging unit can be automatically achieved through the built-in signal recognition and signal connection method. When debugging the unit to be debugged, there is no need to look up information to confirm the different pin definitions of the UART pin header, avoiding wiring confusion caused by different pin definitions, and further avoiding the problem that connection errors cannot be debugged.

[0083] See Figure 7As shown in the figure, an embodiment of the present application discloses a device debugging apparatus, which is applied to a debugging unit that is connected to a debugging unit through a cable at one end and connected to the universal asynchronous receiver / transmitter pin of the unit to be debugged at the other end. Specifically, it may include:

[0084] An information determination module 11, configured to respectively determine whether start bit information is contained in a first preset buffer and a second preset buffer; the first preset buffer and the second preset buffer each store a universal asynchronous transceiver signal sent by the unit to be debugged and received through a preset first signal line and a second signal line respectively;

[0085] A signal line determination module 12, configured to determine the signal line corresponding to the buffer containing the start bit information as the data sending end signal line of the unit to be debugged, and determine the correspondence between the first signal line, the second signal line, the data sending end signal line and the data receiving end signal line of the unit to be debugged;

[0086] A signal line connection module 13, configured to use the correspondence to respectively connect the data sending end signal line and the data receiving end signal line of the unit to be debugged to the data receiving end and the data sending end of a preset data conversion device, and use the preset data conversion device to implement the conversion between the universal asynchronous transceiver signal and the target debugging signal, so that the debugging unit can use the target debugging signal to debug the unit to be debugged.

[0087] In this application, one end of the debugging unit is connected to the debugging unit through a cable, and the other end is connected to the pins of the universal asynchronous receiver / transmitter (UART) of the unit to be debugged. The debugging unit first determines whether the start bit information is contained in the first preset buffer and the second preset buffer respectively; the first preset buffer and the second preset buffer each store the UART signals sent by the unit to be debugged and received through the preset first signal line and second signal line respectively; the signal line corresponding to the buffer containing the start bit information is determined as the data transmission end signal line of the unit to be debugged, and the corresponding relationship between the first signal line, the second signal line, the data transmission end signal line and the data reception end signal line of the unit to be debugged is determined; the data transmission end signal line and the data reception end signal line of the unit to be debugged are respectively connected to the data reception end and the data transmission end of the preset data conversion device by using the corresponding relationship, and the preset data conversion device is used to realize the conversion between the UART signal and the target debugging signal, so that the debugging unit can use the target debugging signal to debug the unit to be debugged. In this way, this application determines whether the corresponding signal line is the data transmission end signal line of the unit to be debugged by monitoring whether the data in the preset buffer contains the start bit, so as to accurately determine which end of the UART pins is the TXD and which end is the RXD without knowing the different pin definitions of the UART pins of the unit to be debugged, so as to realize the correct connection of the signal lines between the UART pins and the debugging unit, and the plug-and-play function can be realized when the debugging unit is connected to the UART pins.

[0088] Further, the embodiment of this application also discloses an electronic device. Figure 8 It is a structural diagram of the electronic device 20 shown according to the exemplary embodiment, and the content in the figure cannot be regarded as any limitation on the scope of use of this application.

[0089] Figure 8 It is a structural schematic diagram of an electronic device 20 provided by the embodiment of this application. The electronic device 20 may specifically include: at least one processor 21, at least one memory 22, a power supply 23, a display screen 24, an input / output interface 25, a communication interface 26, and a communication bus 27. Among them, the memory 22 is used to store a computer program, and the computer program is loaded and executed by the processor 21 to implement the relevant steps in the device debugging method disclosed in any of the foregoing embodiments. In addition, the electronic device 20 in this embodiment may specifically be an electronic computer.

[0090] In this embodiment, the power supply 23 is used to provide operating voltage for each hardware device on the electronic device 20; the communication interface 26 can create a data transmission channel between the electronic device 20 and external devices, and the communication protocol it follows can be any communication protocol applicable to the technical solution of this application, and no specific limitation is imposed on it here; the input / output interface 25 is used to obtain external input data or output data to the outside, and its specific interface type can be selected according to specific application requirements, and no specific limitation is made here.

[0091] In addition, the memory 22, as a carrier for resource storage, can be a read-only memory, a random access memory, a magnetic disk, an optical disk, etc. The resources stored thereon can include an operating system 221, a computer program 222, virtual machine data 223, etc., and the virtual machine data 223 can include various kinds of data. The storage method can be transient storage or permanent storage.

[0092] Among them, the operating system 221 is used to manage and control each hardware device and the computer program 222 on the electronic device 20, and it can be Windows Server, Netware, Unix, Linux, etc. In addition to the computer program that can be used to complete the device debugging method executed by the electronic device 20 disclosed in any of the foregoing embodiments, the computer program 222 can further include computer programs that can be used to complete other specific tasks.

[0093] Furthermore, this application also discloses a computer-readable storage medium. The computer-readable storage medium mentioned here includes a random access memory (Random Access Memory, RAM), internal memory, read-only memory (Read-Only Memory, ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disks, magnetic disks, optical disks, or any other form of storage medium well-known in the technical field. Among them, when the computer program is executed by a processor, it implements the device debugging method disclosed above. For the specific steps of this method, reference can be made to the corresponding content disclosed in the foregoing embodiments, and details are not described here again.

[0094] In this specification, the various embodiments are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. For the same or similar parts among the embodiments, reference can be made to each other. For the devices disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple. For the relevant parts, reference can be made to the description in the method section. Professionals can further realize that the units and algorithm steps of the examples described in combination with the embodiments disclosed in this article can be implemented by electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Professionals can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of this application.

[0095] The steps of the methods or algorithms described in combination with the embodiments disclosed in this article can be directly implemented by hardware, software modules executed by a processor, or a combination of both. The software modules can be placed in a random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium well-known in the technical field.

[0096] Finally, it should also be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including a..." does not exclude the existence of additional identical elements in the process, method, article or device including the said element.

[0097] The above has introduced in detail the device debugging method, device, equipment, and storage medium provided by the present invention. Specific examples are used in this article to elaborate on the principles and implementation manners of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention; at the same time, for those of ordinary skill in the art, according to the idea of the present invention, there will be changes in the specific implementation manners and application scopes. In summary, the content of this specification should not be construed as a limitation to the present invention.

Claims

1. A device debugging method, characterized in that, it is applied to a debugging unit whose one end is connected to a debugging unit through a cable and the other end is connected to the universal asynchronous receiver / transmitter pin of the unit to be debugged, and includes: respectively determining whether the start bit information is contained in the first preset buffer and the second preset buffer; the first preset buffer and the second preset buffer respectively store the universal asynchronous transceiver signals sent by the unit to be debugged and received through the preset first signal line and second signal line; determining the signal line corresponding to the buffer containing the start bit information as the data sending end signal line of the unit to be debugged, and determining the corresponding relationship between the first signal line, the second signal line, the data sending end signal line and the data receiving end signal line of the unit to be debugged; using the corresponding relationship to connect the data sending end signal line and the data receiving end signal line of the unit to be debugged to the data receiving end and the data sending end of the preset data conversion device respectively, and using the preset data conversion device to implement the conversion between the universal asynchronous transceiver signal and the target debugging signal, so that the debugging unit can use the target debugging signal to debug the unit to be debugged.

2. The device debugging method according to claim 1, characterized in that, before respectively determining whether the start bit information is contained in the first preset buffer and the second preset buffer, it further includes: receiving the universal asynchronous transceiver signal sent by the unit to be debugged through the first signal line and the second signal line; converting the level of the universal asynchronous transceiver signal to a preset debugging level, and storing the universal asynchronous transceiver signal after level conversion into the preset buffer corresponding to the corresponding signal line.

3. The device debugging method according to claim 1, characterized in that, the step of determining the signal line corresponding to the buffer containing the start bit information as the data sending end signal line of the unit to be debugged, and determining the corresponding relationship between the first signal line, the second signal line, the data sending end signal line and the data receiving end signal line of the unit to be debugged includes: determining the signal line corresponding to the buffer containing the start bit information as the data sending end signal line of the unit to be debugged, and determining the other signal line among the first signal line and the second signal line except the data sending end signal line of the unit to be debugged as the data receiving end signal line of the unit to be debugged; determining the corresponding relationship between the first signal line, the second signal line, the data sending end signal line and the data receiving end signal line of the unit to be debugged.

4. The device debugging method according to claim 1, characterized in that, after respectively determining whether the start bit information is contained in the first preset buffer and the second preset buffer, it further includes: If neither the first preset buffer nor the second preset buffer contains start bit information, a data request is sent to the unit under test using the third preset buffer based on a first control strategy, and it is determined whether the first preset buffer receives a universal asynchronous transceiver signal containing start bit information; the third preset buffer is located in the line where the data sending end of the preset data conversion device is located; If the first preset buffer receives a universal asynchronous transceiver signal containing start bit information, the first signal line is determined as the data sending end signal line of the unit under test, and the step of determining the corresponding relationships among the first signal line, the second signal line, the data sending end signal line, and the data receiving end signal line of the unit under test is executed; If the first preset buffer does not receive a universal asynchronous transceiver signal containing start bit information, a data request is sent to the unit under test using the third preset buffer based on a second control strategy, and it is determined whether the second preset buffer receives a universal asynchronous transceiver signal containing start bit information; If the second preset buffer receives a universal asynchronous transceiver signal containing start bit information, the second signal line is determined as the data sending end signal line of the unit under test, and the step of determining the corresponding relationships among the first signal line, the second signal line, the data sending end signal line, and the data receiving end signal line of the unit under test is executed; If the second preset buffer does not receive a universal asynchronous transceiver signal containing start bit information, the working state of the unit under test is determined to be abnormal, and a warning signal is controlled to be emitted by a preset flashing light.

5. The device debugging method according to claim 4, wherein, The sending a data request to the unit under test using the third preset buffer based on the first control strategy includes: Pulling the SEL signal low to a low level and sending a data request to the unit under test using the third preset buffer; Correspondingly, the sending a data request to the unit under test using the third preset buffer based on the second control strategy includes: Pulling the SEL signal high to a high level and sending a data request to the unit under test using the third preset buffer.

6. The device debugging method according to claim 1, wherein, The using the preset data conversion device to implement the conversion between the universal asynchronous transceiver signal and the target debugging signal so that the debugging unit can use the target debugging signal to debug the unit under test includes: Using the preset data conversion device to implement the conversion between the universal asynchronous transceiver signal and the universal serial bus signal so that the debugging unit can use a universal serial bus interface preset in the debugging unit and use the target debugging signal to debug the unit under test.

7. The device debugging method according to any one of claims 1 to 6, wherein, The connecting the data sending end signal line and the data receiving end signal line of the unit under test to the data receiving end and the data sending end of the preset data conversion device respectively using the corresponding relationships includes: Determining the SEL signal value based on the corresponding relationships; Based on the line connection mode corresponding to the SEL signal value by using a preset signal conversion device, connect the data sending end signal line and the data receiving end signal line of the unit to be debugged to the data receiving end and the data sending end of a preset data conversion device respectively.

8. A device debugging apparatus characterized in that it is applied to a debugging unit that is connected to a debugging unit through a cable at one end and connected to the universal asynchronous receiver / transmitter pins of the unit to be debugged at the other end, and includes: An information determination module, configured to respectively determine whether start bit information is contained in a first preset buffer and a second preset buffer; the first preset buffer and the second preset buffer each store a universal asynchronous transceiver signal sent by the unit to be debugged and received through a preset first signal line and a second signal line respectively; A signal line determination module, configured to determine the signal line corresponding to the buffer containing the start bit information as the data sending end signal line of the unit to be debugged, and determine the correspondence between the first signal line, the second signal line, the data sending end signal line and the data receiving end signal line of the unit to be debugged; A signal line connection module, configured to connect the data sending end signal line and the data receiving end signal line of the unit to be debugged to the data receiving end and the data sending end of a preset data conversion device respectively by using the correspondence, and use the preset data conversion device to implement the conversion between the universal asynchronous transceiver signal and the target debugging signal, so that the debugging unit can use the target debugging signal to debug the unit to be debugged.

9. An electronic device characterized in that it includes a processor and a memory; wherein, when the processor executes the computer program stored in the memory, it implements the device debugging method according to any one of claims 1 to 7.

10. A computer-readable storage medium characterized in that it is used to store a computer program; wherein, when the computer program is executed by a processor, it implements the device debugging method according to any one of claims 1 to 7.

Images