Gate tunneling current model and extraction method thereof
By introducing a first function of the active region environmental parameters into the gate tunneling current model, the problem that existing models cannot accurately characterize the gate tunneling current is solved, achieving higher fitting accuracy and more rational circuit design.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANGHAI HUALI INTEGRATED CIRCUIT CORP
- Filing Date
- 2022-09-29
- Publication Date
- 2026-07-10
AI Technical Summary
Existing SPICE models cannot accurately characterize the relationship between gate tunneling current and active region length, leading to inaccurate circuit design and affecting device performance and reliability.
In the gate tunneling current model, a first function formed by the environmental parameters of the active region is introduced, and the model fitting accuracy is improved by modifying the length and width parameters of the active region.
It improves the fitting accuracy of the gate tunneling current model, which can better reflect the characteristics of the device under different layout effects, help design a more reasonable layout, and improve circuit performance and production yield.
Smart Images
Figure CN115526143B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor integrated circuit manufacturing, and particularly to a gate tunneling current model. This invention also relates to a method for extracting the gate tunneling current model. Background Technology
[0002] The magnitude of the gate tunneling current increases exponentially with the reduction of semiconductor device size and the thinning of the gate oxide layer, thereby affecting the device's static power consumption and device performance. Therefore, for the SPICE model, accurately characterizing the gate tunneling current is crucial for subsequent circuit design.
[0003] Due to the mechanical stress generated by the shallow trench isolation (STI) technique during fabrication, physical parameters of the device, such as carrier mobility, impurity diffusion coefficient, and effective carrier mass, undergo a series of changes. This leads to changes in electrical parameters, such as threshold voltage and drain saturation current, with the length of the active region (LOD), including gate tunneling current characteristics. This effect becomes even more significant when device sizes are scaled down to below 90nm.
[0004] Existing SPICE models commonly use relationships between electrical characteristics such as device threshold voltage and drain saturation current and the active region length to characterize the changes in device characteristics caused by stress. However, the relationship between gate tunneling current and these characteristics is not addressed. This prevents circuit designers from obtaining reliable and accurate gate currents using existing general SPICE models, causing challenges for subsequent circuit manufacturing and device reliability optimization.
[0005] like Figure 1 The diagram shown is the architecture of the existing gate tunneling current model, Figure 101. The formula for the existing gate tunneling current model is:
[0006] Ig=f(w,l,V) (1);
[0007] Where Ig represents the gate tunneling current of the device; f() represents a function of the gate tunneling current, w represents the width of the channel region of the semiconductor device, l represents the length of the channel region of the semiconductor device, and V represents the bias voltage of the semiconductor device. It can be seen that w, l, and V are all related to the structural parameters of the semiconductor device itself, and are independent of the environmental parameters of the active region. Summary of the Invention
[0008] The technical problem to be solved by this invention is to provide a gate tunneling current model that can simulate the influence of the active region environment on the gate tunneling current of a device, thereby improving the model fitting accuracy and facilitating the design of a more reasonable layout. To this end, this invention also provides a method for extracting the gate tunneling current model.
[0009] To address the aforementioned technical problems, the gate tunneling current model provided by this invention is used to simulate the gate tunneling current of semiconductor devices.
[0010] The gate tunneling current in the gate tunneling current model is formed by multiplying the main function by the first function.
[0011] The first function is a function formed by the active region environmental parameters of the semiconductor device, used to simulate the effect of the active region environment on the gate tunneling current.
[0012] A further improvement is that the active region environmental parameters include a first active region length and a second active region length; the first active region length is the distance between the first side of the gate structure of the semiconductor device and the field oxygen outside the first side of the gate structure; the second active region length is the distance between the second side of the gate structure of the semiconductor device and the field oxygen outside the second side of the gate structure, wherein the field oxygen surrounds the periphery of the active region of the semiconductor device.
[0013] A further improvement is that the parameters of the first function also include the length and width of the channel region.
[0014] A further improvement is that the formula for the first function is:
[0015] Where f1() represents the first function; pwr() represents the power function;
[0016] SA represents the length of the first active region, and SB represents the length of the second active region;
[0017] W represents the width of the trench area, and L represents the length of the trench area;
[0018] γ1,α1,A1,B1,b1,C1,c1,D1,d1,γ2,α2,A2,B2,b2,C2,c2,D2,d2 are all fitting parameters.
[0019] A further improvement is that the parameters of the body function of the gate tunneling current model include:
[0020] The width and length of the channel region and the bias voltage.
[0021] A further improvement is that, while keeping the main function unchanged, the fitting parameters of the first function are obtained by changing the lengths of the first and second active regions, and fitting the gate tunneling current curve formed by the gate tunneling current model with the actual measured gate tunneling current curve.
[0022] A further improvement is that the lengths of the first and second active regions are modified through layout design.
[0023] To address the aforementioned technical problems, the method for extracting the gate tunneling current model provided by this invention, where the gate tunneling current model is used to simulate the gate tunneling current of a semiconductor device, includes the following steps:
[0024] Step 1: Set the gate tunneling current of the gate tunneling current model to be formed by multiplying the main function by the first function;
[0025] The first function is a function formed by the active region environmental parameters of the semiconductor device, used to simulate the effect of the active region environment on the gate tunneling current.
[0026] Step 2: Use the semiconductor device, which is unaffected by the active region environment, to perform parameter fitting on the main function.
[0027] Step 3: While keeping the main function unchanged, change the active region environmental parameters of the semiconductor device to fit the first function to obtain the fitting parameters of the first function.
[0028] A further improvement is that the active region environmental parameters include a first active region length and a second active region length; the first active region length is the distance between the first side of the gate structure of the semiconductor device and the field oxygen outside the first side of the gate structure; the second active region length is the distance between the second side of the gate structure of the semiconductor device and the field oxygen outside the second side of the gate structure, wherein the field oxygen surrounds the periphery of the active region of the semiconductor device.
[0029] A further improvement is that the parameters of the first function also include the length and width of the channel region.
[0030] A further improvement is that the formula for the first function is:
[0031] Where f1() represents the first function; pwr() represents the power function;
[0032] SA represents the length of the first active region, and SB represents the length of the second active region;
[0033] W represents the width of the trench area, and L represents the length of the trench area;
[0034] γ1,α1,A1,B1,b1,C1,c1,D1,d1,γ2,α2,A2,B2,b2,C2,c2,D2,d2 are all fitting parameters.
[0035] A further improvement is that the parameters of the body function of the gate tunneling current model include:
[0036] The width and length of the channel region and the bias voltage.
[0037] A further improvement is that, in step three, the fitting parameters of the first function are obtained by changing the lengths of the first and second active regions to fit the gate tunneling current curve formed by the gate tunneling current model and the actual measured gate tunneling current curve.
[0038] A further improvement is that the lengths of the first and second active regions are modified through layout design.
[0039] A further improvement is that, after step three is completed, a step of verifying the gate tunneling current model is also included.
[0040] This invention adds a product term composed of a first function to the main function of the gate tunneling current model. The first function is a function formed by the active region environmental parameters of the semiconductor device. In this way, when the active region environmental parameters change, this invention can accurately simulate the effect of such changes on the gate tunneling current. Therefore, this invention can simulate the effect of the active region environment on the gate tunneling current of the device, thereby improving the model fitting accuracy.
[0041] The active region environmental parameters of this invention are mainly the active region length, namely the first active region length and the second active region length. Therefore, this invention can more accurately build a gate tunneling current model for various active region lengths and better reflect the actual circuit characteristics of the device.
[0042] This invention can better reflect the characteristics of devices under different layout effects, and is closer to the actual situation, thus making it more applicable and enabling the design of more reasonable layouts based on the gate tunneling current model. Attached Figure Description
[0043] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:
[0044] Figure 1 This is an architecture diagram of the existing gate tunneling current model;
[0045] Figure 2 This is a layout of the semiconductor device according to an embodiment of the present invention;
[0046] Figure 3 This is an architectural diagram of the gate tunneling current model according to an embodiment of the present invention;
[0047] Figure 4 This is a schematic diagram of the first function of the gate tunneling current model in an embodiment of the present invention;
[0048] Figure 5 This is a flowchart of the method for extracting the gate tunneling current model according to an embodiment of the present invention;
[0049] Figure 6A It is a gate tunneling current fitting curve using an existing gate tunneling current model;
[0050] Figure 6B It is the gate tunneling current fitting curve using the gate tunneling current model of the embodiment of the present invention. Detailed Implementation
[0051] like Figure 2 The diagram shown is a layout of a semiconductor device according to an embodiment of the present invention; as shown Figure 3 As shown is the architecture diagram 301 of the gate tunneling current model according to an embodiment of the present invention; as Figure 4 The diagram shown is 302, which is the architecture diagram of the first function of the gate tunneling current model in an embodiment of the present invention. The gate tunneling current model in this embodiment of the present invention is used to simulate the gate tunneling current of a semiconductor device.
[0052] The gate tunneling current in the gate tunneling current model is formed by multiplying the main function by the first function.
[0053] The first function is a function formed by the active region environmental parameters of the semiconductor device, used to simulate the effect of the active region environment on the gate tunneling current. For example... Figure 2 As shown, in this embodiment of the invention, a semiconductor device is formed in an active region 201, the periphery of which is field oxide such as shallow trench isolation (STI). The semiconductor device includes a gate structure 202. The gate structure 202 is typically formed by stacking a gate dielectric layer and a gate conductive material layer, the gate dielectric layer including a gate oxide layer or a high dielectric constant layer. The gate conductive material layer including a polysilicon gate or a metal gate. A channel region 203 is formed in the surface region of the active region 201 covered by the gate structure 202; a source region and a drain region are formed in the active region 201 on both sides of the gate structure 202. Contact holes 204 are formed on the top of the source region, the drain region, and the gate structure 202, and are connected to the source, drain, and gate composed of a front metal layer through contact holes 205.
[0054] The active region environmental parameters include a first active region length SA and a second active region length SB; the first active region length SA is the distance between the first side of the gate structure 202 of the semiconductor device and the field oxygen outside the first side of the gate structure 202; the second active region length SB is the distance between the second side of the gate structure 202 of the semiconductor device and the field oxygen outside the second side of the gate structure 202, wherein the field oxygen surrounds the periphery of the active region of the semiconductor device.
[0055] The parameters of the first function also include the length L and width W of the channel region.
[0056] In this embodiment of the invention, the parameters of the main function of the gate tunneling current model include:
[0057] The width and length of the channel region and the bias voltage.
[0058] like Figure 3 As shown in this embodiment of the invention, the formula for the gate tunneling current in the gate tunneling current model is:
[0059] Ig=f(w,l,V)*f1(SA,SB) (3)
[0060] Ig represents the gate tunneling current.
[0061] Where Ig represents the device gate tunneling current.
[0062] Similar to formula (1), f() represents the main function, i.e., the function of the gate tunneling current, w represents the width of the channel region of the semiconductor device, l represents the length of the channel region of the semiconductor device, and V represents the bias voltage of the semiconductor device. It can be seen that w, l, and V are all related to the structural parameters of the semiconductor device itself.
[0063] like Figure 4 As shown, the formula for the first function is:
[0064]
[0065] Where f1() represents the first function; pwr() represents the power function;
[0066] SA represents the length of the first active region, and SB represents the length of the second active region;
[0067] W represents the width of the trench area, and L represents the length of the trench area;
[0068] γ1,α1,A1,B1,b1,C1,c1,D1,d1,γ2,α2,A2,B2,b2,C2,c2,D2,d2 are all fitting parameters.
[0069] In this embodiment of the invention, under the condition that the main function remains unchanged, the fitting parameters of the first function are obtained by changing the first active region length SA and the second active region length SB, and fitting the gate tunneling current curve formed by the gate tunneling current model and the actual measured gate tunneling current curve.
[0070] The lengths of the first active region SA and the second active region SB are modified in the layout design.
[0071] This invention, based on the original gate tunneling current model (i.e., the main function), considers the impact of changes in the active region length on the device's gate tunneling current. This introduces a function related to changes in the active region length into the original gate tunneling current model, increasing the characterization of the device's gate tunneling current characteristics under different active region lengths. This greatly assists designers in considering the impact of changes in the active region length on the device during circuit design, making the new gate tunneling current model more applicable.
[0072] In this embodiment of the invention, a product term consisting of a first function is added to the main function of the gate tunneling current model. The first function is a function formed by the active region environmental parameters of the semiconductor device. In this way, when the active region environmental parameters change, this embodiment of the invention can accurately simulate the impact of such changes on the gate tunneling current. Therefore, this embodiment of the invention can simulate the impact of the active region environment on the gate tunneling current of the device, thereby improving the model fitting accuracy.
[0073] The active region environmental parameters in this embodiment of the invention are mainly the active region length, namely the first active region length SA and the second active region length SB. Therefore, this embodiment of the invention can more accurately build a gate tunneling current model for various active region lengths and better reflect the actual circuit characteristics of the device.
[0074] The embodiments of the present invention can better reflect the characteristics of the device under different layout effects, and are closer to the actual situation, thus making them more applicable and enabling the design of more reasonable layouts based on the gate tunneling current model.
[0075] like Figure 5 The diagram shows a flowchart of the method for extracting the gate tunneling current model according to an embodiment of the present invention. In this method, the gate tunneling current model is used to simulate the gate tunneling current of a semiconductor device, and includes the following steps:
[0076] Step 1: Set the gate tunneling current of the gate tunneling current model to be formed by multiplying the main function by the first function.
[0077] The first function is a function formed by the active region environmental parameters of the semiconductor device, used to simulate the effect of the active region environment on the gate tunneling current.
[0078] Subsequently, the method of the embodiments of the present invention further includes Figure 5 Steps S101 and S102 are shown in the figure.
[0079] In step S101, device structures with different active region lengths are designed. For example... Figure 2 As shown, the length of the active region can be changed through layout design, and thus the... Figure 2 The first active region length SA and the second active region length SB are shown in the figure.
[0080] Next, the semiconductor devices are fabricated onto the semiconductor substrate according to the layout design.
[0081] Step S102 involves measuring device data. Step S102 can measure the structural and electrical parameters of the semiconductor device.
[0082] Step 2: Use the semiconductor device, which is unaffected by the active region environment, to perform parameter fitting on the main function.
[0083] Figure 5 In the process, step two is achieved by repeating steps S103 and S104 in a loop.
[0084] In step S103, the basic gate tunneling current model parameters are established and modified.
[0085] In the method of this invention embodiment, the basic gate tunneling current model is the main function, and the parameters of the main function include: the width and length of the channel region and the bias voltage. The width, length, and bias voltage of the channel region are all measurable parameters. The main function is: f(w,l,V);
[0086] Where w represents the width of the channel region of the semiconductor device, l represents the length of the channel region, and V represents the bias voltage of the semiconductor device, including the gate bias voltage, such as the gate-source voltage Vgs. It can be seen that w, l, and V are all related to the structural parameters of the semiconductor device itself and can all be obtained through measurement. Fitting parameters are also set in f(w, lV).
[0087] In step S104, curve fitting is performed on the size and voltage-related data; that is, the fitting parameters of f(w,l,V) are obtained by fitting based on w,l,V. If the fitting is not good, the fitting parameters of (w,l,V) are modified until a good fit is obtained. Once a good fit is obtained, the main function f(w,l,V) is obtained. After a good fit, the subsequent step S105 is performed.
[0088] Step 3: While keeping the main function unchanged, change the active region environmental parameters of the semiconductor device to fit the first function to obtain the fitting parameters of the first function.
[0089] In the method of this invention, the fitting of the model curve related to the active region length mainly includes:
[0090] The fitting parameters of the first function are obtained by fitting the gate tunneling current curve formed by the gate tunneling current model and the actual measured gate tunneling current curve by changing the first active region length SA and the second active region length SB.
[0091] The lengths of the first active region SA and the second active region SB are modified in the layout design, i.e., implemented in the preceding step S101.
[0092] Figure 5 In the process, step three is achieved by repeating steps S105 and S106 in a loop.
[0093] Step S105 involves establishing and modifying models related to different active region environments. In the method of this embodiment, the active region environment parameters include a first active region length SA and a second active region length SB; the first active region length SA is the distance between the first side of the gate structure 202 of the semiconductor device and the field oxygen outside the first side of the gate structure 202; the second active region length SB is the distance between the second side of the gate structure 202 of the semiconductor device and the field oxygen outside the second side of the gate structure 202, wherein the field oxygen surrounds the periphery of the active region of the semiconductor device.
[0094] The parameters of the first function also include the length and width of the channel region.
[0095] The formula for the first function is:
[0096] Where f1() represents the first function; pwr() represents the power function;
[0097] SA represents the length of the first active region SA, and SB represents the length of the second active region SB;
[0098] W represents the width of the trench area, and L represents the length of the trench area;
[0099] γ1,α1,A1,B1,b1,C1,c1,D1,d1,γ2,α2,A2,B2,b2,C2,c2,D2,d2 are all fitting parameters.
[0100] Step S106 involves fitting the model curve related to the length of the active region.
[0101] If the fitting in step S106 is not good, return to step S105 to modify the values of each fitting parameter, and then proceed to step S106 again; if the result of step S106 is a good fit, then establish the gate tunneling current model.
[0102] In the method of this embodiment of the invention, after step three is completed, a step of verifying the gate tunneling current model is also included, that is, performing... Figure 5 Step S107 is for the verification of the gate tunneling current model.
[0103] In advanced integrated circuits, the magnitude of gate tunneling current increases exponentially with decreasing gate oxide layer thickness and smaller device size, thus attracting increasing attention from circuit design engineers. Furthermore, the mechanical stress generated by shallow trench isolation (STI) technology and the varying lengths of the active region also influence the gate tunneling current characteristics. Existing SPICE models often use functions relating device threshold voltage, drain saturation current, and active region length to characterize the changes in device characteristics caused by this stress; however, the relationship between gate tunneling current and these parameters is not addressed. This is a significant deficiency in existing gate tunneling current models.
[0104] This invention, based on the original device gate tunneling current model, considers the impact of changes in the active region length on the device gate tunneling current. By introducing a function related to the active region length into the original gate tunneling current model, it enhances the characterization of the device gate tunneling current characteristics under different active region lengths, establishing a more accurate and widely applicable device gate tunneling current model.
[0105] like Figure 6A The figure shows the gate tunneling current fitting curve using the existing gate tunneling current model; Figure 6AIn the diagram, the circled data represents the gate tunneling current test data for various active region lengths, namely SA and SB, where SA and SB are equal. SA sizes include 0.075 μm, 0.205 μm, 0.335 μm, and 2.205 μm. Curve 401 represents the gate tunneling current test data curve for an SA of 0.075 μm, and curve 402 represents the gate tunneling current test data curve for an SA of 2.205 μm. The gate tunneling current test data curves for the other two SA sizes are located between curves 401 and 402. Curve 403 is the gate tunneling current fitting curve for various SAs implemented using existing gate tunneling current models. It can be seen that the fitting curves for various SAs are close to curve 403. However, curves 401 and 403 are significantly different. Existing gate tunneling current models cannot simulate the influence of active region length on gate tunneling current.
[0106] like Figure 6B The figure shows the gate tunneling current fitting curves using the gate tunneling current model of this invention; curves 401 to 402 and Figure 6A The curves are identical; curve 501 is the gate tunneling current curve of a semiconductor device with an SA of 0.075 micrometers, obtained by fitting the gate tunneling current model of this embodiment. It can be seen that curve 501 and curve 401 overlap well. Curve 502 is the gate tunneling current curve of a semiconductor device with an SA of 2.205 micrometers, obtained by fitting the gate tunneling current model of this embodiment. It can be seen that curve 501 and curve 402 overlap well. Furthermore, Figure 6B In the above embodiments, the gate tunneling current curves of the semiconductor devices corresponding to the other two lengths SA obtained by fitting the gate tunneling current model of the present invention can be separated and respectively match the test data curves of the same SA. Therefore, the gate tunneling current model of the present invention can well simulate the influence of the active region length on the gate tunneling current, thereby improving the simulation accuracy.
[0107] In the method of this invention, to characterize the impact of different active region lengths on device performance, a design-related layout is first added, drawing multiple test structures with active region lengths different from the device body. Then, measurements are performed on devices manufactured based on this design layout, and the measurement data is analyzed. After a conventional device gate tunneling current model is well fitted, the fitting parameters of the function coefficients, i.e., f1(), related to different active region lengths are adjusted. This is achieved through comparison... Figure 6A and Figure 6B It can be seen that, Figure 6B Compare Figure 6AThe fit is better. This allows us to obtain a gate tunneling current model related to different active region lengths, enabling the new model to better reflect the characteristics of actual devices. Designers can then use this model to understand the relevant characteristics of the device under different active region lengths, helping them to take this factor into account at the beginning of the design process, obtain a more reasonable circuit design, improve circuit performance, and increase foundry production yield.
[0108] The present invention has been described in detail above through specific embodiments, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.
Claims
1. A gate tunneling current model system, characterized in that: The gate tunneling current model system is used to simulate the gate tunneling current of semiconductor devices; The gate tunneling current model system has a gate tunneling current model, and the gate tunneling current of the gate tunneling current model is formed by multiplying the main function by the first function; The first function is a function formed by the active region environmental parameters of the semiconductor device, used to simulate the influence of the active region environment on the gate tunneling current; The active region environmental parameters include a first active region length and a second active region length; the first active region length is the distance between the first side of the gate structure of the semiconductor device and the field oxygen outside the first side of the gate structure; the second active region length is the distance between the second side of the gate structure of the semiconductor device and the field oxygen outside the second side of the gate structure, wherein the field oxygen surrounds the periphery of the active region of the semiconductor device. The parameters of the first function also include the length and width of the channel region; The formula for the first function is: ； Where f1() represents the first function; pwr() represents the power function; SA represents the length of the first active region, and SB represents the length of the second active region; W represents the width of the trench area, and L represents the length of the trench area; All of these are fitting parameters.
2. The gate tunneling current model system as described in claim 1, characterized in that: The parameters of the main function of the gate tunneling current model include: The width and length of the channel region and the bias voltage.
3. The gate tunneling current model system as described in claim 2, characterized in that: Under the condition that the main function remains unchanged, the fitting parameters of the first function are obtained by fitting the gate tunneling current curve formed by the gate tunneling current model and the actual measured gate tunneling current curve by changing the length of the first active region and the length of the second active region.
4. The gate tunneling current model system as described in claim 3, characterized in that: The lengths of the first and second active regions are modified through layout design.
5. A method for extracting a gate tunneling current model, characterized in that, The gate tunneling current model is used to simulate the gate tunneling current of semiconductor devices, and includes the following steps: Step 1: Set the gate tunneling current of the gate tunneling current model to be formed by multiplying the main function by the first function; The first function is a function formed by the active region environmental parameters of the semiconductor device, used to simulate the influence of the active region environment on the gate tunneling current; The active region environmental parameters include a first active region length and a second active region length; the first active region length is the distance between the first side of the gate structure of the semiconductor device and the field oxygen outside the first side of the gate structure; the second active region length is the distance between the second side of the gate structure of the semiconductor device and the field oxygen outside the second side of the gate structure, wherein the field oxygen surrounds the periphery of the active region of the semiconductor device. The parameters of the first function also include the length and width of the channel region; The formula for the first function is: ； Where f1() represents the first function; pwr() represents the power function; SA represents the length of the first active region, and SB represents the length of the second active region; W represents the width of the trench area, and L represents the length of the trench area; All are fitting parameters; Step 2: Use the semiconductor device, which is unaffected by the active region environment, to perform parameter fitting on the main function; Step 3: While keeping the main function unchanged, change the active region environmental parameters of the semiconductor device to fit the first function to obtain the fitting parameters of the first function.
6. The method for extracting the gate tunneling current model as described in claim 5, characterized in that: The parameters of the main function of the gate tunneling current model include: The width and length of the channel region and the bias voltage.
7. The method for extracting the gate tunneling current model as described in claim 6, characterized in that: In step three, the fitting parameters of the first function are obtained by fitting the gate tunneling current curve formed by the gate tunneling current model and the actual measured gate tunneling current curve by changing the length of the first active region and the length of the second active region.
8. The method for extracting the gate tunneling current model as described in claim 7, characterized in that: The lengths of the first and second active regions are modified through layout design.
9. The method for extracting the gate tunneling current model as described in claim 5, characterized in that: After step three is completed, the process also includes a step of verifying the gate tunneling current model.