Circuit detection method and apparatus, electronic device, and computer-readable medium and product

Abstract

The application discloses a circuit detection method and device, electronic equipment, and computer readable medium and product. The method comprises: acquiring a to-be-detected picture corresponding to a to-be-detected circuit board and a to-be-detected identifier, wherein the to-be-detected identifier comprises an identifier corresponding to a to-be-detected connecting line in the to-be-detected circuit board; based on the to-be-detected identifier, extracting a region corresponding to the connecting line corresponding to the to-be-detected identifier from the to-be-detected picture as a target connecting line region; and determining an identification result of the to-be-detected circuit board based on the difference between the target connecting line region and a standard connecting line region, wherein the identification result is used to represent whether the target connecting line region has a defect or not. By determining the target connecting line region based on the to-be-detected identifier and comparing the difference between the target connecting line region and the standard connecting line region, whether the to-be-detected circuit board has a defect can be determined, the consumption of computing resources can be reduced, the processing time can be reduced, and the efficiency can be improved.

Description

Technical Field

[0001] This application relates to the field of circuit board technology, and more specifically, to a circuit testing method, apparatus, electronic device, computer-readable medium, and product. Background Technology

[0002] Currently, with the rapid development of electronic information technology, the wiring on circuit boards is becoming increasingly dense. Although defect detection can be performed on manufactured circuit boards, current methods for defect detection consume significant computing resources and require a long processing time. Summary of the Invention

[0003] This application proposes a circuit testing method, apparatus, electronic device, computer-readable medium, and product to improve the above-mentioned deficiencies.

[0004] In a first aspect, embodiments of this application provide a circuit testing method, the method comprising: acquiring a test image and a test identifier corresponding to a circuit board to be tested, the test identifier including an identifier corresponding to a test connection line in the circuit board to be tested; based on the test identifier, extracting the area corresponding to the connection line corresponding to the test identifier from the test image as a target connection line area; and determining the identification result of the circuit board to be tested based on the difference between the target connection line area and the standard connection line area, the identification result being used to characterize whether the target connection line area has a defect or not.

[0005] Secondly, embodiments of this application also provide a circuit detection device applied to an electronic device. The device includes: an acquisition unit, configured to acquire the lock holding state of the current thread in response to a preemption request from a target thread, the lock holding state including holding a public lock or not holding a public lock; a processing unit, configured to release the public lock held by the current thread and preempt the CPU resources occupied by the current thread if the lock holding state of the current thread is holding a public lock; and an execution unit, configured to execute the target thread based on the preempted CPU resources.

[0006] Thirdly, embodiments of this application also provide an electronic device, including: one or more processors; a memory; and one or more computer programs, wherein the one or more computer programs are stored in the memory and configured to be executed by the one or more processors to cause the electronic device to perform the method described in the first aspect.

[0007] Fourthly, embodiments of this application also provide a computer-readable medium storing processor-executable program code, which, when executed by the processor, causes the processor to perform the method described in the first aspect.

[0008] Fifthly, embodiments of this application also provide a computer program product, including a computer program / instructions that, when executed by a processor, implement the method described in the first aspect.

[0009] The circuit testing method, apparatus, electronic device, computer-readable medium, and product provided in this application first acquire a test image and a test identifier corresponding to the circuit board to be tested. Then, based on the test identifier, the region corresponding to the connecting line of the test identifier is extracted from the test image as the target connecting line region. Finally, the identification result of the circuit board to be tested can be determined based on the difference between the target connecting line region and the standard connecting line region. The identification result is used to characterize whether the target connecting line region has a defect or not. Determining whether the circuit board to be tested has a defect by comparing all regions in the test image with all regions in the standard template image consumes a lot of computing resources, is time-consuming, and inefficient. Since the defective region in the circuit board to be tested is generally the region corresponding to the connecting line, this application determines whether the circuit board to be tested has a defect by determining the target connecting line region based on the test identifier and comparing the difference between the target connecting line region and the standard connecting line region. This reduces the consumption of computing resources, reduces processing time, and improves efficiency.

[0010] Other features and advantages of the embodiments of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the embodiments of this application. The objects and other advantages of the embodiments of this application may be realized and obtained by means of the structures particularly pointed out in the written description, claims, and drawings. Attached Figure Description

[0011] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 A flowchart of the circuit detection method provided in an embodiment of this application is shown;

[0013] Figure 2 A schematic diagram of a circuit board provided in an embodiment of this application is shown;

[0014] Figure 3 A schematic diagram of a circuit board provided in yet another embodiment of this application is shown;

[0015] Figure 4A schematic diagram of a circuit board provided in another embodiment of this application is shown;

[0016] Figure 5 A flowchart of a circuit detection method provided in another embodiment of this application is shown;

[0017] Figure 6 A diagram illustrating an implementation of step S250 is shown;

[0018] Figure 7 A diagram illustrating an implementation of step S251 is shown;

[0019] Figure 8 A flowchart of a circuit detection method according to another embodiment of this application is shown;

[0020] Figure 9 A diagram illustrating an implementation of step S350 is shown;

[0021] Figure 10 A structural diagram of the circuit detection device provided in an embodiment of this application is shown;

[0022] Figure 11 A structural block diagram of the electronic device provided in an embodiment of this application is shown;

[0023] Figure 12 This paper shows a structural block diagram of a computer-readable storage medium provided in an embodiment of this application;

[0024] Figure 13 A structural block diagram of a computer program product provided in an embodiment of this application is shown. Detailed Implementation

[0025] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, and not all of them. The components of the embodiments of the present application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of the present application. All other embodiments obtained by those skilled in the art based on the embodiments of the present application without inventive effort are within the scope of protection of the present application.

[0026] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this application, terms such as "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0027] Currently, with the rapid development of electronic information technology, the wiring on circuit boards is becoming increasingly dense. Although defect detection can be performed on manufactured circuit boards, current methods require significant computing resources and long processing times. How to perform defect detection on circuit boards with less computing resources and in a shorter time is a problem that urgently needs to be solved.

[0028] Currently, electronic devices are capable of performing increasingly diverse functions. Circuit boards, as a crucial component of electronic devices, are exhibiting increasingly dense wiring and a growing number of electronic components. Furthermore, integrated circuits (ICs) can be mounted on circuit boards, encapsulated within a packaging substrate mounted on the circuit board. The packaging substrate serves two purposes: firstly, it protects, secures, and supports the IC, enhancing its thermal conductivity and heat dissipation, and ensuring the IC is not easily damaged by physical forces; secondly, the upper layer of the packaging substrate connects to the IC, while the lower layer connects to the circuit board, enabling electrical and physical connections, power distribution, and signal distribution. For example, different traces on the circuit board can be electrically connected to different pins of the IC within the packaging substrate.

[0029] However, during the manufacturing of circuit boards or package substrates, wiring errors may occur, such as missing or incorrect connections. For example, if traces A1 and A2 on a circuit board are designed to be isolated, but are mistakenly electrically connected during manufacturing, this will cause a short circuit between traces A1 and A2. As another example, if traces A1 and A2 are designed to be electrically connected, but are mistakenly isolated during manufacturing, this will cause an open circuit between traces A1 and A2. Therefore, defect detection is necessary for the manufactured circuit boards or package substrates.

[0030] For some solutions, open / short circuit tests can be performed on circuit boards or packaging substrates. If open / short circuit problems are found in some circuit boards or packaging substrates during the open / short circuit test, the problematic circuit boards or packaging substrates can be screened out for further defect detection to determine the specific location of the open or short circuit defect.

[0031] In the traditional circuit board manufacturing industry, manual inspection with magnifying glasses and visual inspection are generally used. The main method is to determine whether the circuit board has defects such as short circuit or open circuit by inspecting its appearance.

[0032] In other solutions, images of the manufactured circuit boards or packaging substrates can be collected, and template images can be obtained from a large number of circuit boards or packaging substrates that have been determined to be good products. The images can then be compared with the template images to identify defects such as short circuits or open circuits in the images.

[0033] However, the inventors discovered during their research that the aforementioned methods for manually detecting defects are labor-intensive, inefficient, prone to omissions, and have low accuracy, failing to meet production demands. Furthermore, the method of identifying defects in images by comparing them with template images requires a large number of already approved circuit boards or packaging substrates to determine the acceptable templates. For small-batch manufacturing of circuit boards and packaging substrates, obtaining template images is difficult. Moreover, comparing images with template images consumes significant resources and is not efficient in identifying defects.

[0034] Therefore, in order to overcome the above-mentioned defects, this application provides a circuit testing method, apparatus, electronic device, computer-readable medium, and product.

[0035] Please see Figure 1 , Figure 1 This application illustrates a circuit detection method provided by an embodiment of the present application. This method can be applied to electronic devices, and the specific execution subject can be a processor in the electronic device. The method includes steps S110 to S130.

[0036] Step S110: Obtain the image to be tested and the identification mark to be tested corresponding to the circuit board to be tested. The identification mark to be tested includes the identification mark corresponding to the connection line to be tested in the circuit board to be tested.

[0037] In some implementation methods, a portion of the manufactured circuit board can be selected as the circuit board to be tested.

[0038] In some implementations, the circuit board can be single-layered, and may include connecting lines. These connecting lines are typically made of a metallic conductor, such as copper, meaning that different points on the same connecting line are generally conductive. One example is that the connecting lines include traces. These traces can be used to electrically connect different components that are electrically connected to the circuit board or package substrate. For example, if the first pin of component 1 is connected to trace A1, and the second pin of component 2 is connected to trace A1, then the first pin of component 1 and the second pin of component 2 are substantially electrically connected.

[0039] Different traces can be isolated from each other, meaning they are not electrically connected; however, different traces can also be electrically connected to each other. For example, please refer to... Figure 2 , Figure 2A schematic diagram of a circuit board 200 is shown. Figure 2 The circuit board 200 shown includes traces 201, 202, and 203. Trace 201 is isolated from both traces 202 and 203; that is, trace 201 is not electrically connected to trace 202, nor is trace 202 electrically connected to trace 203. However, trace 202 and trace 203 are electrically connected. Therefore, traces 202 and 203 can form a connection line.

[0040] Different traces can have different widths, and traces of different widths can withstand different maximum current values. It's easy to understand that the wider the trace, the greater the maximum current it can handle. For example, if the trace width is 10 mils, the maximum current it can handle is 1 ampere (A); if the trace width is 30 mils, the maximum current it can handle is 1.9 amperes; and if the trace width is 100 mils, the maximum current it can handle is 4.2 amperes.

[0041] Furthermore, for some more complex circuit boards, the target function may not be achievable with a single layer. Therefore, the circuit board can be multi-layered, such as double-layered or four-layered. In some implementations, for multi-layered circuit boards, the connecting lines may also include vias. Vias are similar to traces and are generally made of a metallic conductor material, such as copper. Multi-layered circuit boards may include trace layers and via layers. The trace layers may contain traces, and the via layers may contain vias. The via layers can electrically connect adjacent trace layers.

[0042] Therefore, for two routing layers adjacent to the same via layer, vias at the same location are essentially electrically connected. Consequently, routing traces on different layers connected to the same via are also essentially electrically connected. For an example, please refer to [link to example]. Figure 3 , Figure 3 A schematic diagram of a circuit board 300 is shown, including a first routing layer 301, a first via layer 302, and a second routing layer 303. The first routing layer 301 is provided with routing traces 3011, the second routing layer 303 is provided with routing traces 3031, and the first via layer 302 is provided with vias 3021. The first vias 3021 are connected to both routing traces 3011 and 3031. Therefore, routing traces 3011 and 3031 are electrically connected through vias 3021.

[0043] A circuit board may include traces and vias, and a connection line may include a single trace or a single via; a connection line may also include multiple traces and multiple vias. Optionally, as the foregoing analysis shows, a circuit board may include multiple layers; therefore, a connection line may also include traces or vias in different layers, wherein traces and vias belonging to the same connection line are electrically connected. For example, please refer to... Figure 4 , Figure 4 A circuit board 400 is shown, comprising three layers: a first routing layer 401, a first via layer 402, and a second routing layer 403. The first routing layer 401 includes traces 4011 and 4012, and vias 4013. The first via layer 402 includes vias 4013. The second routing layer 403 includes traces 4031 and 4032, and vias 4013. The traces 4011 of the first routing layer 401 are electrically connected to the traces 4031 of the second routing layer 403 vias 4013. Therefore, traces 4011, vias 4013, and traces 4031 can belong to the same connection line.

[0044] In one embodiment provided in this application, the circuit board to be tested can be multiple circuit boards obtained in production, that is, the circuit boards obtained in production are tested; the circuit board to be tested can also be a circuit board that has defects after pre-testing multiple circuit boards obtained in production, and the specific details can be found in the following embodiments.

[0045] As the foregoing analysis shows, the circuit board under test may contain multiple connecting lines. Testing each connecting line would consume significant computing resources and result in low testing efficiency. Therefore, when testing the circuit board, a testing identifier can be obtained first. This identifier includes the identifiers corresponding to the connecting lines on the circuit board to be tested. Then, testing is performed only on the connecting lines corresponding to these testing identifiers. This reduces resource consumption and improves testing efficiency.

[0046] The identifier to be inspected can be the identifier corresponding to a connection line that is prone to defects. For example, it can be directly specified by the user. For instance, the user can specify the identifier corresponding to the ground connection line in the circuit board to be inspected as the identifier to be inspected. In other implementations, multiple circuit boards produced can be pre-inspected. Circuit boards with defects found after pre-inspection can be used as the circuit boards to be inspected. If a defect is found in a circuit board after pre-inspection, the connection line corresponding to the defect can be obtained. At this time, the defective connection line can be directly used as the identifier to be inspected, including the identifier corresponding to the connection line to be inspected in the circuit board to be inspected. Then, based on the identifier to be inspected, defect inspection of the circuit board to be inspected can be performed, which can reduce the consumption of resources and improve the inspection efficiency.

[0047] Furthermore, the image corresponding to the circuit board to be inspected is the inspection image. It's easy to understand that the number of inspection images should correspond to the number of layers on the circuit board to be inspected. That is, if the circuit board to be inspected is single-layered, then there can be one inspection image; if the circuit board to be inspected includes multiple layers, then there are multiple inspection images, and each inspection image corresponds to one layer of the circuit board to be inspected.

[0048] Optionally, in addition to using the circuit board produced above as the circuit board to be tested, the packaging substrate produced can also be used as the circuit board to be tested, or the MLO board or SLP type carrier board produced can also be used as the circuit board to be tested. This application does not limit the scope of the application.

[0049] Step S120: Based on the identifier to be detected, extract the region corresponding to the connecting line of the identifier to be detected from the image to be detected, and use it as the target connecting line region.

[0050] In some implementations, to detect whether there are defects in the connecting lines corresponding to the identifier to be inspected on the circuit board to be inspected, the region corresponding to the connecting line of the identifier to be inspected can be extracted from the image to be inspected for the circuit board to be inspected, and designated as the target connecting line region. Then, based on the target connecting line region, it is determined whether there are defects in the connecting lines corresponding to the identifier to be inspected on the circuit board to be inspected.

[0051] If the circuit board to be tested has only one layer, the target area corresponding to the connecting line in the image to be tested can be directly determined based on the identification markings. Since the circuit board to be tested has only one layer, this layer is the top circuit board. It's easy to understand that the top circuit board typically has markings to represent different connecting lines, i.e., silkscreen information. For example, a "GND" marking can be set at the ground connection line to indicate that the connection line is a ground connection line, and a "3.3V" marking can be set at the 3.3V connection line to indicate that the connection line is a 3.3V power connection line. Therefore, when the circuit board to be tested has only one layer, the image corresponding to the top circuit board to be tested is the top image to be tested. First, the various markings in the top image to be tested can be obtained, and then each of the obtained markings can be compared with the identification markings to be tested. The markings that match the identification markings to be tested are taken as target markings. Then, the detection area corresponding to the connecting line of the target marking in the top image to be tested can be determined based on the target markings. At this point, the detection area corresponding to the connecting line of the target marking in the top image to be tested can be directly taken as the target connecting line area.

[0052] Furthermore, if the circuit board to be tested is multi-layered, the image to be tested corresponding to the circuit to be tested can include the top layer image to be tested and images of other layers to be tested. Similar to the method described above, the detection area corresponding to the connection line of the target identifier in the top layer image to be tested can also be determined by the target identifier. Then, based on the detection area and other layers of images to be tested, the target connection line area is jointly determined. For specific methods, please refer to the following embodiments.

[0053] Step S130: Based on the difference between the target connection line area and the standard connection line area, determine the identification result of the circuit board to be tested. The identification result is used to characterize whether there is a defect or not in the target connection line area.

[0054] It's easy to understand that the connection area defined by the design documents can be considered a standard connection area. Therefore, a standard connection area can be the connection area defined by the inspection mark in the design documents corresponding to the circuit board to be inspected. The smaller the difference between the connection area on the manufactured circuit board and the connection area defined by the design documents, the smaller the defects in the connection area of ​​the manufactured circuit board. When there is no difference between the connection area on the manufactured circuit board and the connection area defined by the design documents, it indicates that the target connection area of ​​the manufactured circuit board is free of defects.

[0055] In some implementations, the acquired target connection line area can be compared with a standard connection line area to determine the identification result of the circuit board to be inspected, wherein the identification result is used to characterize whether the target connection line area has defects or not.

[0056] It's easy to understand that if the range corresponding to the target connection area is the same as the range corresponding to the standard connection area, it indicates that there is no difference between the target connection area and the standard connection area, and in this case, it can be determined that the target connection area of ​​the circuit board under test is free of defects. If the range corresponding to the target connection area differs from the range corresponding to the standard connection area, it indicates that there is a difference between the target connection area and the standard connection area, and in this case, it can be determined that the target connection area of ​​the circuit board under test is defective.

[0057] Furthermore, the target connecting line area and the standard connecting line area differ, which may include the target connecting line area being larger than the standard connecting line area, or the target connecting line area being smaller than the standard connecting line area. By observing the different sizes of the target connecting line area and the standard connecting line area, it can be determined that the target connecting line area has different defects. For details, please refer to the description of the subsequent embodiments.

[0058] One example is that the target connecting line region can be identified by highlighting in the image to be detected.

[0059] The circuit testing method, apparatus, electronic device, computer-readable medium, and product provided in this application first acquire a test image and a test identifier corresponding to the circuit board to be tested. Then, based on the test identifier, the region corresponding to the connecting line of the test identifier is extracted from the test image as the target connecting line region. Finally, the identification result of the circuit board to be tested can be determined based on the difference between the target connecting line region and the standard connecting line region. The identification result is used to characterize whether the target connecting line region has a defect or not. Determining whether the circuit board to be tested has a defect by comparing all regions in the test image with all regions in the standard template image consumes a lot of computing resources, is time-consuming, and inefficient. Since the defective region in the circuit board to be tested is generally the region corresponding to the connecting line, this application determines whether the circuit board to be tested has a defect by determining the target connecting line region based on the test identifier and comparing the difference between the target connecting line region and the standard connecting line region. This reduces the consumption of computing resources, reduces processing time, and improves efficiency.

[0060] Please see Figure 5 , Figure 5 This application illustrates a circuit detection method provided by an embodiment of the present application. This method can be applied to electronic devices, and the specific execution subject can be a processor in the electronic device. The method includes steps S210 to S260.

[0061] Step S210: Obtain the image to be tested and the identification mark to be tested corresponding to the circuit board to be tested. The identification mark to be tested includes the identification mark corresponding to the connection line to be tested in the circuit board to be tested.

[0062] The process of obtaining the image and identifier of the circuit board to be tested has been described in detail in the previous embodiments and will not be repeated here.

[0063] In some implementations, the obtained image of the circuit board to be inspected may include different colors. For example, the circuit board may be marked with a green background, traces or vias in the circuit board may be marked with yellow, and chips or components on the circuit board may be marked with black. It is easy to understand that areas with defects on the circuit board to be inspected are generally traces or vias. Therefore, after obtaining the image of the circuit board to be inspected, the image can be preprocessed to highlight traces and vias. One example is that the obtained image can be binarized. Specifically, the grayscale value of each pixel in the image can be obtained, and then a specified threshold is set. The grayscale value of each pixel in the image is compared with the specified threshold. Pixels with grayscale values ​​less than the specified threshold are set to a first color, and pixels with grayscale values ​​equal to or greater than the specified threshold are set to a second color. Therefore, through this binarization process, the image to be detected can be processed to include only two colors, and by setting a specified threshold, the traces and vias can be displayed as one color, while other parts can be displayed as the second color.

[0064] Furthermore, as can be seen from the foregoing analysis, the circuit board to be tested may include multiple layers. Therefore, images to be tested can be collected for each layer of the circuit board to be tested, thereby obtaining multiple images to be tested, each of which corresponds to each layer of the circuit board to be tested.

[0065] Optionally, since each image to be detected may have a slight size error, in some implementations, the acquired images to be detected can be processed to ensure size consistency, so as to obtain images to be detected with consistent size.

[0066] Step S220: Obtain the identifier in the top-level image to be detected.

[0067] Step S230: Take the identifier in the top-level image to be detected that is the same as the identifier to be detected as the target identifier.

[0068] In some implementations, the circuit board to be tested comprises multiple layers, and the images to be tested comprise multiple images. It is easily understood that each image to be tested can be an image corresponding to each layer of the circuit board to be tested, thus each image to be tested corresponds sequentially to each layer of the circuit board to be tested. For example, if the circuit board to be tested comprises three layers, then there are three images to be tested, with the first layer corresponding to the first image to be tested, the second layer corresponding to the second image to be tested, and the third layer corresponding to the third image to be tested. The first layer of the circuit board to be tested can generally be the top layer, therefore the first image to be tested can be the top image to be tested.

[0069] As the foregoing analysis shows, the top-level circuit board under test generally has identification information to represent different connection lines. Therefore, the identification information in the top-level image under test can be obtained first. Further, the identification information in the top-level image under test that is identical to the identification information to be tested is taken as the target identification. For example, if the identification information in the top-level image under test includes "3.3V", "5V", "SIG", and "GND", and if the identification information to be tested obtained in the previous steps includes "GND", then it is easy to see that the identification "GND" in the top-level image under test is identical to the identification information to be tested, and therefore the identification "GND" can be taken as the target identification.

[0070] Step S240: Extract the region to be detected corresponding to the connecting line corresponding to the target identifier from the top-level image to be detected.

[0071] As can be seen from the foregoing analysis, in some implementation methods, the top-level circuit board to be tested includes connecting lines, and the target identifier corresponds to a portion of these connecting lines. Therefore, the top-level image to be tested also contains the connecting lines included in the top-level circuit board to be tested, thus allowing the detection area corresponding to the connecting lines of the target identifier to be extracted from the top-level image to be tested.

[0072] The top-level image to be detected contains icons, each with a corresponding connecting line. Furthermore, different icons correspond to different connecting lines. Therefore, the area in the top-level image where the connecting line corresponding to the target icon is located can be considered as the detection area.

[0073] Optionally, in other implementations, after obtaining the identifier to be inspected, the corresponding area of ​​the identifier can be found in the design file of the circuit board to be inspected. The design file includes a standard identifier and the corresponding connecting line area. Then, the design file is compared with the top-level image to be inspected to determine the area to be inspected in the top-level image.

[0074] Step S250: Based on the area to be detected, determine the target connecting line area.

[0075] As described in the preceding steps, the area to be inspected is the corresponding area in the top-level image to be inspected. However, the circuit board to be inspected may include multiple layers. If only the area to be inspected in the top-level image is determined, it essentially means that only the area to be inspected in the top-level circuit board is being inspected for defects, which may result in missing defects in other layers. Therefore, after determining the area to be inspected corresponding to the top-level image, corresponding areas in other layers of images to be inspected can also be determined based on the area to be inspected. This allows the area to be inspected and the corresponding areas to be integrated to obtain the target connection line area. Thus, the target connection line area includes the area in each layer of the circuit board to be inspected that corresponds to the inspection mark.

[0076] For details, please refer to Figure 6 , Figure 6 A diagram illustrating one embodiment of step S250 is shown, specifically including steps S251 and S252.

[0077] Step S251: From each of the multiple images to be detected, excluding the top-level image to be detected, determine the subordinate regions to be detected that have a connection relationship with the region to be detected.

[0078] Step S252: Based on the region to be detected and the subordinate regions to be detected, the target connection line region is obtained by integration.

[0079] As the foregoing analysis shows, each layer of the circuit board under test can include connecting lines, and these connecting lines can be electrically connected to each other. Therefore, after determining the area to be tested using the top-layer image, since this area is essentially the region corresponding to the connecting line to be tested in the top-layer image, it is possible to obtain subordinate areas to be tested that are connected to the area to be tested in each of the multiple images under test (excluding the top-layer image). This allows us to obtain the subordinate connecting lines to be tested that are connected to the connecting lines in each layer of the circuit board under test (excluding the top-layer image).

[0080] The connection relationships can include direct and indirect connections. Regions in the next image to be detected that are directly connected to the region to be detected can be considered as having a direct connection to the region to be detected. Furthermore, in images other than the top image and its next image, regions connected to the region to be detected can be considered as having an indirect connection. For details, please refer to [link to relevant documentation]. Figure 7 , Figure 7A diagram illustrating one embodiment of step S251 is shown, specifically including steps S253 and S254.

[0081] Step S253: Based on the detection order, the region in the next image to be detected after the top-level image to be detected that is connected to the region to be detected is taken as a subordinate region to be detected with a direct connection relationship.

[0082] Step S254: Based on the detection order, traverse each subsequent image to be detected, and in each subsequent image to be detected, the region connected to the subordinate detection region with a direct connection relationship is taken as the subordinate detection region with an indirect connection relationship.

[0083] In some implementations, in a multilayer circuit board to be tested, each layer of the circuit board to be tested corresponds to one image to be tested, and multiple images to be tested can be arranged in a testing order, wherein the testing order can be the order in which the multilayer circuit boards to be tested are arranged.

[0084] Therefore, after determining the region to be detected through the aforementioned steps, based on the detection order, the region in the next image to be detected after the top-level image to be detected that is connected to the region to be detected can be regarded as a subordinate region to be detected with a direct connection relationship.

[0085] Specifically, determining the region connected to the area to be detected essentially involves determining whether the connecting lines corresponding to the area to be detected included in the top-level image to be detected have an electrical connection with the connecting lines in the next image to be detected. In one implementation, the top-level image to be detected after the aforementioned preprocessing steps and the next image to be detected can be overlaid. Then, it is checked whether there is a connecting line in the next image to be detected that at least partially overlaps with the connecting line corresponding to the area to be detected in the top-level image. If so, it can be determined that the connecting line with at least partial overlap has a direct connection relationship with the connecting line corresponding to the area to be detected. Therefore, the area corresponding to the connecting line with a direct connection relationship in the next image to be detected can be considered a subordinate area to be detected.

[0086] Furthermore, the circuit board to be inspected can be multi-layered. Therefore, following the inspection sequence, each subsequent image to be inspected can be traversed to check if there exists a connecting line in each image that at least partially overlaps with the connecting line corresponding to the subordinate inspection area in the next image. If such a connecting line exists, it can be determined that the partially overlapping connecting line is connected to the connecting line corresponding to the subordinate inspection area, thus determining that the partially overlapping connecting line is indirectly connected to the connecting line corresponding to the inspection area in the top-level image. Therefore, the area corresponding to the connecting line with the indirect connection can be considered the subordinate inspection area.

[0087] As the analysis above shows, for multi-layer circuit boards under test, the top layer is generally a trace layer, and trace layers and via layers are usually spaced apart. Therefore, the layer below a trace layer can be a via layer, and the layer below a via layer can be another trace layer. Thus, for example, when traversing each subsequent image under test, if the current image under test is the nth trace layer, then the connecting lines in the current image under test include traces. If the layer below the current image under test is the mth via layer, then tracetovia(Ln, Vm) can be used to represent finding the related subordinate areas under test in the mth via layer through the nth trace layer. If the current image to be detected is the m-th punched layer, then it can be known that the connecting lines in the current image to be detected include vias. If the next layer of the current image to be detected is the n-th routing layer, then viatotrace(Vm, Ln) can be used to find the related subordinate regions to be detected in the m-th punched layer through the n-th routing layer.

[0088] Therefore, in some implementations, if we assume that the multilayer circuit board to be tested includes x+y layers, specifically including an x-layer routing layer and a y-layer via layer, the top layer to be tested may include the first routing layer, and can therefore be represented by L1. The next layer to be tested may include the first via layer, and can therefore be represented by V1. Thus, by first calling tracetovia(L1, V1), we can find the regions in the first via layer that are connected to the regions to be tested in the first routing layer, which are considered as subordinate regions to be tested with a direct connection. Furthermore, we can execute viatotrace(V1, L2) to find the regions in the second routing layer that are connected to the subordinate regions to be tested in the first via layer, which are considered as subordinate regions to be tested with an indirect connection. Furthermore, you can continue to execute tracetovia and viatotrace at intervals. For example, you can execute tracetovia(L2,V2) until tracetovia(L(x-1),Vy) and viatotrace(Vy,Lx), thereby traversing each image to be detected.

[0089] Optionally, after traversing each image to be detected, you can start from the bottom-most image and traverse each image again. That is, start by executing `tracetovia(Lx, Vy)`, then execute `viatotrace(L(x-1), Vy)`, and so on until `tracetovia(L2, V1)` and `viatotrace(V_1, L_1)`, thus traversing all images to be detected. The number of times each image is traversed can be set according to user needs. It's easy to understand that the more times each image is traversed, the higher the accuracy of identifying subordinate regions connected to the detected region; conversely, the fewer times each image is traversed, the shorter the traversal time and the less computational resources consumed.

[0090] Furthermore, after removing the subordinate regions to be detected, the target connection line region can be obtained by integrating the regions to be detected and the subordinate regions to be detected.

[0091] Step S260: Based on the difference between the target connection line area and the standard connection line area, determine the identification result of the circuit board to be tested. The identification result is used to characterize whether there is a defect or not in the target connection line area.

[0092] Step S260 has been described in detail in the foregoing embodiments and will not be repeated here.

[0093] Please see Figure 8 , Figure 8This application illustrates a circuit detection method provided by an embodiment of the present application. This method can be applied to electronic devices, and the specific execution subject can be a processor in the electronic device. The method includes steps S310 to S350.

[0094] Step S310: Among multiple circuit boards, identify those with open circuits or short circuits, and designate them as the circuit boards to be tested.

[0095] Step S320: The identifiers corresponding to the open or short circuits in the connection lines of the circuit board to be tested are used as the identifiers to be tested.

[0096] In some implementation methods, since the number of circuit boards produced is generally large, treating each produced circuit board as a test board and checking for defects using the methods described in the foregoing embodiments would consume significant processing resources and reduce processing efficiency. Therefore, pre-inspection can be performed on the produced circuit boards, such as open-circuit / short-circuit testing. Open-circuit / short-circuit testing identifies circuit boards with open or short circuits, allowing these to be used as test boards. This reduces the number of circuit boards to be tested without affecting the accuracy of the inspection, thus reducing resource consumption and improving processing efficiency.

[0097] Furthermore, if a defect is found in the circuit board after pre-inspection, the corresponding connection line can be obtained. This defective connection line can then be directly used as the identifier to be inspected, including the identifier corresponding to the connection line to be inspected in the circuit board. Defect inspection of the circuit board can then be performed based on this identifier. As described in the example above, if the pre-inspection is an open / short circuit detection, the circuit board to be inspected, after the open / short circuit detection, can also be identified, along with the identifier corresponding to the open or short circuit connection line. For example, if the "GND" connection line is short-circuited, the identifier "GND" can be obtained as the identifier to be inspected.

[0098] Step S330: Obtain the image to be tested and the identification mark to be tested corresponding to the circuit board to be tested. The identification mark to be tested includes the identification mark corresponding to the connection line to be tested in the circuit board to be tested.

[0099] Step S340: Based on the identifier to be detected, extract the region corresponding to the connecting line of the identifier to be detected from the image to be detected, and use it as the target connecting line region.

[0100] Step S350: Based on the difference between the target connection line area and the standard connection line area, determine the identification result of the circuit board to be tested. The identification result is used to characterize whether there is a defect or not in the target connection line area.

[0101] Steps S330 and S340 have been described in detail in the foregoing embodiments and will not be repeated here.

[0102] In some implementations, defects can include open circuits and short circuits. By comparing the target connection area with a standard connection area, it can be determined whether the target connection area of ​​the circuit board under test has a defect or not. Furthermore, when a defect exists in the target connection area, it can be determined whether the defect is an open circuit or a short circuit. For details, please refer to [link to relevant documentation]. Figure 9 , Figure 9 A diagram illustrating one embodiment of step S350 is shown, including steps S351 and S352.

[0103] Step S351: If the range corresponding to the target connection line area is larger than the range corresponding to the standard connection line area, the area outside the range corresponding to the target connection line area is determined as the area on the circuit board to be tested where the target connection line area has a short circuit.

[0104] Step S352: If the range corresponding to the target connection line area is smaller than the range corresponding to the standard connection line area, the area outside the range corresponding to the standard connection line area is determined as the area on the circuit board to be tested where the target connection line area has an open circuit.

[0105] It is easy to understand that if the range corresponding to the target connection line area is larger than the range corresponding to the standard connection line area, it indicates that there are still some target connection lines outside the standard connection line area, which may cause a short circuit. Since the circuit board under test has open circuits or short circuits, it can be determined that the target connection line area on the circuit board under test has a short circuit. Specifically, the area with a short circuit can be the area outside the range corresponding to the standard connection line area, excluding the range corresponding to the target connection line area.

[0106] Similarly, if the range corresponding to the target connection area is smaller than the range corresponding to the standard connection area, it indicates that within the range corresponding to the standard connection area, there are still some areas where the target connection area is absent, which may cause an open circuit. Since the circuit board under test has an open circuit or a short circuit, it can be determined that the target connection area on the circuit board under test has an open circuit. Specifically, the area with a short circuit can be any area within the range corresponding to the standard connection area, excluding the area corresponding to the target connection area. Similarly, the area with an open circuit can be any area within the range corresponding to the standard connection area, excluding the area corresponding to the target connection area.

[0107] The circuit testing method, apparatus, electronic device, computer-readable medium, and product provided in this application first identify the circuit board to be tested from multiple circuit boards, and use the identifiers corresponding to the open-circuit or short-circuit connections on the circuit board to be tested as the test identifiers. Then, an image of the circuit board to be tested and the test identifiers are acquired. Based on the test identifiers, the area corresponding to the connection lines of the test identifiers is extracted from the image to be tested as the target connection line area. Finally, the identification result of the circuit board to be tested can be determined based on the difference between the target connection line area and the standard connection line area, where the identification result indicates whether the target connection line area has a defect or not. If the identification result is determined for each manufactured circuit board based on the difference between the target connection line area and the standard connection line area, it will consume a lot of processing resources and reduce testing efficiency. However, this application, by identifying the circuit board to be tested with open-circuit or short-circuit defects from multiple manufactured circuit boards and then testing the circuit board to be tested, can reduce the processing resource consumption and improve processing efficiency without reducing the accuracy of defect detection.

[0108] Please see Figure 10 The diagram shows a structural block diagram of a circuit detection device 1000 provided in an embodiment of this application, including: an acquisition unit 1010, an extraction unit 1020, and a determination unit 1030.

[0109] The acquisition unit 1010 is used to acquire the image to be tested and the identification to be tested corresponding to the circuit board to be tested, wherein the identification to be tested includes the identification corresponding to the connection line to be tested in the circuit board to be tested.

[0110] Furthermore, the acquisition unit 1010 is also used to detect, among multiple circuit boards, circuit boards with open circuits or short circuits, as circuit boards to be tested; and to use the identifiers corresponding to the connection lines with open circuits or short circuits in the circuit boards to be tested as the identifiers to be tested.

[0111] The extraction unit 1020 is used to extract the region corresponding to the connecting line of the identifier to be detected from the image to be detected, based on the identifier to be detected, as the target connecting line region.

[0112] Furthermore, the extraction unit 1020 is also used to obtain the identifier in the top-level image to be detected; take the identifier in the top-level image to be detected that is the same as the identifier to be detected as the target identifier; extract the region to be detected corresponding to the connecting line corresponding to the target identifier from the top-level image to be detected; and determine the target connecting line region based on the region to be detected.

[0113] Furthermore, the extraction unit 1020 determines subordinate regions that have a connection relationship with the region to be detected from each of the multiple images to be detected, excluding the top-level image to be detected; and integrates the region to be detected and the subordinate regions to be detected to obtain the target connection line region.

[0114] Furthermore, based on the detection order, the extraction unit 1020 identifies regions connected to the detection region in the next detection image after the top-level detection image as subordinate detection regions with a direct connection relationship; and based on the detection order, it traverses each subsequent detection image and identifies regions connected to subordinate detection regions with a direct connection relationship in each subsequent detection image as subordinate detection regions with an indirect connection relationship.

[0115] The determining unit 1030 is used to determine the identification result of the circuit board to be tested based on the difference between the target connection line area and the standard connection line area. The identification result is used to characterize whether there is a defect or not in the target connection line area.

[0116] Furthermore, the determining unit 1030 is also configured to, if the range corresponding to the target connection area is larger than the range corresponding to the standard connection area, determine the area outside the range corresponding to the target connection area as a short circuit area on the circuit board to be tested; if the range corresponding to the target connection area is smaller than the range corresponding to the standard connection area, determine the area outside the range corresponding to the target connection area as an open circuit area on the circuit board to be tested.

[0117] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the above-described apparatus and unit can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0118] In the several embodiments provided in this application, the coupling between the units can be electrical, mechanical or other forms of coupling.

[0119] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0120] Please see Figure 11 , Figure 11This paper illustrates a structural block diagram of an electronic device 1100 provided in an embodiment of this application. The circuit detection method provided in the foregoing embodiments of this application can be applied to this electronic device 1100. The electronic device 1100 in this application may include one or more of the following components: a processor 1110 and a memory 1120, and one or more application programs, wherein the processor 1110 is electrically connected to the memory 1120, and the one or more programs are configured to execute the method as described in the foregoing method embodiments.

[0121] Processor 1110 may include one or more processing cores. Processor 1110 connects to various parts within the electronic device 100 using various interfaces and lines, and performs various functions and processes data of the electronic device 100 by running or executing instructions, programs, code sets, or instruction sets stored in memory 1120, and by calling data stored in memory 1120. Optionally, processor 1110 may be implemented using at least one hardware form of Digital Signal Processing (DSP), Field-Programmable Gate Array (FPGA), or Programmable Logic Array (PLA). Processor 1110 may integrate one or more of the following: Central Processing Unit (CPU), Graphics Processing Unit (GPU), and modem. The CPU primarily handles the operating system, user interface, and computer programs; the GPU is responsible for rendering and drawing the displayed content; and the modem handles wireless communication. It is understood that the modem may also not be integrated into processor 1110 and may be implemented separately using a communication chip. Specifically, the processor 1110 can be used to execute the methods described in the above embodiments.

[0122] In some implementations, memory 1120 may include random access memory (RAM) or read-only memory (ROM). Memory 1120 can be used to store instructions, programs, code, code sets, or instruction sets. Memory 1120 may include a program storage area and a data storage area, wherein the program storage area may store instructions for implementing an operating system, instructions for implementing at least one function, instructions for implementing the various method embodiments described below, etc. The data storage area may also store data created by the electronic device 1100 during use.

[0123] Please refer to Figure 12This diagram illustrates a structural block diagram of a computer-readable storage medium provided in an embodiment of this application. The computer-readable medium 1200 stores program code that can be called by a processor to execute the methods described in the above method embodiments.

[0124] The computer-readable storage medium 1200 may be an electronic memory such as flash memory, EEPROM (Electrically Erasable Programmable Read-Only Memory), EPROM, hard disk, or ROM. Optionally, the computer-readable storage medium 1200 includes a non-transitory computer-readable storage medium. The computer-readable storage medium 1200 has storage space for program code 1210 that performs any of the method steps described above. This program code can be read from or written to one or more computer program products. The program code 1210 may, for example, be compressed in a suitable form.

[0125] Please refer to Figure 13 The diagram illustrates a structural block diagram 1300 of a computer program product provided in an embodiment of this application. The computer program product 1300 includes a computer program / instructions 1310, which, when executed by a processor, implements the steps of the aforementioned method.

[0126] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A circuit detection method, characterized in that, The method includes: Multiple circuit boards are tested for open circuit or short circuit to identify those with open circuit or short circuit, which are then designated as the circuit boards to be tested. The identifiers corresponding to the open or short circuits in the circuit board to be tested are used as the test identifiers. Obtain the image to be inspected corresponding to the circuit board to be inspected. The circuit board to be inspected is a single-layer circuit board. The image to be inspected is the top layer image to be inspected. The top layer image to be inspected includes the identifiers of multiple silkscreen information. The identifiers of each silkscreen information are compared with the identifiers to be detected. The identifiers that are the same as the identifiers to be detected are taken as the target identifiers. Then, the detection area corresponding to the connecting line of the target identifier in the top-level image to be detected is determined by the target identifiers, and it is taken as the target connecting line area. Based on the difference between the target connection area and the standard connection area determined by the identification to be tested through the design document, the identification result of the circuit board to be tested is determined, and the identification result is used to characterize whether the target connection area has defects or not.

2. The method according to claim 1, characterized in that, The circuit board to be inspected comprises multiple layers, and the images to be inspected comprise multiple images, each image corresponding sequentially to each layer of the circuit board to be inspected. The step of extracting the region corresponding to the connecting line of the identifying mark from the images to be inspected, as the target connecting line region, includes: Obtain the identifier from the top-level image to be detected; The identifier in the top-level image to be detected that is identical to the identifier to be detected is taken as the target identifier; The detection region corresponding to the connecting line corresponding to the target identifier is extracted from the top-level image to be detected; Based on the area to be detected, the target connecting line area is determined.

3. The method according to claim 2, characterized in that, Determining the target connector region based on the region to be detected includes: From each of the multiple images to be detected, excluding the top-level image, a subordinate region to be detected that has a connection relationship with the region to be detected is determined. The target connection line region is obtained by integrating the region to be detected and the subordinate regions to be detected.

4. The method according to claim 3, characterized in that, Multiple images to be detected are arranged in detection order. The connection relationships include direct and indirect connections. The step of determining subordinate regions to be detected that have a connection relationship with the region to be detected from each of the multiple images to be detected, excluding the top-level image, includes: Based on the detection order, the region in the next image to be detected after the top-level image to be detected that is connected to the region to be detected is regarded as a subordinate region to be detected with a direct connection relationship. Based on the detection order, each subsequent image to be detected is traversed, and the region in each subsequent image to be detected that is directly connected to a subordinate region to be detected is taken as a subordinate region to be detected that has an indirect connection.

5. The method according to claim 1, characterized in that, The defects include open circuits and short circuits. The determination of the identification result of the circuit board under test based on the difference between the target connection area and the standard connection area includes: If the range corresponding to the target connection area is larger than the range corresponding to the standard connection area, the area outside the range corresponding to the target connection area, excluding the range corresponding to the standard connection area, is determined as the area on the circuit board to be tested where the target connection area has a short circuit. If the range corresponding to the target connection area is smaller than the range corresponding to the standard connection area, the area outside the range corresponding to the standard connection area is determined as the area on the circuit board to be tested where the target connection area has an open circuit.

6. A circuit testing device, characterized in that, The device includes: The acquisition unit is used to perform open circuit or short circuit detection on multiple circuit boards to detect the circuit boards with open circuits or short circuits as the circuit boards to be tested. The identifiers corresponding to the open or short circuit connection lines in the circuit board to be tested are used as the identifiers to be tested; the image to be tested corresponding to the circuit board to be tested is obtained. The circuit board to be tested is a single-layer circuit board, and the image to be tested is the top layer image to be tested. The top layer image to be tested includes multiple silkscreen information identifiers. The extraction unit is used to compare the identifiers of each silkscreen information with the identifiers to be detected, and to take the identifiers that are the same as the identifiers to be detected as the target identifiers. Then, the target identifiers determine the detection area corresponding to the connecting lines of the target identifiers in the top-level image to be detected, which is taken as the target connecting line area. The determining unit is used to determine the identification result of the circuit board to be inspected based on the difference between the target connection line area and the standard connection line area determined by the identification to be inspected through the design document. The identification result is used to characterize whether the target connection line area has a defect or not.

7. An electronic device, characterized in that, include: One or more processors; Memory; One or more applications, wherein the one or more applications are stored in the memory and configured to be executed by the one or more processors, the one or more applications being configured to perform the method as described in any one of claims 1-5.

8. A computer-readable storage medium, characterized in that, The computer-readable storage medium contains program code that can be invoked by a processor to execute the method as described in any one of claims 1-5.

9. A computer program product, comprising a computer program or instructions, characterized in that, When the computer program or instructions are executed by a processor, they implement the method described in any one of claims 1-5.

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