A shift register circuit, a display panel and a display device

Abstract

The present invention discloses a shift register circuit, a display panel and a display device, comprising: a charge pump unit controls the amount of a signal coupled from a second clock terminal to a third node; a signal input unit controls the potential of a first node according to a first clock signal of a first clock terminal, an input signal of a signal input terminal and the potential of a third node; an isolation module disconnects the path between the third node and the first node at least at the start of the input signal jumping to an enable level for controlling the first output transistor to turn on, and connects the path between the third node and the first node at least when the input signal is a non-enable level for controlling the first output transistor to turn off, according to an isolation control signal; a second control module controls the potential of a second node according to a signal input unit, a first clock signal, a second clock signal, a first level signal and a second level signal. The above technical scheme can solve the problem of tailing caused by unstable output signal of a shift register circuit and improve the display quality.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of display technology, and in particular to a shift register circuit, a display panel, and a display device. Background Art

[0002] With the development of display technology, people have higher and higher requirements for display quality. In the prior art, a pixel circuit is provided in the display panel, and a drive signal is output through a scanning drive circuit to drive the pixel circuit in the display panel to display the picture. The drive circuit usually includes a plurality of cascaded shift register circuits. However, when the shift register circuit is working, the output signal is prone to instability, resulting in a tailing problem, thereby affecting the display quality of the entire display device. Summary of the invention

[0003] The present invention provides a shift register circuit, a display panel and a display device to solve the problem that the output signal of the shift register circuit is prone to instability and tailing when working, thereby improving the display quality.

[0004] In a first aspect, an embodiment of the present invention provides a shift register circuit, comprising: a first control module, a second control module, an isolation module and an output module;

[0005] The output module includes a first output transistor and a second output transistor; the gate of the first output transistor is electrically connected to a first node, the first electrode of the first output transistor is electrically connected to a first level end, and the second electrode of the first output transistor is electrically connected to a signal output end; the gate of the second output transistor is electrically connected to a second node, the second electrode of the second output transistor is electrically connected to a second level end, and the second electrode of the second output transistor is electrically connected to the signal output end;

[0006] The first control module includes a signal input unit and a charge pump unit; the signal input unit is electrically connected to the first clock terminal, the signal input terminal, the first node and the third node respectively; the charge pump unit is electrically connected to the second clock terminal and the third node respectively; the charge pump unit is used to control the amount of the signal coupled from the second clock terminal to the third node; the signal input unit is used to control the potential of the first node according to the first clock signal of the first clock terminal, the input signal of the signal input terminal and the potential of the third node;

[0007] The isolation module is electrically connected to the third node, the first node and the isolation control terminal respectively; the isolation module is used to disconnect the path between the third node and the first node at least in the initial stage when the input signal jumps to the enable level for controlling the first output transistor to be turned on, and to connect the path between the third node and the first node at least when the input signal is at the non-enable level for controlling the first output transistor to be turned off, according to the isolation control signal of the isolation control terminal;

[0008] The second control module is electrically connected to the signal input unit, the first clock end, the second clock end, the second node, the first level end and the second level end, respectively, and is used to control the potential of the second node under the control of the signal input unit, the first clock signal, the second clock signal, the first level signal of the first level end and the second level signal of the second level end.

[0009] In a second aspect, an embodiment of the present invention further provides a display panel, comprising: a plurality of pixel circuits arranged in an array and a plurality of cascaded shift register circuits as described in the first aspect;

[0010] The signal output end of the shift register circuit at each level is electrically connected to at least part of the pixel circuits located in the same row; except for the shift register circuit at the last level, the signal output end of the shift register circuit at each remaining level is electrically connected to the signal input end of the shift register circuit at the next level, and the signal input end of the shift register circuit at the first level receives a start pulse signal.

[0011] In a third aspect, an embodiment of the present invention further provides a display device, comprising the display panel described in the third aspect.

[0012] The technical solution of the present invention is to disconnect the path between the third node and the first node at least in the starting stage when the input signal jumps to the enable level for controlling the conduction of the first output transistor, that is, the stage when the signal output end jumps from outputting the second level signal to the first level signal, by setting the isolation module according to the isolation control signal of the isolation control end. In this way, the first level signal output by the signal output end can pull down the potential of the gate of the first output transistor, that is, the potential of the first node, through the coupling effect of the parasitic capacitance of the first output transistor, to ensure that the potential of the first node is low enough, so that the opening degree of the first output transistor is large enough, and the first level signal is completely output through the first output transistor; at the same time, because the isolation module disconnects the path between the third node and the first node, it can be avoided that the second clock signal of the second clock end is coupled through the charge pump unit to affect the potential stability of the first node, thereby avoiding affecting the accurate and stable output of the signal output end, avoiding the tailing problem, and improving the display quality. In addition, the isolation module turns on the path between the third node and the first node according to the isolation control signal of the isolation control end at least when the input signal is a non-enable level for controlling the shutdown of the first output transistor, so that the charge pump unit controls the amount of the signal coupled from the second clock end to the third node, and then can control the potential of the first node to always be maintained within the non-enable level range, thereby ensuring the potential stability of the first node, so that the signal output end outputs a stable signal, thereby improving the display quality.

[0013] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0015] Figure 1 A schematic diagram of the structure of a shift register circuit provided by an embodiment of the present invention;

[0016] Figure 2 A driving timing diagram of a shift register circuit provided by an embodiment of the present invention;

[0017] Figure 3 A schematic diagram of the structure of another shift register circuit provided by an embodiment of the present invention;

[0018] Figure 4A schematic structural diagram of another shift register circuit provided by an embodiment of the present invention;

[0019] Figure 5 A schematic structural diagram of another shift register circuit provided by an embodiment of the present invention;

[0020] Figure 6 A schematic structural diagram of another shift register circuit provided by an embodiment of the present invention;

[0021] Figure 7 A schematic structural diagram of another shift register circuit provided by an embodiment of the present invention;

[0022] Figure 8 A schematic structural diagram of another shift register circuit provided by an embodiment of the present invention;

[0023] Fig. 9 A schematic structural diagram of another shift register circuit provided by an embodiment of the present invention;

[0024] Fig.10 A schematic structural diagram of another shift register circuit provided by an embodiment of the present invention;

[0025] Fig.11 A schematic structural diagram of another shift register circuit provided by an embodiment of the present invention;

[0026] Fig.12 A schematic structural diagram of another shift register circuit provided by an embodiment of the present invention;

[0027] Fig.13 A schematic structural diagram of another shift register circuit provided by an embodiment of the present invention;

[0028] Fig.14 A schematic structural diagram of another shift register circuit provided by an embodiment of the present invention;

[0029] Fig.15 A schematic diagram of the structure of a display panel provided by an embodiment of the present invention;

[0030] Fig.16 A schematic structural diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0031] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0032] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0033] Figure 1 A schematic diagram of a shift register circuit provided by an embodiment of the present invention is shown in FIG. Figure 1 As shown, the shift register circuit includes a first control module 10 , a second control module 20 , an isolation module 30 and an output module 40 .

[0034] The output module 40 includes a first output transistor T1 and a second output transistor T2; the gate of the first output transistor T1 is electrically connected to the first node N1, the first electrode of the first output transistor T1 is electrically connected to the first level terminal VGL, and the second electrode of the first output transistor T1 is electrically connected to the signal output terminal OUT; the gate of the second output transistor T2 is electrically connected to the second node N2, the second electrode of the second output transistor T2 is electrically connected to the second level terminal VGH, and the second electrode of the second output transistor T2 is electrically connected to the signal output terminal OUT.

[0035] The first control module 10 includes a signal input unit 11 and a charge pump unit 12; the signal input unit 11 is electrically connected to the first clock terminal CK, the signal input terminal IN, the first node N1 and the third node N3 respectively; the charge pump unit 12 is electrically connected to the second clock terminal XCK and the third node N3 respectively; the charge pump unit 12 is used to control the signal amount coupled from the second clock terminal XCK to the third node N3; the signal input unit 11 is used to control the potential of the first node N1 according to the first clock signal ck of the first clock terminal CK, the input signal Vin of the signal input terminal IN and the potential of the third node N3.

[0036] The isolation module 30 is electrically connected to the third node N3, the first node N1 and the isolation control terminal SX respectively; the isolation module 30 is used to disconnect the path between the third node N3 and the first node N1 at least in the initial stage when the input signal Vin jumps to the enable level for controlling the first output transistor T1 to be turned on, and to turn on the path between the third node N3 and the first node N1 at least when the input signal Vin is a non-enable level for controlling the first output transistor T1 to be turned off.

[0037] The second control module 20 is electrically connected to the signal input unit 11, the first clock terminal CK, the second clock terminal XCK, the second node N2, the first level terminal VGL and the second level terminal VGH, and is used to control the potential of the second node N2 under the control of the signal input unit 11, the first clock signal ck, the second clock signal xck, the first level signal Vgl of the first level terminal VGL and the second level signal Vgh of the second level terminal VGH.

[0038] Among them, the first clock signal ck may be a pulse signal that alternates between a high level signal (such as vgh) and a low level signal (such as vgl), and similarly, the second clock signal xck may also be a pulse signal that alternates between a high level vgh and a low level vgl. Usually, a high level vgh and a low level vgl that is continuous with it constitute a pulse cycle, and the enable levels of the second clock signal xck and the first clock signal ck do not overlap each other, that is, when the first clock signal ck is a high level vgh, the second clock signal xck may be a low level vgl, and vice versa, when the first clock signal ck is a low level vgl, the second clock signal xck may be a high level vgh. The low level vgl may be the enable level of the first clock signal ck and the second clock signal xck, and the high level vgh may be the non-enable level of the first clock signal ck and the second clock signal xck; or, the high level vgh may be the enable level of the first clock signal ck and the second clock signal xck, and the low level vgl may be the non-enable level of the first clock signal ck and the second clock signal xck. It can be understood that the enable level and the disable level of the first clock signal ck and the second clock signal xck can be set as required, and the embodiment of the present invention does not specifically limit this.

[0039] The first level signal Vgl of the first level terminal VGL and the second level signal Vgh of the second level terminal VGH can be fixed signals. For example, when the first level signal Vgl of the first level terminal VGL is a low level signal (for example, vgl), the second level signal Vgh of the second level terminal VGH can be a high level signal (for example, vgh); conversely, when the first level signal Vgl of the first level terminal VGL is a high level signal vgh, the second level signal Vgh of the second level terminal VGH can be a low level signal vgl. It can be understood that the first level signal Vgl of the first level terminal VGL and the second level signal Vgh of the second level terminal VGH can be set as needed, and the embodiment of the present invention does not specifically limit this.

[0040] The isolation control signal sx of the isolation control terminal SX may also be a pulse signal that alternates between a high level signal (e.g., vgh) and a low level signal (e.g., vgl). For example, when the isolation control signal sx is at a high level vgh, the isolation module 30 may be controlled to conduct the path between the third node N3 and the first node N1. Conversely, when the isolation control signal sx is at a low level vgl, the isolation module 30 may be controlled to disconnect the path between the third node N3 and the first node N1. It is understandable that the isolation control signal sx controls the isolation module 30 to conduct or disconnect the path between the third node N3 and the first node N1. The specific signal can be set as needed, and the embodiment of the present invention does not specifically limit this.

[0041] It should be noted that the isolation control signal sx that controls the isolation module 30 to disconnect the path between the third node N3 and the first node N1 can be the same as or different from the enable level that controls the first output transistor T1 to turn on, and can be set as needed. The embodiment of the present invention does not specifically limit this.

[0042] Continue to refer Figure 1 The output module 40 may further include a capacitor C400 electrically connected between the second level terminal VGH and the second node N2 to store the potential of the second node N2 and maintain the stability of the potential of the second node N2.

[0043] The channel types of the first output transistor T1 and the second output transistor T2 may be the same or different, and the embodiment of the present invention does not limit this. When the first output transistor T1 is a P-channel transistor, the enable level of the second node N2 that controls the first output transistor T1 to be turned on is a low level vgl, so that the first level signal Vgl of the first level terminal VGL is transmitted to the signal output terminal OUT, otherwise, the non-enable level of the second node N2 that controls the first output transistor T1 to be turned off is a high level vgh. When the first output transistor T1 is an N-channel transistor, the enable level of the second node N2 that controls the first output transistor T1 to be turned on is a high level vgh, so that the first level signal Vgl of the first level terminal VGL is transmitted to the signal output terminal OUT, otherwise, the non-enable level of the second node N2 that controls the first output transistor T1 to be turned off is a low level vgl. Similarly, when the second output transistor T2 is a P-channel transistor, the enable level of the second node N2 that controls the second output transistor T2 to be turned on is a low level vgl, so that the second level signal Vgh of the second level terminal VGH is transmitted to the signal output terminal OUT, otherwise, the non-enable level of the second node N2 that controls the second output transistor T2 to be turned off is a high level vgh. When the second output transistor T2 is an N-channel transistor, the enable level of the second node N2 that controls the second output transistor T2 to be turned on is a high level vgh, so that the second level signal Vgh of the second level terminal VGH is transmitted to the signal output terminal OUT, otherwise, the non-enable level of the second node N2 that controls the second output transistor T2 to be turned off is a low level vgl.

[0044] For example, Figure 2 A driving timing diagram of a shift register circuit provided by an embodiment of the present invention, combined with reference to Figure 1 and Figure 2 As shown, taking the first output transistor T1 and the second output transistor T2 as P-channel transistors, when the isolation control signal sx of the isolation control terminal SX is at a high level vgh, the isolation transistor T3 is controlled to disconnect the path between the third node N3 and the first node N1 as an example.

[0045] In the stage t1, the input signal Vin is a non-enable level (i.e., a high level vgh) for controlling the first output transistor T1 to be turned off, the isolation control signal sx of the isolation control terminal SX is a high level vgh, and the path between the third node N3 and the first node N1 is turned on. The signal input unit 11 controls the potential of the first node N1 under the control of the first clock signal ck of the first clock terminal CK and the potential of the third node N3, so that the potential of the first node N1 is maintained at a high level vgh, and the first output transistor T1 is controlled to be turned off. At the same time, in at least part of the stage when the input signal Vin is a high level vgh, the isolation module 30, under the control of the isolation control signal sx, can turn on the path between the third node N3 and the first node N1, so that the potential of the first node N1 matches the potential of the third node N3. At this time, the charge pump unit 12 controls the signal amount coupled from the second clock terminal XCK to the third node N3, so that the potential of the first node N1 can always be maintained within the non-enable level range. Correspondingly, the second control module 20 controls the potential of the second node N2 under the control of the first clock terminal CK, the second clock terminal XCK, the first level signal Vgl, the second level signal Vgh and the signal input unit 11, so that when the potential of the second node N2 is at the enable level (low level vgl), the second output transistor T2 is controlled to be turned on, and the second level signal Vgh (high level vgh) is transmitted to the signal output terminal OUT.

[0046] In the t2 stage, the input signal Vin is the enable level (i.e., the low level vgl) for controlling the conduction of the first output transistor T1, the isolation control signal sx of the isolation control terminal SX is the low level vgl, the path between the third node N3 and the first node N1 is disconnected, the first clock signal ck is the high level vgh, and the second clock signal xck is the low level vgl. In this way, the input signal Vin cannot be transmitted to the first node N1 through the signal input unit 11, and the potential of the first node N1 remains at the potential of the previous moment, i.e., the high level vgh. At the same time, the potential of the second node N2 also remains at the potential of the previous moment, i.e., the low level vgl, and the low level vgl of the second node N2 continues to control the conduction of the second output transistor T2, and transmits the second level signal Vgh (high level vgh) to the signal output terminal OUT.

[0047] In the t3 phase, the input signal Vin is the enable level (i.e., low level vgl) for controlling the conduction of the first output transistor T1, the isolation control signal sx of the isolation control terminal SX is low level vgl, the path between the third node N3 and the first node N1 is disconnected, the first clock signal ck is low level vgl, and the second clock signal xck is high level vgh. In this way, the signal input unit 11 controls the input signal Vin to be transmitted to the first node N1 under the control of the first clock signal ck of the first clock terminal CK and the potential of the third node N3, so that the potential of the first node N1 matches the input signal Vin, and controls The first output transistor T1 is turned on, and the first level signal Vgl (low level vgl) is transmitted to the signal output terminal OUT. Due to the parasitic capacitance of the first output transistor T1, when the output signal of the signal output terminal OUT jumps from the second level signal vgh to the first level signal vgl, the potential of the gate of the first output transistor T1 is pulled down through the coupling effect of the parasitic capacitance in the first output transistor T1, that is, the potential of the first node N1 is pulled down, so that the potential of the first node N1 is low enough to ensure that the first output transistor T1 is reliably turned on, and then the signal output terminal OUT accurately outputs the first level signal vgl. At this time, because the isolation module 30 disconnects the path between the third node N3 and the first node N1 under the control of the isolation control signal sx, the charge pump unit 12 can avoid the influence of the high level vgh of the second clock signal xck coupled to the third node N3 on the first node N1, so as to maintain the stability of the potential of the first node N1, thereby ensuring the accurate and stable output of the signal output terminal OUT, avoiding the tailing phenomenon, and thus improving the display quality of the display device.

[0048] In the embodiment of the present invention, an isolation module is set according to the isolation control signal of the isolation control end, at least in the starting stage when the input signal jumps to the enable level for controlling the conduction of the first output transistor, that is, the stage when the signal output end jumps from outputting the second level signal to the first level signal, to disconnect the path between the third node and the first node. In this way, the first level signal output by the signal output end can pull down the potential of the gate of the first output transistor, that is, the potential of the first node, through the coupling effect of the parasitic capacitance in the first output transistor, to ensure that the potential of the first node is low enough, so that the opening degree of the first output transistor is large enough, and the first level signal is completely output through the first output transistor; at the same time, because the isolation module disconnects the path between the third node and the first node, it can be avoided that the second clock signal of the second clock end is coupled through the charge pump unit to affect the potential stability of the first node, thereby avoiding affecting the accurate and stable output of the signal output end, avoiding the tailing problem, and improving the display quality. In addition, the isolation module turns on the path between the third node and the first node according to the isolation control signal of the isolation control end at least when the input signal is a non-enable level for controlling the shutdown of the first output transistor, so that the charge pump unit controls the amount of the signal coupled from the second clock end to the third node, and then can control the potential of the first node to always be maintained within the non-enable level range, thereby ensuring the potential stability of the first node, so that the signal output end outputs a stable signal, thereby improving the display quality.

[0049] It can be understood that the level of the enable level and the non-enable level is related to the structure of the module controlled by it. For example, when the module includes a transistor and the transistor is a P-channel transistor, the enable level is a low level and the non-enable level is a high level; and when the module includes a transistor and the transistor is an N-channel transistor, the enable level is a high level and the non-enable level is a low level. In the embodiment of the present invention, the level of the enable level and the non-enable level can be limited according to actual needs. For ease of description, unless otherwise specified, the embodiments of the present invention are all based on the example that the enable level in the signal input to the shift register circuit is a low level, the non-enable level is a high level, and the enable level in the output signal output from the signal output end of the shift register circuit to the pixel circuit in the display panel is a high level and the non-enable level is a low level.

[0050] Optional, Figure 3 A schematic diagram of the structure of another shift register circuit provided by an embodiment of the present invention is shown in FIG. Figure 3 As shown, the isolation module 30 includes an isolation transistor T3; a gate of the isolation transistor T3 is electrically connected to the isolation control terminal SX, a first electrode of the isolation transistor T3 is electrically connected to the third node N3, and a second electrode of the isolation transistor T3 is electrically connected to the first node N1.

[0051] Specifically, the isolation transistor T3 may be a P-channel transistor or an N-channel transistor. When the isolation transistor T3 is a P-channel transistor, the isolation control signal sx that controls the isolation module 30 to conduct the path between the third node N3 and the first node N1 is a low level vgl, and the isolation control signal sx that controls the isolation module 30 to disconnect the path between the third node N3 and the first node N1 is a high level vgh. When the isolation transistor T3 is an N-channel transistor, the isolation control signal sx that controls the isolation module 30 to conduct the path between the third node N3 and the first node N1 is a high level vgh, and the isolation control signal sx that controls the isolation module 30 to disconnect the path between the third node N3 and the first node N1 is a low level vgl.

[0052] In an optional embodiment, continue to refer to Figure 3 , the isolation transistor T3 is an N-channel transistor. For example, the material of the active layer of the isolation transistor T3 includes an oxide semiconductor, such as IGZO. It can be understood that the N-channel transistor has a larger switching ratio and off-state current than the P-channel transistor, which can reduce the leakage current of the transistor, making the potential of the first node N1 more stable. At the same time, the N-channel transistor has low power consumption, which is conducive to low power consumption of the shift register circuit.

[0053] For the convenience of description, unless otherwise specified, the drawings of the following embodiments are all illustrated by taking the isolation transistor T3 as an N-channel transistor as an example.

[0054] Optional, Figure 4 A structural diagram of another shift register circuit provided by an embodiment of the present invention is shown in FIG. Figure 4 As shown, the signal input unit 11 includes an input transistor T4 and a first voltage-stabilizing transistor T5; the gate of the input transistor T4 is electrically connected to the first clock terminal CK, the first electrode of the input transistor T4 is electrically connected to the signal input terminal IN, the second electrode of the input transistor T4 and the first electrode of the first voltage-stabilizing transistor T5 are electrically connected to the third node N3; the second electrode of the first voltage-stabilizing transistor T5 is electrically connected to the first node N1; the gate of the first voltage-stabilizing transistor T5 is electrically connected to the first level terminal VGL; the first level signal Vgl of the first level terminal VGL controls the first voltage-stabilizing transistor T5 to be in the on state.

[0055] Among them, the input transistor T4 can be a P-channel transistor or an N-channel transistor. When the input transistor T4 is a P-channel transistor, the enable level of the first clock signal ck is a low level vgl that can control the input transistor T4 to be in a conductive state, and the non-enable level of the first clock signal ck is a high level vgh that can control the input transistor T4 to be in a closed state; and when the input transistor T4 is an N-channel transistor, the enable level of the first clock signal ck is a high level vgh that can control the input transistor T4 to be in a conductive state, and the non-enable level of the first clock signal ck is a low level vgl that can control the input transistor T4 to be in a closed state. Figure 4 The schematic diagram of the shift register circuit structure in which the input transistor T4 is a P-channel transistor is shown only as an example, but is not limited thereto.

[0056] Specifically, the first clock signal ck of the first clock terminal CK can control the input transistor T4 to be turned on or off, so that when the input transistor T4 is in the on state, the input signal Vin of the signal input terminal IN is transmitted to the third node N3. At the same time, the first level signal Vgl can control the first voltage stabilizing transistor T5 to be turned on or off, and when the first voltage stabilizing transistor T5 is turned on, the input signal Vin continues to be transmitted to the first node N1 through the first voltage stabilizing transistor T5.

[0057] In addition, due to the existence of the threshold voltage of the first voltage-stabilizing transistor T5, the first voltage-stabilizing transistor T5 will be in the on state only when the difference between the first level signal Vgl and the potential at the third node N3 or the first node N1 to which the first voltage-stabilizing transistor T5 is electrically connected is less than the threshold voltage of the first voltage-stabilizing transistor T5. When this condition is not met, the first voltage-stabilizing transistor T5 will be in the off state. At this time, the first voltage-stabilizing transistor T5 can protect the device electrically connected to the other node when the potential of one of the third node N3 and the first node N1 is abnormal.

[0058] It is understandable that, in the case of no special instructions, the signal input unit 11 in the following embodiments is Figure 4 The structure in is illustrated.

[0059] In an alternative embodiment, Figure 5 A structural diagram of another shift register circuit provided by an embodiment of the present invention is shown in FIG. Figure 5 As shown, the channel type of the input transistor T4 is different from the channel type of the isolation transistor T3; wherein the signal input terminal IN is multiplexed as the isolation control terminal SX.

[0060] Specifically, when the input transistor T4 is a P-channel transistor, the isolation transistor T3 is an N-channel transistor. Conversely, when the input transistor T4 is an N-channel transistor, the isolation transistor T3 is a P-channel transistor. This can be set as needed, and the embodiment of the present invention does not specifically limit this.

[0061] Exemplarily, taking the input transistor T4 as a P-channel transistor and the isolation transistor T3 as an N-channel transistor as an example, since at the initial stage when the input signal Vin jumps to the enable level for controlling the first output transistor T1 to be turned on, that is, the input signal Vin is at a low level vgl, at this time, the isolation control signal sx controls the isolation module 30 to disconnect the path between the third node N3 and the first node N1, that is, the isolation control signal sx is at a low level vgl; and when the input signal Vin is at a non-enable level for controlling the first output transistor T1 to be turned off, that is, the input signal Vin is at a high level vgh, at this time, the isolation control signal sx controls the isolation module 30 to turn on the path between the third node N3 and the first node N1, that is, the isolation control signal sx is at a high level vgh. In this way, the signal input terminal IN can be set to be multiplexed as the isolation control terminal SX to reduce the number of signal lines, which is conducive to simplifying the line layout, thereby facilitating the narrow frame design of the display panel.

[0062] Optional, Figure 6 A structural diagram of another shift register circuit provided by an embodiment of the present invention is shown in FIG. Figure 6 As shown, the charge pump unit 12 includes a first capacitor C1; a first plate of the first capacitor C1 is electrically connected to the second clock terminal XCK, and a second plate of the first capacitor C1 is electrically connected to the third node N3. Thus, when the second clock signal xck of the second clock terminal XCK jumps from an enable level (i.e., a low level vgl) to a non-enable level (i.e., a high level vgh), under the coupling effect of the first capacitor C1, the potential of the third node N3 is raised to a potential equivalent to the jump amount of the second clock signal xck; conversely, when the second clock signal xck of the second clock terminal XCK jumps from a non-enable level (i.e., a high level vgh) to an enable level (i.e., a low level vgl), under the coupling effect of the first capacitor C1, the potential of the third node N3 can be pulled down to a potential equivalent to the jump amount of the second clock signal xck.

[0063] Optional, Figure 7 A structural diagram of another shift register circuit provided by an embodiment of the present invention is shown in FIG. Figure 7As shown, the second control module 20 includes a second node 21 control unit and a fourth node control unit 22; the fourth node control unit 22 is electrically connected to the signal input unit 11, the first clock terminal CK, the first level terminal VGL and the fourth node N4 respectively; the fourth node control unit 22 is used to control the potential of the fourth node N4 under the control of the signal input unit 11, the first clock signal ck and the first level signal Vgl; the second node control unit 21 is electrically connected to the second clock terminal XCK, the fourth node N4 and the second node N2 respectively; the second node control unit 21 is used to control the potential of the second node N2 according to the potential of the fourth node N4 and the second clock signal xck.

[0064] Specifically, the fourth node control unit 22 can control the potential of the fourth node N4 under the control of the signal input unit 11, the first clock signal ck and the first level signal Vgl, and at the same time, the second control unit 21 controls the potential of the second node N2 under the control of the potential of the fourth node N4 and the second clock signal xck. Since when the potential of the first node N1 is the enable level, the potential of the second node N2 needs to be the non-enable level, that is, when the first node N1 is the enable level, the second node control unit 21 should not be able to transmit the enable level to the second node N2, so the second clock signal xck should be the non-enable level that controls the second node control unit 21 to be unable to transmit the enable level to the second node N2.

[0065] Optional, Figure 8 A structural diagram of another shift register circuit provided by an embodiment of the present invention is shown in FIG. Figure 8 As shown, the fourth node control unit 22 includes a first control transistor T6 and a second control transistor T7; the gate of the first control transistor T6 is electrically connected to the signal input unit 11, the first electrode of the first control transistor T6 is electrically connected to the first clock terminal CK, and the second electrode of the first control transistor T6 is electrically connected to the fourth node N4; the gate of the second control transistor T7 is electrically connected to the first clock terminal CK, the first electrode of the second control transistor T7 is electrically connected to the first level terminal VGL, and the second electrode of the second control transistor T7 is electrically connected to the fourth node N4.

[0066] Specifically, the first control transistor T6 can be turned on or off under the control of the signal input unit 11, and transmit the first clock signal ck to the fourth node N4 in the on state, or the second control transistor T7 can be turned on or off under the control of the first clock signal ck, and transmit the first level signal Vgl to the fourth node N4 in the on state.

[0067] Optional, continue to refer to Figure 8, the first electrode of the first control transistor T6 is electrically connected to the third node N3 with the signal input unit 11. In this way, when the first control transistor T6 is a P-channel transistor, when the potential of the third node N3 is a low level vgl, the first control transistor T6 can be controlled to be turned on, and when the potential of the third node N3 is a high level vgh, the first control transistor T6 can be controlled to be turned off. Conversely, when the first control transistor T6 is an N-channel transistor, when the potential of the third node N3 is a low level vgl, the first control transistor T6 can be controlled to be turned off, and when the potential of the third node N3 is a high level vgh, the first control transistor T6 can be controlled to be turned on, and the embodiment of the present invention does not specifically limit this. Figure 8 The schematic diagram exemplarily shows a structure in which the first control transistor T6 and the second control transistor T7 are both P-channel transistors.

[0068] In an alternative embodiment, Fig. 9 A structural diagram of another shift register circuit provided by an embodiment of the present invention is shown in FIG. Fig. 9 As shown, the second node control unit 21 may include a third control transistor T15, a fourth control transistor T16 and a third capacitor C3; the gate of the third control transistor T15 is electrically connected to the second clock terminal XCK, the second electrode of the third control transistor T15 is electrically connected to the second node N2, the gate of the fourth control transistor T16 and the first plate of the third capacitor C3 are both electrically connected to the fourth node N4, the first electrode of the fourth control transistor T16 is electrically connected to the second clock terminal XCK, the first electrode of the third control transistor T15, the second electrode of the fourth control transistor T16 and the second plate of the third capacitor C3 are electrically connected to the fifth node N5. In this way, the fourth control transistor T16 can be turned on or off under the control of the potential of the fourth node N4, and transmits the second clock signal xck to the fifth node N5 in the on state. Due to the effect of the third capacitor C3, the potential of the second node N2 can be more stably maintained at the enable level. Meanwhile, the third control transistor T15 can be turned on or off under the control of the potential of the fifth node N5, and transmits the potential of the fifth node N5 to the second node N2 in the turned-on state, so that the potential of the second node N2 is an enable level.

[0069] Understandably, Fig. 9 The schematic diagram of the structure of the shift register circuit is only exemplarily shown, but not limited to this. Those skilled in the art can design it according to their needs, and the present invention does not make specific limitations on this. For the convenience of description in the following embodiments, the second node control unit 21 is Fig. 9 The structure shown is used as an example for explanation.

[0070] Optional, Fig.10 A structural diagram of another shift register circuit provided by an embodiment of the present invention is shown in FIG. Fig.10As shown, the fourth node control unit 22 further includes a second capacitor C2; a first plate of the second capacitor C2 is electrically connected to the second level end VGH, and a second plate of the second capacitor C2 is electrically connected to the gate of the first control transistor T6. Thus, when the potential of the third node N3 is an enable level for controlling the first control transistor T6 to be turned on, the potential of the third node N3 can be made more stable due to the storage function of the second capacitor C2.

[0071] In another alternative embodiment, Fig.11 A structural diagram of another shift register circuit provided by an embodiment of the present invention is shown in FIG. Fig.11 As shown, the signal input unit 11 includes a first input transistor T9, a second input transistor T10 and a first voltage-stabilizing transistor T5; the gate of the first input transistor T9 and the gate of the second input transistor T10 are both electrically connected to the first clock terminal CK; the first electrode of the first input transistor T9 and the first electrode of the second input transistor T10 are both electrically connected to the signal input terminal IN; the second electrode of the first input transistor T9 and the first electrode of the first voltage-stabilizing transistor T5 are electrically connected to the third node N3, and the second electrode of the second input transistor T10 is electrically connected to the first electrode of the first control transistor T6; the gate of the first voltage-stabilizing transistor T5 is electrically connected to the first level terminal VGL, and the first electrode of the first voltage-stabilizing transistor T5 is electrically connected to the first node N1; the first level signal Vgl of the first level terminal VGL controls the first voltage-stabilizing transistor T5 to be in a conducting state.

[0072] The first input transistor T9 and the second input transistor T10 may be P-channel transistors or N-channel transistors, which are not specifically limited in the embodiment of the present invention. Fig.11 The schematic diagram exemplarily shows a structure in which the first input transistor T9 and the second input transistor T10 are both P-channel transistors.

[0073] Specifically, the first clock signal ck of the first clock terminal CK can simultaneously control the first input transistor T9 and the second input transistor T10 to be turned on or off, so that when the first input transistor T9 and the second input transistor T10 are in the on state, the input signal Vin of the signal input terminal IN is transmitted to the third node N3, and the input signal Vin is transmitted to the gate of the first control transistor T6, so that the first control transistor T6 is turned on or off under the control of the input signal Vin.

[0074] Based on any of the above embodiments, optionally, Fig.12 A structural diagram of another shift register circuit provided by an embodiment of the present invention is shown in FIG. Fig.12As shown, it also includes: an interlocking module 50; the interlocking module 50 is electrically connected to the third node N3, the fourth node N4, the second clock terminal XCK, the second level terminal VGH and the second node N2 respectively; the interlocking module 50 is used to control the potential of the second node N2 under the control of the potential of the third node N3 and the second level signal Vgh, and to control the potential of the third node N3 under the control of the potential of the fourth node N4, the second clock signal xck and the second level signal Vgh.

[0075] Specifically, when the signal output terminal OUT needs to output the first level signal Vgl, the potential of the first node N1 should be an enable level that can control the first output transistor T1 to be turned on and transmit the first level signal Vgl to the signal output terminal OUT. At this time, in order to ensure the accuracy of the first level signal Vgl output by the signal output terminal OUT, the potential of the second node N2 should be a non-enable level that controls the second output transistor T2 to be turned off, and cannot transmit the second level signal Vgh to the signal output terminal OUT; and when the signal output terminal OUT needs to output the second level signal Vgh, the potential of the second node N2 should be an enable level that can control the second output transistor T2 to be turned on and transmit the second level signal Vgh to the signal output terminal OUT. At this time, in order to ensure the accuracy of the second level signal Vgh output by the signal output terminal OUT, the potential of the first node N2 should be a non-enable level that controls the first output transistor T1 to be turned off, and cannot transmit the first level signal Vgl to the signal output terminal OUT.

[0076] In this way, when the signal output terminal OUT needs to output the first level signal Vgl, the interlock module 50 transmits the second level signal Vgh to the second node N2 under the control of the potential of the third node N3, so that the potential of the second node N2 remains at a non-enable level; and, when the signal output terminal OUT needs to output the second level signal Vgh, the interlock module 50 transmits the second level signal Vgh to the third node N3 under the control of the potential of the fourth node N4 and the second clock signal xck, and when the first voltage-stabilizing transistor T5 is turned on, continues to transmit the second level signal Vgh to the first node N1, so that the potential of the first node N1 remains at a non-enable level, so that the potential of the second node N2 and the potential of the first node N1 are mutually clamped, thereby ensuring that the shift register circuit works in an orderly manner and improving the accuracy and stability of the output signal of the shift register circuit.

[0077] In an alternative embodiment, Fig.13 A structural diagram of another shift register circuit provided by an embodiment of the present invention is shown in FIG. Fig.13As shown, the interlocking module 50 includes a first interlocking transistor T11, a second interlocking transistor T12 and a third interlocking transistor T13; the gate of the first interlocking transistor T11 is electrically connected to the third node N3, the first electrode of the first interlocking transistor T11 is electrically connected to the second level terminal VGH, and the second electrode of the first interlocking transistor T11 is electrically connected to the second node N2; the gate of the second interlocking transistor T12 is electrically connected to the fourth node N4, the first electrode of the second interlocking transistor T12 is electrically connected to the second level terminal VGH, and the second electrode of the second interlocking transistor T12 is electrically connected to the first electrode of the third interlocking transistor T13; the gate of the third interlocking transistor T13 is electrically connected to the second clock terminal XCK, and the second electrode of the third interlocking transistor T13 is electrically connected to the third node N3.

[0078] Specifically, the first interlock transistor T11 can be turned on or off under the control of the potential of the third node N3, and transmits the second level signal Vgh to the second node N2 when it is turned on; the second interlock transistor T12 can be turned on or off under the control of the potential of the fourth node N4, and the third interlock transistor T13 can be turned on or off under the control of the second clock signal xck, and when the second interlock transistor T12 and the third interlock transistor T13 are both turned on, the second level signal Vgh is transmitted to the third node N3, and when the first voltage-stabilizing transistor T5 is turned on, the second level signal Vgh is further transmitted to the first node N1, so as to realize mutual clamping of the second node N2 and the first node N1, so that the first output transistor T1 controlled by the potential of the first node N1 and the second output transistor T2 controlled by the second node N2 will not be turned on at the same time, so that no path is formed between the second level terminal VGH and the first level terminal VGL, so as to prevent the second level terminal VGH and the first level terminal VGL from being short-circuited, thereby preventing the display panel from flickering when displaying light. The first interlocking transistor T8 , the second interlocking transistor T9 and the third interlocking transistor T10 may be N-channel transistors or P-channel transistors, and may be designed as required, which is not specifically limited in the embodiment of the present invention.

[0079] Optional, Fig.14 A structural diagram of another shift register circuit provided by an embodiment of the present invention is shown in FIG. Fig.14 As shown, the shift register circuit also includes a second voltage-stabilizing transistor T14; the third node N3 includes a first subnode N31 and a second subnode N32; the gate of the second voltage-stabilizing transistor T14 is electrically connected to the first level end VGL, the first electrode of the second voltage-stabilizing transistor T14 is electrically connected to the first subnode N31, and the second electrode of the second voltage-stabilizing transistor T14 is electrically connected to the second subnode N32; wherein, the charge pump unit 12 is electrically connected to the second subnode N32 of the third node N3; the gates of the signal input unit 11 and the first control transistor T6 are both electrically connected to the first subnode N31 of the third node N3.

[0080] Exemplarily, taking the second voltage-stabilizing transistor T14 as a P-channel transistor as an example, the first level signal Vgl controls the second voltage-stabilizing transistor T7 to be in the on state, so that the potential of the original third node N3 can be distributed to the first sub-node N31 and the second sub-node N32, avoiding the joint action of the second control module 20, the signal input unit 11 and the charge pump unit 12, causing the third node N3 to change and affecting the operation of the shift register circuit. In this way, by setting the second voltage-stabilizing transistor T14, when the potential of one of the first sub-node N31 and the second sub-node N32 is abnormal, it can protect the device electrically connected to the other node.

[0081] Based on the same inventive concept, an embodiment of the present invention further provides a display panel, which display panel 100 includes a display area AA and a non-display area NA surrounding the display area; the non-display area NA includes the shift register circuit 101 provided by any of the above embodiments. Therefore, the display panel provided by the embodiment of the present invention includes the technical features of the shift register circuit provided by the embodiment of the present invention, and can achieve the beneficial effects of the shift register circuit provided by the embodiment of the present invention. The similarities can be referred to the above description of the shift register circuit provided by the embodiment of the present invention, and will not be repeated here.

[0082] For example, Fig.15 A schematic diagram of the structure of a display panel provided by an embodiment of the present invention is shown in FIG. Fig.15 As shown, the display panel 100 includes a plurality of pixel circuits P arranged in an array and a plurality of cascaded shift register circuits 101 provided by any one of the above-mentioned embodiments; the signal output terminal OUT of each stage of the shift register circuit 101 is electrically connected to at least part of the pixel circuits P located in the same row; except for the last stage of the shift register circuit 101, the signal output terminal OUT of each stage of the shift register circuit 101 is electrically connected to the signal input terminal IN of the next stage of the shift register circuit 101, and the signal input terminal IN of the first stage of the shift register circuit 101 receives a start pulse signal.

[0083] It can be understood that when the pixel circuit P is a typical 7T1C pixel circuit, the signal output by the shift register circuit can be a light-emitting control signal for controlling the light-emitting control transistor in the pixel circuit P to be turned on or off, and / or, the signal output by the shift register circuit can also be a scanning signal for controlling the N-channel transistor (for example, an initialization transistor and / or a threshold compensation transistor) in the pixel circuit P to be turned on or off. The embodiment of the present invention does not specifically limit this.

[0084] Among them, taking the case where the signal output by the shift register circuit can be a light-emitting control signal for controlling the light-emitting control transistor in the pixel circuit P to be turned on or off as an example, the signal input terminal IN of the first shift register circuit 101 is electrically connected to the light-emitting control start signal line STV that transmits the start pulse signal Vstv, and the signal input terminal IN of each shift register circuit 101 from the second-stage shift register circuit 101 to the n-stage shift register circuit is electrically connected to the signal output terminal OUT of the previous-stage shift register circuit, so that the start pulse signal Vstv transmitted by the light-emitting control start signal line STV controls the start time and end time of the enable level of the light-emitting control signal output by the first shift register circuit 101, and in other stages of the shift register circuit, the light-emitting control signal output by the signal output terminal OUT of the previous-stage shift register circuit controls the start time and end time of the light-emitting control signal outputted therefrom, so that each stage of the shift register circuit starts to output the enable level of the light-emitting control signal in sequence, and stops outputting the enable level of the light-emitting control signal in sequence.

[0085] In addition, each level of the shift register circuit 101 is also electrically connected to the clock signal line CK for transmitting the first clock signal ck and the clock signal line XCK for transmitting the second clock signal xck, the first level line Lg for transmitting the first level signal Vgl, the second level line H for transmitting the second level signal Vgh, and the isolation control line SX for transmitting the isolation control signal sx.

[0086] The embodiment of the present invention, by setting up cascaded shift register circuits, can control the start time and end time of the enable level of the light-emitting control signal output by each shift register circuit, so as to realize row-by-row control of each pixel circuit; and when each shift register circuit can stably and accurately output the light-emitting control signal, each pixel circuit can control the light-emitting element electrically connected thereto to emit light stably, thereby improving the display quality.

[0087] Based on the same inventive concept, an embodiment of the present invention further provides a display device, Fig.16 A schematic diagram of a display device according to an embodiment of the present invention is shown in FIG. Fig.16 As shown, the display device 1 includes the display panel 100 provided by any embodiment of the present invention. Therefore, the display device 1 provided by the embodiment of the present invention includes the technical features of the display panel 100 provided by the embodiment of the present invention, and can achieve the beneficial effects of the display panel 100 provided by the embodiment of the present invention. The same points can be referred to the above description of the display panel 100 provided by the embodiment of the present invention, which will not be repeated here. The display device 1 provided by the embodiment of the present invention can be Fig.16The mobile phone shown can also be any electronic product with a display function, including but not limited to the following categories: televisions, laptops, desktop displays, tablet computers, digital cameras, smart bracelets, smart glasses, car displays, medical equipment, industrial control equipment, touch interactive terminals, etc. The embodiments of the present invention do not specifically limit this.

[0088] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A shift register circuit, It is characterized in that include: A first control module, a second control module, an isolation module and an output module; The output module includes a first output transistor and a second output transistor; The gate of the first output transistor is electrically connected to the first node, the first electrode of the first output transistor is electrically connected to the first level end, and the second electrode of the first output transistor is electrically connected to the signal output end; the gate of the second output transistor is electrically connected to the second node, the second electrode of the second output transistor is electrically connected to the second level end, and the second electrode of the second output transistor is electrically connected to the signal output end; The first control module includes a signal input unit and a charge pump unit; the signal input unit is electrically connected to the first clock terminal, the signal input terminal, the first node and the third node respectively; the charge pump unit is electrically connected to the second clock terminal and the third node respectively; the charge pump unit is used to control the amount of the signal coupled from the second clock terminal to the third node; the signal input unit is used to control the potential of the first node according to the first clock signal of the first clock terminal, the input signal of the signal input terminal and the potential of the third node; The isolation module is electrically connected to the third node, the first node and the isolation control terminal respectively; The isolation module is used to disconnect the path between the third node and the first node according to the isolation control signal of the isolation control terminal, at least in the initial stage when the input signal jumps to the enable level for controlling the first output transistor to be turned on, and to connect the path between the third node and the first node at least when the input signal is at the non-enable level for controlling the first output transistor to be turned off; The second control module is electrically connected to the signal input unit, the first clock end, the second clock end, the second node, the first level end and the second level end, respectively, and is used to control the potential of the second node under the control of the signal input unit, the first clock signal, the second clock signal of the second clock end, the first level signal of the first level end and the second level signal of the second level end.

2. The shift register circuit according to claim 1, It is characterized in that The isolation module includes an isolation transistor; The gate of the isolation transistor is electrically connected to the isolation control terminal, the first electrode of the isolation transistor is electrically connected to the third node, and the second electrode of the isolation transistor is electrically connected to the first node.

3. The shift register circuit according to claim 2, It is characterized in that The isolation transistor is an N-channel transistor.

4. The shift register circuit according to claim 2, It is characterized in that The signal input unit includes an input transistor and a first voltage stabilizing transistor; The gate of the input transistor is electrically connected to the first clock terminal, the first electrode of the input transistor is electrically connected to the signal input terminal, and the second electrode of the input transistor and the first electrode of the first voltage regulator transistor are electrically connected to the third node; The second electrode of the first voltage stabilizing transistor is electrically connected to the first node; the gate of the first voltage stabilizing transistor is electrically connected to the first level end; and the first level signal of the first level end controls the first voltage stabilizing transistor to be in a conducting state.

5. The shift register circuit according to claim 4, It is characterized in that The channel type of the input transistor is different from the channel type of the isolation transistor; Wherein, the signal input terminal is multiplexed as the isolation control terminal.

6. The shift register circuit according to claim 1, It is characterized in that The charge pump unit includes a first capacitor; a first plate of the first capacitor is electrically connected to the second clock terminal, and a second plate of the first capacitor is electrically connected to the third node.

7. The shift register circuit according to claim 1, It is characterized in that The second control module includes a second node control unit and a fourth node control unit; The fourth node control unit is electrically connected to the signal input unit, the first clock end, the first level end and the fourth node respectively; the fourth node control unit is used to control the potential of the fourth node under the control of the signal input unit, the first clock signal and the first level signal; The second node control unit is electrically connected to the second clock terminal, the fourth node and the second node respectively; The second node control unit is used to control the potential of the second node according to the potential of the fourth node and the second clock signal.

8. The shift register circuit according to claim 7, It is characterized in that The fourth node control unit includes a first control transistor and a second control transistor; The gate of the first control transistor is electrically connected to the signal input unit, the first electrode of the first control transistor is electrically connected to the first clock terminal, and the second electrode of the first control transistor is electrically connected to the fourth node; A gate of the second control transistor is electrically connected to the first clock end, a first electrode of the second control transistor is electrically connected to the first level end, and a second electrode of the second control transistor is electrically connected to the fourth node.

9. The shift register circuit according to claim 8, It is characterized in that The first electrode of the first control transistor and the signal input unit are electrically connected to the third node.

10. The shift register circuit according to claim 8, It is characterized in that The fourth node control unit also includes a second capacitor; The first plate of the second capacitor is electrically connected to the second level end, and the second plate of the second capacitor is electrically connected to the gate of the first control transistor.

11. The shift register circuit according to claim 8, It is characterized in that The signal input unit includes a first input transistor, a second input transistor and a first voltage stabilizing transistor; The gate of the first input transistor and the gate of the second input transistor are both electrically connected to the first clock terminal; the first electrode of the first input transistor and the first electrode of the second input transistor are both electrically connected to the signal input terminal; the second electrode of the first input transistor and the first electrode of the first voltage stabilizing transistor are electrically connected to the third node, and the second electrode of the second input transistor is electrically connected to the first electrode of the first control transistor; The gate of the first voltage stabilizing transistor is electrically connected to the first level end, and the first electrode of the first voltage stabilizing transistor is electrically connected to the first node; the first level signal of the first level end controls the first voltage stabilizing transistor to be in a conducting state.

12. The shift register circuit according to claim 7, It is characterized in that Also includes: Interlock module; The interlocking module is electrically connected to the third node, the fourth node, the second clock terminal, the second level terminal and the second node respectively; The interlocking module is used to control the potential of the second node under the control of the potential of the third node and the second level signal, and to control the potential of the third node under the control of the potential of the fourth node, the second clock signal and the second level signal.

13. The shift register circuit according to claim 12, It is characterized in that The interlock module includes a first interlock transistor, a second interlock transistor and a third interlock transistor; The gate of the first interlock transistor is electrically connected to the third node, the first electrode of the first interlock transistor is electrically connected to the second level end, and the second electrode of the first interlock transistor is electrically connected to the second node; The gate of the second interlock transistor is electrically connected to the fourth node, the first electrode of the second interlock transistor is electrically connected to the second level end, and the second electrode of the second interlock transistor is electrically connected to the first electrode of the third interlock transistor; A gate of the third interlock transistor is electrically connected to the second clock terminal, and a second electrode of the third interlock transistor is electrically connected to the third node.

14. The shift register circuit according to claim 12, It is characterized in that Also includes: a second voltage stabilizing transistor; The third node includes a first subnode and a second subnode; the gate of the second voltage-stabilizing transistor is electrically connected to the first level end, the first electrode of the second voltage-stabilizing transistor is electrically connected to the first subnode, and the second electrode of the second voltage-stabilizing transistor is electrically connected to the second subnode; The charge pump unit is electrically connected to the second sub-node of the third node; the signal input unit and the fourth node control unit are both electrically connected to the first sub-node of the third node.

15. A display panel, It is characterized in that include: A plurality of pixel circuits arranged in an array and a plurality of cascaded shift register circuits as claimed in any one of claims 1 to 14; The signal output end of the shift register circuit at each level is electrically connected to at least part of the pixel circuits located in the same row; except for the shift register circuit at the last level, the signal output end of the shift register circuit at each remaining level is electrically connected to the signal input end of the shift register circuit at the next level, and the signal input end of the shift register circuit at the first level receives a start pulse signal.

16. A display device, It is characterized in that include: The display panel as claimed in claim 15.

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