Method for improving thickness uniformity of hard mask layer after polishing of word line polysilicon layer

Abstract

The present application provides a method for improving the thickness uniformity of a hard mask layer after polishing a wordline polysilicon layer, comprising: providing a substrate, the substrate being divided into a core region and a peripheral region, with multiple flash memory gate structures formed on the core region; depositing a hard mask layer to cover the core region and the peripheral region; etching the hard mask layer to form multiple strip-shaped trenches in the hard mask layer in the core region; depositing a wordline polysilicon layer to cover the hard mask layer and fill the multiple strip-shaped trenches; polishing the wordline polysilicon layer and the hard mask layer until the thickness of the hard mask layer exceeds a predetermined thickness by a reserved portion; and performing an immersion process to remove the reserved portion of the hard mask layer. By first polishing the hard mask layer to a thickness exceeding a predetermined thickness by a reserved portion and then performing an immersion process to remove the reserved portion, the thickness uniformity of the hard mask layer after polishing the wordline polysilicon layer is improved, and the residue of the hard mask layer during subsequent etching of the hard mask layer is reduced.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a method for improving the thickness uniformity of a hard mask layer after grinding a word line polysilicon layer. Background Art

[0002] Flash memory, also known as flash memory, has become the mainstream non-volatile memory. Based on its structure, flash memory can be divided into NOR flash and NAND flash. Flash memory's key feature is its ability to retain stored information for long periods of time without power. Its advantages include high integration, fast access speeds, and ease of erasure and rewriting. Consequently, it has found widespread application in a variety of fields, including microcomputers and automated control.

[0003] Existing flash memories consist of a core memory circuit (cell circuit) located on a substrate and peripheral circuits surrounding the core memory circuit. The core memory circuit includes transistors with relatively small feature sizes, while the peripheral circuit primarily comprises conventional MOS transistors with larger feature sizes for high-voltage, medium-voltage, and low-voltage circuits. If embedded, they also include corresponding low-voltage logic circuits. The distance between the gates of adjacent transistors in the core memory circuit is very small, while the distance between the gates of two transistors in the peripheral circuit is relatively large.

[0004] Polysilicon planarization technology (Poly CMP) is widely used in the manufacturing process of embedded flash memory, such as planarization of floating gates and word lines.

[0005] In the prior art, devices in the flash memory cell array area are first fabricated, including multiple spaced-apart flash memory gate structures. Devices in the peripheral circuit area, such as logic gates in the logic area and word lines in the flash memory cell array area, are then separately fabricated. When fabricating the word lines in the flash memory cell array area, a hard mask layer is first formed on the substrate, covering the flash memory cell array area and the peripheral circuit area. Etching is then performed to form multiple strip-shaped trenches in the hard mask layer over the flash memory cell array area. A polysilicon layer is then deposited on the substrate to fill the trenches. The polysilicon layer in the peripheral circuit area is then removed by grinding, along with the exposed portion of the hard mask layer, to a thickness sufficient for subsequent etching.

[0006] Since the spacing between the multiple spaced flash memory gate structures in the flash memory cell array area is small and there is a height difference between this area and the peripheral circuit area, the different polishing rates in different areas result in poor uniformity in the thickness of the hard mask layer after polishing the word line polysilicon layer. This makes it easy to form hard mask layer residues during subsequent etching of the hard mask layer. This situation is very likely to occur in the shallow trench isolation structure between the flash memory cell array area and the peripheral circuit area. Summary of the Invention

[0007] In view of the above-mentioned shortcomings of the prior art, the object of the present application is to provide a method for improving the thickness uniformity of the hard mask layer after polishing the word line polysilicon layer, comprising:

[0008] A substrate is provided, wherein the substrate is divided into a core area and a peripheral area, and a plurality of flash memory gate structures are formed on the core area;

[0009] depositing a hard mask layer to cover the core region and the peripheral region;

[0010] Etching the hard mask layer to form a plurality of strip-shaped trenches in the hard mask layer in the core region;

[0011] depositing a wordline polysilicon layer to cover the hard mask layer and fill the plurality of strip-shaped trenches;

[0012] Polishing the word line polysilicon layer and the hard mask layer until the thickness of the hard mask layer exceeds the predetermined thickness by a reserved portion;

[0013] A soaking process is performed to remove the reserved portion of the hard mask layer.

[0014] Preferably, the process parameters of the immersion process are: immersion in 100:1 hydrofluoric acid for 40s-1000s.

[0015] Preferably, the process parameters of the immersion process are: immersion in 200:1 hydrofluoric acid for 100s-2300s.

[0016] Preferably, the predetermined portion is 100 angstroms to 2000 angstroms.

[0017] Preferably, the deposition is chemical vapor deposition.

[0018] Preferably, the grinding is chemical mechanical grinding.

[0019] Preferably, the flash memory gate structure includes: a floating gate located on the gate oxide layer in the core area, an ONO layer located on the floating gate, a control gate located on the ONO layer, an oxide layer located on the control gate, and sidewalls covering the sidewalls of the floating gate, ONO layer, control gate and oxide layer.

[0020] Preferably, the ONO layer consists of a silicon oxide-silicon nitride-silicon oxide layer.

[0021] As described above, the method provided in the present application for improving the thickness uniformity of the hard mask layer after grinding the word line polysilicon layer has the following beneficial effects: by first grinding the hard mask layer to a reserved portion that is thicker than a predetermined thickness and then performing an immersion process to remove the reserved portion, the thickness uniformity of the hard mask layer after grinding the word line polysilicon layer is improved, and the residue of the hard mask layer during subsequent etching of the hard mask layer is reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the following will briefly introduce the drawings required for use in the specific implementation methods or the description of the prior art. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0023] Figure 1 A flow chart showing a method for improving the thickness uniformity of a hard mask layer after polishing a word line polysilicon layer provided by an embodiment of the present application is shown. DETAILED DESCRIPTION

[0024] The following describes the embodiments of the present application through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present application from the disclosure herein. The present application may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0025] The following is a clear and complete description of the technical solutions in this application in conjunction with the accompanying drawings. Obviously, the embodiments described are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of this application.

[0026] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating positions or location relationships, are used solely to facilitate the description of this application and simplify the description. They are not intended to indicate or imply that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0027] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to internal connections between two components; they can refer to wireless connections or wired connections. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0028] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0029] See also Figure 1 , which shows a flow chart of a method for improving the thickness uniformity of a hard mask layer after polishing a word line polysilicon layer, provided in an embodiment of the present application.

[0030] In step S1 , a substrate is provided. The substrate is divided into a core region and a peripheral region. A plurality of flash memory gate structures are formed on the core region.

[0031] Optionally, the substrate may be a silicon substrate, a germanium substrate, or a silicon-on-insulator substrate; or the substrate material may include other materials, such as a III-V compound such as gallium arsenide. Those skilled in the art may select a substrate material based on the type of transistor to be formed on the substrate, and thus the type of substrate should not limit the scope of protection of the present invention.

[0032] The core area is used to form stacked gate transistors of the core storage circuit, that is, the flash memory gate structure; the peripheral area is used to form MOS transistors of the peripheral circuit. For embedded flash memory, it includes a logic area for forming logic devices.

[0033] A plurality of isolation components are formed in the substrate, wherein the line width of the isolation components in the core region is smaller than the line width of the isolation components in the peripheral region. Typically, the top of the isolation components is higher than the surface of the substrate.

[0034] In this embodiment, the present application forms the isolation component through a shallow trench isolation (STI) process, and the shallow trench isolation process includes but is not limited to shallow trench etching, oxide filling, and oxide planarization.

[0035] Shallow trench etching includes, but is not limited to, isolation oxide layer, nitride deposition, shallow trench isolation using a mask, and STI shallow trench etching. STI oxide filling includes, but is not limited to, trench liner silicon oxide, trench CVD (chemical vapor deposition) oxide filling, or PVD (physical vapor deposition) oxide filling. Planarization of the silicon wafer surface can be achieved through a variety of methods. Planarization of the silicon wafer can be achieved by filling the gaps with SOG (spin-on-glass). SOG can be composed of 80% solvent and 20% silicon dioxide. After deposition, the SOG is baked to evaporate the solvent, leaving the silicon dioxide in the gaps. The entire surface can also be reverse-etched to reduce the thickness of the entire silicon wafer. Planarization can also be effectively performed using a CMP process (also known as a chemical mechanical polishing process), including, but not limited to, polishing the trench oxide (chemical mechanical polishing can be used) and removing the nitride.

[0036] The isolation features can be composed of any insulating material, such as silicon dioxide (SiO2), or a "high-k" dielectric having a high dielectric constant, for example, greater than 3.9. In some cases, the isolation features can be composed of an oxide material. Examples of suitable materials for the isolation features include silicon dioxide (SiO2), hafnium oxide (HfO2), alumina (Al2O3), yttrium oxide (Y2O3), tantalum oxide (Ta2O5), titanium dioxide (TiO2), praseodymium oxide (Pr2O3), zirconium oxide (ZrO2), erbium oxide (ErOx), and other materials now known or later developed with similar properties.

[0037] The flash memory gate structure formed on the core area includes: a floating gate located on the gate oxide layer of the core area, an ONO layer located on the floating gate, the ONO layer consisting of a silicon oxide-silicon nitride-silicon oxide layer; a control gate located on the ONO layer, an oxide layer located on the control gate, and sidewalls covering the sidewalls of the floating gate, the ONO layer, the control gate, and the oxide layer.

[0038] In step S2 , a hard mask layer is deposited to cover the core region and the peripheral region.

[0039] Optionally, the deposition is chemical vapor deposition. Since multiple flash memory gate structures are formed on the core region and the spacing between the flash memory gate structures is small, the deposited hard mask layer is relatively thick to completely fill the trenches between the flash memory gate structures.

[0040] In step S3 , the hard mask layer is etched to form a plurality of strip-shaped trenches in the hard mask layer in the core region.

[0041] A photoresist layer having a plurality of stripe-shaped groove patterns is formed on the hard mask layer through a photolithography process. The hard mask layer is etched using the photoresist layer as a mask to form a plurality of stripe-shaped grooves in the hard mask layer in the core region. The photoresist layer is then removed. For example, the etching is dry etching, and the photoresist layer is removed by an ashing process.

[0042] In step S4 , a wordline polysilicon layer is deposited to cover the hard mask layer and fill the plurality of strip-shaped trenches.

[0043] As an example, the deposition is chemical vapor deposition.

[0044] In step S5 , the wordline polysilicon layer and the hard mask layer are polished until the thickness of the hard mask layer exceeds a predetermined thickness by a reserved portion.

[0045] Optionally, the polishing is chemical mechanical polishing. After the polishing is terminated, no wordline polysilicon layer exists on the peripheral area, and the wordline polysilicon layer in the plurality of strip-shaped trenches in the core area constitutes the wordline polysilicon of the core storage circuit.

[0046] The predetermined thickness refers to the thickness of the hard mask layer that meets the requirements of subsequent etching. For those skilled in the art, the specific value of the predetermined thickness can be determined according to the requirements of subsequent manufacturing processes.

[0047] For those skilled in the art, the specific value of the reserved portion can be determined according to the specific value of the predetermined thickness and the thickness uniformity of the hard mask layer required for subsequent etching. As an example, it can be 100 angstroms to 2000 angstroms.

[0048] In step S6 , a soaking process is performed to remove the reserved portion of the hard mask layer.

[0049] As an example, the process parameters of the DIP process are: 100:1 hydrofluoric acid soaking for 40 seconds to 1000 seconds, or 200:1 hydrofluoric acid soaking for 100 seconds to 2300 seconds.

[0050] For those skilled in the art, appropriate hydrofluoric acid concentration and immersion time can be selected according to the specific value of the reserved portion.

[0051] The specific numerical value of the reserved portion and the specific process parameters of the immersion process adopted are within the scope of protection of the claims of this application.

[0052] It should be noted that the illustrations provided in this embodiment are only used to schematically illustrate the basic concept of the present application. Therefore, the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated.

[0053] Since the spacing between the multiple spaced flash memory gate structures in the core area is small and there is a certain height difference between this area and the peripheral area, the different grinding rates in different areas result in poor uniformity of the thickness of the hard mask layer after grinding the word line polysilicon layer. Through step S5, the hard mask layer removed by grinding is reduced, which can reduce the thickness difference of the hard mask layer in different areas of the substrate; through step S6, since the immersion process has the isotropic characteristic, when the reserved part of the hard mask layer is removed, the thickness difference of the hard mask layer in different areas of the substrate will not be increased.

[0054] In summary, the method provided herein for improving the thickness uniformity of the hard mask layer after polishing the wordline polysilicon layer has the following beneficial effects: by first polishing the hard mask layer to a reserved portion exceeding a predetermined thickness and then performing a DIP process to remove the reserved portion, the uniformity of the hard mask layer thickness after polishing the wordline polysilicon layer is improved, thereby reducing the amount of hard mask layer residue left during subsequent etching of the hard mask layer. Therefore, this method effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0055] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical concepts disclosed herein shall be covered by the claims of this application.

Claims

1. A method for improving the thickness uniformity of a hard mask layer after polishing a word line polysilicon layer, characterized in that: The method comprises: Providing a substrate, the substrate is divided into a core area and a peripheral area, and a plurality of flash memory gate structures are formed on the core area; depositing a hard mask layer to cover the core region and the peripheral region; Etching the hard mask layer to form a plurality of strip-shaped trenches in the hard mask layer in the core region; depositing a wordline polysilicon layer to cover the hard mask layer and fill the plurality of strip-shaped trenches; grinding the word line polysilicon layer and the hard mask layer until the thickness of the hard mask layer exceeds a predetermined thickness by a reserved portion; A soaking process is performed to remove the reserved portion of the hard mask layer.

2. The method according to claim 1, characterized in that The process parameters of the immersion process are: immersion in 100:1 hydrofluoric acid for 40s-1000s.

3. The method according to claim 1, characterized in that The process parameters of the immersion process are: immersion in 200:1 hydrofluoric acid for 100s-2300s.

4. The method according to claim 1, wherein The reserved portion is 100 angstroms to 2000 angstroms.

5. The method according to claim 1, wherein The deposition is chemical vapor deposition.

6. The method according to claim 1, characterized in that The grinding is chemical mechanical grinding.

7. The method according to claim 1, characterized in that The flash memory gate structure includes: a floating gate located on the gate oxide layer of the core area, an ONO layer located on the floating gate, a control gate located on the ONO layer, an oxide layer located on the control gate, and sidewalls covering the sidewalls of the floating gate, the ONO layer, the control gate and the oxide layer.

8. The method according to claim 7, characterized in that The ONO layer consists of silicon oxide-silicon nitride-silicon oxide layers.

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