Ion accelerator standard power supply controller and its dynamic partial reconfigurable method

Abstract

The application relates to an ion accelerator standardized power supply controller and a dynamic local reconfigurable method thereof, which comprises a main plate, a standardized self-defined interface, a main control plate interface and a main control plate; the main plate is provided with a communication interface for communication between the power supply controller and other devices; the standardized self-defined interface is used for connecting the main plate with different function sub-plates, WR sub-plates and power supply modules; the main control plate interface is used for collecting all controllable signals of the main plate to the main control plate; the main control plate is provided with an ARM processor and an FPGA; the ARM processor is configured with an embedded EPICS application program for reading and writing the FPGA and directly publishing related variables in the main control plate into standard EPICS supported PV variables to communicate with an upper computer; the FPGA is configured with a modular bottom layer regulator framework, and the monitoring and control of main circuits of different types of accelerator power supplies are realized by dynamically and locally reconfiguring corresponding modules. The application can be widely applied in the field of ion accelerators.

Description

Technical Field

[0001] This invention relates to a standardized power controller for magnet power supply in ion accelerators and its dynamic local reconfigurable method, belonging to the field of ion accelerators. Background Technology

[0002] An ion accelerator is an acceleration device that uses a high-frequency electric field to accelerate ions along a defined straight or circular trajectory. Ion accelerators cause charged particles to move in a straight line or periodically within a magnetic field and are continuously accelerated in the electric field, giving the ions very high velocities. To confine these ions to a specific trajectory, excitation currents generated by numerous magnets are used to create a confinement magnetic field, providing a defined path for the ion beam. In some applications, voltage sources are also required, such as power sources, electrostatic deflectors, pre-amplifier voltage sources for magnet power supplies, and high-excitation voltage sources. Power supplies can be categorized into various types based on their characteristics. Generally, a large ion accelerator typically consists of dozens or even hundreds of different types and specifications of power supplies.

[0003] Accelerator magnet power supplies are the most diverse and varied type of current source. Modern magnet power supplies are digitized, and due to the different working principles and control methods of different types, there are various types and versions of the embedded controller hardware and its internal control program. Communication interfaces and control protocols differ significantly, sometimes even involving multi-level protocol conversions. This results in low communication reliability and a large workload for program modification and upgrades.

[0004] The core function of a magnet power supply controller is to control the internal main circuit and related hardware of the power supply to achieve the functions and specifications of the magnet power supply. Since accelerator magnet power supplies have the most diverse types and specifications, their working principles and circuit structures are completely different, and the current regulators inside the magnet power supply controllers also vary significantly. Currently, FPGA-based regulator designs are based on a code-interconnected functional module programming model. Different circuit topologies require different PWM strategies, and filtering, current regulation strategies, and current output modes may also differ. These functional modules are currently code-based, and modifications, replacements, debugging, and upgrades are all done manually by programmers at the code level. Each adjustment or optimization of a local function requires global compilation and debugging, which takes a long time. Adding new functions requires adjusting the entire program structure, sometimes introducing new errors. In short, this programming model requires programming, compilation, simulation, downloading, debugging, and testing for every modification; even changing a single number requires going through the entire process, which is time-consuming. It is evident that this modular interconnected programming model is relatively fixed, lacks flexibility, imposes a heavy workload on technical personnel, is inefficient, and is prone to errors. Currently, the program compilation and debugging modes do not support the isolation of local problems. This pattern affects the efficiency of controller software design, maintenance, and upgrades.

[0005] Parameter monitoring and management of accelerator magnet power supplies is also a crucial aspect. Currently, most accelerator magnet power supply controllers use embedded microcontrollers to transmit communication parameters, primarily based on custom protocols. These protocols have limited programmable resources, a limited number of processing threads, slow response times, and are often single-connection, lacking support for multi-connection and connection management mechanisms. Furthermore, magnet power supply controller parameters are often stored in multiple sets after power supply commissioning, and monitoring and recording of these parameters may be required on multiple terminals (multiple local and remote terminals). Current accelerator magnet power supply controllers struggle to meet these demands in terms of parameter processing and response capabilities. Therefore, as future generations of accelerators demand increasingly higher power supply performance, real-time monitoring, storage, and management of power parameters across multiple interfaces is a critical issue that power supply controllers need to address.

[0006] Because circuit topologies and power devices are updated relatively slowly, hardware upgrades are not a concern for extended periods. Therefore, most power controller hardware does not consider hardware platform flexibility and scalability. Accelerator power controller hardware is relatively stable, with most employing a single hardware solution. However, with the development of accelerator technology, the power requirements of next-generation accelerators are increasing. New demands and technologies are constantly emerging, causing hardware to become inadequate for these needs and applications. This necessitates designing controller hardware circuits, layouts, and interfaces to increase flexibility and scalability. Typically, the core board, ADC board, DAC board, and PWM interface may have different requirements for different power supplies. Using a single solution often leads to waste or requires adjustments to the entire hardware architecture due to insufficient local performance. Furthermore, as accelerators continuously increase power performance requirements, the throughput and processing capabilities of existing data communication interfaces are insufficient, necessitating upgrades to meet future applications. How to reliably and real-time cascade and expand existing hardware solutions is also a crucial issue that controllers need to address.

[0007] Currently, accelerator power supplies lack an internal time base. Synchronization and relative timekeeping within the power controller are achieved through external triggering and counter counting, resulting in relatively low synchronization accuracy. To support higher-precision timing systems, the power controller needs to design and add support boards and interfaces for these systems. These boards and interfaces allow the power controller to obtain absolute and accurate time stamps, enabling precise time tagging of accelerator power supply data and providing more accurate synchronization and tagging capabilities. Future performance improvements in next-generation accelerators will inevitably require power supplies with more precise time synchronization, and data with accurate time tags to facilitate system analysis, prediction, and protection of the power supply and related equipment's normal and abnormal states.

[0008] Furthermore, with the development of science and technology, fields such as medical ion accelerators, nuclear waste biodegradation, and isotope production have placed higher demands on the long-term operational reliability of next-generation high-power, high-current accelerator power supplies. Methods to improve the reliability of an accelerator power system by increasing the reliability of a single power supply are limited. This is because all power supplies in an accelerator power system typically need to operate simultaneously in a certain state to ensure normal accelerator operation, which is equivalent to all power supplies operating in series. Even if one power supply deviates from its set output value, it will affect the system. The reliability improvement of a single power supply is limited; therefore, traditional power controllers often neglect how to better support and improve power supply reliability. We know that parallel connection of modular power supplies is a major means of improving the reliability, flexibility, and combination of existing accelerator power supplies. However, existing accelerator power controllers often only focus on the regulation and control of the current of a single power supply, lacking support for series-parallel connection, interlocking, and bus-based operation of modular power supplies. In addition, the access, disconnection, anomalies, and lifespan of modular power supplies require corresponding management strategies from the controller to create more reliable combined power supplies. Therefore, for accelerator power supplies with high reliability requirements, the controller needs a control interface and management mechanism for series-parallel connection of modular power supplies.

[0009] In summary, the field of ion accelerators currently lacks universal, unified, and standardized power controllers and their software design methods to improve the quality and reliability of accelerator power controllers, increase the efficiency of their design, debugging, maintenance, and upgrades, reduce costs, and achieve universality, flexibility, and scalability to meet the high-quality and high-reliability power supply requirements of future generations of accelerators (CiADS, HIAF, isotope, superheavy nucleus, medical accelerators, superconducting accelerators, etc.). Summary of the Invention

[0010] To address the aforementioned problems, the purpose of this invention is to provide a standardized, universal, and unified standardized power controller for ion accelerators and its dynamic local reconfigurable method, thereby achieving universality and uniformity in the hardware and software of ion accelerator power controllers, as well as standardization of power controllers in the field of ion accelerators.

[0011] To achieve the above objectives, the present invention adopts the following technical solution:

[0012] In a first aspect, the present invention provides a standardized power controller for an ion accelerator, comprising: a chassis and a motherboard, a main control board, and several daughter boards disposed within the chassis; the motherboard is provided with various standardized interfaces, including a communication interface, a standardized custom interface, and a main control board interface; the communication interface is used to realize communication between the power controller and internal and external devices of the accelerator power supply; the standardized custom interface is used to realize the connection between the motherboard and the daughter boards with different functions, and also provides a power interface for connecting power modules; the main control board interface is used to realize the connection between the main control board and the motherboard, and to aggregate all controllable signals received by the motherboard to the main control board; the main control board is provided with an ARM processor and an FPGA; the ARM processor is configured with an embedded EPICS application program, used to read and write to the FPGA, and to publish relevant variables in the main control board as standard EPICS-supported PV variables for communication with a host computer; the FPGA is configured with a modular underlying regulator framework, which realizes the monitoring and control of the main circuit of different types of accelerator power supplies by dynamically and locally reconfiguring the corresponding modules in the modular underlying regulator framework.

[0013] Furthermore, the development framework for the embedded EPICS application is based on a device-supported development framework. The device supports 11 standard devices, including reference waveform control, analog input, analog output, quench protection, adjustment parameter reading and writing, current and voltage reading and writing protection, synchronization and triggering, IO reading and writing, status reading and writing, LCD screen reading and writing, and module power supply series and parallel connection.

[0014] Furthermore, the modular underlying regulator framework includes an ADC module, a filtering module, a protection module, an algorithm module, and a pulse modulation module. The ADC module is used to receive feedback current or voltage signals. The filtering module is used to filter the current or voltage signals received by the ADC module and send them to the protection module and the algorithm module. The protection module and the algorithm module process the filtered signals and send them to the pulse modulation module. The pulse modulation module generates a PWM signal and outputs it to the main circuit of the accelerator power supply.

[0015] Furthermore, the sub-board includes at least one of a low-speed AD sub-board, a high-speed AD sub-board, a high-speed DA sub-board, an IO sub-board, a PWM sub-board, and a WR sub-board; the low-speed AD sub-board and the high-speed AD sub-board are used to collect feedback current and voltage signals inside the accelerator power supply at different sampling speeds and convert them into digital signals to be sent to the main control board; the high-speed DA sub-board is used to convert the data generated inside the main control board into analog signal output for observation or as a reference for the fast-response analog power supply; the IO sub-board is used to monitor various status signals and switching signals inside the accelerator power supply; the PWM sub-board is used to convert the PWM signal sent by the main control board into the required signal and send it to the drive circuit of the main circuit of the accelerator power supply; the WR sub-board supports the White Rabbit time synchronization system for time synchronization of the power controller.

[0016] Furthermore, the communication interface includes one Gigabit Ethernet electrical interface, one Gigabit Ethernet SFP interface, two WR board SFP interfaces, two 10 Gigabit SFP+ interfaces, two USB interfaces, one CAN interface, one 485 interface, one serial port, one main control board debugging interface, one WR board debugging interface, two optical receiver ports, two optical output interfaces, one debugging JTAG interface, a system clock / reset interface, one LCD interface, and two SMA interfaces. Each of the communication interfaces is used to connect internal and external devices of the power supply.

[0017] The standardized custom interface includes three 40-pin interfaces, two 60-pin interfaces, and one power interface; the three 40-pin interfaces are used to connect and combine daughterboards with different functions via 40-pin connectors; the two 60-pin interfaces are used to connect the WR daughter card; and the power interface is used to connect the power module via a power connector.

[0018] Furthermore, the chassis includes a front panel, a rear panel, and a top cover, and the front panel and the top cover are detachably mounted on the rear panel;

[0019] The front panel provides maintenance interfaces, including: a reset hole, four power status lights, two USB external interfaces, two Type-C debugging external interfaces, one Gigabit Ethernet external interface, and at least one LCD external interface; and the reset hole, USB external interfaces, Type-C debugging external interfaces, Gigabit Ethernet external interfaces, and LCD external interfaces serve as the exit points for the motherboard's reset interface, USB interface, main control board debugging interface, WR board debugging interface, Gigabit Ethernet external interface, and LCD interface, respectively.

[0020] The rear panel serves as the operating interface for the power supply, including: 24 SMA-type PWM optical I / O external interfaces, one 24-pin J30J electrical external interface, one CAN external interface, one RS485 / 422 external interface, one RS232 / IIC external interface, six SMA electrical signal external interfaces, two WR board SFP external interfaces, four SMA optical signal external interfaces, one Gigabit Ethernet SFP external interface, two 10 Gigabit SFP+ external interfaces, one 220V power port with a switch, and at least one grounding terminal; the 24 SMA-type PWM optical I / O external interfaces serve as outputs for two PWM daughter boards; the one 24-pin J30J electrical external interface serves as an output for an I / O daughter board; the one CAN external interface serves as an output for a CAN interface, used to manage the power supply composed of module power supplies connected in series and parallel; the RS485 / 422 external interface serves as an output for a 485 interface, used for... The system communicates with an independent status control board inside the power supply. The RS232 / IIC external interface serves as a serial port output for communication with an independent LCD screen inside the power supply. Any two of the six SMA electrical signal external interfaces serve as outputs for two SMA interfaces on the motherboard, used to receive electrical trigger signals and external clock signals. The remaining four serve as two analog signal outputs for the high-speed AD and DA daughterboards, used to receive high-speed ADC and high-speed DAC signals. The two WR board SFP external interfaces serve as outputs for the WR board SFP interfaces. The four SMA optical signal ports serve as outputs for two optical output interfaces and two optical receiving interfaces on the motherboard, used for 100Mbps optical communication. The one Gigabit Ethernet SFP external interface and the two 10 Gigabit Ethernet SFP+ external interfaces serve as outputs for one Gigabit Ethernet SFP interface and two 10 Gigabit SFP+ interfaces on the motherboard, respectively.

[0021] Furthermore, the power module is used to provide the DC power required by the motherboard. The DC power supply provides at least one output voltage among ±12V, +12V, ±5V, and ±3.3V, and uses 220V AC power supply to power different types of accelerator power supplies.

[0022] Secondly, the present invention provides a method for dynamically locally reconfigurable power controllers for ion accelerators, comprising the following steps:

[0023] Configure a standardized power controller for ion accelerators, and configure embedded EPICS applications and modular underlying regulator frameworks in the ARM processor and FPGA of the main control board, respectively.

[0024] Based on actual functional requirements, the corresponding modules within the modular underlying regulator framework of the FPGA are dynamically and locally reconfigured, while the corresponding combinations of the daughter boards connected to the motherboard are adjusted accordingly.

[0025] When the system is running or starting up, the embedded EPICS application in the ARM processor reads and writes to the FPGA, and publishes the relevant variables in the main control board as standard EPICS-supported PV variables, and then communicates with the host computer to realize the monitoring and control of the main circuit of the power supply of different types of accelerators.

[0026] Furthermore, the workflow of the embedded EPICS application includes the following steps:

[0027] Boot the Linux system on the ARM processor and initialize it;

[0028] Start the IOC main program in the embedded EPICS application to complete the execution of the self-starting script;

[0029] After the IOC main program starts, it calls the hpu_16.db file to publish all the PV variables therein, and calls the device support program related to each PV variable to set the scan cycle to run, and controls the corresponding data, parameters and status in the FPGA;

[0030] The ARM processor reads or writes PV variable data from the FPGA and synchronizes with the host computer.

[0031] Furthermore, the method for dynamically and locally reconfiguring corresponding modules within the modular underlying regulator framework of the FPGA processor based on actual functional requirements includes:

[0032] 2.1) In reconfiguration mode, generate the bit file full.bit of the modular underlying regulator framework and the partial bit file partial.bit corresponding to each reconfiguration module;

[0033] 2.2) Based on the full.bit and each partial.bit file, generate the corresponding bin files full.bin and partial.bin, and transfer the two bin files to the User_Application user space of the embedded Linux;

[0034] 2.3) Write a first script file to download the full.bin file to the reconfigurable area of ​​the FPGA_PL. The first script file contains all the steps to download the contents of the full.bin file to the reconfigurable area of ​​the FPGA_PL through the PCAP mechanism.

[0035] 2.4) Power on and start the power controller;

[0036] 2.5) Enter Linux and run the first script file to view the power performance metrics under the default configuration;

[0037] 2.6) Based on the dynamic reconfiguration requirements, write a second script file to download the partial.bin file of the specified reconfigurable module to the reconfiguration area of ​​the FPGA_PL terminal;

[0038] 2.7) Run the second script file and check its power performance indicators;

[0039] 2.8) Repeat steps 2.6) to 2.7) to achieve dynamic replacement of other modules.

[0040] This invention, by adopting the above technical solutions, has the following advantages: By setting various standardized interfaces on the motherboard and combining different sub-boards, as well as dynamically reconfiguring the layout of corresponding modules within the underlying regulator framework of the main control board, this invention solves the problems caused by the large number of controller types and software versions within the accelerator power supply. It achieves the universality and unification of the hardware and software of the ion accelerator power controller, and proposes a standardized method for power controllers in the accelerator field. For accelerator power controllers, this invention effectively simplifies design, shortens the development cycle, improves debugging, maintenance, and upgrade efficiency, and ensures the quality and reliability of the power controller. This invention can be widely applied in the field of ion accelerators such as linear accelerators, circular accelerators, and cyclotron accelerators; it can also be widely applied in accelerator application devices such as medical devices, isotope production devices, space irradiation devices, material irradiation devices, nuclear waste treatment devices, and accelerator research devices; and it can also be applied to future next-generation superconducting accelerators and next-generation high-power, high-current accelerator devices. Therefore, this invention can be widely applied in the field of ion accelerators. Attached Figure Description

[0041] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Throughout the drawings, the same reference numerals denote the same parts. In the drawings:

[0042] Figure 1 This is a standardized power controller hardware structure diagram provided in an embodiment of the present invention;

[0043] Figure 2 This is a structural diagram of the standardized power controller main control board provided in an embodiment of the present invention;

[0044] Figures 3a to 3f This is a standardized power controller sub-board structure diagram provided in an embodiment of the present invention, wherein, Figure 3a It's a PWM1 board. Figure 3b It's a PWM2 board. Figure 3c It's an I / O board. Figure 3d It is a low-speed AD board. Figure 3e It is a high-speed AD board. Figure 3f It is a high-speed DA board;

[0045] Figures 4a-4c This is a standardized power controller chassis structure diagram provided in an embodiment of the present invention, wherein, Figure 4a It's the front panel of the computer case. Figure 4b This is a top view of the computer case. Figure 4c This is a picture of the rear panel of the computer case;

[0046] Figure 5 This is a flowchart of the standardized power controller embedded EPICS software provided in an embodiment of the present invention;

[0047] Figure 6 This is a structural diagram of a standardized power reconfiguration regulator provided in an embodiment of the present invention;

[0048] The markings in the diagram are as follows:

[0049] 1-4. Connectors; 5. Handle; 6. Reset hole; 7. Power status indicator; 8. USB external interface; 9. Type-C debugging external interface; 10. Gigabit Ethernet external interface; 11. LCD external interface; 12. Mounting hole; 13. 24 SMA PWM optical I / O external interfaces; 14. 24-pin J30J electrical external interface; 15. CAN external interface; 16. RS485 / 422 external interface; 17. RS232 / IIC external interface; 18. SMA electrical signal external interface; 19. WR board SFP external interface; 20. SMA optical signal external interface; 21. Gigabit Ethernet SFP external interface; 22. 10 Gigabit SFP+ external interface; 23. 220V power port with switch; 24. Grounding terminal. Detailed Implementation

[0050] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the described embodiments of the present invention are within the scope of protection of the present invention.

[0051] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0052] Due to the universality, uniformity, flexibility, and scalability of the hardware and software design of the ion accelerator power controller proposed in this invention, a standardized and dynamically locally reconfigurable accelerator power controller is formed. The relevant content is described below so that those skilled in the art can have a clearer understanding of the content of this invention.

[0053] Accelerator magnet power supplies typically comprise hundreds or even thousands of units, with a wide variety of types and specifications. The lack of universality and standardization in the hardware, software, and communication protocols of these power controllers leads to inefficiencies and high personnel costs, as each power supply requires dedicated manpower and effort for design, debugging, maintenance, and upgrades. To achieve uniformity and flexibility in accelerator power controllers and to realize standardization, consideration must be given to both the hardware and software aspects of the power controllers.

[0054] In terms of hardware, the required hardware functions for all types of power supplies currently used in ion accelerators have been statistically analyzed and summarized. On a high-performance hardware platform, the flexibility and scalability of the accelerator power controller hardware are enhanced by adding multiple standardized interfaces with proven reliability. Using these standardized interfaces, the original integrated hardware design is divided into different daughterboards. By replacing or adding daughterboards with standardized interfaces, the needs of the accelerator power supply for different hardware functions and interfaces can be met, facilitating hardware reconfiguration and upgrades. The design of the standardized interfaces must be able to meet the functional expansion needs of the daughterboards, especially ensuring sufficient power supply types, the number of input / output ports, and bandwidth.

[0055] In terms of software, the control programs within the accelerator power controller exist in various types and versions, with significant differences in communication interfaces and control protocols, even involving multi-level protocol conversions. This results in low communication reliability and a large workload for program modification and upgrades. To unify the communication protocol and improve software flexibility and scalability, this invention adopts embedded EPICS (Experimental Physics and Industrial Control Systems) as the standard application layer software for the accelerator power controller. EPICS is based on the powerful programming environment of embedded Linux, and its communication layer is encapsulated and unified through the CA (Channel Access) mechanism. Its communication response speed is suitable for accelerator power monitoring, and its programming structure is unified and convenient. Utilizing its rich programming resources and ecosystem, an embedded IOC (Input / Output Controller) is written, and software functions are added and upgraded through PV (Process Variable) variables and device support. Simultaneously, the required control quantities can be directly published as PV variables, a standard in the accelerator field, facilitating flexible and reliable monitoring from multiple terminals. This achieves the universality and uniformity of the application layer program for the power controller.

[0056] Currently, the design of regulators on accelerator power controllers involves functional modules based on FPGA code. Different circuit topologies require different PWM (Pulse Width Modulation) strategies, and filtering, current regulation strategies, and current output modes may also differ. Furthermore, some module functions are quite dispersed, used in some power supplies but not others. For example, synchronization and triggering functions, and series / parallel management functions for module power supplies, require modifications, additions, removals, and reorganizations at the code level, along with overall compilation and debugging. This process is time-consuming, error-prone, inefficient, and prone to introducing new problems. To address these issues, this invention utilizes the platform's supported Internal Processor Configuration Access Port (PCAP) and EPICS application layer software to initiate a dynamic local reconfiguration process for FPGA functional modules. The regulators within the FPGA can be modularly designed, including modules with frequently changing requirements such as ADC driver modules, algorithms, filters, PWM, synchronization, and triggering. These modules and their interfaces are standardized to facilitate replacement, reorganization, and generation of regulators and control strategies for different power supplies, thereby achieving dynamic local reconfiguration of the power supply's internal controller. Introducing the dynamic local reconfiguration method increases the flexibility of FPGA internal logic design, saves compilation time, facilitates the reuse of existing functional modules, and improves efficiency. It also represents a technological breakthrough by enabling one power controller to be instantly changed to another through software settings, thus achieving complete unification and universality of accelerator power controllers.

[0057] Example 1

[0058] like Figure 1As shown, the standardized power controller for an ion accelerator provided in this embodiment includes: a chassis and a motherboard, a main control board, and several daughter boards disposed within the chassis. The motherboard integrates and interconnects the main control board, each daughter board, and the power module, ensuring high-speed and reliable data exchange between the main control board and each daughter board, while also ensuring the integrity of power supply to each interface. Specifically, the motherboard is equipped with various standardized interfaces, including communication interfaces, standardized custom interfaces, and a main control board interface. The communication interfaces enable communication between the controller and other internal and external devices within the power supply. The standardized custom interfaces connect the motherboard to different functional daughterboards and provide power interfaces for connecting power modules. The main control board interface connects the main control board on the motherboard to the various standardized interfaces on the motherboard and aggregates all controllable signals from the motherboard to the main control board. The main control board contains an ARM processor and an FPGA. The ARM processor has an embedded EPICS application program for reading and writing to the FPGA and directly publishing quantities that need to be controlled via the network from the main control board as standard EPICS-supported PV variables for communication with the host computer. The FPGA contains a modular underlying regulator framework, which dynamically reconfigures corresponding modules within the framework to monitor and control the main circuits of different types of accelerator power supplies.

[0059] Preferably, the motherboard uses Xilinx's ZYNQ series FPGA as the main control chip.

[0060] Preferably, the communication interface includes one Gigabit Ethernet electrical interface (RJ-45 interface in the figure), one Gigabit Ethernet SFP interface (SFP interface 1 in the figure), two WR board SFP interfaces supporting the high-precision White Rabbit time synchronization system, two 10 Gigabit SFP+ interfaces (SFP+1 and SFP+2 in the figure), two USB interfaces (UART-MUSB and PS_USB3.0 in the figure), one CAN interface (PS_CAN2.0 in the figure), one 485 (or 422) interface (PS-UART-485 in the figure), one serial port (RS232 or IIC) (PS-IIC / RS232 in the figure), one main control board debugging interface (UART1 in the figure), one WR board debugging interface (UART2 in the figure), two optical receiving interfaces (2×HFBR2406 in the figure), two optical output interfaces (1×HFBR1404 in the figure), one debugging JTAG interface, a system clock / reset interface, one LCD interface, and two SMA interfaces.

[0061] Preferably, the standardized custom interface includes three 40-pin interfaces, two 60-pin interfaces, and one power interface. The three 40-pin interfaces are used to connect and combine different daughterboards via 40-pin connectors to improve the flexibility and scalability of the control board. The two 60-pin interfaces are used to connect the WR daughterboard supporting the high-precision White Rabbit timing system. The power interface is used to connect the power module via a power connector. The 40-pin interface connector contains many high-speed parallel signal lines, including 32 high-speed digital I / O lines and 8 power terminals. While the requirements for this port are relatively low, the interface design and connector selection must at least meet the requirements of 100MHz bandwidth and long-term reliable connection. The standardized interface on the motherboard contains a large number of high-speed parallel signal lines and high-speed differential lines, and must be designed according to high-speed PCB design specifications.

[0062] Because accelerator power supplies come in various types and specifications, and current parameters and control functions also vary, a unified controller hardware platform would need to support many common standard interfaces. Furthermore, there are functional daughterboards, which typically have numerous functions and are frequently upgraded and changed; to ensure their uniformity and versatility, standardized definitions are usually required.

[0063] Preferably, such as Figure 2 As shown, the main control board constitutes a minimal microprocessor system, while supporting all standard interfaces of the baseboard and providing both software and soft-core programmability; it enables high-speed data transmission, digital signal processing, control algorithms, data storage and management, and the operation and integration of the sub-boards.

[0064] Specifically, the main control board consists of an ARM (PS) processor, an FPGA (PL), four DDR3 chips, two QSPI chips, and one eMMC FLASH chip, forming a high-performance microprocessor system. This system is the control center of the entire controller, responsible for all standardized interface data transmission and reception, and simultaneously processing and receiving data from all daughter boards in real time. Standard communication interfaces include: SFP Ethernet interface (except the SFP on the WR board), Gigabit Ethernet interface, CAN interface, RS485 / 422 interface, RS232 / IIC interface, USB interface, and SD card, all controlled by the ARM's standard peripherals. Custom communication ports, including SFP+ interface, optical output interface, optical receiver interface, LED, CLK and TRIG signals, 40-pin interface, and 60-pin interface, are implemented by the FPGA (PL). The FPGA handles highly real-time and custom-related signals.

[0065] Preferably, the embedded EPICS application configured within the ARM processor is a general-purpose embedded architecture software used to control various types of accelerator magnet power supplies and publish the required control quantities as PV variables. The software system is an application software based on embedded EPICS. This software is based on an embedded Linux system, supports multiple programming languages, and has rich programming resources and ecosystem; it also supports dynamic local reconfiguration, allowing for flexible and rapid replacement or reconfiguration of the FPGA underlying regulator through the EPICS software. This includes replacing and reconfiguring ADC driver modules, algorithms, filters, PWM modules, etc., to generate different regulation and control strategies. The software is easy to upgrade and maintain, has a short development cycle, and is highly versatile. It can directly publish the required control quantities as PV variables, which are standard in the accelerator field, facilitating flexible and reliable monitoring from multiple terminals. This application, starting from the perspective of universality, uniformity, and flexibility of accelerator power supplies, provides standard control functions for accelerator power supplies, realizing a new technology for software control of almost all types of accelerator magnet power supplies.

[0066] The development framework for the embedded EPICS application configured within the ARM processor is based on the device-supported development framework. It adapts to different accelerator power supply types by adding or modifying device support. The device support includes 11 standard device supports, such as reference waveform control, analog input, analog output, quench protection, adjustment parameter read / write, current and voltage read / write protection, synchronization and triggering, IO read / write, status read / write, LCD screen read / write, and module power supply.

[0067] The modular underlying regulator framework configured within the FPGA includes an ADC module, a filtering module, a protection module, an algorithm module, and a pulse modulation module. The ADC module receives feedback current or voltage signals; the filtering module filters the signals received by the ADC module and sends them to the protection and algorithm modules; the protection and algorithm modules process the filtered signals and then send them to the pulse modulation module; the pulse modulation module generates a PWM signal and outputs it to the main circuit of the power supply. By updating and replacing the specific implementations of some or all modules within the modular underlying regulator framework...

[0068] Preferably, the main control board and the motherboard are connected via four main control board connection ports and four 120-pin connectors, primarily for the connection and distribution of high-speed digital signals and power. This interface can be defined as a standardized main control board interface. The main control board is also a daughter board, and this daughter board connection method facilitates the modification and upgrading of the main control board without changing the motherboard. The motherboard design is designed to be compatible with commercial main control boards as much as possible, which facilitates early verification. Furthermore, where conditions permit, cost-effective commercial main control boards can be directly purchased to shorten the project development cycle. In addition, the main control board generates significant heat, so a passive cooling solution is adopted, and a fan can be installed on it for heat dissipation.

[0069] Preferably, the daughterboard is designed independently based on the actual needs of the accelerator power supply, with the hardware functions that need to be frequently changed and replaced. In this embodiment, the daughterboards all support a standardized 40-pin interface.

[0070] like Figures 3a to 3f As shown in this embodiment, the daughterboard mainly includes a low-speed AD daughterboard, a high-speed AD daughterboard, a high-speed DA daughterboard, an IO daughterboard, and a PWM daughterboard. The low-speed AD daughterboard and the high-speed AD daughterboard are mainly used to collect the feedback current and voltage signals of the accelerator power supply at different sampling speeds and convert them into digital signals to be sent to the main control board. The high-speed DA daughterboard is mainly used to convert the data generated inside the main control board into analog signal output for observation or as a reference for the fast-response analog power supply. The IO daughterboard is mainly used to monitor the control of various status signals and switching signals inside the accelerator power supply. The PWM daughterboard is mainly used to convert the PWM signal sent by the main control board into the required signal and then send it to the drive circuit of the main circuit.

[0071] Preferably, the AD converter is designed as a separate daughterboard because different power supplies have different functional performance requirements for the AD converter, and their costs and prices also vary. To adapt to the different power supply needs of accelerators, it is designed as a separate daughterboard. The low-speed AD daughterboard is mainly used to acquire the feedback current and voltage of the accelerator power supply, and is a key component in ensuring the power supply performance indicators. Its design must meet high acquisition accuracy and stability requirements. In high-precision applications, temperature stability also needs to be considered to meet the accuracy requirements of the accelerator power supply.

[0072] Specifically, such as Figure 3d As shown, the low-speed AD daughterboard includes a 40-pin standard daughterboard interface, a level conversion circuit, a low-speed AD acquisition chip, a reference source, and a front-end conditioning circuit. The low-speed AD acquisition chip is used for high-precision sampling of current and voltage under the reference source signal; to be compatible with most power supply sampling rates, a 1Msps sampling rate can be used. The level conversion circuit provides digital signal isolation for the sampling signal from the low-speed AD acquisition chip to protect the main control board. The front-end conditioning circuit performs low-pass filtering to improve acquisition accuracy; it can employ passive second-order filtering or an overcurrent protection circuit.

[0073] More preferably, since the accelerator power supply needs to collect a relatively large amount of current and voltage, the low-speed AD acquisition chip can generally adopt an 8-channel 18-bit high-precision ADC, and correspondingly, the front-end conditioning circuit adopts an 8-channel conditioning circuit. For more high-precision acquisition requirements, multiple low-speed AD daughter boards can be inserted into the motherboard.

[0074] Preferably, the high-speed AD daughterboard is used as a separate daughterboard because some accelerator power supplies require the acquisition, analysis, and processing of fast analog signals. The high-speed AD daughterboard is mainly used to acquire the feedback current and voltage of the high-speed accelerator power supply, and is a key component for power supply performance analysis and equipment protection. Its design typically needs to meet requirements in several aspects, including bandwidth and reliability. In high-speed applications, the distributed parameters of the circuit also need to be considered to meet the accelerator's requirements for the speed and synchronization of analog signal acquisition.

[0075] Specifically, such as Figure 3e As shown, the high-speed AD daughterboard is similar to the low-speed AD daughterboard. However, unlike the low-speed AD daughterboard, a single accelerator power supply typically requires less rapid current and voltage acquisition. Therefore, the high-speed AD daughterboard generally uses two 14-bit high-speed ADCs, and a sampling rate of 65Msps can be used to ensure compatibility with most power supplies. Correspondingly, the front-end conditioning circuit uses two-way conditioning circuitry. Similarly, for higher-speed acquisition requirements, multiple high-speed AD daughterboards can be inserted into the baseboard.

[0076] Preferably, the high-speed DA daughterboard is used as a separate daughterboard because the accelerator power supply requires observation of internal data and also needs to control the output current of certain fast-response linear power supplies through analog output signals. The high-speed DA daughterboard is a key component for digital power supply performance tuning and serves as the reference generation unit for the accelerator's fast-response analog power supply. It primarily converts data from the accelerator power supply controller into signals for observation or as a reference for the fast-response analog power supply. The design of the high-speed DA daughterboard typically needs to meet high sampling rates and stability requirements. In high-speed applications, the distributed parameters of the circuit also need to be considered to meet the accelerator power supply's requirements for speed and synchronization in analog signal output.

[0077] like Figure 3f As shown, in this embodiment, the high-speed DA daughterboard includes a 40-pin standardized daughterboard interface, a DAC chip, a level conversion circuit, a reference source, and a front-end conditioning circuit. Typically, a power supply requires two DAC signals; therefore, the DAC chip can generally be a dual-channel 14-bit high-speed DAC, and a 125Msps sampling rate can be used to ensure compatibility with most power supply sampling rates. In addition, a level conversion circuit is used for digital signal isolation, and the two-channel conditioning circuit primarily functions as amplitude limiting; overcurrent protection circuits can also be used. For higher-speed acquisition requirements, multiple high-speed DA daughterboards can be inserted into the mainboard.

[0078] Preferably, the I / O board is used as a separate sub-board because some low-power accelerator power supplies require a circuit state controller. The I / O sub-board is mainly used to monitor the internal status signals and switching signals of the accelerator power supply. The I / O board is the main unit for independent digital power supply power-on / off, reset, and internal fault detection. Low-speed I / O sub-boards typically need to meet reliability and interference immunity requirements. In high-voltage applications, interference between circuit state changes also needs to be considered to meet the reliability control requirements of the accelerator power supply for status signal output and input.

[0079] like Figure 3c As shown, the I / O daughterboard specifically includes a 40-pin standardized daughterboard interface, relay circuitry, and level conversion circuitry. Typically, a power supply requires 20 input signals and 4 relay switch outputs. A 5V voltage threshold is generally used as a higher voltage threshold to improve anti-interference capabilities. Furthermore, level conversion circuitry is also used for digital signal isolation. For power supplies with poor EMC, the internal status board can be controlled via an RS485 / 422 port using a data signal bus.

[0080] Preferably, the PWM daughterboard is used as a separate daughterboard because different accelerator power supplies have different PWM channel counts and electrical requirements. The PWM daughterboard is mainly used to convert the PWM signal sent from the accelerator power controller into the required signal and then send it to the drive circuit of the main circuit. The PWM daughterboard is a key component for digital power supply feedback control, and optical signals are usually used for driving in power supplies with high interference. The PWM daughterboard usually needs to meet the requirements of reliability and anti-interference. The PWM requirements of most accelerator power supplies can be obtained by combining PWM daughterboards. In cases with strict timing requirements, the output state of the PWM must have a strict state before the controller starts, so an interlocking mechanism is required to ensure the initial state of the PWM.

[0081] like Figure 3a and Figure 3b As shown, in this embodiment, the PWM daughterboard includes a first PWM daughterboard and a second PWM daughterboard. The first PWM daughterboard outputs all 12 PWM channels (e.g., ...). Figure 3a As shown), the second PWM daughterboard has 8 outputs and 4 inputs (as shown). Figure 3b (As shown). This is also to ensure compatibility with most power supplies that require input signals. A power supply typically needs multiple PWM signals, which can usually be achieved using a 5MDB HFBR. For additional PWM channels, they can be routed from the 40-pin connector on the baseboard. Furthermore, the WR board is a MINI board purchased from Xinhetai that supports the White Rabbit timing system, while the power module is a commercially available standard module power supply that has passed EMC testing and meets requirements.

[0082] Furthermore, the WR daughterboard is used to support high-precision time synchronization for the controller. From a time synchronization perspective, accelerator power supplies typically come in two types: those that support time synchronization and those that do not. Therefore, the time synchronization function is implemented as a separate daughterboard. The WR daughterboard has two JMDSS interfaces that connect to the motherboard. These interfaces are different, one male and one female, to prevent reverse pairing. The WR daughterboard is relatively small, about the size of two matchboxes. To ensure reliable and stable operation, it can have its own heatsink and can be screwed onto the base plate. As a standard WR daughterboard, its interfaces meet the requirements for time synchronization, and unnecessary power supplies can be removed to avoid waste.

[0083] Furthermore, the power supply module provides the DC power required by the circuit board. The DC power supply has four output voltages: ±12V, +12V, ±5V, and ±3.3V, powered by 220V AC. These standard voltages supply power to different circuit units. Separate power supplies provide isolation and local protection. Also, since different circuits have varying requirements for voltage stability and specifications, separate power supplies contribute to high cost-effectiveness. In addition, different types of accelerator power supplies have different voltage requirements, allowing for flexible allocation of these voltages. Unnecessary voltages can be removed, avoiding waste.

[0084] Preferably, such as Figures 4a-4c The diagram shows the structure of the chassis provided in this embodiment. The chassis is a container for mounting the accelerator power controller circuit board. In the strong magnetic and electric environment inside the ion accelerator power supply, mounting the circuit board inside the chassis provides excellent shielding. It adopts a standard 1U height and 19-inch width size for easy installation. Considering application in different racks, the chassis depth is not limited, but should be between 230cm and 300cm. The chassis consists of front and rear panels; the front panel and top cover can be removed for easy installation of the internal circuit boards. To facilitate heat dissipation of the internal circuitry, ventilation openings can be made on both sides of the chassis, and these are shielded with electromagnetic shielding mesh.

[0085] like Figure 4aAs shown, the front panel of the chassis primarily provides maintenance interfaces, including a reset hole that corresponds to the relevant interfaces on the motherboard, four power status LEDs, two USB external ports, two Type-C debugging ports, one Gigabit Ethernet external port (RJ45), and an LCD external port. The reset hole, USB external ports, Type-C debugging ports, Gigabit Ethernet external port, and LCD external port serve as the outputs for the motherboard's reset port, USB port, main control board debugging port, WR board debugging port, Gigabit Ethernet port, and LCD port, respectively. The LCD external port is also used to mount a 1.3-inch OLED screen to display information such as IP address and power status. In addition, the front panel also includes a handle and mounting holes for connecting to the rear panel.

[0086] like Figure 4c As shown, the rear panel of the chassis is mainly used for the working interfaces during power supply operation, including the following interfaces that are connected to the corresponding interfaces on the motherboard: 24 SMA-type PWM optical I / O external interfaces, 1 24-pin J30J electrical external interface, 1 CAN external interface, 1 RS485 / 422 external interface, 1 RS232 / IIC external interface, 6 SMA-type electrical signal external interfaces, 2 WR board SFP external interfaces, 4 SMA optical signal external interfaces, 1 Gigabit Ethernet SFP external interface, 2 10 Gigabit SFP+ external interfaces, 1 220V power port with switch, and 1 grounding terminal. Specifically, 24 SMA-type PWM optical I / O external interfaces serve as the outputs of two PWM daughterboards; a 24-pin J31J electrical external interface serves as the output of the I / O daughterboard; a CAN external interface serves as the output of the CAN interface on the motherboard, used to manage the power supply composed of modular power supplies (including standardized hot-swappable modular power supplies) connected in series and parallel; an RS485 / 422 external interface serves as the output of the serial port on the motherboard, used to communicate with the independent status control board inside the power supply; RS232 / IIC is used to communicate with the independent LCD screen inside the power supply; any two of the six SMA electrical signal external interfaces serve as two SMA interfaces on the motherboard. The motherboard has four ports: one for receiving electrical trigger signals and external clock signals; the remaining four ports serve as two analog signal ports for the high-speed AD and DA daughterboards, used to receive high-speed ADC and DAC signals; two WR board SFP ports serve as ports for the WR board SFP interfaces; four SMA optical signal ports serve as ports for two optical output interfaces and two optical receive interfaces on the motherboard, used for 100Mbps optical communication; one Gigabit Ethernet SFP external interface and two 10 Gigabit SFP+ external interfaces serve as ports for one Gigabit Ethernet SFP interface and two 10 Gigabit SFP+ interfaces on the motherboard, respectively.

[0087] Example 2

[0088] Based on the aforementioned standardized power controller for ion accelerators, this invention also provides a method for dynamically locally reconfigurable standardized power controllers for particle accelerators, comprising the following steps:

[0089] 1) Configure a standardized power controller for the ion accelerator, and configure an embedded EPICS application and a modular underlying regulator framework in the ARM processor and FPGA of the main control board, respectively.

[0090] 2) Based on actual functional requirements, dynamically reconfigure the corresponding modules in the modular underlying regulator framework within the FPGA, and simultaneously adjust the corresponding combinations of the daughterboards connected to the motherboard.

[0091] 3) When the system is running or starting up, the embedded EPICS application in the ARM processor reads and writes to the FPGA, and publishes the relevant variables that need to be controlled via the network in the main control board directly as standard EPICS-supported PV variables, and then communicates with the host computer to realize the monitoring and control of the main circuit of the power supply of different types of accelerators.

[0092] Preferably, in step 1) above, configuring an embedded EPICS application in the main control board means that the power controller application layer software uses embedded EPICS software as standard software to directly publish PV variables to monitor and control the power supply, thereby achieving unification and standardization at the communication layer.

[0093] The embedded EPICS software is based on a Linux environment and is developed using cross-compilation with the EPICS base (version 3.15.6) to create embedded EPICS IOC programs (refer to the EPICS reference manual). The embedded IOC programs run on the onboard hard-core ARM processor. Communication between the host computer and the FPGA is achieved through EPICS PV variables. The EPICS IOC can directly access the FPGA's on-chip register resources through peripheral drivers in the onboard ARM processor, performing read and write operations on register parameters. It can also access waveform data and local bus data through peripheral drivers in the onboard ARM processor. The system can display power supply current, voltage, status, and other information acquired in the FPGA on the host computer CSS monitoring interface using EPICS PV values, with an update rate of 0.5-1Hz. It can also configure regulators, module power management, and waveform data in the power controller via EPICS PV variables on the host computer CSS monitoring interface. Furthermore, it can set the DAC output signal in the power controller via the host computer CSS monitoring interface, with a maximum output frequency of 125MHz. In the power controller FPGA, each high-speed ADC acquisition channel needs to have a historical data storage capacity of over 100Kbytes, using DDR3 / 4 memory for each ADC. The data acquisition channel uses a 200ms rolling buffer, a 1µs sampling interval, and 20,000 historical data points. The host computer's CSS monitoring interface can display parameters such as upstream voltage, number of power modules, runtime, operating current, operating status, power-on time, and last fault. It needs to have basic self-checking functions after power-on, such as the status of each power supply, current, voltage, current status, temperature status, interface connection status, and communication status. During operation, it needs to monitor necessary status signals and issue alarms for abnormal temperatures, voltages, currents, and interface connection statuses, using status indicator lights and data packets for fault alarms.

[0094] like Figure 5 As shown, the workflow of the embedded EPICS configured in the main control board includes the following steps:

[0095] 1.1) Boot the Linux system on the ARM processor and initialize it;

[0096] 1.2) Start the IOC main program, complete the execution of the startup script, and have the procServ program maintain the process running in the background; where procServ is a program used to maintain the IOC main program process, ensuring that the IOC main program starts automatically and keeps its process running.

[0097] 1.3) After the IOC main program starts, it calls the hpu_16.db file to publish all the PV variables therein, and calls the device support program connected to each PV variable to set the scan cycle for operation. That is, it controls the corresponding data, parameters or status in the FPGA processor through the network. The hpu_16.db file is used by the ARM processor to access data from the FPGA processor. It contains the data structure of the PV variables, the scan cycle and the definition of the device support program call, etc.

[0098] 1.4) Read the save.sav file in the save folder (this file is a configuration file provided by the official autosave device, which specifies the values ​​of the PV variables to be saved), and write the saved PV values ​​into the corresponding PV variables. That is, the ARM processor reads data from the save.sav file and uploads it to the host computer.

[0099] Preferably, the method for booting and initializing the Linux system in step 1.1) above includes:

[0100] 1.1.1) Load the u-boot program to boot the Linux system;

[0101] 1.1.2) After the Linux system boots up, it runs the startup script in / etc / rc.locl, which loads the top.bin file to configure the full bitstream;

[0102] 1.1.3) Load the pl.dtbo file to configure the device tree, including DMA, RS485, etc.; where the pl.dtbo file is a custom device tree startup file, used to describe the hardware information related to the underlying regulator part of the FPGA processor;

[0103] 1.1.4) Load drivers including DMA device driver, RS485 device driver, IIC device driver, and equally spaced data retrieval device;

[0104] 1.1.5) Configure the serial port baud rate and start / stop parity bit of / dev / ttyPS1.

[0105] Preferably, in step 2) above, at the FPGA level, before the adoption of dynamic reconfiguration technology, every modification to the FPGA module requires recompilation, re-debugging, and program download, resulting in a long development cycle and low efficiency. Correspondingly, several power supply topologies may lead to several FPGA regulators. This results in numerous design versions of the FPGA regulator in the controller, lacking flexibility and adaptability. For this reason, a single regulator or some functional units cannot be applied to multiple power supply types.

[0106] This invention employs dynamic local reconfiguration technology for the algorithm design of the underlying regulator and other variable functional units, decomposing them into variable functional units. For example... Figure 6 As shown, this structure provides a regulator programming framework, including an ADC module, a filtering module, a protection module, an algorithm module, and a pulse modulation module. Utilizing FPGA's PCAP technology, the implementation of some or all of these modules can be dynamically changed during system runtime or startup. This allows for dynamic replacement and upgrades of these modules, ultimately reorganizing the internal modules of the regulator to form a new regulator, increasing the flexibility, adaptability, and scalability of the regulator design. For power supplies, dynamic local reconfiguration enables rapid switching between one power FPGA regulator program and another, allowing a single controller to control the main circuits of multiple types of accelerator power supplies. This achieves the universality and uniformity of the power controller, serving as a standardized design. Furthermore, this method eliminates the need for recompilation and downloading after program compilation; only configuration is required to quickly switch between different power supply programs, significantly improving efficiency.

[0107] Specifically, such as Figure 6 As shown, the method for dynamically and partially reconfigurable power controllers includes the following steps:

[0108] 2.1) In reconfiguration mode, the FPGA IDE (Vivado) generates the full.bit file for the complete regulator and the partial.bit file for each reconfiguration module.

[0109] 2.2) Use the FPGA IDE to generate corresponding bin files full.bin and partial.bin for each full.bit and each partial.bit, and transfer the above two bin files to the User_Application user space of the embedded Linux through the SSH protocol / card reader (SD card);

[0110] 2.3) Write a script file rc1 to download the full.bin file to the reconfigurable area of ​​the PL. This script file contains all the steps to download the contents of the bin file to the reconfigurable area of ​​the FPGA_PL through the PCAP mechanism. Different script files only need to change the file name;

[0111] 2.4) Power on the power controller, enter the Linux system and run the script file rc1 to view the power performance indicators under the default configuration;

[0112] 2.5) Based on the dynamic reconfiguration requirements, write a script file rc2 to download the partial.bin file of the specified reconfigurable module to the reconfiguration area on the PL side. Compared with the script file rc1, only the file name of the bin file for obtaining different modules needs to be changed in the script file rc1.

[0113] 2.6) Run the script file rc2 to view its power performance indicators;

[0114] 2.7) Repeat steps 2.5) to 2.6) to dynamically replace other modules.

[0115] In summary, this invention provides a standardized power controller and its dynamic local reconfigurable method for the internal power supply of an ion accelerator magnet. Utilizing a unified controller within the power controller, without compiling code, it achieves universality, uniformity, and standardization of the internal power supply controller by setting the main circuit structure of almost all known power supply types (including series-parallel module power supplies, superconducting power supplies, sine wave scanning power supplies, point scanning power supplies, dipole iron power supplies, quadrupole iron power supplies, solenoid power supplies, correction power supplies, injection rail power supplies, switching iron power supplies, fast quadrupole iron power supplies, triangular wave scanning power supplies, etc.). The embedded EPICS application is an embedded IOC that directly publishes quantities within the power supply that need to be controlled via the network as EPICS standard PV variables, achieving unified and standardized external communication for different types of power supplies. The embedded EPICS program can develop and expand the power supply's functionality by adding or modifying device support, and supports White Rabbit time synchronization. During system operation or startup, local modules of the digital regulator within the FPGA can be dynamically replaced or reconfigured to quickly form a new regulator to adapt to new main circuit topologies or various functional control requirements within the power supply. This invention can be widely applied in the field of next-generation high-requirement ion accelerators.

[0116] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A standardized power controller for an ion accelerator, characterized in that, include: The chassis and the motherboard, main control board and several daughter boards disposed within the chassis; The motherboard is equipped with various standardized interfaces, including communication interfaces, standardized custom interfaces, and main control board interfaces; The communication interface is used to enable communication between the power controller and internal and external devices of the accelerator power supply. The standardized custom interface is used to connect the motherboard to the daughterboards with different functions, and also provides a power interface for connecting the power module. The main control board interface is used to connect the main control board to the motherboard and to aggregate all controllable signals received by the motherboard to the main control board. The main control board is equipped with an ARM processor and an FPGA. The ARM processor is equipped with an embedded EPICS application, which is used to read and write to the FPGA, and publish the relevant variables in the main control board as standard EPICS-supported PV variables, and then communicate with the host computer. The FPGA is configured with a modular underlying regulator framework. By dynamically and locally reconfiguring the corresponding modules within the modular underlying regulator framework, the monitoring and control of the main power supply circuits of different types of accelerators can be achieved. The development framework for the embedded EPICS application is based on a device-supported development framework. The device support includes 11 standard device supports, such as reference waveform control, analog input, analog output, quench protection, adjustment parameter reading and writing, current and voltage reading and writing protection, synchronization and triggering, IO reading and writing, status reading and writing, LCD screen reading and writing, and module power supply series and parallel connection. The modular underlying regulator framework includes an ADC module, a filtering module, a protection module, an algorithm module, and a pulse modulation module. The ADC module is used to receive feedback current or voltage signals. The filtering module is used to filter the current or voltage signals received by the ADC module and send them to the protection module and the algorithm module. The protection module and the algorithm module process the filtered signals and then send them to the pulse modulation module. The pulse modulation module generates a PWM signal and outputs it to the main circuit of the accelerator power supply.

2. The standardized power controller for an ion accelerator as described in claim 1, characterized in that, The sub-board includes at least one of a low-speed AD sub-board, a high-speed AD sub-board, a high-speed DA sub-board, an IO sub-board, a PWM sub-board, and a WR sub-board. The low-speed AD sub-board and the high-speed AD sub-board are used to collect feedback current and voltage signals inside the accelerator power supply at different sampling speeds and convert them into digital signals to be sent to the main control board. The high-speed DA sub-board is used to convert the data generated inside the main control board into analog signals for output, for observation or as a reference for the fast-response analog power supply. The IO sub-board is used to monitor various status signals and switching signals inside the accelerator power supply. The PWM sub-board is used to convert the PWM signal sent by the main control board into the required signal and send it to the drive circuit of the main circuit of the accelerator power supply. The WR sub-board supports the White Rabbit time synchronization system for time synchronization of the power controller.

3. A standardized power controller for an ion accelerator as described in claim 2, characterized in that, The communication interface includes one Gigabit Ethernet electrical interface, one Gigabit Ethernet SFP interface, two WR board SFP interfaces, two 10 Gigabit SFP+ interfaces, two USB interfaces, one CAN interface, one 485 interface, one serial port, one main control board debugging interface, one WR board debugging interface, two optical receiver ports, two optical output interfaces, one debugging JTAG interface, a system clock / reset interface, one LCD interface, and two SMA interfaces. Each of the communication interfaces is used to connect internal and external devices of the power supply. The standardized custom interface includes three 40-pin interfaces, two 60-pin interfaces, and one power interface; the three 40-pin interfaces are used to connect and combine daughterboards with different functions via 40-pin connectors; the two 60-pin interfaces are used to connect the WR daughterboard; and the power interface is used to connect the power module via a power connector.

4. A standardized power controller for an ion accelerator as described in claim 3, characterized in that, The chassis includes a front panel, a rear panel, and a top cover, and the front panel and the top cover are detachably mounted on the rear panel; The front panel provides maintenance interfaces, including: a reset hole, four power status lights, two USB external interfaces, two Type-C debugging external interfaces, one Gigabit Ethernet external interface, and at least one LCD external interface; and the reset hole, USB external interfaces, Type-C debugging external interfaces, Gigabit Ethernet external interfaces, and LCD external interfaces serve as the exit points for the motherboard's reset interface, USB interface, main control board debugging interface, WR board debugging interface, Gigabit Ethernet external interface, and LCD interface, respectively. The rear panel is used for the operating interface during power supply operation, including: 24 SMA-type PWM optical I / O external interfaces, 1 24-pin J30J electrical external interface, 1 CAN external interface, 1 RS485 / 422 external interface, 1 RS232 / IIC external interface, 6 SMA electrical signal external interfaces, 2 WR board SFP external interfaces, 4 SMA optical signal external interfaces, 1 Gigabit Ethernet SFP external interface, 2 10 Gigabit SFP+ external interfaces, 1 220V power port with switch, and at least one of the following: a grounding terminal. The 24 SMA-type PWM optical I / O external interfaces serve as outputs for two PWM daughterboards; the 1 24-pin J30J electrical external interface serves as an output for the I / O daughterboard; the 1 CAN external interface serves as an output for the CAN interface on the motherboard, used to manage the power supply composed of module power supplies connected in series and parallel; the RS485 / 422 external interface serves as an output for the 485 interface, used to communicate with the independent status control board inside the power supply; the RS232 / IIC external interface serves as an output for the serial port on the motherboard, used to communicate with the independent LCD screen inside the power supply; any two of the 6 SMA electrical signal external interfaces serve as outputs for the 2... The motherboard has four SMA interfaces for receiving electrical trigger signals and external clock signals. The remaining four serve as two analog signal outputs for the high-speed AD and DA daughterboards, used to receive high-speed ADC and high-speed DAC signals. The two WR board SFP external interfaces serve as outputs for the WR board SFP interfaces. The four SMA optical signal external interfaces serve as outputs for two optical output interfaces and two optical receiving interfaces on the motherboard, used for 100Mbps optical communication. The one Gigabit Ethernet SFP external interface and the two 10 Gigabit SFP+ external interfaces serve as outputs for one Gigabit Ethernet SFP interface and two 10 Gigabit SFP+ interfaces on the motherboard, respectively.

5. A standardized power controller for an ion accelerator as described in claim 1, characterized in that, The power module is used to provide the DC power required by the motherboard. The DC power supply provides at least one output voltage among ±12V, +12V, ±5V, and ±3.3V, and uses 220V AC power supply for powering the internal circuit boards of the controller.

6. A method for dynamically locally reconfigurable power controllers for ion accelerators as described in any one of claims 1 to 5, characterized in that, Includes the following steps: Configure a standardized power controller for ion accelerators, and configure embedded EPICS applications and modular underlying regulator frameworks in the ARM processor and FPGA of the main control board, respectively. Based on actual functional requirements, the corresponding modules within the modular underlying regulator framework of the FPGA are dynamically and locally reconfigured, while the corresponding combinations of the daughter boards connected to the motherboard are adjusted accordingly. When the system is running or starting up, the embedded EPICS application in the ARM processor reads and writes to the FPGA, and publishes the relevant variables in the main control board as standard EPICS-supported PV variables, and then communicates with the host computer to realize the monitoring and control of the main circuit of the power supply of different types of accelerators.

7. The method for dynamically locally reconfigurable power controllers for ion accelerators as described in claim 6, characterized in that, The workflow of the embedded EPICS application includes the following steps: Boot the Linux system on the ARM processor and initialize it; Start the IOC main program in the embedded EPICS application to complete the execution of the self-starting script; After the IOC main program starts, it calls the hpu_16.db file to publish all the PV variables therein, and calls the device support program related to each PV variable to set the scan cycle to run, and controls the corresponding data, parameters and status in the FPGA; The ARM processor reads or writes PV variable data from the FPGA and synchronizes with the host computer.

8. A method for dynamically locally reconfigurable power controllers for ion accelerators as described in claim 6, characterized in that, The method for dynamically and locally reconfiguring corresponding modules within the modular underlying regulator framework of an FPGA based on actual functional requirements includes: 2.1) In reconfiguration mode, generate the bit file full.bit of the modular underlying regulator framework and the partial bit file partial.bit corresponding to each reconfiguration module; 2.2) Based on the full.bit and each partial.bit file, generate the corresponding bin files full.bin and partial.bin, and transfer the two bin files to the User_Application user space of the embedded Linux; 2.3) Write a first script file to download the full.bin file to the reconfigurable area of ​​the FPGA_PL terminal. The first script file contains all the steps to download the contents of the full.bin file to the reconfigurable area of ​​the FPGA_PL terminal through the PCAP mechanism. 2.4) Power-on startup of the power controller; 2.5) Enter Linux and run the first script file to view the power performance metrics under the default configuration; 2.6) Based on the dynamic reconfiguration requirements, write a second script file to download the partial.bin file of the specified reconfigurable module to the reconfiguration area of ​​the FPGA_PL terminal; 2.7) Run the second script file and check its power performance indicators; 2.8) Repeat steps 2.6) to 2.7) to achieve dynamic replacement of other modules.

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