Drive circuit, drive method, shift register, and display device

Abstract

The application provides a driving circuit, a driving method, a shift register and a display device. The driving circuit comprises a first control circuit, a second control circuit, a first output circuit, a second output circuit and an output terminal; the first control circuit is controlled by a control signal provided at a control terminal to turn on or off the connection between a first node and a first control voltage terminal; the second control circuit is controlled by the control signal to turn on or off the connection between a second node and a second control voltage terminal. By adopting the first control circuit and / or the second control circuit, when the first clock signal terminal continuously provides a first voltage signal during the holding period, the driving signal can be restored to the first voltage signal by the first control circuit and / or the second control circuit when the potential of the driving signal is not the first voltage signal, so that the working stability of the driving circuit is ensured.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to a driving circuit, driving method, shift register, and display device. Background Technology

[0002] In related technologies, when driving a display device at low frequency, during the holding period, when the clock signal terminal in the driving circuit provides a low voltage signal, the first output transistor in the first output circuit and the second output transistor in the second output circuit of the driving circuit are turned off. Since the first and second output transistors are under voltage stress for a long time, the characteristics of the first and second output transistors will drift, which will cause the potential of the driving signal provided by the driving circuit to be unable to be maintained at the first voltage, resulting in abnormal driving of the driving circuit. Summary of the Invention

[0003] The main objective of this invention is to provide a driving circuit, driving method, shift register, and display device to solve the problem that existing driving circuits, during the holding period, cause the potential of the driving signal provided by the driving circuit to fail to maintain the first voltage, resulting in abnormal driving of the driving circuit.

[0004] In one aspect, embodiments of the present invention provide a driving circuit, including a first control circuit, a second control circuit, a first output circuit, a second output circuit, and an output terminal;

[0005] The first output circuit is electrically connected to the first node, the first clock signal terminal and the output terminal respectively, and is used to turn on or off the connection between the output terminal and the first clock signal terminal under the control of the potential of the first node.

[0006] The second output circuit is electrically connected to the second node, the output terminal, and the first voltage terminal, respectively, and is used to turn on or off the connection between the output terminal and the first voltage terminal under the control of the potential of the second node;

[0007] The first control circuit is electrically connected to the control terminal, the first node and the first control voltage terminal respectively, and is used to turn on or off the connection between the first node and the first control voltage terminal under the control of the control signal provided by the control terminal.

[0008] The second control circuit is electrically connected to the control terminal, the second node, and the second control voltage terminal, respectively, and is used to turn on or off the connection between the second node and the second control voltage terminal under the control of the control signal.

[0009] Optionally, the first control circuit includes a first control transistor;

[0010] The control electrode of the first control transistor is electrically connected to the control terminal, the first electrode of the first control transistor is electrically connected to the first control voltage terminal, and the second electrode of the first control transistor is electrically connected to the first node.

[0011] Optionally, the second control circuit includes a second control transistor;

[0012] The control electrode of the second control transistor is electrically connected to the control terminal, the first electrode of the second control transistor is electrically connected to the second control voltage terminal, and the second electrode of the second control transistor is electrically connected to the second node.

[0013] Optionally, the first output circuit includes a first output transistor, and the second output circuit includes a second output transistor, wherein,

[0014] The control electrode of the first output transistor is electrically connected to the first node, the first electrode of the first output transistor is electrically connected to the first clock signal terminal, and the second electrode of the first output transistor is electrically connected to the output terminal.

[0015] The control electrode of the second output transistor is electrically connected to the second node, the first electrode of the second output transistor is electrically connected to the first voltage terminal, and the second electrode of the second output transistor is electrically connected to the output terminal.

[0016] Optionally, the driving circuit described in at least one embodiment of the present invention further includes a third node control circuit, a second node control circuit, a fourth node control circuit, a sixth node control circuit, and a first node control circuit, wherein,

[0017] The third node control circuit is electrically connected to the first clock signal terminal, the second clock signal terminal, the input terminal, and the third node, respectively, and is used to control the connection or disconnection between the third node and the input terminal under the control of the first clock signal provided by the first clock signal terminal and the second clock signal provided by the second clock signal terminal.

[0018] The second node control circuit is electrically connected to the second node, the second voltage terminal, the fourth node, the third clock signal terminal, and the control node, respectively. It is used to control the connection or disconnection between the control node and the second voltage terminal under the control of the potential of the fourth node, control the connection or disconnection between the control node and the third clock signal terminal under the control of the potential of the second node, and control the potential of the second node according to the potential of the control node.

[0019] The fourth node control circuit is electrically connected to the first voltage terminal, the second clock signal terminal, the fourth node, and the third node, respectively. It is used to control the connection or disconnection between the fourth node and the first voltage terminal under the control of the second clock signal, and to control the connection or disconnection between the fourth node and the second clock signal terminal under the control of the potential of the third node.

[0020] The sixth node control circuit is electrically connected to the fifth node, the third clock signal terminal and the sixth node respectively, and is used to control the connection or disconnection between the sixth node and the third clock signal terminal under the control of the potential of the fifth node, and to control the potential of the sixth node according to the potential of the fifth node.

[0021] The first node control circuit is electrically connected to the sixth node, the third clock signal terminal, the first node, the second node, and the first clock signal terminal, respectively. It is used to control the connection or disconnection between the sixth node and the first node under the control of the third clock signal provided by the third clock signal terminal, control the connection or disconnection between the first node and the first clock signal terminal under the control of the potential of the second node, and control the potential of the first node according to the first clock signal.

[0022] Optionally, the third node and the second node are the same node; or,

[0023] The driving circuit further includes a first on / off control circuit, which is electrically connected to the third node, the second node and the first voltage terminal respectively. The first on / off control circuit is used to control the connection between the third node and the second node under the control of the first voltage signal provided by the first voltage terminal.

[0024] Optionally, the fourth node and the fifth node are the same node; or,

[0025] The driving circuit further includes a second on / off control circuit, which is electrically connected to the fourth node, the fifth node and the first voltage terminal respectively. The second on / off control circuit is used to control the connection between the fourth node and the fifth node under the control of the first voltage signal provided by the first voltage terminal.

[0026] Optionally, the first node control circuit includes a first transistor, a second transistor, and a first capacitor;

[0027] The control electrode of the first transistor is electrically connected to the third clock signal terminal, the first electrode of the first transistor is electrically connected to the sixth node, and the second electrode of the first transistor is electrically connected to the first node.

[0028] The control electrode of the second transistor is electrically connected to the second node, the first electrode of the second transistor is electrically connected to the first clock signal terminal, and the second electrode of the second transistor is electrically connected to the first node.

[0029] The first terminal of the first capacitor is electrically connected to the first node, and the second terminal of the first capacitor is electrically connected to the first clock signal terminal.

[0030] The second node control circuit includes a third transistor, a fourth transistor, and a second capacitor, wherein,

[0031] The control electrode of the third transistor is electrically connected to the second node, the first electrode of the third transistor is electrically connected to the third clock signal terminal, and the second electrode of the third transistor is electrically connected to the control node.

[0032] The control electrode of the fourth transistor is electrically connected to the fourth node, the first electrode of the fourth transistor is electrically connected to the second voltage terminal, and the second electrode of the fourth transistor is electrically connected to the control node.

[0033] The first end of the second capacitor is electrically connected to the second node, and the second end of the second capacitor is electrically connected to the control node.

[0034] Optionally, the third node control circuit includes a fifth transistor and a sixth transistor, the fourth node control circuit includes a seventh transistor and an eighth transistor, and the sixth node control circuit includes a ninth transistor and a third capacitor, wherein...

[0035] The control electrode of the fifth transistor is electrically connected to the first clock signal terminal, and the first electrode of the fifth transistor is electrically connected to the input terminal.

[0036] The control electrode of the sixth transistor is electrically connected to the second clock signal terminal, the first electrode of the sixth transistor is electrically connected to the second electrode of the fifth transistor, and the second electrode of the sixth transistor is electrically connected to the third node;

[0037] The control electrode of the seventh transistor is electrically connected to the second clock signal terminal, the first electrode of the seventh transistor is electrically connected to the first voltage terminal, and the second electrode of the seventh transistor is electrically connected to the fourth node.

[0038] The control electrode of the eighth transistor is electrically connected to the third node, the first electrode of the eighth transistor is electrically connected to the second clock signal terminal, and the second electrode of the eighth transistor is electrically connected to the fourth node.

[0039] The control electrode of the ninth transistor is electrically connected to the fifth node, the first electrode of the ninth transistor is electrically connected to the third clock signal terminal, and the second electrode of the ninth transistor is electrically connected to the sixth node.

[0040] The first terminal of the third capacitor is electrically connected to the fifth node, and the second terminal of the third capacitor is electrically connected to the sixth node.

[0041] In a second aspect, embodiments of the present invention provide a driving method applied to the aforementioned driving circuit, wherein the driving cycle includes a driving period and a holding period; the driving method includes:

[0042] During the driving period, the first clock signal terminal provides a first clock signal, and the driving circuit outputs a driving signal through the first output circuit and the second output circuit; under the control of the control signal provided by the control terminal, the first control circuit disconnects the connection between the first node and the first control voltage terminal, and under the control of the control signal, the second control circuit disconnects the connection between the second node and the second control voltage terminal.

[0043] During at least a portion of the holding period, the first clock signal terminal provides a first voltage signal;

[0044] During at least a portion of the time period, the first control circuit, under the control of the control signal provided by the control terminal, connects the first node to the first control voltage terminal, and the second control circuit, under the control of the control signal, connects the second node to the second control voltage terminal.

[0045] Optionally, the driving method described in at least one embodiment of the present invention further includes:

[0046] During at least a portion of the time period, both the first control voltage terminal and the second control voltage terminal provide valid voltage signals.

[0047] Optionally, the at least part of the time period includes a first time period and a second time period set sequentially, and the driving method further includes:

[0048] During the first time period, the first control voltage terminal provides a valid voltage signal, and the second control voltage terminal provides an invalid voltage signal; during the second time period, the first control voltage terminal provides an invalid voltage signal, and the second control voltage terminal provides a valid voltage signal; or...

[0049] During the first time period, the first control voltage terminal provides an invalid voltage signal, and the second control voltage terminal provides an valid voltage signal; during the second time period, the first control voltage terminal provides a valid voltage signal, and the second control voltage terminal provides an invalid voltage signal.

[0050] Optionally, the at least partial time period includes at least two hold phases set sequentially, each hold phase including a third time period and a fourth time period set sequentially; the driving method further includes:

[0051] In the third time period, the first control voltage terminal provides a valid voltage signal, and the second control voltage terminal provides an invalid voltage signal; in the fourth time period, the first control voltage terminal provides an invalid voltage signal, and the second control voltage terminal provides a valid voltage signal; or...

[0052] During the third time period, the first control voltage terminal provides an invalid voltage signal, and the second control voltage terminal provides an valid voltage signal; during the fourth time period, the first control voltage terminal provides a valid voltage signal, and the second control voltage terminal provides an invalid voltage signal.

[0053] Optionally, the step of providing a first voltage signal at the first clock signal terminal during at least a portion of the holding period includes: providing a first voltage signal at the first clock signal terminal during a portion of the holding period;

[0054] The driving method further includes: during the time period other than the partial time period included in the holding period, the first control circuit disconnects the connection between the first node and the first control voltage terminal under the control of the control signal provided by the control terminal, and the second control circuit disconnects the connection between the second node and the second control voltage terminal under the control of the control signal.

[0055] In a third aspect, embodiments of the present invention provide a shift register including multiple stages of the aforementioned driving circuitry.

[0056] In a fourth aspect, embodiments of the present invention provide a display device including the shift register described above.

[0057] The driving circuit, driving method, shift register, and display device described in the embodiments of the present invention employ a first control circuit and / or a second control circuit so that, during the holding period, when the first clock signal terminal continuously provides a first voltage signal, if the potential of the driving signal is not the first voltage signal, the first control circuit and / or the second control circuit can control the driving signal to be restored to the first voltage signal, thereby ensuring the stability of the driving circuit operation. Attached Figure Description

[0058] Figure 1 This is a structural diagram of the driving circuit described in an embodiment of the present invention;

[0059] Figure 2 This is a timing diagram of the driving circuit described in an embodiment of the present invention;

[0060] Figure 3This is another timing diagram of the driving circuit described in the embodiment of the present invention;

[0061] Figure 4 This is a circuit diagram of the driving circuit according to at least one embodiment of the present invention;

[0062] Figure 5 This invention is as follows Figure 4 A timing diagram of at least one embodiment of the driving circuit shown;

[0063] Figure 6 This is a timing diagram of the driving circuit described in at least one embodiment of the present invention;

[0064] Figure 7 This is a timing diagram of the driving circuit described in at least one embodiment of the present invention;

[0065] Figure 8 This is a timing diagram of the driving circuit described in at least one embodiment of the present invention;

[0066] Figure 9 This is a timing diagram of the driving circuit described in at least one embodiment of the present invention;

[0067] Figure 10 This is a timing diagram of the driving circuit described in at least one embodiment of the present invention;

[0068] Figure 11 This is a timing diagram of the driving circuit described in at least one embodiment of the present invention;

[0069] Figure 12 This is a timing diagram of the driving circuit described in at least one embodiment of the present invention;

[0070] Figure 13 This is a circuit diagram of the driving circuit according to at least one embodiment of the present invention;

[0071] Figure 14 This is a circuit diagram of the driving circuit according to at least one embodiment of the present invention;

[0072] Figure 15 yes Figure 14 The timing diagram shows the operation of at least one embodiment of the driving circuit. Detailed Implementation

[0073] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0074] In all embodiments of this invention, the transistors used can be bipolar junction transistors (BJTs), thin-film transistors (TFTs), field-effect transistors (FETs), or other devices with similar characteristics. In these embodiments, to distinguish between the two terminals of the transistor other than the control terminal, one terminal is referred to as the first terminal, and the other as the second terminal.

[0075] In actual operation, when the transistor is a bipolar junction transistor (BJT), the control electrode can be the base, the first electrode can be the collector, and the second electrode can be the emitter; or, the control electrode can be the base, the first electrode can be the emitter, and the second electrode can be the collector.

[0076] In actual operation, when the transistor is a thin-film transistor or a field-effect transistor, the control electrode can be the gate, the first electrode can be the drain, and the second electrode can be the source; or, the control electrode can be the gate, the first electrode can be the source, and the second electrode can be the drain.

[0077] like Figure 1 As shown, the driving circuit described in this embodiment of the invention includes a first control circuit 11, a second control circuit 12, a first output circuit 13, a second output circuit 14, and an output terminal O1;

[0078] The first output circuit 13 is electrically connected to the first node N1, the first clock signal terminal K1 and the output terminal O1 respectively, and is used to turn on or off the connection between the output terminal O1 and the first clock signal terminal K1 under the control of the potential of the first node N1.

[0079] The second output circuit 14 is electrically connected to the second node N2, the output terminal O1 and the first voltage terminal V1 respectively, and is used to turn on or off the connection between the output terminal O1 and the first voltage terminal V1 under the control of the potential of the second node N2.

[0080] The first control circuit 11 is electrically connected to the control terminal R1, the first node N1 and the first control voltage terminal RG1 respectively, and is used to turn on or off the connection between the first node N1 and the first control voltage terminal RG1 under the control of the control signal provided by the control terminal R1.

[0081] The second control circuit 12 is electrically connected to the control terminal R1, the second node N2, and the second control voltage terminal RG2, respectively, and is used to turn on or off the connection between the second node N2 and the second control voltage terminal RG2 under the control of the control signal.

[0082] The driving circuit described in at least one embodiment of the present invention may be included in a shift register, which may be applied to a display device and may be used to provide a gate driving signal or a light emission control signal, but is not limited thereto.

[0083] In a specific implementation, when the display device is driven at a low frequency, the driving cycle may include a driving period and a holding period. During the driving period, the multi-stage driving circuits included in the shift register sequentially output driving signals; during the holding period, the multi-stage driving circuits included in the shift register unit all output a first voltage signal.

[0084] In at least one embodiment of the present invention, when the driving circuit is used to provide a gate driving signal, when the transistor whose control electrode in the pixel circuit of the display device is connected to the gate driving signal is an n-type transistor, the first voltage signal can be a low voltage signal; when the transistor whose gate electrode in the pixel circuit of the display device is connected to the gate driving signal is a p-type transistor, the first voltage signal can be a high voltage signal.

[0085] When the driving circuit is used to provide a light emission control signal, when the transistor whose control electrode in the pixel circuit of the display device is connected to the light emission control signal is an n-type transistor, the first voltage signal can be a low voltage signal; when the transistor whose control electrode in the pixel circuit of the display device is connected to the light emission control signal is a p-type transistor, the first voltage signal can be a high voltage signal.

[0086] In at least one embodiment of the present invention, the first voltage signal is illustrated as a low voltage signal.

[0087] When performing low-frequency driving (e.g., when lighting at 1Hz), the duration of the driving cycle can be 60 frames, the duration of the driving period can be 1 frame, the duration of the hold period can be 59 frames, and the hold period can be a Vertical Blank period.

[0088] like Figure 2 As shown, in one case, during the corresponding output time period in the driving period S1, the potential of the driving signal output by O1 is high voltage, and K1 provides the first clock signal; during the holding period S2, O1 outputs a low voltage signal, and K1 continuously provides a low voltage signal, which can save power consumption.

[0089] like Figure 3As shown, in another case, during the corresponding output time period in the driving period S1, the potential of the driving signal output by O1 is high voltage, and K1 provides a first clock signal; the holding period S2 includes a first holding time period S21 and a second holding time period S22; during the first holding time period S21, K1 provides the first clock signal, and during the second holding time period S22, K1 continuously provides a low voltage signal to save power consumption.

[0090] In related technologies, during the holding period S2, when K1 provides a low voltage signal, the first output transistor in the first output circuit 13 and the second output transistor in the second output circuit 14 are under voltage stress for a long time, which causes characteristic drift of both the first and second output transistors. This results in the drive signal potential not being maintained at the first voltage, leading to abnormal drive of the drive circuit. Based on this, the drive circuit described in at least one embodiment of the present invention employs a first control circuit 11 and / or a second control circuit 12 to ensure the stability of the drive circuit when, during the holding period S2, K1 continuously provides a low voltage signal and the potential of the drive signal is not the first voltage signal, allowing the first control circuit 11 and / or the second control circuit 12 to control the restoration of the drive signal to the first voltage signal, thus ensuring the stability of the drive circuit operation.

[0091] Optionally, the first control circuit includes a first control transistor;

[0092] The control electrode of the first control transistor is electrically connected to the control terminal, the first electrode of the first control transistor is electrically connected to the first control voltage terminal, and the second electrode of the first control transistor is electrically connected to the first node.

[0093] Optionally, the second control circuit includes a second control transistor;

[0094] The control electrode of the second control transistor is electrically connected to the control terminal, the first electrode of the second control transistor is electrically connected to the second control voltage terminal, and the second electrode of the second control transistor is electrically connected to the second node.

[0095] Optionally, the first output circuit includes a first output transistor, and the second output circuit includes a second output transistor, wherein,

[0096] The control electrode of the first output transistor is electrically connected to the first node, the first electrode of the first output transistor is electrically connected to the first clock signal terminal, and the second electrode of the first output transistor is electrically connected to the output terminal.

[0097] The control electrode of the second output transistor is electrically connected to the second node, the first electrode of the second output transistor is electrically connected to the first voltage terminal, and the second electrode of the second output transistor is electrically connected to the output terminal.

[0098] like Figure 4 As shown, in Figure 1 Based on at least one embodiment of the driving circuit shown, the first control circuit 11 includes a first control transistor T01;

[0099] The gate of the first control transistor T01 is electrically connected to the control terminal R1, the source of the first control transistor T01 is electrically connected to the first control voltage terminal RG1, and the drain of the first control transistor T01 is electrically connected to the first node N1.

[0100] The second control circuit 12 includes a second control transistor T02;

[0101] The gate of the second control transistor T02 is electrically connected to the control terminal R1, the source of the second control transistor T02 is electrically connected to the second control voltage terminal RG2, and the drain of the second control transistor T02 is electrically connected to the second node N2.

[0102] The first output circuit 13 includes a first output transistor T11, and the second output circuit includes a second output transistor T12, wherein,

[0103] The gate of the first output transistor T11 is electrically connected to the first node N1, the source of the first output transistor T11 is electrically connected to the first clock signal terminal K1, and the drain of the first output transistor T11 is electrically connected to the output terminal O1.

[0104] The gate of the second output transistor T12 is electrically connected to the second node N2, the source of the second output transistor T12 is electrically connected to the low voltage terminal V01, and the drain of the second output transistor T12 is electrically connected to the output terminal O1.

[0105] exist Figure 4 In at least one embodiment of the driving circuit shown, the first voltage terminal may be a low voltage terminal V01, and each transistor may be a p-type thin-film transistor, but this is not a limitation.

[0106] The present invention is as follows Figure 4 At least one embodiment of the driving circuit shown, when in operation, such as Figure 5 As shown, the driving cycle includes a driving period S1 and a holding period S2 set sequentially.

[0107] During the driving period S1, R1 provides a high voltage signal, RG1 and RG2 provide low voltage signals, T01 and T02 are both turned off, N1 is disconnected from RG1, and N2 is disconnected from RG2.

[0108] During the driving period S1, K1 provides the first clock signal, and during the holding period S2, K1 continuously provides a low voltage signal.

[0109] During the holding period S2, R1 provides a low voltage signal, RG1 and RG2 provide low voltage signals, T01 and T02 are both turned on, N1 is connected to RG1, and N2 is connected to RG2 to ensure that the potentials of N1 and N2 are both low voltages. This ensures that during the holding period S2, the first output transistor included in the first output circuit 13 and the second output transistor included in the second output circuit 14 are both turned on to prevent abnormal driving.

[0110] In at least one embodiment of the present invention, when K1 continuously provides a low voltage signal during the holding period S2, both the first output transistor and the second output transistor can be turned on during the holding period S2, so that O1 outputs a low voltage signal.

[0111] The present invention is as follows Figure 4 At least one embodiment of the driving circuit shown, when in operation, such as Figure 6 As shown, the driving cycle includes a driving period S1 and a holding period S2 set sequentially; the holding period S2 includes a first time period S31 and a second time period S32 set sequentially.

[0112] During the driving period S1, R1 provides a high voltage signal, RG1 and RG2 provide low voltage signals, T01 and T02 are both turned off, N1 is disconnected from RG1, and N2 is disconnected from RG2.

[0113] During the holding period S2, R1 provides a low voltage signal, T01 and T02 are both turned on, N1 is connected to RG1, and N2 is connected to RG2;

[0114] During the driving period S1, K1 provides the first clock signal, and during the holding period S2, K1 continuously provides a low voltage signal.

[0115] During the first time period S31, RG1 provides a high voltage signal, RG2 provides a low voltage signal, N1 has a high voltage potential, and N2 has a low voltage potential, so that the first output transistor included in the first output circuit 13 is turned off, and the second output transistor included in the second output circuit 14 is turned on, to prevent abnormal driving.

[0116] During the second time period S32, RG1 provides a low voltage signal, RG2 provides a high voltage signal, N1 has a low voltage potential, and N2 has a high voltage potential, so that the first output transistor included in the first output circuit 13 is turned on, and the second output transistor included in the second output circuit 14 is turned off to prevent abnormal driving.

[0117] The present invention is as follows Figure 4 In at least one embodiment of the driving circuit shown, when K1 continuously provides a low voltage signal during the holding period S2, the first output transistor or the second output transistor can be turned on at any point in the holding period S2 to achieve the purpose of O1 continuously outputting a low voltage signal.

[0118] The present invention is as follows Figure 4 At least one embodiment of the driving circuit shown, when in operation, such as Figure 7 As shown, the driving cycle includes a driving period S1 and a holding period S2 set sequentially; the holding period S2 includes a first time period S31 and a second time period S32 set sequentially.

[0119] During the driving period S1, R1 provides a high voltage signal, RG1 and RG2 provide low voltage signals, T01 and T02 are both turned off, N1 is disconnected from RG1, and N2 is disconnected from RG2.

[0120] During the holding period S2, R1 provides a low voltage signal, T01 and T02 are both turned on, N1 is connected to RG1, and N2 is connected to RG2;

[0121] During the hold period S2, K1 continuously provides a low voltage signal;

[0122] During the first time period S31, RG1 provides a low voltage signal, RG2 provides a high voltage signal, N1 has a low voltage potential, and N2 has a high voltage potential, so that the first output transistor included in the first output circuit 13 is turned on, and the second output transistor included in the second output circuit 14 is turned off to prevent abnormal driving.

[0123] During the second time period S32, RG1 provides a high voltage signal, RG2 provides a low voltage signal, N1 has a high voltage potential, and N2 has a low voltage potential, so that the first output transistor included in the first output circuit 13 is turned off, and the second output transistor included in the second output circuit 14 is turned on, preventing abnormal driving.

[0124] The present invention is as follows Figure 4 At least one embodiment of the driving circuit shown, when in operation, such as Figure 8As shown, the driving cycle includes a driving period S1 and a holding period S2 set sequentially; the holding period S2 includes a first holding phase and a second holding phase set sequentially, the first holding phase includes a first third period S41 and a first fourth period S42 set sequentially; the second holding phase includes a second third period S51 and a second fourth period S52 set sequentially.

[0125] During the driving period S1, R1 provides a high voltage signal, RG1 and RG2 provide low voltage signals, T01 and T02 are both turned off, N1 is disconnected from RG1, and N2 is disconnected from RG2.

[0126] During the holding period S2, R1 provides a low voltage signal, T01 and T02 are both turned on, N1 is connected to RG1, and N2 is connected to RG2;

[0127] During the driving period S1, K1 provides the first clock signal, and during the holding period S2, K1 continuously provides a low voltage signal.

[0128] During the first third time period S41 and the second third time period S51, RG1 provides a high voltage signal, RG2 provides a low voltage signal, N1 has a high voltage potential, and N2 has a low voltage potential, so that the first output transistor included in the first output circuit 13 is turned off, and the second output transistor included in the second output circuit 14 is turned on, to prevent abnormal driving.

[0129] During the first fourth time period S42 and the second fourth time period S52, RG1 provides a low voltage signal, RG2 provides a high voltage signal, N1 has a low voltage potential, and N2 has a high voltage potential, so that the first output transistor included in the first output circuit 13 is turned on, and the second output transistor included in the second output circuit 14 is turned off to prevent abnormal driving.

[0130] The present invention is as follows Figure 4 At least one embodiment of the driving circuit shown, when in operation, such as Figure 9 As shown, the driving cycle includes a driving period S1 and a holding period S2 set sequentially; the holding period S2 includes a first holding phase and a second holding phase set sequentially, the first holding phase includes a first third period S31 and a first fourth period S32 set sequentially; the second holding phase includes a second third period S41 and a second fourth period S42 set sequentially.

[0131] During the driving period S1, R1 provides a high voltage signal, RG1 and RG2 provide low voltage signals, T01 and T02 are both turned off, N1 is disconnected from RG1, and N2 is disconnected from RG2.

[0132] During the holding period S2, R1 provides a low voltage signal, T01 and T02 are both turned on, N1 is connected to RG1, and N2 is connected to RG2;

[0133] During the driving period S1, K1 provides the first clock signal, and during the holding period S2, K1 continuously provides a low voltage signal.

[0134] During the first third time period S41 and the second third time period S51, RG1 provides a low voltage signal, RG2 provides a high voltage signal, N1 has a low voltage potential, and N2 has a high voltage potential, so that the first output transistor included in the first output circuit 13 is turned on, and the second output transistor included in the second output circuit 14 is turned off to prevent abnormal driving.

[0135] During the first fourth time period S42 and the second fourth time period S52, RG1 provides a high voltage signal, RG2 provides a low voltage signal, N1 has a high voltage potential, and N2 has a low voltage potential, so that the first output transistor included in the first output circuit 13 is turned off, and the second output transistor included in the second output circuit 14 is turned on, preventing abnormal driving.

[0136] Optionally, the number of holding phases included in the holding period S2 is not limited to two, but can be at least two.

[0137] The present invention is as follows Figure 4 At least one embodiment of the driving circuit shown, when in operation, such as Figure 10 As shown, the driving cycle includes a driving period S1 and a holding period S2 set sequentially; the holding period S2 includes a first holding period S21 and a second holding period S22 set sequentially.

[0138] During the driving period S1, K1 provides a first clock signal, R1 provides a high voltage signal, RG1 and RG2 provide low voltage signals, T01 and T02 are both turned off, N1 is disconnected from RG1, and N2 is disconnected from RG2.

[0139] During the first holding period S21, R1 provides a high voltage signal, RG1 and RG2 provide low voltage signals, T01 and T02 are both turned off, N1 is disconnected from RG1, and N2 is disconnected from RG2;

[0140] During the driving period S1 and the first holding period S21, K1 provides a first clock signal;

[0141] During the second holding period S22, K1 provides a low voltage signal;

[0142] During the second holding period S22, R1 provides a low voltage signal, RG1 and RG2 provide low voltage signals, T01 and T02 are both turned on, N1 is connected to RG1, and N2 is connected to RG2, so as to ensure that the potentials of N1 and N2 are both low voltage, so that during the holding period S2, the first output transistor included in the first output circuit 13 and the second output transistor included in the second output circuit 14 are both turned on to prevent abnormal driving.

[0143] The present invention is as follows Figure 4 In at least one embodiment of the driving circuit shown, when K1 provides a first clock signal during a first holding period S21 and K1 continuously provides a low voltage signal during a second holding period S22, both the first output transistor and the second output transistor can be turned on during the second holding period S22, so that O1 continuously outputs a low voltage signal.

[0144] The present invention is as follows Figure 4 At least one embodiment of the driving circuit shown, when in operation, such as Figure 11 As shown, the driving cycle includes a driving period S1 and a holding period S2 set sequentially; the holding period S2 includes a first holding period S21 and a second holding period S22 set sequentially; the second holding period S22 includes a first period S31 and a second period S32 set sequentially.

[0145] During the driving period S1, K1 provides a first clock signal, R1 provides a high voltage signal, RG1 and RG2 provide low voltage signals, T01 and T02 are both turned off, N1 is disconnected from RG1, and N2 is disconnected from RG2.

[0146] During the first holding period S21, R1 provides a high voltage signal, RG1 and RG2 provide low voltage signals, T01 and T02 are both turned off, N1 is disconnected from RG1, and N2 is disconnected from RG2;

[0147] During the driving period S1 and the first holding period S21, K1 provides a first clock signal;

[0148] During the second holding period S22, K1 provides a low voltage signal;

[0149] During the first time period S31, RG1 provides a high voltage signal, RG2 provides a low voltage signal, N1 has a high voltage potential, and N2 has a low voltage potential, so that the first output transistor included in the first output circuit 13 is turned off, and the second output transistor included in the second output circuit 14 is turned on, to prevent abnormal driving.

[0150] During the second time period S32, RG1 provides a low voltage signal, RG2 provides a high voltage signal, N1 has a low voltage potential, and N2 has a high voltage potential, so that the first output transistor included in the first output circuit 13 is turned on, and the second output transistor included in the second output circuit 14 is turned off to prevent abnormal driving.

[0151] The present invention is as follows Figure 4 In at least one embodiment of the driving circuit shown, when K1 provides a first clock signal during a first holding period S21 and continuously provides a low voltage signal during a second holding period S22, the first output transistor or the second output transistor can be turned on at any point in the second holding period S22 to achieve the purpose of continuously outputting a low voltage signal by O1.

[0152] In specific implementation, it can also be controlled that in the first time period S31, RG1 provides a low voltage signal and RG2 provides a high voltage signal, and in the second time period S32, RG1 provides a high voltage signal and RG2 provides a low voltage signal.

[0153] The present invention is as follows Figure 4 At least one embodiment of the driving circuit shown, when in operation, such as Figure 12 As shown, the driving cycle includes a driving period S1 and a holding period S2 set sequentially; the holding period S2 includes a first holding period S21 and a second holding period S22 set sequentially; the second holding period S22 includes a first holding phase and a second holding phase set sequentially, the first holding phase includes a first third period S31 and a first fourth period S32 set sequentially; the second holding phase includes a second third period S41 and a second fourth period S42 set sequentially.

[0154] During the driving period S1, K1 provides a first clock signal, R1 provides a high voltage signal, RG1 and RG2 provide low voltage signals, T01 and T02 are both turned off, N1 is disconnected from RG1, and N2 is disconnected from RG2.

[0155] During the first holding period S21, R1 provides a high voltage signal, RG1 and RG2 provide low voltage signals, T01 and T02 are both turned off, N1 is disconnected from RG1, and N2 is disconnected from RG2;

[0156] During the driving period S1 and the first holding period S21, K1 provides a first clock signal;

[0157] During the second holding period S22, K1 provides a low voltage signal;

[0158] During the first third time period S41 and the second third time period S51, RG1 provides a high voltage signal, RG2 provides a low voltage signal, N1 has a high voltage potential, and N2 has a low voltage potential, so that the first output transistor included in the first output circuit 13 is turned off, and the second output transistor included in the second output circuit 14 is turned on, to prevent abnormal driving.

[0159] During the first fourth time period S42 and the second fourth time period S52, RG1 provides a low voltage signal, RG2 provides a high voltage signal, N1 has a low voltage potential, and N2 has a high voltage potential, so that the first output transistor included in the first output circuit 13 is turned on, and the second output transistor included in the second output circuit 14 is turned off to prevent abnormal driving.

[0160] In practice, during each third time period, RG1 can be controlled to provide a low voltage signal and RG2 to provide a high voltage signal, and during each fourth time period, RG1 can be controlled to provide a high voltage signal and RG2 to provide a low voltage signal.

[0161] Optionally, the number of holding phases included in the second holding time period S22 is not limited to two, but can be at least two.

[0162] In specific implementations, the driving circuit described in at least one embodiment of the present invention further includes a third node control circuit, a second node control circuit, a fourth node control circuit, a sixth node control circuit, and a first node control circuit, wherein,

[0163] The third node control circuit is electrically connected to the first clock signal terminal, the second clock signal terminal, the input terminal, and the third node, respectively, and is used to control the connection or disconnection between the third node and the input terminal under the control of the first clock signal provided by the first clock signal terminal and the second clock signal provided by the second clock signal terminal.

[0164] The second node control circuit is electrically connected to the second node, the second voltage terminal, the fourth node, the third clock signal terminal, and the control node, respectively. It is used to control the connection or disconnection between the control node and the second voltage terminal under the control of the potential of the fourth node, control the connection or disconnection between the control node and the third clock signal terminal under the control of the potential of the second node, and control the potential of the second node according to the potential of the control node.

[0165] The fourth node control circuit is electrically connected to the first voltage terminal, the second clock signal terminal, the fourth node, and the third node, respectively. It is used to control the connection or disconnection between the fourth node and the first voltage terminal under the control of the second clock signal, and to control the connection or disconnection between the fourth node and the second clock signal terminal under the control of the potential of the third node.

[0166] The sixth node control circuit is electrically connected to the fifth node, the third clock signal terminal and the sixth node respectively, and is used to control the connection or disconnection between the sixth node and the third clock signal terminal under the control of the potential of the fifth node, and to control the potential of the sixth node according to the potential of the fifth node.

[0167] The first node control circuit is electrically connected to the sixth node, the third clock signal terminal, the first node, the second node, and the first clock signal terminal, respectively. It is used to control the connection or disconnection between the sixth node and the first node under the control of the third clock signal provided by the third clock signal terminal, control the connection or disconnection between the first node and the first clock signal terminal under the control of the potential of the second node, and control the potential of the first node according to the first clock signal.

[0168] Optionally, the second voltage terminal can be a high voltage terminal, but is not limited thereto.

[0169] In at least one embodiment of the present invention, the third node and the second node can be the same node; or,

[0170] The driving circuit further includes a first on / off control circuit, which is electrically connected to the third node, the second node and the first voltage terminal respectively. The first on / off control circuit is used to control the connection between the third node and the second node under the control of the first voltage signal provided by the first voltage terminal.

[0171] In at least one embodiment of the present invention, the fourth node and the fifth node may be the same node; or,

[0172] The driving circuit further includes a second on / off control circuit, which is electrically connected to the fourth node, the fifth node and the first voltage terminal respectively. The second on / off control circuit is used to control the connection between the fourth node and the fifth node under the control of the first voltage signal provided by the first voltage terminal.

[0173] In at least one embodiment of the present invention, the first on / off control circuit may include a normally open transistor, and the second on / off control circuit may also include a normally open transistor. The normally open transistor included in the first on / off control circuit can prevent the potential change of the second node from being too large by voltage division, and the normally open transistor included in the second on / off control circuit can prevent the potential change of the fifth node from being too large by voltage division.

[0174] like Figure 13 As shown, in Figure 4Based on at least one embodiment of the driving circuit shown, at least one embodiment of the driving circuit of the present invention further includes a third node control circuit 51, a second node control circuit 52, a fourth node control circuit 53, a sixth node control circuit 54, a first node control circuit 55, a first on / off control circuit 56, and a second on / off control circuit 57, wherein,

[0175] The third node control circuit 51 is electrically connected to the first clock signal terminal K1, the second clock signal terminal K2, the input terminal I1 and the third node N3 respectively, and is used to control the connection or disconnection between the third node N3 and the input terminal I1 under the control of the first clock signal provided by the first clock signal terminal K1 and the second clock signal provided by the second clock signal terminal K2.

[0176] The second node control circuit 52 is electrically connected to the second node N2, the second voltage terminal V2, the fourth node N4, the third clock signal terminal K3, and the control node N0, respectively. It is used to control the connection or disconnection between the control node N0 and the second voltage terminal V2 under the control of the potential of the fourth node N4, control the connection or disconnection between the control node N0 and the third clock signal terminal K3 under the control of the potential of the second node N2, and control the potential of the second node N2 according to the potential of the control node N0.

[0177] The fourth node control circuit 53 is electrically connected to the first voltage terminal V1, the second clock signal terminal K2, the fourth node N4 and the third node N3 respectively. It is used to control the connection or disconnection between the fourth node N4 and the first voltage terminal V1 under the control of the second clock signal provided by K2, and to control the connection or disconnection between the fourth node N4 and the second clock signal terminal K2 under the control of the potential of the third node N3.

[0178] The sixth node control circuit 54 is electrically connected to the fifth node N5, the third clock signal terminal K3 and the sixth node N6 respectively. It is used to control the connection or disconnection between the sixth node N6 and the third clock signal terminal K3 under the control of the potential of the fifth node N5, and to control the potential of the sixth node N6 according to the potential of the fifth node N5.

[0179] The first node control circuit 55 is electrically connected to the sixth node N6, the third clock signal terminal K3, the first node N1, the second node N2, and the first clock signal terminal K1, respectively. It is used to control the connection or disconnection between the sixth node N6 and the first node N1 under the control of the third clock signal provided by the third clock signal terminal K3, to control the connection or disconnection between the first node N1 and the first clock signal terminal K1 under the control of the potential of the second node N2, and to control the potential of the first node N1 according to the first clock signal provided by K1.

[0180] The first on / off control circuit 56 is electrically connected to the third node N3, the second node N2 and the first voltage terminal V1 respectively. The first on / off control circuit 56 is used to control the connection or disconnection between the third node N3 and the second node N2 under the control of the first voltage signal provided by the first voltage terminal V1.

[0181] The second on / off control circuit 57 is electrically connected to the fourth node N4, the fifth node N5 and the first voltage terminal V1 respectively. The second on / off control circuit 57 is used to control the connection or disconnection between the fourth node N4 and the fifth node N5 under the control of the first voltage signal provided by the first voltage terminal V1.

[0182] The present invention is as follows Figure 13 In at least one embodiment of the driving circuit shown, during operation, the third node control circuit 51 controls the potential of the third node N3 under the control of the first clock signal and the second clock signal; the second node control circuit 52 controls the potential of the second node N2 according to the third clock signal under the control of the potential of the fourth node N4 and the potential of the second node N2; the fourth node control circuit 53 controls the potential of the fourth node N4 according to the second clock signal under the control of the second clock signal and the potential of the third node N3; the sixth node control circuit 54 controls the potential of the sixth node N6 according to the third clock signal under the control of the potential of the fifth node N5; the first node control circuit 55 controls the potential of the first node N1 according to the potential of the sixth node N6 and the first clock signal under the control of the third clock signal, the potential of the second node N2, and the potential of the sixth node N6; the first on / off control circuit 56 controls the connection or disconnection between the third node N3 and the second node N2 under the control of the first voltage signal; and the second on / off control circuit 57 controls the connection or disconnection between the fourth node N4 and the fifth node N5 under the control of the first voltage signal.

[0183] Optionally, the first node control circuit includes a first transistor, a second transistor, and a first capacitor;

[0184] The control electrode of the first transistor is electrically connected to the third clock signal terminal, the first electrode of the first transistor is electrically connected to the sixth node, and the second electrode of the first transistor is electrically connected to the first node.

[0185] The control electrode of the second transistor is electrically connected to the second node, the first electrode of the second transistor is electrically connected to the first clock signal terminal, and the second electrode of the second transistor is electrically connected to the first node.

[0186] The first terminal of the first capacitor is electrically connected to the first node, and the second terminal of the first capacitor is electrically connected to the first clock signal terminal.

[0187] The second node control circuit includes a third transistor, a fourth transistor, and a second capacitor, wherein,

[0188] The control electrode of the third transistor is electrically connected to the second node, the first electrode of the third transistor is electrically connected to the third clock signal terminal, and the second electrode of the third transistor is electrically connected to the control node.

[0189] The control electrode of the fourth transistor is electrically connected to the fourth node, the first electrode of the fourth transistor is electrically connected to the second voltage terminal, and the second electrode of the fourth transistor is electrically connected to the control node.

[0190] The first end of the second capacitor is electrically connected to the second node, and the second end of the second capacitor is electrically connected to the control node.

[0191] Optionally, the third node control circuit includes a fifth transistor and a sixth transistor, the fourth node control circuit includes a seventh transistor and an eighth transistor, and the sixth node control circuit includes a ninth transistor and a third capacitor, wherein...

[0192] The control electrode of the fifth transistor is electrically connected to the first clock signal terminal, and the first electrode of the fifth transistor is electrically connected to the input terminal.

[0193] The control electrode of the sixth transistor is electrically connected to the second clock signal terminal, the first electrode of the sixth transistor is electrically connected to the second electrode of the fifth transistor, and the second electrode of the sixth transistor is electrically connected to the third node;

[0194] The control electrode of the seventh transistor is electrically connected to the second clock signal terminal, the first electrode of the seventh transistor is electrically connected to the first voltage terminal, and the second electrode of the seventh transistor is electrically connected to the fourth node.

[0195] The control electrode of the eighth transistor is electrically connected to the third node, the first electrode of the eighth transistor is electrically connected to the second clock signal terminal, and the second electrode of the eighth transistor is electrically connected to the fourth node.

[0196] The control electrode of the ninth transistor is electrically connected to the fifth node, the first electrode of the ninth transistor is electrically connected to the third clock signal terminal, and the second electrode of the ninth transistor is electrically connected to the sixth node.

[0197] The first terminal of the third capacitor is electrically connected to the fifth node, and the second terminal of the third capacitor is electrically connected to the sixth node.

[0198] like Figure 14 As shown, in Figure 13 Based on at least one embodiment of the driving circuit shown, the first node control circuit includes a first transistor T1, a second transistor T2, and a first capacitor C1;

[0199] The gate of the first transistor T1 is electrically connected to the third clock signal terminal K3, the source of the first transistor T1 is electrically connected to the sixth node N6, and the drain of the first transistor T1 is electrically connected to the first node N1.

[0200] The gate of the second transistor T2 is electrically connected to the second node N2, the source of the second transistor T2 is electrically connected to the first clock signal terminal K1, and the drain of the second transistor T2 is electrically connected to the first node N1.

[0201] The first terminal of the first capacitor C1 is electrically connected to the first node N1, and the second terminal of the first capacitor C1 is electrically connected to the first clock signal terminal K1.

[0202] The second node control circuit includes a third transistor T3, a fourth transistor T4, and a second capacitor C2, wherein,

[0203] The gate of the third transistor T3 is electrically connected to the second node N2, the source of the third transistor T3 is electrically connected to the third clock signal terminal K3, and the drain of the third transistor T3 is electrically connected to the control node N0.

[0204] The gate of the fourth transistor T4 is electrically connected to the fourth node N4, the source of the fourth transistor T4 is electrically connected to the high voltage terminal V02, and the drain of the fourth transistor T4 is electrically connected to the control node N0.

[0205] The first terminal of the second capacitor C2 is electrically connected to the second node N2, and the second terminal of the second capacitor C2 is electrically connected to the control node N0.

[0206] The third node control circuit includes a fifth transistor T5 and a sixth transistor T6; the fourth node control circuit includes a seventh transistor T7 and an eighth transistor T8; and the sixth node control circuit includes a ninth transistor T9 and a third capacitor C3.

[0207] The gate of the fifth transistor T5 is electrically connected to the first clock signal terminal K1, and the source of the fifth transistor T5 is electrically connected to the input terminal I1.

[0208] The gate of the sixth transistor T6 is electrically connected to the second clock signal terminal K2, the source of the sixth transistor is electrically connected to the drain of the fifth transistor T5, and the drain of the sixth transistor T6 is electrically connected to the third node N3.

[0209] The gate of the seventh transistor T7 is electrically connected to the second clock signal terminal K2, the source of the seventh transistor T7 is electrically connected to the low voltage terminal V01, and the drain of the seventh transistor T7 is electrically connected to the fourth node N4.

[0210] The gate of the eighth transistor T8 is electrically connected to the third node N3, the source of the eighth transistor T8 is electrically connected to the second clock signal terminal K2, and the drain of the eighth transistor T8 is electrically connected to the fourth node N4.

[0211] The gate of the ninth transistor T9 is electrically connected to the fifth node N5, the source of the ninth transistor T9 is electrically connected to the third clock signal terminal K3, and the drain of the ninth transistor T9 is electrically connected to the sixth node N6.

[0212] The first terminal of the third capacitor C3 is electrically connected to the fifth node N5, and the second terminal of the third capacitor C3 is electrically connected to the sixth node N6;

[0213] The first on / off control circuit includes a tenth transistor T10, and the second on / off control circuit includes an eleventh transistor T11;

[0214] The gate of the tenth transistor T10 is electrically connected to the low voltage terminal V01, the source of the tenth transistor T10 is electrically connected to the third node N3, and the drain of the tenth transistor T10 is electrically connected to the second node N2.

[0215] The gate of the eleventh transistor T11 is electrically connected to the low voltage terminal V01, the source of the eleventh transistor T11 is electrically connected to the fourth node N4, and the drain of the eleventh transistor T11 is electrically connected to the fifth node N5.

[0216] exist Figure 14In at least one embodiment of the driving circuit shown, all transistors are p-type thin-film transistors, but this is not a limitation.

[0217] In the present invention as Figure 14 In at least one embodiment of the driving circuit shown, the first voltage terminal is a low voltage terminal V01, and the second voltage terminal is a high voltage terminal V02.

[0218] like Figure 15 As shown, the present invention is as follows Figure 14 When at least one embodiment of the driving circuit shown is in operation, the operating period of the driving circuit may include a first stage t1, a second stage t2, a third stage t3, and a fourth stage t4.

[0219] In the first stage t1, I1 provides a low voltage signal, K1 provides a low voltage for the first clock signal, K2 provides a low voltage for the second clock signal, K3 provides a high voltage for the third clock signal, T7 is on, T5 and T6 are on, N3 is at a low voltage, T8 is on, N4 is at a low voltage, T4 is on, N0 is at a high voltage, N2 is at a low voltage, T3 is on, N5 is at a low voltage, T9 is on, N6 is at a high voltage, T1 is off, T2 is on, N1 is at a low voltage, T11 and T12 are both on, and O1 outputs a low voltage signal.

[0220] In the second stage t2, I1 provides a low voltage signal, K1 provides a high voltage first clock signal, K2 provides a high voltage second clock signal, and K3 provides a high voltage third clock signal.

[0221] In the second stage t2, when the potential of the third clock signal is low, T6 is turned off, the potential of N3 remains low, T7 is turned off, T8 is turned on, the potential of N4 is high, the potential of N5 is high, T4 is turned off, the potential of N2 is low, T2 is turned on, the potential of N1 is high, T11 is turned off, T12 is turned on, and O1 outputs a low voltage signal.

[0222] In the third stage t3, I1 provides a high voltage signal, K1 provides a low voltage for the first clock signal, K2 provides a low voltage for the second clock signal, K3 provides a high voltage for the second clock signal, T7 is on, N4 is at a low voltage, N5 is at a low voltage, T5 and T6 are both on, N3 is at a high voltage, N2 is at a high voltage, T8 is off, T4 is on, T3 is off, T9 is on, N6 is at a high voltage, T1 is off, T11 and T12 are both off, and O1 maintains a low voltage output signal.

[0223] In the fourth stage t4, I1 provides a low voltage signal, K1 provides a high voltage first clock signal, K2 provides a high voltage second clock signal, and K3 provides a high voltage third clock signal.

[0224] In the fourth stage t4, when the potential of the third clock signal is low, T6 is turned off, the potential of N3 remains high, the potential of N2 is high, T2 is turned off, T8 is turned off, T7 is turned off, the potential of N4 remains low, the potential of N5 is low, T9 is turned on, the potential of N6 changes from low to high, T1 is turned on, and the potential of N1 becomes -3V (in the fourth stage t4, both T1 and T9 are turned on. Due to the threshold voltage loss when the p-type thin film transistor transmits a low potential, the potential of N1 becomes -3V). At this time, the potential of the first clock signal is 7V, T11 is turned on, T12 is turned off, and O1 outputs a high voltage signal.

[0225] The present invention is as follows Figure 14 At least one embodiment of the driving circuit shown, when in operation,

[0226] In the second stage t2, when the potential of the third clock signal is high, T1 is turned off, the potential of N1 remains high, T11 continues to be turned off, the potential of N2 is low, and T12 continues to be turned on.

[0227] In the fourth stage, when the potential of the third clock signal is high, T1 is turned off, the potential of N1 remains negative, T11 continues to be turned on, the potential of N2 is high, and T12 continues to be turned off.

[0228] The present invention is as follows Figure 14 In at least one embodiment of the driving circuit shown, when in operation, T11 can be normally open to prevent the potential of N2 from changing too much by voltage division, and T12 can be normally open to prevent the potential of N5 from changing too much by voltage division.

[0229] The driving method described in this embodiment of the invention is applied to the aforementioned driving circuit, and the driving cycle includes a driving period and a holding period; the driving method includes:

[0230] During the driving period, the first clock signal terminal provides a first clock signal, and the driving circuit outputs a driving signal through the first output circuit and the second output circuit; under the control of the control signal provided by the control terminal, the first control circuit disconnects the connection between the first node and the first control voltage terminal, and under the control of the control signal, the second control circuit disconnects the connection between the second node and the second control voltage terminal.

[0231] During at least a portion of the holding period, the first clock signal terminal provides a first voltage signal;

[0232] During at least a portion of the time period, the first control circuit, under the control of the control signal provided by the control terminal, connects the first node to the first control voltage terminal, and the second control circuit, under the control of the control signal, connects the second node to the second control voltage terminal.

[0233] The driving method described in at least one embodiment of the present invention employs a first control circuit and / or a second control circuit so that, during the holding period, when the first clock signal terminal continuously provides a first voltage signal, if the potential of the driving signal is not the first voltage signal, the first control circuit and / or the second control circuit can control the driving signal to be restored to the first voltage signal, thereby ensuring the stability of the driving circuit operation.

[0234] Optionally, the driving method described in at least one embodiment of the present invention further includes:

[0235] During at least a portion of the time period, both the first control voltage terminal and the second control voltage terminal provide effective voltage signals, such that the first output transistor included in the first output circuit and the second output transistor included in the second output circuit are both turned on, thereby causing the driving circuit to output a first voltage signal through its output terminal.

[0236] In at least one embodiment of the present invention, when the first output transistor and the second output transistor are n-type transistors, the effective voltage signal is a high voltage signal and the invalid voltage signal is a low voltage signal; when the first output transistor and the second output transistor are p-type transistors, the effective voltage signal is a low voltage signal and the invalid voltage signal is a high voltage signal.

[0237] In at least one embodiment of the present invention, the at least partial time period includes a first time period and a second time period set sequentially, and the driving method further includes:

[0238] During the first time period, a valid voltage signal is provided at the first control voltage terminal, and an invalid voltage signal is provided at the second control voltage terminal; during the second time period, an invalid voltage signal is provided at the first control voltage terminal, and a valid voltage signal is provided at the second control voltage terminal, such that the first output transistor is turned off and the second output transistor is turned on; or...

[0239] During the first time period, the first control voltage terminal provides an invalid voltage signal, and the second control voltage terminal provides an valid voltage signal; during the second time period, the first control voltage terminal provides a valid voltage signal, and the second control voltage terminal provides an invalid voltage signal, so that the first output transistor is turned on and the second output transistor is turned off.

[0240] Optionally, the at least partial time period includes at least two hold phases set sequentially, each hold phase including a third time period and a fourth time period set sequentially; the driving method further includes:

[0241] In the third time period, the first control voltage terminal provides a valid voltage signal, and the second control voltage terminal provides an invalid voltage signal; in the fourth time period, the first control voltage terminal provides an invalid voltage signal, and the second control voltage terminal provides a valid voltage signal, so that the first output transistor is turned off and the second output transistor is turned on; or...

[0242] During the third time period, the first control voltage terminal provides an invalid voltage signal, and the second control voltage terminal provides an valid voltage signal; during the fourth time period, the first control voltage terminal provides a valid voltage signal, and the second control voltage terminal provides an invalid voltage signal, so that the first output transistor is turned on and the second output transistor is turned off.

[0243] In at least one embodiment of the present invention, the step of providing a first voltage signal at the first clock signal terminal during at least a portion of the holding period includes: providing a first voltage signal at the first clock signal terminal during a portion of the holding period;

[0244] The driving method further includes: during the time period other than the partial time period included in the holding period, the first control circuit disconnects the connection between the first node and the first control voltage terminal under the control of the control signal provided by the control terminal, and the second control circuit disconnects the connection between the second node and the second control voltage terminal under the control of the control signal.

[0245] The shift register described in this embodiment of the invention includes multiple stages of the aforementioned driving circuits.

[0246] In at least one embodiment of the present invention, the input terminal of the first-stage driving circuit in the shift register is connected to a start signal;

[0247] Except for the first-stage drive circuit, the input terminals of each stage of the drive circuit are electrically connected to the output terminals of the adjacent previous stage drive circuit.

[0248] In at least one embodiment of the shift register described in this invention, the clock signal input to the first clock signal terminal of the odd-numbered stage driving circuit may be different from the clock signal input to the first clock signal terminal of the even-numbered stage driving circuit. For example, when the waveform of the clock signal input to the first clock signal terminal of the even-numbered stage driving circuit is as follows... Figure 15 When the waveform corresponding to K1 is displayed, the clock signal input to the first clock signal terminal of the odd-numbered stage drive circuit can be as follows: Figure 15 The waveform corresponding to K4 (K4 is the fourth clock signal) is shown, but it is not limited to this.

[0249] The display device described in this embodiment of the invention includes the shift register described above.

[0250] The display device provided in this embodiment of the invention can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0251] The above description represents the preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A driving circuit, comprising a first control circuit, a second control circuit, a first output circuit, a second output circuit, and an output terminal; The first output circuit is electrically connected to the first node, the first clock signal terminal and the output terminal respectively, and is used to turn on or off the connection between the output terminal and the first clock signal terminal under the control of the potential of the first node. The second output circuit is electrically connected to the second node, the output terminal, and the first voltage terminal, respectively, and is used to turn on or off the connection between the output terminal and the first voltage terminal under the control of the potential of the second node; The first control circuit is electrically connected to the control terminal, the first node and the first control voltage terminal respectively, and is used to turn on or off the connection between the first node and the first control voltage terminal under the control of the control signal provided by the control terminal. The second control circuit is electrically connected to the control terminal, the second node, and the second control voltage terminal, respectively, and is used to turn on or off the connection between the second node and the second control voltage terminal under the control of the control signal. The driving circuit further includes a third node control circuit, a second node control circuit, a fourth node control circuit, a sixth node control circuit, and a first node control circuit, wherein, The third node control circuit is electrically connected to the first clock signal terminal, the second clock signal terminal, the input terminal, and the third node, respectively, and is used to control the connection or disconnection between the third node and the input terminal under the control of the first clock signal provided by the first clock signal terminal and the second clock signal provided by the second clock signal terminal. The second node control circuit is electrically connected to the second node, the second voltage terminal, the fourth node, the third clock signal terminal, and the control node, respectively. It is used to control the connection or disconnection between the control node and the second voltage terminal under the control of the potential of the fourth node, control the connection or disconnection between the control node and the third clock signal terminal under the control of the potential of the second node, and control the potential of the second node according to the potential of the control node. The fourth node control circuit is electrically connected to the first voltage terminal, the second clock signal terminal, the fourth node, and the third node, respectively. It is used to control the connection or disconnection between the fourth node and the first voltage terminal under the control of the second clock signal, and to control the connection or disconnection between the fourth node and the second clock signal terminal under the control of the potential of the third node. The sixth node control circuit is electrically connected to the fifth node, the third clock signal terminal and the sixth node respectively, and is used to control the connection or disconnection between the sixth node and the third clock signal terminal under the control of the potential of the fifth node, and to control the potential of the sixth node according to the potential of the fifth node. The first node control circuit is electrically connected to the sixth node, the third clock signal terminal, the first node, the second node, and the first clock signal terminal, respectively. It is used to control the connection or disconnection between the sixth node and the first node under the control of the third clock signal provided by the third clock signal terminal, control the connection or disconnection between the first node and the first clock signal terminal under the control of the potential of the second node, and control the potential of the first node according to the first clock signal.

2. The driving circuit as described in claim 1, wherein, The first control circuit includes a first control transistor; The control electrode of the first control transistor is electrically connected to the control terminal, the first electrode of the first control transistor is electrically connected to the first control voltage terminal, and the second electrode of the first control transistor is electrically connected to the first node.

3. The driving circuit as described in claim 1, wherein, The second control circuit includes a second control transistor; The control electrode of the second control transistor is electrically connected to the control terminal, the first electrode of the second control transistor is electrically connected to the second control voltage terminal, and the second electrode of the second control transistor is electrically connected to the second node.

4. The driving circuit according to any one of claims 1 to 3, wherein, The first output circuit includes a first output transistor, and the second output circuit includes a second output transistor, wherein, The control electrode of the first output transistor is electrically connected to the first node, the first electrode of the first output transistor is electrically connected to the first clock signal terminal, and the second electrode of the first output transistor is electrically connected to the output terminal. The control electrode of the second output transistor is electrically connected to the second node, the first electrode of the second output transistor is electrically connected to the first voltage terminal, and the second electrode of the second output transistor is electrically connected to the output terminal.

5. The driving circuit as described in claim 1, wherein, The third node and the second node are the same node; or... The driving circuit further includes a first on / off control circuit, which is electrically connected to the third node, the second node and the first voltage terminal respectively. The first on / off control circuit is used to control the connection between the third node and the second node under the control of the first voltage signal provided by the first voltage terminal.

6. The driving circuit as described in claim 1, wherein, The fourth node and the fifth node are the same node; or, The driving circuit further includes a second on / off control circuit, which is electrically connected to the fourth node, the fifth node and the first voltage terminal respectively. The second on / off control circuit is used to control the connection between the fourth node and the fifth node under the control of the first voltage signal provided by the first voltage terminal.

7. The driving circuit as described in claim 1, wherein, The first node control circuit includes a first transistor, a second transistor, and a first capacitor; The control electrode of the first transistor is electrically connected to the third clock signal terminal, the first electrode of the first transistor is electrically connected to the sixth node, and the second electrode of the first transistor is electrically connected to the first node. The control electrode of the second transistor is electrically connected to the second node, the first electrode of the second transistor is electrically connected to the first clock signal terminal, and the second electrode of the second transistor is electrically connected to the first node. The first terminal of the first capacitor is electrically connected to the first node, and the second terminal of the first capacitor is electrically connected to the first clock signal terminal. The second node control circuit includes a third transistor, a fourth transistor, and a second capacitor, wherein, The control electrode of the third transistor is electrically connected to the second node, the first electrode of the third transistor is electrically connected to the third clock signal terminal, and the second electrode of the third transistor is electrically connected to the control node. The control electrode of the fourth transistor is electrically connected to the fourth node, the first electrode of the fourth transistor is electrically connected to the second voltage terminal, and the second electrode of the fourth transistor is electrically connected to the control node. The first end of the second capacitor is electrically connected to the second node, and the second end of the second capacitor is electrically connected to the control node.

8. The driving circuit as described in claim 1, wherein, The third node control circuit includes a fifth transistor and a sixth transistor, the fourth node control circuit includes a seventh transistor and an eighth transistor, and the sixth node control circuit includes a ninth transistor and a third capacitor. The control electrode of the fifth transistor is electrically connected to the first clock signal terminal, and the first electrode of the fifth transistor is electrically connected to the input terminal. The control electrode of the sixth transistor is electrically connected to the second clock signal terminal, the first electrode of the sixth transistor is electrically connected to the second electrode of the fifth transistor, and the second electrode of the sixth transistor is electrically connected to the third node; The control electrode of the seventh transistor is electrically connected to the second clock signal terminal, the first electrode of the seventh transistor is electrically connected to the first voltage terminal, and the second electrode of the seventh transistor is electrically connected to the fourth node. The control electrode of the eighth transistor is electrically connected to the third node, the first electrode of the eighth transistor is electrically connected to the second clock signal terminal, and the second electrode of the eighth transistor is electrically connected to the fourth node. The control electrode of the ninth transistor is electrically connected to the fifth node, the first electrode of the ninth transistor is electrically connected to the third clock signal terminal, and the second electrode of the ninth transistor is electrically connected to the sixth node. The first terminal of the third capacitor is electrically connected to the fifth node, and the second terminal of the third capacitor is electrically connected to the sixth node.

9. A driving method applied to a driving circuit as described in any one of claims 1 to 8, wherein the driving cycle includes a driving period and a holding period; the driving method includes: During the driving period, the first clock signal terminal provides a first clock signal, and the driving circuit outputs a driving signal through the first output circuit and the second output circuit. Under the control of the control signal provided by the control terminal, the first control circuit disconnects the connection between the first node and the first control voltage terminal, and the second control circuit disconnects the connection between the second node and the second control voltage terminal under the control of the control signal. During at least a portion of the holding period, the first clock signal terminal provides a first voltage signal; During at least a portion of the time period, the first control circuit, under the control of the control signal provided by the control terminal, connects the first node to the first control voltage terminal, and the second control circuit, under the control of the control signal, connects the second node to the second control voltage terminal.

10. The driving method as described in claim 9, wherein, Also includes: During at least a portion of the time period, both the first control voltage terminal and the second control voltage terminal provide valid voltage signals.

11. The driving method as described in claim 9, wherein, The at least part of the time period includes a first time period and a second time period set sequentially, and the driving method further includes: During the first time period, the first control voltage terminal provides a valid voltage signal, and the second control voltage terminal provides an invalid voltage signal; during the second time period, the first control voltage terminal provides an invalid voltage signal, and the second control voltage terminal provides a valid voltage signal; or... During the first time period, the first control voltage terminal provides an invalid voltage signal, and the second control voltage terminal provides an valid voltage signal; during the second time period, the first control voltage terminal provides a valid voltage signal, and the second control voltage terminal provides an invalid voltage signal.

12. The driving method as described in claim 9, wherein, The at least partial time period includes at least two sequentially configured holding phases, each holding phase including a sequentially configured third time period and a fourth time period; the driving method further includes: In the third time period, the first control voltage terminal provides a valid voltage signal, and the second control voltage terminal provides an invalid voltage signal; in the fourth time period, the first control voltage terminal provides an invalid voltage signal, and the second control voltage terminal provides a valid voltage signal; or... During the third time period, the first control voltage terminal provides an invalid voltage signal, and the second control voltage terminal provides an valid voltage signal; during the fourth time period, the first control voltage terminal provides a valid voltage signal, and the second control voltage terminal provides an invalid voltage signal.

13. The driving method according to any one of claims 9 to 12, wherein, The step of providing a first voltage signal at the first clock signal terminal during at least a portion of the holding period includes: providing a first voltage signal at the first clock signal terminal during a portion of the holding period; The driving method further includes: during the time period other than the partial time period included in the holding period, the first control circuit disconnects the connection between the first node and the first control voltage terminal under the control of the control signal provided by the control terminal, and the second control circuit disconnects the connection between the second node and the second control voltage terminal under the control of the control signal.

14. A shift register comprising multiple stages of drive circuitry as described in any one of claims 1 to 8.

15. A display device comprising the shift register as claimed in claim 14.

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