Pixel circuit, pixel driving method and display device

Abstract

The application provides a pixel circuit, a pixel driving method and a display device. The pixel circuit comprises a first initialization circuit and a compensation circuit. The first initialization circuit controls a first initial voltage to be provided to a driving control node under the control of a first initial control signal. The compensation circuit controls a compensation node to be in communication with a first node under the control of a compensation control signal. At least one of the first initialization circuit and the compensation circuit comprises an oxide thin film transistor and a low-temperature polysilicon thin film transistor connected in series with each other.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a pixel circuit, a pixel driving method and a display device. BACKGROUND

[0002] The existing LTPS (low temperature polysilicon) display panel is applied to the display field requiring high switching speed by using the high mobility characteristic of LTPS; however, due to the transistor characteristic of LTPS TFT (thin film transistor), there is a leakage problem, and the display effect is not ideal in the low frequency display field. SUMMARY

[0003] The main purpose of the present application is to provide a pixel circuit, a pixel driving method and a display device, which can alleviate the problem that the existing pixel circuit will appear leakage, thereby affecting display.

[0004] In one aspect, the embodiment of the present application provides a pixel circuit, comprising a first initialization circuit and a compensation circuit;

[0005] The first initialization circuit is electrically connected with a driving control node, a first initialization control end and a first initialization voltage end respectively, and is used for controlling the first initialization voltage end to provide a first initialization voltage to the driving control node under the control of a first initialization control signal provided by the first initialization control end;

[0006] The compensation circuit is electrically connected with a compensation control end, a compensation node and a first node respectively, and is used for controlling the compensation node to be in communication with the first node under the control of a compensation control signal provided by the compensation control end;

[0007] At least one of the first initialization circuit and the compensation circuit comprises an oxide thin film transistor and a low temperature polysilicon thin film transistor connected in series with each other.

[0008] Optionally, the compensation node and the driving control node are the same node.

[0009] Optionally, the compensation node and the driving control node are different nodes.

[0010] The first initialization circuit is further electrically connected with a first voltage end; the first initialization circuit comprises a control sub-circuit and an initialization sub-circuit, wherein,

[0011] The control sub-circuit is electrically connected with the first voltage end, the driving control node and the compensation node respectively, and is used for controlling the driving control node to be in communication with the compensation node under the control of a first voltage signal provided by the first voltage end;

[0012] The initialization sub-circuit is electrically connected with the first initial control end, the first initial voltage end and the compensation node respectively, and is configured to control the first initial voltage to be written into the compensation node under control of the first initial control signal.

[0013] Optionally, the control sub-circuit comprises a first transistor, and the initialization sub-circuit comprises a second transistor.

[0014] The control electrode of the first transistor is electrically connected with the first voltage end, the first electrode of the first transistor is electrically connected with the compensation node, and the second electrode of the first transistor is electrically connected with the driving control node.

[0015] The control electrode of the second transistor is electrically connected with the first initial control end, the first electrode of the second transistor is electrically connected with the first initial voltage end, and the second electrode of the second transistor is electrically connected with the compensation node.

[0016] The first transistor is a low-temperature polysilicon thin film transistor, and the second transistor is an oxide thin film transistor.

[0017] The first voltage end is a first low-voltage end.

[0018] Optionally, the first initialization circuit is further electrically connected with a first voltage end; the first initialization circuit comprises a control sub-circuit and an initialization sub-circuit, and wherein,

[0019] The control sub-circuit is electrically connected with the first voltage end, the first initial voltage end and a second node respectively, and is configured to control the first initial voltage to be written into the second node under control of a first voltage signal provided by the first voltage end.

[0020] The initialization sub-circuit is electrically connected with the first initial control end, the second node and the driving control node respectively, and is configured to control the second node to be in communication with the driving control node under control of the first initial control signal.

[0021] Optionally, the control sub-circuit comprises a first transistor, and the initialization sub-circuit comprises a second transistor, and wherein,

[0022] The control electrode of the first transistor is electrically connected with the first voltage end, the first electrode of the first transistor is electrically connected with the first initial voltage end, and the second electrode of the first transistor is electrically connected with the second node.

[0023] The control electrode of the second transistor is electrically connected with the first initial control end, the first electrode of the second transistor is electrically connected with the second node, and the second electrode of the second transistor is electrically connected with the driving control node.

[0024] The first transistor is a low-temperature polysilicon thin film transistor, and the second transistor is an oxide thin film transistor.

[0025] The first voltage terminal is a first low voltage terminal.

[0026] Optionally, the first initialization circuit is further electrically connected with a first voltage terminal; the first initialization circuit comprises a control sub-circuit and an initialization sub-circuit, wherein,

[0027] The first initialization circuit is electrically connected with the first voltage terminal, the driving control node and the second node respectively, and is used for controlling the communication between the driving control node and the second node under the control of a first voltage signal provided by the first voltage terminal.

[0028] The second initialization circuit is electrically connected with the first initial control terminal, the first initial voltage terminal and the second node respectively, and is used for controlling the writing of the first initial voltage into the second node under the control of the first initial control signal.

[0029] Optionally, the control sub-circuit comprises a first transistor, and the initialization sub-circuit comprises a second transistor.

[0030] The control electrode of the first transistor is electrically connected with the first voltage terminal, the first electrode of the first transistor is electrically connected with the second node, and the second electrode of the first transistor is electrically connected with the driving control node.

[0031] The control electrode of the second transistor is electrically connected with the first initial control terminal, the first electrode of the second transistor is electrically connected with the first initial voltage terminal, and the second electrode of the second transistor is electrically connected with the second node.

[0032] The first transistor is a low-temperature polysilicon thin film transistor, and the second transistor is an oxide thin film transistor.

[0033] The first voltage terminal is a first low voltage terminal.

[0034] Optionally, the compensation circuit is further electrically connected with a first voltage terminal, and the compensation circuit comprises a first compensation sub-circuit and a second compensation sub-circuit.

[0035] The first compensation sub-circuit is electrically connected with the first voltage terminal, a compensation node and a third node respectively, and is used for controlling the communication between the compensation node and the third node under the control of a first voltage signal provided by the first voltage terminal.

[0036] The second compensation sub-circuit is electrically connected with the compensation control end, the third node and the first node respectively, and is configured to control the third node and the first node to be in communication under the control of the compensation control signal.

[0037] Optionally, the first compensation sub-circuit comprises a third transistor, and the second compensation sub-circuit comprises a fourth transistor.

[0038] The control electrode of the third transistor is electrically connected with the first voltage end, the first electrode of the third transistor is electrically connected with the compensation node, and the second electrode of the third transistor is electrically connected with the third node.

[0039] The control electrode of the fourth transistor is electrically connected with the compensation control end, the first electrode of the fourth transistor is electrically connected with the compensation node, and the second electrode of the fourth transistor is electrically connected with the third node.

[0040] The third transistor is an oxide thin film transistor, and the fourth transistor is a low-temperature polysilicon thin film transistor.

[0041] Optionally, the compensation circuit is further electrically connected with a first voltage end, and the compensation circuit comprises a first compensation sub-circuit and a second compensation sub-circuit.

[0042] The first compensation sub-circuit is electrically connected with the first voltage end, the third node and the first node respectively, and is configured to control the third node and the first node to be in communication under the control of a first voltage signal provided by the first voltage end.

[0043] The second compensation sub-circuit is electrically connected with the compensation control end, the third node and the compensation node respectively, and is configured to control the third node and the compensation node to be in communication under the control of the compensation control signal.

[0044] Optionally, the first compensation sub-circuit comprises a third transistor, and the second compensation sub-circuit comprises a fourth transistor.

[0045] The control electrode of the third transistor is electrically connected with the first voltage end, the first electrode of the third transistor is electrically connected with the third node, and the second electrode of the third transistor is electrically connected with the first node.

[0046] The control electrode of the fourth transistor is electrically connected with the compensation control end, the first electrode of the fourth transistor is electrically connected with the compensation node, and the second electrode of the fourth transistor is electrically connected with the third node.

[0047] The third transistor is an oxide thin film transistor, and the fourth transistor is a low-temperature polysilicon thin film transistor.

[0048] Optionally, the pixel circuit according to any one of the embodiments of the present application further comprises a light emitting element, a driving circuit, a light emitting control circuit, a data writing circuit and an energy storage circuit, wherein,

[0049] The data writing circuit is electrically connected with a data writing control terminal, a data line and a fourth node respectively, and is configured to write a data voltage provided by the data line into the fourth node under control of a data writing control signal provided by the data writing control terminal;

[0050] The light emitting control circuit is electrically connected with a light emitting control line, a second voltage terminal, the fourth node, the first node and the light emitting element respectively, and is configured to control the fourth node to be in communication with the second voltage terminal and control the first node to be in communication with the light emitting element under control of a light emitting control signal provided by the light emitting control line;

[0051] The energy storage circuit has a first end electrically connected with the driving control node and a second end electrically connected with the second voltage terminal, and is configured to store electric energy;

[0052] The driving circuit is electrically connected with the driving control node, the fourth node and the first node respectively, and is configured to generate a driving current flowing from the fourth node to the first node under control of a potential of the driving control node.

[0053] Optionally, the pixel circuit according to any one of the embodiments of the present application further comprises a second initialization circuit;

[0054] The second initialization circuit is electrically connected with the data writing control terminal, a second initial voltage terminal and a first electrode of the light emitting element respectively, and is configured to write a second initial voltage provided by the second initial voltage terminal into the first electrode of the light emitting element under control of the data writing control signal;

[0055] A second electrode of the light emitting element is electrically connected with a third voltage terminal.

[0056] Optionally, the driving circuit comprises a driving transistor, the light emitting control circuit comprises a fifth transistor and a sixth transistor, the data writing circuit comprises a seventh transistor, and the energy storage circuit comprises a storage capacitor, wherein,

[0057] A control electrode of the driving transistor is electrically connected with the driving control node, a first electrode of the driving transistor is electrically connected with the fourth node, and a second electrode of the driving transistor is electrically connected with the first node;

[0058] A control electrode of the fifth transistor is electrically connected with the light emitting control line, a first electrode of the fifth transistor is electrically connected with the second voltage terminal, and a second electrode of the fifth transistor is electrically connected with the fourth node;

[0059] a control electrode of the sixth transistor is electrically connected with the light emitting control line, a first electrode of the sixth transistor is electrically connected with the first node, and a second electrode of the sixth transistor is electrically connected with the light emitting element;

[0060] a control electrode of the seventh transistor is electrically connected with the data write control terminal, a first electrode of the seventh transistor is electrically connected with the data line, and a second electrode of the seventh transistor is electrically connected with the fourth node;

[0061] a first end of the storage capacitor is electrically connected with the drive control node, and a second end of the storage capacitor is electrically connected with the second voltage terminal.

[0062] Optionally, the second initialization circuit comprises an eighth transistor.

[0063] a control electrode of the eighth transistor is electrically connected with the data write control terminal, a first electrode of the eighth transistor is electrically connected with the second initial voltage terminal, and a second electrode of the eighth transistor is electrically connected with the first electrode of the light emitting element;

[0064] the eighth transistor is a low-temperature polycrystalline silicon thin film transistor.

[0065] In a second aspect, an embodiment of the present application provides a pixel driving method applied to the pixel circuit, and a display period comprises an initialization stage and a data write stage arranged in sequence; the pixel driving method comprises:

[0066] in the initialization stage, the first initialization circuit controls the first initial voltage terminal to provide the first initial voltage to the drive control node under the control of the first initial control signal provided by the first initial control terminal;

[0067] in the data write stage, the compensation circuit controls the compensation node and the first node to be in communication under the control of the compensation control signal provided by the compensation control terminal.

[0068] Optionally, the drive control node and the compensation node are the same node; or,

[0069] The driving control node and the compensation node are different nodes, the first initialization circuit is further electrically connected with a first voltage terminal, the first initialization circuit includes a control sub-circuit and an initialization sub-circuit, and the first initialization circuit controls the first initial voltage terminal to provide the first initial voltage to the driving control node under the control of a first initial control signal provided by a first initial control terminal. The step of controlling the driving control node and the compensation node to be in communication under the control of a first voltage signal provided by the first voltage terminal includes that the control sub-circuit controls the driving control node and the compensation node to be in communication under the control of the first voltage signal provided by the first voltage terminal. The initialization sub-circuit controls the first initial voltage to be written into the compensation node under the control of the first initial control signal.

[0070] Optionally, the driving control node and the compensation node are the same node, the first initialization circuit is further electrically connected with a first voltage terminal, the first initialization circuit includes a control sub-circuit and an initialization sub-circuit, and the first initialization circuit controls the first initial voltage terminal to provide the first initial voltage to the driving control node under the control of a first initial control signal provided by a first initial control terminal. The step of controlling the driving control node and the compensation node to be in communication under the control of a first voltage signal provided by the first voltage terminal includes that the control sub-circuit controls the driving control node and the compensation node to be in communication under the control of the first voltage signal provided by the first voltage terminal. The initialization sub-circuit controls the first initial voltage to be written into the compensation node under the control of the first initial control signal.

[0071] The control sub-circuit controls the first initial voltage to be written into the second node under the control of a first voltage signal provided by the first voltage terminal, and the initialization sub-circuit controls the second node and the driving control node to be in communication under the control of the first initial control signal.

[0072] Optionally, the driving control node and the compensation node are the same node, the first initialization circuit is further electrically connected with a first voltage terminal, the first initialization circuit includes a control sub-circuit and an initialization sub-circuit, and the first initialization circuit controls the first initial voltage terminal to provide the first initial voltage to the driving control node under the control of a first initial control signal provided by a first initial control terminal. The step of controlling the driving control node and the compensation node to be in communication under the control of a first voltage signal provided by the first voltage terminal includes that the control sub-circuit controls the driving control node and the compensation node to be in communication under the control of the first voltage signal provided by the first voltage terminal. The initialization sub-circuit controls the first initial voltage to be written into the compensation node under the control of the first initial control signal.

[0073] The control sub-circuit controls the driving control node and the second node to be in communication under the control of a first voltage signal provided by the first voltage terminal, and the initialization sub-circuit controls the first initial voltage to be written into the second node under the control of the first initial control signal.

[0074] Optionally, the compensation circuit is further electrically connected with a first voltage terminal, the compensation circuit includes a first compensation sub-circuit and a second compensation sub-circuit, and the compensation circuit controls the compensation node and the first node to be in communication under the control of a compensation control signal provided by a compensation control terminal. The step of controlling the compensation node and the first node to be in communication under the control of a compensation control signal provided by a compensation control terminal includes that the first compensation sub-circuit controls the compensation node and the first node to be in communication under the control of a first compensation signal provided by the first voltage terminal, and the second compensation sub-circuit controls the compensation node and the first node to be in communication under the control of a second compensation signal provided by the first voltage terminal.

[0075] The first compensation sub-circuit controls the communication between the third node and the first node under the control of a first voltage signal provided by the first voltage terminal; and the second compensation sub-circuit controls the communication between the third node and the compensation node under the control of the compensation control signal.

[0076] Optionally, the compensation circuit further has a first voltage terminal electrically connected thereto, and the compensation circuit comprises a first compensation sub-circuit and a second compensation sub-circuit; the compensation circuit controls the communication between the compensation node and the first node under the control of a compensation control signal provided by a compensation control terminal, and the step of controlling the communication between the compensation node and the first node comprises:

[0077] The first compensation sub-circuit controls the communication between the third node and the first node under the control of a first voltage signal provided by the first voltage terminal; and the second compensation sub-circuit controls the communication between the third node and the compensation node under the control of the compensation control signal.

[0078] In a third aspect, the embodiment of the present application further provides a display device comprising the pixel circuit.

[0079] The pixel circuit, the pixel driving method and the display device can well maintain the potential of the driving control node, so as to alleviate the phenomenon that the potential of the driving control node cannot be well maintained due to the leakage, and further affect the display. BRIEF DESCRIPTION OF DRAWINGS

[0080] Figure 1 is a structural diagram of the pixel circuit according to the embodiment of the present application;

[0081] Figure 2 is a structural diagram of the pixel circuit according to at least one embodiment of the present application;

[0082] Figure 3 is a structural diagram of the pixel circuit according to at least one embodiment of the present application;

[0083] Figure 4 is a structural diagram of the pixel circuit according to at least one embodiment of the present application;

[0084] Figure 5 is a structural diagram of the pixel circuit according to at least one embodiment of the present application;

[0085] Figure 6 is a structural diagram of the pixel circuit according to at least one embodiment of the present application;

[0086] Figure 7 is a structural diagram of the pixel circuit according to at least one embodiment of the present application;

[0087] Figure 8 is a structural diagram of the pixel circuit according to at least one embodiment of the present application;

[0088] Figure 9 is a timing diagram of the pixel circuit according to at least one embodiment of the present application;

[0089] Figure 10 is a circuit diagram of the pixel circuit according to at least one embodiment of the present application;

[0090] Figure 11 is a circuit diagram of the pixel circuit according to at least one embodiment of the present application;

[0091] Figure 12 is a circuit diagram of the pixel circuit according to at least one embodiment of the present application;

[0092] Figure 13 is a structural diagram of the pixel circuit according to at least one embodiment of the present application;

[0093] Figure 14 is a circuit diagram of the pixel circuit according to at least one embodiment of the present application. DETAILED DESCRIPTION

[0094] The technical solutions in the embodiments of the present application will be clearly and completely described in connection with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0095] The transistors used in all the embodiments of the present application can be triodes, thin film transistors, field effect transistors or other devices with the same characteristics. In the embodiments of the present application, in order to distinguish the two poles of the transistor except the control pole, one pole is called the first pole and the other pole is called the second pole.

[0096] In actual operation, when the transistor is a triode, the control pole can be a base, the first pole can be a collector, and the second pole can be an emitter; or the control pole can be a base, the first pole can be an emitter, and the second pole can be a collector.

[0097] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the control pole can be a gate, the first pole can be a drain, and the second pole can be a source; or the control pole can be a gate, the first pole can be a source, and the second pole can be a drain.

[0098] The pixel circuit according to the embodiments of the present application comprises a first initialization circuit and a compensation circuit.

[0099] The first initialization circuit is electrically connected with the driving control node, the first initial control end and the first initial voltage end respectively, and is configured to control the first initial voltage end to provide a first initial voltage to the driving control node under the control of a first initial control signal provided by the first initial control end.

[0100] The compensation circuit is electrically connected with the compensation control end, the compensation node and the first node respectively, and is configured to control the compensation node to be in communication with the first node under the control of a compensation control signal provided by the compensation control end.

[0101] At least one of the first initialization circuit and the compensation circuit comprises an oxide thin film transistor and a low-temperature polysilicon thin film transistor connected in series with each other.

[0102] In the embodiment of the present application, the oxide thin film transistor is included in the leakage path of the driving control node, and the low-leakage characteristic of the oxide thin film transistor is utilized to well maintain the potential of the driving control node, so as to alleviate the phenomenon that the potential of the driving control node cannot be well maintained due to the leakage, and further affect the display.

[0103] In at least one embodiment of the present application, the leakage path of the driving control node can include a first leakage path of the driving control node to the first initial voltage end and a second leakage path of the driving control node to the second initial voltage end.

[0104] In the pixel circuit in the embodiment of the present application, at least one of the first initialization circuit and the compensation circuit comprises an oxide thin film transistor and a low-temperature polysilicon thin film transistor connected in series with each other, so that the circuit for initializing the potential of the driving control node and / or the circuit for compensation not only comprises the oxide thin film transistor, but also comprises the low-temperature polysilicon thin film transistor.

[0105] In at least one embodiment of the present application, when the low-temperature polysilicon thin film transistor is a normally-on transistor and the low-temperature polysilicon thin film transistor is directly electrically connected with the driving control node, the potential of the driving control node can be stabilized.

[0106] In at least one embodiment of the present application, when one of the first initialization circuit and the compensation circuit comprises an oxide thin film transistor and a low-temperature polysilicon thin film transistor connected in series with each other, the other of the first initialization circuit and the compensation circuit can comprise an oxide thin film transistor, so as to further improve the leakage phenomenon, but not limited thereto.

[0107] In the working process of the pixel circuit in the embodiment of the present application, the display period can include an initialization stage and a data writing stage arranged in sequence.

[0108] In the initialization stage, the first initialization circuit controls the first initial voltage terminal to provide the first initial voltage to the driving control node under the control of the first initial control signal provided by the first initial control terminal;

[0109] In the data writing stage, the compensation circuit controls the communication between the compensation node and the first node under the control of the compensation control signal provided by the compensation control terminal, so as to compensate the threshold voltage of the driving transistor in the pixel circuit.

[0110] Optionally, the driving control node and the compensation node can be the same node.

[0111] Optionally, the driving control node and the compensation node can be different nodes; the first initialization circuit is further electrically connected with the first voltage terminal; the first initialization circuit comprises a control sub-circuit and an initialization sub-circuit, wherein,

[0112] The first initialization circuit is electrically connected with the first voltage terminal, the driving control node and the compensation node respectively, and is used for controlling the communication between the driving control node and the compensation node under the control of the first voltage signal provided by the first voltage terminal.

[0113] The second initialization circuit is electrically connected with the first initial control terminal, the first initial voltage terminal and the second node respectively, and is used for controlling the first initial voltage to be written into the compensation node under the control of the first initial control signal.

[0114] In at least one embodiment of the present application, the control sub-circuit comprises a first transistor, and the initialization sub-circuit comprises a second transistor.

[0115] The control electrode of the first transistor is electrically connected with the first voltage terminal, the first electrode of the first transistor is electrically connected with the compensation node, and the second electrode of the first transistor is electrically connected with the driving control node.

[0116] The control electrode of the second transistor is electrically connected with the first initial control terminal, the first electrode of the second transistor is electrically connected with the first initial voltage terminal, and the second electrode of the second transistor is electrically connected with the compensation node.

[0117] The first transistor is a low-temperature polysilicon thin film transistor, and the second transistor is an oxide thin film transistor.

[0118] The first voltage terminal is a first low-voltage terminal.

[0119] As Figure 1 shown in the figure, the pixel circuit in the embodiment of the present application comprises a first initialization circuit 11 and a compensation circuit 12.

[0120] The first initialization circuit 11 is electrically connected to the drive control node N0, the first initial control terminal S0, and the first initial voltage terminal I1, respectively, and is used to control the first initial voltage terminal I1 to provide a first initial voltage to the drive control node N0 under the control of the first initial control signal provided by the first initial control terminal S0.

[0121] The compensation circuit 12 is electrically connected to the compensation control terminal S1, the drive control node N0, and the first node N1, respectively, and is used to control the connection between the drive control node N0 and the first node N1 under the control of the compensation control signal provided by the compensation control terminal S1.

[0122] exist Figure 1 In at least one embodiment of the pixel circuit shown, the first initialization circuit 11 includes an oxide thin-film transistor and a low-temperature polycrystalline silicon thin-film transistor connected in series; and / or, the compensation circuit 12 includes an oxide thin-film transistor and a low-temperature polycrystalline silicon thin-film transistor connected in series.

[0123] exist Figure 1 In at least one embodiment of the pixel circuit shown, the compensation node and the drive control node N0 are the same node.

[0124] Optionally, the drive control node N0 can be a node electrically connected to the control terminal of the drive circuit in the pixel circuit, and the first node can be a node electrically connected to the second terminal of the drive circuit in the pixel circuit.

[0125] Optionally, the first voltage terminal can be a first low voltage terminal.

[0126] like Figure 2 As shown, the pixel circuit of at least one embodiment of the present invention may include a first initialization circuit and a compensation circuit 12; the compensation node Nc and the driving control node N0 are different nodes; the first initialization circuit is also electrically connected to a first voltage terminal V1; the first initialization circuit includes a control sub-circuit 31 and an initialization sub-circuit 32.

[0127] The control sub-circuit 31 is electrically connected to the first voltage terminal V1, the drive control node N0, and the compensation node Nc, respectively, and is used to control the connection between the drive control node N0 and the compensation node Nc under the control of the first voltage signal provided by the first voltage terminal V1.

[0128] The initialization sub-circuit 32 is electrically connected to the first initial control terminal S0, the first initial voltage terminal I1, and the compensation node Nc, respectively, and is used to control the writing of the first initial voltage provided by the first initial voltage terminal I1 into the compensation node Nc under the control of the first initial control signal.

[0129] The compensation circuit 12 is electrically connected with the compensation control end S1, the compensation node Nc and the first node N1 respectively, and is used for controlling the compensation node Nc to be in communication with the first node N1 under the control of a compensation control signal provided by the compensation control end S1.

[0130] In Figure 2 In at least one embodiment of the pixel circuit shown, the control sub-circuit 31 can include a low-temperature polysilicon thin film transistor, and the initialization sub-circuit 32 can include an oxide thin film transistor.

[0131] The present application is as Figure 2 In at least one embodiment of the pixel circuit shown, the display period can include an initialization stage and a data writing stage arranged in sequence in operation.

[0132] In the initialization stage, the control sub-circuit 31 controls the driving control node N0 to be in communication with the compensation node Nc under the control of the first voltage signal; and the initialization sub-circuit 32 controls the first initialization voltage provided by the first initialization voltage end I1 to be written into the compensation node Nc under the control of the first initialization control signal, so as to control the first initialization voltage to be written into the driving control node N0.

[0133] In the data writing stage, the control sub-circuit 31 controls the driving control node N0 to be in communication with the compensation node Nc under the control of the first voltage signal; the compensation circuit 12 controls the first node N1 to be in communication with the compensation node Nc under the control of the compensation control signal, so as to make the first node N1 to be in communication with the driving control node N0, thereby compensating the threshold voltage of the driving transistor in the driving circuit in the pixel circuit.

[0134] In at least one embodiment of the present application, when the compensation node and the driving control node are the same node, the first initialization circuit can further be electrically connected with the first voltage end; the first initialization circuit can include a control sub-circuit and an initialization sub-circuit, wherein,

[0135] The control sub-circuit is electrically connected with the first voltage end, the first initialization voltage end and the second node respectively, and is used for controlling the first initialization voltage to be written into the second node under the control of the first voltage signal provided by the first voltage end.

[0136] The initialization sub-circuit is electrically connected with the first initialization control end, the second node and the driving control node respectively, and is used for controlling the second node to be in communication with the driving control node under the control of the first initialization control signal.

[0137] In a specific implementation, the first initialization circuit can include a control sub-circuit and an initialization sub-circuit, the control sub-circuit writes the first initial voltage to the second node under the control of the first voltage signal, and the initialization sub-circuit controls the communication between the second node and the driving control node under the control of the first initial control signal to control the writing of the first initial voltage to the driving control node.

[0138] As shown in at least one embodiment of the pixel circuit shown in Figure 3 As shown in at least one embodiment of the pixel circuit shown in Figure 1 Based on at least one embodiment of the pixel circuit shown in

[0139] The control sub-circuit 31 is electrically connected with the first voltage terminal V1, the first initial voltage terminal I1 and the second node N2 respectively, and is configured to control the writing of the first initial voltage to the second node N2 under the control of the first voltage signal provided by the first voltage terminal V1.

[0140] The initialization sub-circuit 32 is electrically connected with the first initial control terminal S0, the second node N2 and the driving control node N0 respectively, and is configured to control the communication between the second node N2 and the driving control node N0 under the control of the first initial control signal.

[0141] In at least one embodiment of the pixel circuit shown in Figure 3 The control sub-circuit 31 can include a low-temperature polysilicon transistor, and the initialization sub-circuit 32 can include an oxide thin film transistor.

[0142] At least one embodiment of the pixel circuit shown in Figure 3 In operation, the display period can include an initialization stage and a data writing stage arranged in sequence.

[0143] In the initialization stage, the control sub-circuit 31 controls the writing of the first initial voltage to the second node N2 under the control of the first voltage signal provided by the first voltage terminal V1, and the initialization sub-circuit 32 controls the communication between the second node N2 and the driving control node N0 under the control of the first initial control signal.

[0144] In the data writing stage, the compensation circuit 12 controls the communication between the driving control node N0 and the first node N1 under the control of the compensation control signal provided by the compensation control terminal S1 to compensate the threshold voltage of the driving transistor in the pixel circuit.

[0145] Optionally, the control sub-circuit includes a first transistor, and the initialization sub-circuit includes a second transistor.

[0146] The control electrode of the first transistor is electrically connected to the first voltage terminal, the first electrode of the first transistor is electrically connected to the first initial voltage terminal, and the second electrode of the first transistor is electrically connected to the second node.

[0147] The control electrode of the second transistor is electrically connected to the first initial control terminal, the first electrode of the second transistor is electrically connected to the second node, and the second electrode of the second transistor is electrically connected to the drive control node.

[0148] The first transistor is a low-temperature polycrystalline silicon thin-film transistor, and the second transistor is an oxide thin-film transistor;

[0149] The first voltage terminal is the first low voltage terminal.

[0150] In a specific implementation, the first transistor can be a normally open transistor.

[0151] In at least one embodiment of the present invention, when the compensation node and the drive control node are the same node, the first initialization circuit is also electrically connected to the first voltage terminal; the first initialization circuit includes a control sub-circuit and an initialization sub-circuit, wherein...

[0152] The control sub-circuit is electrically connected to the first voltage terminal, the drive control node, and the second node, respectively, and is used to control the connection between the drive control node and the second node under the control of the first voltage signal provided by the first voltage terminal;

[0153] The initialization sub-circuit is electrically connected to the first initial control terminal, the first initial voltage terminal, and the second node, respectively, and is used to control the writing of the first initial voltage to the second node under the control of the first initial control signal.

[0154] In a specific implementation, the first initialization circuit may include a control sub-circuit and an initialization sub-circuit. Under the control of the first voltage signal, the control sub-circuit controls the connection between the drive control node and the second node. Under the control of the first initial control signal, the initialization sub-circuit controls the writing of the first initial voltage to the second node, thereby writing the first initial voltage to the drive control node.

[0155] like Figure 4 As shown, in Figure 1 Based on at least one embodiment of the pixel circuit shown, the first initialization circuit may also be electrically connected to the first voltage terminal V1; the first initialization circuit includes a control sub-circuit 31 and an initialization sub-circuit 32, wherein,

[0156] The control sub-circuit 31 is electrically connected with the first voltage terminal V1, the driving control node N0 and the second node N2 respectively, and is configured to control the communication between the driving control node N0 and the second node N2 under the control of the first voltage signal provided by the first voltage terminal V1.

[0157] The initialization sub-circuit 32 is electrically connected with the first initial control terminal S0, the first initial voltage terminal I1 and the second node N2 respectively, and is configured to control the writing of the first initial voltage into the second node N2 under the control of the first initial control signal.

[0158] In at least one embodiment of the pixel circuit shown in the figure, the control sub-circuit 31 can include a low-temperature polysilicon thin film transistor, and the initialization sub-circuit 32 can include an oxide thin film transistor. Figure 4 In at least one embodiment of the pixel circuit shown in the figure, the control sub-circuit 31 can include a low-temperature polysilicon thin film transistor, and the initialization sub-circuit 32 can include an oxide thin film transistor.

[0159] Figure 4 In at least one embodiment of the pixel circuit shown in the figure, the display period can include an initialization stage and a data writing stage arranged in sequence.

[0160] In the initialization stage, the control sub-circuit 31 controls the communication between the driving control node N0 and the second node N2 under the control of the first voltage signal provided by the first voltage terminal V1, and the initialization sub-circuit 32 controls the writing of the first initial voltage into the second node N2 under the control of the first initial control signal.

[0161] In the data writing stage, the compensation circuit 12 controls the communication between the driving control node N0 and the first node N1 under the control of the compensation control signal provided by the compensation control terminal S1, so as to compensate the threshold voltage of the driving transistor in the pixel circuit.

[0162] Optionally, the control sub-circuit includes a first transistor, and the initialization sub-circuit includes a second transistor.

[0163] The control electrode of the first transistor is electrically connected with the first voltage terminal, the first electrode of the first transistor is electrically connected with the second node, and the second electrode of the first transistor is electrically connected with the driving control node.

[0164] The control electrode of the second transistor is electrically connected with the first initial control terminal, the first electrode of the second transistor is electrically connected with the first initial voltage terminal, and the second electrode of the second transistor is electrically connected with the second node.

[0165] The first transistor is a low-temperature polysilicon thin film transistor, and the second transistor is an oxide thin film transistor.

[0166] The first voltage terminal is a first low-voltage terminal.​

[0167] In a specific implementation, the first transistor can be a normally-on transistor.

[0168] In at least one embodiment of the present application, the compensation circuit is further electrically connected with the first voltage terminal, and the compensation circuit comprises a first compensation sub-circuit and a second compensation sub-circuit.

[0169] The first compensation sub-circuit is electrically connected with the first voltage terminal, the compensation node and the third node respectively, and is configured to control the communication between the compensation node and the third node under the control of the first voltage signal provided by the first voltage terminal.

[0170] The second compensation sub-circuit is electrically connected with the compensation control terminal, the third node and the first node respectively, and is configured to control the communication between the third node and the first node under the control of the compensation control signal.

[0171] In a specific implementation, the compensation circuit can comprise a first compensation sub-circuit and a second compensation sub-circuit, the first compensation sub-circuit controls the communication between the compensation node and the third node under the control of the first voltage signal, and the second compensation sub-circuit controls the communication between the third node and the first node under the control of the compensation control signal, so as to control the communication between the compensation node and the first node.

[0172] Optionally, the first compensation sub-circuit can comprise a low-temperature polysilicon thin film transistor, and the second compensation sub-circuit can comprise an oxide thin film transistor.

[0173] As shown in Figure 5 As shown in at least one embodiment of the pixel circuit shown in Figure 1 The compensation circuit is further electrically connected with the first voltage terminal V1, and the compensation circuit comprises a first compensation sub-circuit 51 and a second compensation sub-circuit 52.

[0174] The first compensation sub-circuit 51 is electrically connected with the first voltage terminal V1, the driving control node N0 and the third node N3 respectively, and is configured to control the communication between the driving control node N0 and the third node N3 under the control of the first voltage signal provided by the first voltage terminal V1.

[0175] The second compensation sub-circuit 52 is electrically connected with the compensation control terminal S1, the third node N3 and the first node N1 respectively, and is configured to control the communication between the third node N3 and the first node N1 under the control of the compensation control signal.

[0176] In Figure 5In at least one illustrated embodiment, the first compensation sub-circuit 51 can include a low-temperature polysilicon thin film transistor, and the second compensation sub-circuit 52 can include an oxide thin film transistor.

[0177] The present application is as Figure 5 In at least one illustrated embodiment of the pixel circuit, a display period can include an initialization stage and a data writing stage arranged in sequence.

[0178] In the initialization stage, the first initialization circuit 11 controls the first initialization voltage terminal I1 to provide a first initialization voltage to the driving control node N0 under the control of a first initialization control signal provided by the first initialization control terminal S0.

[0179] In the data writing stage, the first compensation sub-circuit 51 controls the driving control node N0 and the third node N3 to be in communication under the control of a first voltage signal provided by the first voltage terminal V1, and the second compensation sub-circuit 52 controls the third node N3 and the first node N1 to be in communication under the control of the compensation control signal, so as to control the first node N1 and the driving control node N0 to be in communication.

[0180] Optionally, the first compensation sub-circuit includes a third transistor, and the second compensation sub-circuit includes a fourth transistor.

[0181] The control electrode of the third transistor is electrically connected with the first voltage terminal, the first electrode of the third transistor is electrically connected with the compensation node, and the second electrode of the third transistor is electrically connected with the third node.

[0182] The control electrode of the fourth transistor is electrically connected with the compensation control terminal, the first electrode of the fourth transistor is electrically connected with the third node, and the second electrode of the fourth transistor is electrically connected with the first node.

[0183] The third transistor is an oxide thin film transistor, and the fourth transistor is a low-temperature polysilicon thin film transistor.

[0184] In a specific implementation, the first voltage terminal can be a first low-voltage terminal, and the third transistor can be a normally-on transistor.

[0185] In at least one embodiment of the present application, the compensation circuit is further electrically connected with a first voltage terminal, and the compensation circuit includes a first compensation sub-circuit and a second compensation sub-circuit.

[0186] The first compensation sub-circuit is electrically connected with the first voltage terminal, the third node, and the first node, respectively, and is configured to control the third node and the first node to be in communication under the control of a first voltage signal provided by the first voltage terminal.

[0187] The second compensation sub-circuit is electrically connected with the compensation control end, the third node and the compensation node respectively, and is configured to control the third node and the compensation node to be in communication under the control of the compensation control signal.

[0188] In a specific implementation, the compensation circuit can include a first compensation sub-circuit and a second compensation sub-circuit. The first compensation sub-circuit is configured to control the third node and the first node to be in communication under the control of the first voltage signal, and the second compensation sub-circuit is configured to control the third node and the compensation node to be in communication under the control of the compensation control signal, so as to control the first node and the compensation node to be in communication.

[0189] As shown in FIG. 1, Figure 6 As shown in FIG. 1, Figure 1 Based on at least one embodiment of the pixel circuit shown in FIG. 1, the compensation circuit is further electrically connected with a first voltage end V1, and the compensation circuit includes a first compensation sub-circuit 51 and a second compensation sub-circuit 52.

[0190] The first compensation sub-circuit 51 is electrically connected with the first voltage end V1, the third node N3 and the first node N1 respectively, and is configured to control the third node N3 and the first node N1 to be in communication under the control of the first voltage signal provided by the first voltage end V1.

[0191] The second compensation sub-circuit 52 is electrically connected with the compensation control end S1, the third node N3 and the driving control node N0 respectively, and is configured to control the third node N3 and the driving control node N0 to be in communication under the control of the compensation control signal.

[0192] In at least one embodiment shown in FIG. 1, Figure 6 In at least one embodiment shown in FIG. 1, the first compensation sub-circuit 51 can include a low-temperature polysilicon thin film transistor, and the second compensation sub-circuit 52 can include an oxide thin film transistor.

[0193] At least one embodiment of the pixel circuit shown in FIG. 1 is in operation, and the display period can include an initialization stage and a data writing stage arranged in sequence. Figure 6 At least one embodiment of the pixel circuit shown in FIG. 1 is in operation, and the display period can include an initialization stage and a data writing stage arranged in sequence.

[0194] In the initialization stage, the first initialization circuit 11 controls the first initialization voltage end I1 to provide a first initialization voltage to the driving control node N0 under the control of the first initialization control signal provided by the first initialization control end S0.

[0195] In the data writing stage, the first compensation sub-circuit 51 controls the communication between the third node N3 and the first node N1 under the control of the first voltage signal provided by the first voltage terminal V2; and the second compensation sub-circuit 52 controls the communication between the third node N3 and the driving control node N0 under the control of the compensation control signal, so as to control the communication between the first node N1 and the driving control node N0.

[0196] Optionally, the first compensation sub-circuit comprises a third transistor, and the second compensation sub-circuit comprises a fourth transistor.

[0197] The control electrode of the third transistor is electrically connected with the first voltage terminal, the first electrode of the third transistor is electrically connected with the third node, and the second electrode of the third transistor is electrically connected with the first node.

[0198] The control electrode of the fourth transistor is electrically connected with the compensation control terminal, the first electrode of the fourth transistor is electrically connected with the compensation node, and the second electrode of the fourth transistor is electrically connected with the third node.

[0199] The third transistor is an oxide thin film transistor, and the fourth transistor is a low-temperature polysilicon thin film transistor.

[0200] Optionally, the pixel circuit can further comprise a light emitting element, a driving circuit, a light emitting control circuit, a data writing circuit and an energy storage circuit.

[0201] The data writing circuit is electrically connected with a data writing control terminal, a data line and a fourth node respectively, and is used for controlling the data voltage provided by the data line to be written into the fourth node under the control of a data writing control signal provided by the data writing control terminal.

[0202] The light emitting control circuit is electrically connected with a light emitting control line, a second voltage terminal, the fourth node, the first node and the light emitting element respectively, and is used for controlling the communication between the fourth node and the second voltage terminal and the communication between the first node and the light emitting element under the control of a light emitting control signal provided by the light emitting control line.

[0203] The first end of the energy storage circuit is electrically connected with the driving control node, and the second end of the energy storage circuit is electrically connected with the second voltage terminal, and the energy storage circuit is used for storing electric energy.

[0204] The driving circuit is electrically connected with the driving control node, the fourth node and the first node respectively, and is used for generating a driving current flowing from the fourth node to the first node under the control of the potential of the driving control node.

[0205] In at least one embodiment of the present invention, the pixel circuit may include a light-emitting element, a driving circuit, a light-emitting control circuit, a data writing circuit, and an energy storage circuit. The light-emitting control circuit is used for light-emitting control, the data writing circuit is used for writing data voltage, the energy storage circuit is used for maintaining the potential of the driving control node, and the driving circuit generates a driving current flowing from the fourth node to the first node under the control of the potential of the driving control node.

[0206] Optionally, the light-emitting element can be an organic light-emitting diode.

[0207] Optionally, the second voltage terminal can be a high voltage terminal.

[0208] In at least one embodiment of the present invention, the pixel circuit may further include a second initialization circuit;

[0209] The second initialization circuit is electrically connected to the data writing control terminal, the second initial voltage terminal, and the first electrode of the light-emitting element, respectively, and is used to control the writing of the second initial voltage provided by the second initial voltage terminal into the first electrode of the light-emitting element under the control of the data writing control signal;

[0210] The second electrode of the light-emitting element is electrically connected to the third voltage terminal.

[0211] Optionally, the third voltage terminal can be a second low voltage terminal.

[0212] Optionally, the pixel circuit further includes a second initialization circuit, which, under the control of the data write control signal, writes a second initial voltage to the first electrode of the light-emitting element to clear the residual charge on the first electrode of the light-emitting element and controls the light-emitting element not to emit light.

[0213] Optionally, the first initial voltage and the second initial voltage can be the same, but are not limited thereto.

[0214] like Figure 7 As shown, in Figure 1 Based on at least one embodiment of the pixel circuit shown, the pixel circuit may further include a light-emitting element 70, a driving circuit 71, a light-emitting control circuit 72, a data writing circuit 73, an energy storage circuit 74, and a second initialization circuit 75, wherein,

[0215] The data writing circuit 73 is electrically connected to the data writing control terminal S2, the data line D0 and the fourth node N4 respectively, and is used to control the data voltage provided by the data line D0 to be written to the fourth node N4 under the control of the data writing control signal provided by the data writing control terminal S2.

[0216] The light emitting control circuit 72 is electrically connected with the light emitting control line E1, the second voltage terminal V2, the fourth node N4, the first node N1 and the light emitting element 70 respectively, and is used for controlling the communication between the fourth node N4 and the second voltage terminal V2 and the communication between the first node N1 and the first electrode of the light emitting element 70 under the control of the light emitting control signal provided by the light emitting control line E1;

[0217] The first end of the energy storage circuit 74 is electrically connected with the driving control node N0, and the second end of the energy storage circuit 74 is electrically connected with the second voltage terminal V2, and the energy storage circuit 74 is used for storing electric energy;

[0218] The driving circuit 71 is electrically connected with the driving control node N0, the fourth node N4 and the first node N1 respectively, and is used for generating the driving current flowing from the fourth node N4 to the first node N1 under the control of the potential of the driving control node N0;

[0219] The second initialization circuit 75 is electrically connected with the data write control terminal S2, the second initial voltage terminal I2 and the first electrode of the light emitting element 70 respectively, and is used for controlling the writing of the second initial voltage provided by the second initial voltage terminal I2 into the first electrode of the light emitting element 70 under the control of the data write control signal;

[0220] The second electrode of the light emitting element 70 is electrically connected with the third voltage terminal V3.

[0221] The pixel circuit of the present application has the advantages that Figure 7 At least one embodiment of the pixel circuit shown in the present application has the advantages that

[0222] In the initialization stage, the first initialization circuit 11 controls the first initial voltage terminal I1 to provide the first initial voltage to the driving control node N0 under the control of the first initial control signal provided by the first initial control terminal S0;

[0223] In the data writing stage, the data writing circuit 73 is controlled by the data writing control signal provided by the data writing control end S2 to write the data voltage provided by the data line D0 into the fourth node N4; the compensation circuit is controlled by the compensation control signal provided by the compensation control end S1 to control the communication between the driving control node N0 and the first node N1, so that the driving circuit 71 is controlled to turn on the connection between the fourth node N4 and the first node N1 at the beginning of the data writing stage, and the energy storage circuit 74 is charged through the data voltage to change the potential of the driving control node N0, until the driving circuit 71 turns off the connection between N4 and N1, at which time the potential of N0 is related to the data voltage and the threshold voltage of the driving transistor in the driving circuit 71, so as to compensate the threshold voltage of the driving transistor;

[0224] In the light emitting stage, the light emitting control circuit 72 is controlled by the light emitting control signal provided by the light emitting control line E1 to control the communication between the fourth node N4 and the second voltage end V2, and to control the communication between the first node N1 and the first electrode of the light emitting element 70, and the driving circuit 71 is controlled by the potential of the driving control node N0 to generate the driving current flowing from the fourth node N4 to the first node N1 to drive the light emitting element 70 to emit light.

[0225] Optionally, the driving circuit comprises a driving transistor, the light emitting control circuit comprises a fifth transistor and a sixth transistor, the data writing circuit comprises a seventh transistor, and the energy storage circuit comprises a storage capacitor.

[0226] The control electrode of the driving transistor is electrically connected with the driving control node, the first electrode of the driving transistor is electrically connected with the fourth node, and the second electrode of the driving transistor is electrically connected with the first node.

[0227] The control electrode of the fifth transistor is electrically connected with the light emitting control line, the first electrode of the fifth transistor is electrically connected with the second voltage end, and the second electrode of the fifth transistor is electrically connected with the fourth node.

[0228] The control electrode of the sixth transistor is electrically connected with the light emitting control line, the first electrode of the sixth transistor is electrically connected with the first node, and the second electrode of the sixth transistor is electrically connected with the light emitting element.

[0229] The control electrode of the seventh transistor is electrically connected with the data writing control end, the first electrode of the seventh transistor is electrically connected with the data line, and the second electrode of the seventh transistor is electrically connected with the fourth node.

[0230] The first end of the storage capacitor is electrically connected with the driving control node, and the second end of the storage capacitor is electrically connected with the second voltage terminal.

[0231] Optionally, the driving transistor, the fifth transistor, the sixth transistor and the seventh transistor are low-temperature polysilicon thin film transistors.

[0232] Optionally, the second initialization circuit comprises an eighth transistor.

[0233] The control electrode of the eighth transistor is electrically connected with the data write control terminal, the first electrode of the eighth transistor is electrically connected with the second initial voltage terminal, and the second electrode of the eighth transistor is electrically connected with the first electrode of the light emitting element.

[0234] The eighth transistor is a low-temperature polysilicon thin film transistor.

[0235] As shown in Figure 8 As shown in at least one embodiment of the pixel circuit shown in Figure 7 The light emitting element is an organic light emitting diode O1.

[0236] The driving circuit 71 comprises a driving transistor Td, the light emitting control circuit comprises a fifth transistor T5 and a sixth transistor T6, the data write circuit 73 comprises a seventh transistor T7, the energy storage circuit 74 comprises a storage capacitor C1, and the second initialization circuit 75 comprises an eighth transistor T8.

[0237] The first initialization circuit comprises a control sub-circuit 31 and an initialization sub-circuit 32, wherein the control sub-circuit 31 comprises a first transistor T1, and the initialization sub-circuit 32 comprises a second transistor T2; and the compensation circuit 12 comprises a fourth transistor T4.

[0238] The gate of the first transistor T1 is electrically connected with a first low voltage terminal, the source of the first transistor T1 is electrically connected with the first initial voltage terminal I1, and the drain of the first transistor T1 is electrically connected with the second node N2; and the first low voltage terminal is used for providing a first low voltage signal V01.

[0239] The gate of the second transistor T2 is electrically connected with the first initial control terminal S0, the drain of the second transistor T2 is electrically connected with the second node N2, and the source of the second transistor T2 is electrically connected with the driving control node N0.

[0240] The gate of the fourth transistor T4 is electrically connected with a compensation control terminal S1, the drain of the fourth transistor T4 is electrically connected with the driving control node N0, and the source of the fourth transistor T4 is electrically connected with the first node N1.

[0241] a gate of the driving transistor Td is electrically connected with the driving control node N0, a source of the driving transistor Td is electrically connected with the fourth node N4, and a drain of the driving transistor Td is electrically connected with the first node N1;

[0242] a gate of the fifth transistor T5 is electrically connected with the light emitting control line E1, a source of the fifth transistor T5 is electrically connected with a high voltage terminal, and a drain of the fifth transistor T5 is electrically connected with the fourth node N4; the high voltage terminal is used for providing a high voltage signal V02;

[0243] a gate of the sixth transistor T6 is electrically connected with the light emitting control line E1, a source of the sixth transistor T6 is electrically connected with the first node N1, and a drain of the sixth transistor T6 is electrically connected with an anode of O1;

[0244] a control electrode of the seventh transistor T7 is electrically connected with the data write control terminal S2, a source of the seventh transistor T7 is electrically connected with the data line D0, and a drain of the seventh transistor T7 is electrically connected with the fourth node N4;

[0245] a first terminal of the storage capacitor C1 is electrically connected with the driving control node N0, and a second terminal of the storage capacitor C1 is electrically connected with the high voltage terminal;

[0246] a gate of the eighth transistor T8 is electrically connected with the data write control terminal S2, a source of the eighth transistor T8 is electrically connected with a second initial voltage terminal I2, and a drain of the eighth transistor T8 is electrically connected with an anode of O1;

[0247] a cathode of O1 is electrically connected with a second low voltage terminal, and the second low voltage terminal is used for providing a second low voltage signal V03.

[0248] In at least one embodiment of the pixel circuit shown in Figure 8 In at least one embodiment of the pixel circuit shown in

[0249] In at least one embodiment of the pixel circuit shown in Figure 8 In at least one embodiment of the pixel circuit shown in

[0250] T2 and T4 are n-type transistors, and Td, T1, T5, T6, T7 and T8 are p-type transistors.

[0251] In at least one embodiment of the pixel circuit shown in Figure 8At least one embodiment of the pixel circuit shown in the figure is in operation, and initialization of N0 is completed by T1 and T2, wherein T1 is a low-temperature polysilicon thin film transistor, and T2 is an oxide thin film transistor.

[0252] In Figure 8 In at least one embodiment shown in the figure, the voltage value of the first initial voltage provided by I1 can be greater than the voltage value of the second initial voltage provided by I2, there are two transistors in the first leakage path from N0 to I1, there are three transistors in the second leakage path from N0 to I2, and by setting the voltage value of the first initial voltage to be greater than the voltage value of the second initial voltage (for example, the voltage value of the first initial voltage can be about -2.2V, and the voltage value of the second initial voltage can be about -2.5V), the voltage difference between the driving control node N0 and the first initial voltage terminal I1 is small, and the leakage phenomenon is improved.

[0253] When the pixel circuit is in a high-brightness display mode, since the voltage value of the second low-voltage signal is correspondingly reduced to achieve high brightness, the voltage value of the second initial voltage can also be correspondingly reduced (at this time, the voltage value of the second initial voltage can be related to the voltage value of the second low-voltage signal), and the voltage value of the first initial voltage can be greater than the voltage value of the second initial voltage, so as to reduce or minimize the leakage current from N0 to I1.

[0254] When the pixel circuit is in a low-brightness display mode, since the voltage value of the second low-voltage signal is correspondingly increased to achieve low brightness, the voltage value of the second initial voltage can also be correspondingly increased (at this time, the voltage value of the second initial voltage can be related to the voltage value of the second low-voltage signal), and the voltage value of the second initial voltage can be greater than the voltage value of the first initial voltage, so as to reduce the leakage current from the driving control node to the second initial voltage terminal.

[0255] In at least one embodiment of the present application, “about -2.2V” can mean greater than or equal to -2.3V and less than or equal to -2.1V, but is not limited thereto.

[0256] “About -2.5V” can mean greater than or equal to -2.6V and less than or equal to -2.4V, but is not limited thereto.

[0257] As Figure 9 As Figure 8 At least one embodiment of the pixel circuit shown in the figure is in operation, and the display period can include an initialization stage t1, a data writing stage t2 and a light emitting stage t3 arranged in sequence.

[0258] In the initialization stage t1, S0 provides a low-voltage signal, and T1 and T2 are opened to provide the first initial voltage provided by I1 to N0, so that Td can be opened at the beginning of the data writing stage.

[0259] In the initialization stage t1, S1 provides a low voltage signal, T4 is off, S2 and E1 provide high voltage signals, T5, T6, T7 and T8 are all off;

[0260] In the data writing stage t2, S0 provides a high voltage signal, T1 is on, T2 is off, S1 provides a high voltage signal, T4 is on, S2 provides a low voltage signal, the data voltage Vd provided by D0 is written into N4 through T7;

[0261] At the beginning of the data writing stage t2, Td is on to charge C1 with the data voltage Vd and raise the potential of N0 until the potential of N0 becomes Vd+Vth, and then Td is off, where Vth is the threshold voltage of Td;

[0262] In the data writing stage t2, S2 provides a low voltage signal, T8 is on to write the second initial voltage provided by I2 into the anode of O1 to clear the residual charge in the anode of O1; E1 provides a high voltage signal, and T5 and T6 are both off;

[0263] In the light emitting stage t3, S0 provides a high voltage signal, S1 provides a low voltage signal, T1 is on, T2 is off, T4 is off, S2 provides a high voltage signal, E1 provides a low voltage signal, T7 and T8 are both off, Td, T5 and T6 are all on, and Td drives O1 to emit light.

[0264] Figure 10 At least one embodiment of the pixel circuit shown is different from the pixel circuit shown in Figure 8 At least one embodiment of the pixel circuit shown is different from the pixel circuit shown in

[0265] The source of the first transistor T1 is electrically connected with the second node N2, and the drain of the first transistor T1 is electrically connected with the driving control node N0.

[0266] The drain of the second transistor T2 is electrically connected with the first initial voltage terminal I1, and the source of the second transistor T2 is electrically connected with the second node N2.

[0267] In Figure 10 In at least one embodiment of the pixel circuit shown, T2 and T4 are oxide thin film transistors, and Td, T1, T5, T6, T7 and T8 are all low-temperature polysilicon thin film transistors.

[0268] T2 and T4 are n-type transistors, and Td, T1, T5, T6, T7 and T8 are all p-type transistors.

[0269] In Figure 10At least one embodiment of the pixel circuit shown in the figure is in operation, the initialization of N0 is completed by T1 and T2, wherein T1 is a low-temperature polysilicon thin film transistor, and T2 is an oxide thin film transistor.

[0270] In addition, in Figure 10 In at least one embodiment of the pixel circuit shown in the figure, T1 is a normally-on transistor, which can protect T2; when the potential of N0 jumps, T1 can alleviate the excessive gate-source voltage of T2 by voltage division; at the same time, T1 is equivalent to a stable MOS (metal-oxide-semiconductor) capacitor, which can effectively stabilize the potential of N0, alleviate the interference of the potential of N1, the potential of N4 and the signal line (for example, S0, S1 and S2) on the potential of N0, and improve Flicker (flicker) at low frequency.

[0271] In Figure 10 In at least one embodiment of the pixel circuit shown in the figure,

[0272] △V(N0) = V(N0) x C0z / (C1z + Cm + Cq);

[0273] Wherein, △V(N0) is the change amount of the potential of N0, C0z is the capacitance value of the formed capacitor between N0 and N4, C1z is the capacitance value of C1, Cm is the capacitance value of the parasitic capacitor between the gate of T1 and N0, and Cq is the capacitance value of the formed capacitor between N0 and other nodes except N4; V(N0) is the potential of N0.

[0274] In Figure 10 In at least one embodiment shown in the figure, the voltage value of the first initial voltage provided by I1 can be greater than the voltage value of the second initial voltage provided by I2, there are two transistors in the first leakage path from N0 to I1, and there are three transistors in the second leakage path from N0 to I2. By setting the voltage value of the first initial voltage to be greater than the voltage value of the second initial voltage (for example, the voltage value of the first initial voltage can be about -2.2V, and the voltage value of the second initial voltage can be about -2.5V), the voltage difference between the driving control node N0 and the first initial voltage terminal I1 is small, and the leakage phenomenon is improved.

[0275] When the pixel circuit is in a high-brightness display mode, since the voltage value of the second low-voltage signal is reduced to achieve high brightness, the voltage value of the second initial voltage can also be reduced accordingly (at this time, the voltage value of the second initial voltage can be related to the voltage value of the second low-voltage signal), and the voltage value of the first initial voltage can be greater than the voltage value of the second initial voltage to reduce or minimize the leakage current from N0 to I1.

[0276] When the pixel circuit is in the low brightness display mode, since the voltage value of the second low voltage signal is correspondingly raised to realize low brightness, the voltage value of the second initial voltage can also be correspondingly raised (at this time, the voltage value of the second initial voltage can be related to the voltage value of the second low voltage signal), and the voltage value of the second initial voltage can be greater than the voltage value of the first initial voltage, so that the leakage current of the driving control node to the second initial voltage end is reduced.

[0277] As shown in Figure 11 the pixel circuit shown in Figure 7 at least one embodiment, the light emitting element is an organic light emitting diode O1;

[0278] The driving circuit 71 includes a driving transistor Td, the light emitting control circuit 72 includes a fifth transistor T5 and a sixth transistor T6, the data writing circuit 73 includes a seventh transistor T7, the energy storage circuit 74 includes a storage capacitor C1, and the second initialization circuit 75 includes an eighth transistor T8.

[0279] The first initialization circuit 11 includes a second initialization transistor T2; the compensation circuit includes a first compensation sub-circuit 51 and a second compensation sub-circuit 52; the first compensation sub-circuit 51 includes a third transistor T3, and the second compensation sub-circuit 52 includes a fourth transistor T4.

[0280] The gate of the second transistor T2 is electrically connected with the first initial control end S0, the drain of the second transistor T2 is electrically connected with the first initial voltage end I1, and the source of the second transistor T2 is electrically connected with the driving control node N0.

[0281] The gate of the third transistor T3 is electrically connected with the first low voltage end, the source of the third transistor T3 is electrically connected with the driving control node N0, and the drain of the third transistor T3 is electrically connected with the third node N3; the first low voltage end is used for providing a first low voltage signal V01.

[0282] The gate of the fourth transistor T4 is electrically connected with the compensation control end S1, the drain of the fourth transistor T4 is electrically connected with the third node N3, and the source of the fourth transistor T4 is electrically connected with the first node N1.

[0283] The gate of the driving transistor Td is electrically connected with the driving control node N0, the source of the driving transistor Td is electrically connected with the fourth node N4, and the drain of the driving transistor Td is electrically connected with the first node N1.

[0284] The gate of the fifth transistor T5 is electrically connected with the light-emitting control line E1, the source of the fifth transistor T5 is electrically connected with a high voltage terminal, and the drain of the fifth transistor T5 is electrically connected with the fourth node N4; the high voltage terminal is used for providing a high voltage signal V02;

[0285] The gate of the sixth transistor T6 is electrically connected with the light-emitting control line E1, the source of the sixth transistor T6 is electrically connected with the first node N1, and the drain of the sixth transistor T6 is electrically connected with the anode of O1;

[0286] The control electrode of the seventh transistor T7 is electrically connected with the data write control terminal S2, the source of the seventh transistor T7 is electrically connected with the data line D0, and the drain of the seventh transistor T7 is electrically connected with the fourth node N4;

[0287] The first end of the storage capacitor C1 is electrically connected with the driving control node N0, and the second end of the storage capacitor is electrically connected with the high voltage terminal;

[0288] The gate of the eighth transistor T8 is electrically connected with the data write control terminal S2, the source of the eighth transistor T8 is electrically connected with a second initial voltage terminal I2, and the drain of the eighth transistor T8 is electrically connected with the anode of O1;

[0289] The cathode of O1 is electrically connected with a second low voltage terminal, and the second low voltage terminal is used for providing a second low voltage signal V03.

[0290] In at least one embodiment of the pixel circuit shown in Figure 11 In at least one embodiment of the pixel circuit shown in

[0291] In at least one embodiment of the pixel circuit shown in Figure 11 In at least one embodiment of the pixel circuit shown in

[0292] T2 and T4 are n-type transistors, and T3, Td, T5, T6, T7 and T8 are p-type transistors.

[0293] In at least one embodiment of the pixel circuit shown in Figure 11In at least one embodiment of the pixel circuit shown, T3 is a normally-on transistor, which can protect T4; when the potential of N0 jumps, T3 can alleviate the excessive gate-source voltage of T4 by voltage division; at the same time, T3 is equivalent to a stable MOS capacitor, which can effectively stabilize the potential of N0, alleviate the interference of the potential of N1, the potential of N4 and the signal lines (for example, S0, S1 and S2) on the potential of N0, and improve Flicker at low frequency.

[0294] In Figure 11 In at least one embodiment shown, since the first leakage path from N0 to I1 only includes one low-temperature polysilicon thin film transistor, it is necessary to reduce the leakage of the leakage path from N0 to I1, and the voltage value of the first initial voltage can be set to be greater than the voltage value of the second initial voltage, for example, the voltage value of the first initial voltage can be about -2.2V (in at least one embodiment of the present application, “about -2.2V” can mean greater than or equal to -2.3V and less than or equal to -2.1V, but is not limited thereto), and the voltage value of the second initial voltage can be about -2.5V (in at least one embodiment of the present application, “about -2.5V” can mean greater than or equal to -2.6V and less than or equal to -2.4V, but is not limited thereto).

[0295] When the pixel circuit is in a high-brightness display mode, since the voltage value of the second low-voltage signal is correspondingly reduced to achieve high brightness, the voltage value of the second initial voltage can also be correspondingly reduced (at this time, the voltage value of the second initial voltage can be related to the voltage value of the second low-voltage signal), and the voltage value of the first initial voltage can be greater than the voltage value of the second initial voltage, so as to reduce or minimize the leakage current from N0 to I1.

[0296] When the pixel circuit is in a low-brightness display mode, since the voltage value of the second low-voltage signal is correspondingly increased to achieve low brightness, the voltage value of the second initial voltage can also be correspondingly increased (at this time, the voltage value of the second initial voltage can be related to the voltage value of the second low-voltage signal), and the voltage value of the second initial voltage can be greater than the voltage value of the first initial voltage, so as to reduce the leakage current from the drive control node to the second initial voltage.

[0297] In Figure 11 In at least one embodiment of the pixel circuit shown, the compensation of the threshold voltage of the drive transistor Td is completed by T3 and T4, wherein T3 is a low-temperature polysilicon thin film transistor, and T4 is an oxide thin film transistor.

[0298] As Figure 9 As Figure 11At least one embodiment of the pixel circuit shown in operation, the display period can include sequentially arranged initialization phase t1, data write phase t2 and light-emitting phase t3;

[0299] In the initialization phase t1, S0 provides a low voltage signal, T2 is open, to provide the first initial voltage provided by I1 to N0, so that at the beginning of the data write phase, Td can be open;

[0300] In the initialization phase t1, T3 is open, S1 provides a low voltage signal, T4 is off, S2 and E1 provide a high voltage signal, T5, T6, T7 and T8 are all off;

[0301] In the data write phase t2, S0 provides a high voltage signal, T2 is off, T3 is open, S1 provides a high voltage signal, T4 is open, S2 provides a low voltage signal, the data voltage Vd provided by D0 is written to N4 through T7;

[0302] At the beginning of the data write phase t2, Td is open, to charge C1 through the data voltage Vd, raise the potential of N0, until the potential of N0 becomes Vd+Vth, Td is off, Vth is the threshold voltage of Td;

[0303] In the data write phase t2, S2 provides a low voltage signal, T8 is open, to write the second initial voltage provided by I2 to the anode of O1, to clear the residual charge of the anode of O1; E1 provides a high voltage signal, T5 and T6 are both off;

[0304] In the light-emitting phase t3, S0 provides a high voltage signal, S1 provides a low voltage signal, T2 is off, T3 is open, T4 is off, S2 provides a high voltage signal, E1 provides a low voltage signal, T7 and T8 are both off, Td, T5 and T6 are all open, Td drives O1 to emit light.

[0305] Figure 12 At least one embodiment of the pixel circuit shown is different from Figure 11 At least one embodiment of the pixel circuit shown is different from

[0306] The source of the third transistor T3 is electrically connected with the third node N3, and the drain of the third transistor T3 is electrically connected with the first node N1;

[0307] The drain of the fourth transistor T4 is electrically connected with the driving control node N0, and the source of the fourth transistor T4 is electrically connected with the third node N3.

[0308] In Figure 12In at least one embodiment of the pixel circuit shown, T2 and T4 can be oxide thin film transistors, and T3, Td, T5, T6, T7 and T8 can all be low temperature polysilicon thin film transistors.

[0309] T2 and T4 are n-type transistors, and T3, Td, T5, T6, T7 and T8 are all p-type transistors.

[0310] In at least one embodiment of the pixel circuit shown, the threshold voltage compensation of the driving transistor Td is completed by T3 and T4, wherein T3 is a low temperature polysilicon thin film transistor, and T4 is an oxide thin film transistor. Figure 12 In at least one embodiment of the pixel circuit shown, the threshold voltage compensation of the driving transistor Td is completed by T3 and T4, wherein T3 is a low temperature polysilicon thin film transistor, and T4 is an oxide thin film transistor.

[0311] Figure 12 In at least one embodiment of the pixel circuit shown, the threshold voltage compensation of the driving transistor Td is completed by T3 and T4, wherein T3 is a low temperature polysilicon thin film transistor, and T4 is an oxide thin film transistor.

[0312] Since the first leakage path from N0 to I1 only contains one low temperature polysilicon thin film transistor, it is necessary to reduce the leakage current of the leakage path from N0 to I1. The voltage value of the first initial voltage can be set to be greater than the voltage value of the second initial voltage. For example, the voltage value of the first initial voltage can be about -2.2V (in at least one embodiment of the present application, “about -2.2V” can mean greater than or equal to -2.3V and less than or equal to -2.1V, but is not limited thereto), and the voltage value of the second initial voltage can be about -2.5V (in at least one embodiment of the present application, “about -2.5V” can mean greater than or equal to -2.6V and less than or equal to -2.4V, but is not limited thereto).

[0313] When the pixel circuit is in a high brightness display mode, since the voltage value of the low voltage signal provided by the low voltage terminal V3 is correspondingly reduced to achieve high brightness, the voltage value of the second initial voltage can also be correspondingly reduced (at this time, the voltage value of the second initial voltage can be related to the voltage value of the low voltage signal provided by V3), and the voltage value of the first initial voltage can be greater than the voltage value of the second initial voltage, so as to reduce or minimize the leakage current from N0 to I1.

[0314] When the pixel circuit is in a low brightness display mode, since the voltage value of the low voltage signal provided by the low voltage terminal V3 is correspondingly increased to achieve low brightness, the voltage value of the second initial voltage can also be correspondingly increased (at this time, the voltage value of the second initial voltage can be related to the voltage value of the low voltage signal provided by V3), and the voltage value of the second initial voltage can be greater than the voltage value of the first initial voltage, so as to reduce the leakage current from the driving control node to the second initial voltage terminal.

[0315] As shown in Figure 13 In at least one embodiment of the pixel circuit shown, the threshold voltage compensation of the driving transistor Td is completed by T3 and T4, wherein T3 is a low temperature polysilicon thin film transistor, and T4 is an oxide thin film transistor. Figure 2 ​On the basis of at least one embodiment of the pixel circuit shown, the pixel circuit can further comprise a light emitting element 70, a driving circuit 71, a light emitting control circuit 72, a data writing circuit 73, an energy storage circuit 74 and a second initialization circuit 75, wherein,

[0316] The data writing circuit 73 is electrically connected with a data writing control end S2, a data line D0 and a fourth node N4 respectively, for controlling writing of a data voltage provided by the data line D0 into the fourth node N4 under control of a data writing control signal provided by the data writing control end S2;

[0317] The light emitting control circuit 72 is electrically connected with a light emitting control line E1, a second voltage end V2, the fourth node N4, a first node N1 and the light emitting element 70 respectively, for controlling communication between the fourth node N4 and the second voltage end V2 and controlling communication between the first node N1 and a first pole of the light emitting element 70 under control of a light emitting control signal provided by the light emitting control line E1;

[0318] A first end of the energy storage circuit 74 is electrically connected with the driving control node N0, and a second end of the energy storage circuit 74 is electrically connected with the second voltage end V2, and the energy storage circuit 74 is used for storing electric energy;

[0319] The driving circuit 71 is electrically connected with the driving control node N0, the fourth node N4 and the first node N1 respectively, for generating a driving current flowing from the fourth node N4 to the first node N1 under control of an electric potential of the driving control node N0;

[0320] The second initialization circuit 75 is electrically connected with the data writing control end S2, a second initial voltage end I2 and the first pole of the light emitting element 70 respectively, for controlling writing of a second initial voltage provided by the second initial voltage end I2 into the first pole of the light emitting element 70 under control of the data writing control signal;

[0321] A second pole of the light emitting element 70 is electrically connected with a third voltage end V3.

[0322] As Figure 14 As Figure 13 On the basis of at least one embodiment of the pixel circuit shown, the light emitting element is an organic light emitting diode O1;

[0323] The driving circuit 71 comprises a driving transistor Td, the light emitting control circuit 72 comprises a fifth transistor T5 and a sixth transistor T6, the data writing circuit 73 comprises a seventh transistor T7, the energy storage circuit 74 comprises a storage capacitor C1, and the second initialization circuit 75 comprises an eighth transistor T8;

[0324] The control sub-circuit 31 comprises a first transistor T1, the initialization sub-circuit 32 comprises a second transistor T2; the compensation circuit 12 comprises a fourth transistor T4;

[0325] The gate of the first transistor T1 is electrically connected with a first low voltage end, the source of the first transistor T1 is electrically connected with a compensation node Nc, and the drain of the first transistor T1 is electrically connected with a driving control node N0;

[0326] The gate of the second transistor T2 is electrically connected with the first initial control end S0, the drain of the second transistor T2 is electrically connected with the first initial voltage end I1, and the source of the second transistor T2 is electrically connected with the compensation node Nc;

[0327] The gate of the fourth transistor T4 is electrically connected with a compensation control end S1, the drain of the fourth transistor T4 is electrically connected with the compensation node Nc, and the source of the fourth transistor T4 is electrically connected with the first node N1;

[0328] The gate of the driving transistor Td is electrically connected with the driving control node N0, the source of the driving transistor Td is electrically connected with the fourth node N4, and the drain of the driving transistor Td is electrically connected with the first node N1;

[0329] The gate of the fifth transistor T5 is electrically connected with the light-emitting control line E1, the source of the fifth transistor T5 is electrically connected with a high voltage end, and the drain of the fifth transistor T5 is electrically connected with the fourth node N4; the high voltage end is used for providing a high voltage signal V02;

[0330] The gate of the sixth transistor T6 is electrically connected with the light-emitting control line E1, the source of the sixth transistor T6 is electrically connected with the first node N1, and the drain of the sixth transistor T6 is electrically connected with the anode of O1;

[0331] The gate of the seventh transistor T7 is electrically connected with the data write control end S2, the source of the seventh transistor T7 is electrically connected with the data line D0, and the drain of the seventh transistor T7 is electrically connected with the fourth node N4;

[0332] The first end of the storage capacitor C1 is electrically connected with the driving control node N0, and the second end of the storage capacitor is electrically connected with the high voltage end;

[0333] The gate of the eighth transistor T8 is electrically connected with the data write control end S2, the source of the eighth transistor T8 is electrically connected with a second initial voltage end I2, and the drain of the eighth transistor T8 is electrically connected with the anode of O1;

[0334] The cathode of O1 is electrically connected to a second low voltage terminal for providing a second low voltage signal V03. In Figure 14 In at least one embodiment of the pixel circuit shown, T1, Td, T5, T6, T7 and T8 are low temperature polysilicon thin film transistors, and T2 and T4 are oxide thin film transistors.

[0335] In Figure 14 In at least one embodiment of the pixel circuit shown, the first voltage terminal is a first low voltage terminal, the second voltage terminal is a high voltage terminal, and the third voltage terminal is a second low voltage terminal.

[0336] In Figure 14 In at least one embodiment of the pixel circuit shown, T1 is a normally-on transistor.

[0337] In Figure 14 In at least one embodiment of the pixel circuit shown, T1 is a normally-on transistor, which can protect T2. When the potential of N0 jumps, T1 can alleviate the gate-source voltage of T2 by voltage division. Meanwhile, T1 is equivalent to a stable MOS (Metal-Oxide-Semiconductor) capacitor, which can effectively stabilize the potential of N0 and alleviate the interference of the potential of N0 by the potential of N1, the potential of N4 and the signal lines (e.g., S0, S1 and S2), especially at low frequency, which can improve Flicker.

[0338] In Figure 14 In at least one embodiment shown, the voltage value of the first initial voltage provided by I1 can be greater than the voltage value of the second initial voltage provided by I2. There are two transistors in the first leakage path from N0 to I1, and there are four transistors in the second leakage path from N0 to I2. By setting the voltage value of the first initial voltage to be greater than the voltage value of the second initial voltage (e.g., the voltage value of the first initial voltage can be about -2.2V, and the voltage value of the second initial voltage can be about -2.5V), the voltage difference between the driving control node N0 and the first initial voltage terminal I1 is small, and the leakage phenomenon is improved.

[0339] When the pixel circuit is in a high brightness display mode, since the voltage value of the second low voltage signal is reduced to achieve high brightness, the voltage value of the second initial voltage can also be reduced accordingly (at this time, the voltage value of the second initial voltage can be related to the voltage value of the second low voltage signal), and the voltage value of the first initial voltage can be greater than the voltage value of the second initial voltage to reduce or minimize the leakage current from N0 to I1.

[0340] When the pixel circuit is in the low brightness display mode, the voltage value of the second initial voltage can be raised accordingly (at this time, the voltage value of the second initial voltage can be related to the voltage value of the second low voltage signal) since the voltage value of the second low voltage signal is raised to realize low brightness, and the voltage value of the second initial voltage can be greater than the voltage value of the first initial voltage, so that the leakage current of the driving control node to the second initial voltage is reduced.

[0341] As shown in Figure 9 As shown in Figure 14 At least one embodiment of the pixel circuit as shown in

[0342] In the initialization stage t1, S0 provides a low voltage signal, T2 is turned on, T1 is turned on, and the first initial voltage provided by I1 is provided to N0, so that Td can be turned on at the beginning of the data writing stage;

[0343] In the initialization stage t1, S1 provides a low voltage signal, T4 is turned off, S2 and E1 provide high voltage signals, and T5, T6, T7 and T8 are all turned off;

[0344] In the data writing stage t2, S0 provides a high voltage signal, T2 is turned off, S1 provides a high voltage signal, T4 is turned on, and T1 is turned on to enable communication between N1 and N0; S2 provides a low voltage signal, and the data voltage Vd provided by D0 is written to N4 through T7;

[0345] At the beginning of the data writing stage t2, Td is turned on to charge C1 through the data voltage Vd, raise the potential of N0, until the potential of N0 becomes Vd+Vth, Td is turned off, and Vth is the threshold voltage of Td;

[0346] In the data writing stage t2, S2 provides a low voltage signal, and T8 is turned on to write the second initial voltage provided by I2 to the anode of O1 to clear the residual charge of the anode of O1; E1 provides a high voltage signal, and T5 and T6 are both turned off;

[0347] In the light emitting stage t3, S0 provides a high voltage signal, S1 provides a low voltage signal, T2 is turned off, T4 is turned off, S2 provides a high voltage signal, E1 provides a low voltage signal, T7 and T8 are both turned off, Td, T5 and T6 are all turned on, and Td drives O1 to emit light.

[0348] The pixel driving method provided by the embodiment of the present application is applied to the pixel circuit described above, and the display period includes the initialization stage and the data writing stage arranged in sequence; the pixel driving method includes:

[0349] In the initialization stage, the first initialization circuit controls the first initial voltage terminal to provide a first initial voltage to the driving control node under control of a first initial control signal provided at a first initial control terminal;

[0350] In the data writing stage, the compensation circuit controls the compensation node to be in communication with the first node under control of a compensation control signal provided at a compensation control terminal.

[0351] In the pixel circuit to which the pixel driving method in the embodiments of the present application is applied, at least one of the first initialization circuit and the compensation circuit comprises an oxide thin film transistor and a low-temperature polysilicon thin film transistor connected in series with each other, so that the circuit for initializing the potential of the driving control node and / or the circuit for compensation comprises not only the oxide thin film transistor but also the low-temperature polysilicon thin film transistor.

[0352] Optionally, the driving control node and the compensation node can be the same node.

[0353] Optionally, the driving control node and the compensation node are different nodes, and the first initialization circuit is further electrically connected with a first voltage terminal; the first initialization circuit comprises a control sub-circuit and an initialization sub-circuit.

[0354] The first initialization circuit controls the first initial voltage terminal to provide a first initial voltage to the driving control node under control of a first initial control signal provided at a first initial control terminal, and the step can comprise: the control sub-circuit controls the driving control node to be in communication with the compensation node under control of a first voltage signal provided at the first voltage terminal; and the initialization sub-circuit controls the first initial voltage to be written into the compensation node under control of the first initial control signal.

[0355] The pixel driving method in at least one of the embodiments of the present application can further comprise: in the data writing stage, the control sub-circuit controls the driving control node to be in communication with the compensation node under control of a first voltage signal provided at the first voltage terminal, so that the first node is in communication with the driving control node.

[0356] In at least one of the embodiments of the present application, when the driving control node and the compensation node are the same node, the first initialization circuit is further electrically connected with a first voltage terminal; the first initialization circuit comprises a control sub-circuit and an initialization sub-circuit, and the step of the first initialization circuit controlling the first initial voltage terminal to provide a first initial voltage to the driving control node under control of a first initial control signal provided at a first initial control terminal comprises:

[0357] The control sub-circuit controls the writing of the first initial voltage into the second node under the control of a first voltage signal provided by the first voltage terminal; and the initialization sub-circuit controls the communication between the second node and the driving control node under the control of the first initial control signal.

[0358] In a specific implementation, the first initialization circuit can include a control sub-circuit and an initialization sub-circuit, the control sub-circuit controls the communication between the driving control node and the second node, and the initialization sub-circuit controls the writing of the first initial voltage into the second node to control the writing of the first initial voltage into the driving control node.

[0359] In at least one embodiment of the present application, when the driving control node and the compensation node are the same node, the first initialization circuit is further electrically connected to the first voltage terminal; the first initialization circuit includes a control sub-circuit and an initialization sub-circuit, and the first initialization circuit controls the first initial voltage terminal to provide a first initial voltage to the driving control node under the control of a first initial control signal provided by the first initial control terminal, and the step of controlling the first initial voltage terminal to provide a first initial voltage to the driving control node includes:

[0360] The control sub-circuit controls the communication between the driving control node and the second node under the control of a first voltage signal provided by the first voltage terminal; and the initialization sub-circuit controls the writing of the first initial voltage into the second node under the control of the first initial control signal.

[0361] In a specific implementation, the first initialization circuit can include a control sub-circuit and an initialization sub-circuit, the control sub-circuit controls the communication between the driving control node and the second node, and the initialization sub-circuit controls the writing of the first initial voltage into the second node to control the writing of the first initial voltage into the driving control node.

[0362] Optionally, the compensation circuit is further electrically connected to the first voltage terminal, and the compensation circuit includes a first compensation sub-circuit and a second compensation sub-circuit; the compensation circuit controls the communication between the driving control node and the first node under the control of a compensation control signal provided by the compensation control terminal, and the step of controlling the communication between the driving control node and the first node under the control of the compensation control signal includes:

[0363] The first compensation sub-circuit controls the communication between the driving control node and the third node under the control of a first voltage signal provided by the first voltage terminal; and the second compensation sub-circuit controls the communication between the third node and the first node under the control of the compensation control signal.

[0364] In a specific implementation, the compensation circuit can include a first compensation sub-circuit and a second compensation sub-circuit, the first compensation sub-circuit controls the communication between the driving control node and the third node, and the second compensation sub-circuit controls the communication between the third node and the first node to control the communication between the driving control node and the first node.

[0365] Optionally, the compensation circuit is further electrically connected with the first voltage terminal, and the compensation circuit comprises a first compensation sub-circuit and a second compensation sub-circuit; under the control of a compensation control signal provided by a compensation control terminal, the compensation circuit controls the communication between the driving control node and the first node to include the following steps:

[0366] The first compensation sub-circuit controls the communication between the third node and the first node under the control of a first voltage signal provided by the first voltage terminal; and the second compensation sub-circuit controls the communication between the third node and the driving control node under the control of the compensation control signal.

[0367] In a specific implementation, the compensation circuit can comprise a first compensation sub-circuit and a second compensation sub-circuit, the first compensation sub-circuit controls the communication between the third node and the first node, and the second compensation sub-circuit controls the communication between the third node and the driving control node, so as to control the communication between the driving control node and the first node.

[0368] The display device provided by the embodiment of the present application comprises the pixel circuit.

[0369] The display device provided by the embodiment of the present application can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, etc.

[0370] The above describes the preferred embodiments of the present application. It should be noted that, for those skilled in the art, without departing from the principles of the present application, a number of improvements and refinements can be made, and these improvements and refinements should also be considered as falling within the scope of protection of the present application.

Claims

1. A pixel circuit, comprising a first initialization circuit and a compensation circuit; The first initialization circuit is electrically connected to the drive control node, the first initial control terminal, and the first initial voltage terminal, respectively, and is used to control the first initial voltage terminal to provide a first initial voltage to the drive control node under the control of the first initial control signal provided by the first initial control terminal; The compensation circuit is electrically connected to the compensation control terminal, the compensation node and the first node respectively, and is used to control the connection between the compensation node and the first node under the control of the compensation control signal provided by the compensation control terminal; At least one of the first initialization circuit and the compensation circuit includes an oxide thin-film transistor and a low-temperature polycrystalline silicon thin-film transistor connected in series. The first initialization circuit is electrically connected to the first voltage terminal and operates under the control of the first voltage signal provided by the first voltage terminal. The transistor whose gate is electrically connected to the first voltage terminal in the first initialization circuit is a normally open transistor. Alternatively, the compensation circuit is electrically connected to the first voltage terminal and operates under the control of the first voltage signal provided by the first voltage terminal. The transistor whose gate is electrically connected to the first voltage terminal in the compensation circuit is a normally open transistor. The first voltage terminal is a DC voltage terminal; The pixel circuit also includes a light-emitting element and a second initialization circuit; The second initialization circuit is electrically connected to the data write control terminal, the second initial voltage terminal, and the first electrode of the light-emitting element, respectively, and is used to control the writing of the second initial voltage provided by the second initial voltage terminal to the first electrode of the light-emitting element under the control of the data write control signal provided by the data write control terminal; the second electrode of the light-emitting element is electrically connected to the third voltage terminal; In high-brightness display mode, the voltage value of the third voltage signal provided by the third voltage terminal is reduced, the voltage value of the first initial voltage is greater than the voltage value of the second initial voltage, and the number of transistors in the first leakage path from the drive control node to the first initial voltage terminal is less than the number of transistors in the second leakage path from the drive control node to the second initial voltage terminal, so that the voltage difference between the drive control node and the first initial voltage terminal is smaller. In low brightness display mode, the voltage value of the third voltage signal is increased, and the voltage value of the second initial voltage is greater than the voltage value of the first initial voltage, so that the leakage current from the drive control node to the second initial voltage terminal is reduced accordingly.

2. The pixel circuit as described in claim 1, wherein, The compensation node and the drive control node are the same node.

3. The pixel circuit as described in claim 1, wherein, The compensation node and the drive control node are different nodes; The first initialization circuit is also electrically connected to the first voltage terminal; the first initialization circuit includes a control sub-circuit and an initialization sub-circuit, wherein, The control sub-circuit is electrically connected to the first voltage terminal, the drive control node, and the compensation node, respectively, and is used to control the connection between the drive control node and the compensation node under the control of the first voltage signal provided by the first voltage terminal; The initialization sub-circuit is electrically connected to the first initial control terminal, the first initial voltage terminal, and the compensation node, respectively, and is used to control the writing of the first initial voltage to the compensation node under the control of the first initial control signal.

4. The pixel circuit as described in claim 3, wherein, The control sub-circuit includes a first transistor, and the initialization sub-circuit includes a second transistor; The control electrode of the first transistor is electrically connected to the first voltage terminal, the first electrode of the first transistor is electrically connected to the compensation node, and the second electrode of the first transistor is electrically connected to the drive control node. The control electrode of the second transistor is electrically connected to the first initial control terminal, the first electrode of the second transistor is electrically connected to the first initial voltage terminal, and the second electrode of the second transistor is electrically connected to the compensation node. The first transistor is a low-temperature polycrystalline silicon thin-film transistor, and the second transistor is an oxide thin-film transistor; The first voltage terminal is the first low voltage terminal.

5. The pixel circuit as described in claim 2, wherein, The first initialization circuit is also electrically connected to the first voltage terminal; the first initialization circuit includes a control sub-circuit and an initialization sub-circuit, wherein, The control sub-circuit is electrically connected to the first voltage terminal, the first initial voltage terminal, and the second node, respectively, and is used to control the writing of the first initial voltage to the second node under the control of the first voltage signal provided by the first voltage terminal. The initialization sub-circuit is electrically connected to the first initial control terminal, the second node, and the drive control node, respectively, and is used to control the second node to connect with the drive control node under the control of the first initial control signal.

6. The pixel circuit as described in claim 5, wherein, The control sub-circuit includes a first transistor, and the initialization sub-circuit includes a second transistor, wherein... The control electrode of the first transistor is electrically connected to the first voltage terminal, the first electrode of the first transistor is electrically connected to the first initial voltage terminal, and the second electrode of the first transistor is electrically connected to the second node. The control electrode of the second transistor is electrically connected to the first initial control terminal, the first electrode of the second transistor is electrically connected to the second node, and the second electrode of the second transistor is electrically connected to the drive control node. The first transistor is a low-temperature polycrystalline silicon thin-film transistor, and the second transistor is an oxide thin-film transistor; The first voltage terminal is the first low voltage terminal.

7. The pixel circuit as described in claim 2, wherein, The first initialization circuit is also electrically connected to the first voltage terminal; the first initialization circuit includes a control sub-circuit and an initialization sub-circuit, wherein, The first initialization circuit is electrically connected to the first voltage terminal, the drive control node, and the second node, respectively, and is used to control the connection between the drive control node and the second node under the control of the first voltage signal provided by the first voltage terminal; The second initialization circuit is electrically connected to the first initial control terminal, the first initial voltage terminal, and the second node, respectively, and is used to control the writing of the first initial voltage to the second node under the control of the first initial control signal.

8. The pixel circuit as described in claim 7, wherein, The control sub-circuit includes a first transistor, and the initialization sub-circuit includes a second transistor; The control electrode of the first transistor is electrically connected to the first voltage terminal, the first electrode of the first transistor is electrically connected to the second node, and the second electrode of the first transistor is electrically connected to the drive control node. The control electrode of the second transistor is electrically connected to the first initial control terminal, the first electrode of the second transistor is electrically connected to the first initial voltage terminal, and the second electrode of the second transistor is electrically connected to the second node. The first transistor is a low-temperature polycrystalline silicon thin-film transistor, and the second transistor is an oxide thin-film transistor; The first voltage terminal is the first low voltage terminal.

9. The pixel circuit according to any one of claims 1 to 8, wherein, The compensation circuit is also electrically connected to the first voltage terminal, and the compensation circuit includes a first compensation sub-circuit and a second compensation sub-circuit. The first compensation sub-circuit is electrically connected to the first voltage terminal, the compensation node, and the third node, respectively, and is used to control the connection between the compensation node and the third node under the control of the first voltage signal provided by the first voltage terminal; The second compensation sub-circuit is electrically connected to the compensation control terminal, the third node, and the first node, respectively, and is used to control the connection between the third node and the first node under the control of the compensation control signal.

10. The pixel circuit as claimed in claim 9, wherein, The first compensation sub-circuit includes a third transistor, and the second compensation sub-circuit includes a fourth transistor; The control electrode of the third transistor is electrically connected to the first voltage terminal, the first electrode of the third transistor is electrically connected to the compensation node, and the second electrode of the third transistor is electrically connected to the third node. The control electrode of the fourth transistor is electrically connected to the compensation control terminal, the first electrode of the fourth transistor is electrically connected to the third node, and the second electrode of the fourth transistor is electrically connected to the first node. The third transistor is an oxide thin-film transistor, and the fourth transistor is a low-temperature polycrystalline silicon thin-film transistor.

11. The pixel circuit according to any one of claims 1 to 8, wherein, The compensation circuit is also electrically connected to the first voltage terminal, and the compensation circuit includes a first compensation sub-circuit and a second compensation sub-circuit. The first compensation sub-circuit is electrically connected to the first voltage terminal, the third node, and the first node respectively, and is used to control the connection between the third node and the first node under the control of the first voltage signal provided by the first voltage terminal; The second compensation sub-circuit is electrically connected to the compensation control terminal, the third node, and the compensation node, respectively, and is used to control the connection between the third node and the compensation node under the control of the compensation control signal.

12. The pixel circuit as claimed in claim 11, wherein, The first compensation sub-circuit includes a third transistor, and the second compensation sub-circuit includes a fourth transistor; The control electrode of the third transistor is electrically connected to the first voltage terminal, the first electrode of the third transistor is electrically connected to the third node, and the second electrode of the third transistor is electrically connected to the first node. The control electrode of the fourth transistor is electrically connected to the compensation control terminal, the first electrode of the fourth transistor is electrically connected to the compensation node, and the second electrode of the fourth transistor is electrically connected to the third node. The third transistor is an oxide thin-film transistor, and the fourth transistor is a low-temperature polycrystalline silicon thin-film transistor.

13. The pixel circuit according to any one of claims 1 to 8, wherein, It also includes light-emitting elements, driving circuits, light-emitting control circuits, data writing circuits, and energy storage circuits, among which, The data writing circuit is electrically connected to the data writing control terminal, the data line and the fourth node respectively, and is used to control the data voltage provided by the data line to be written to the fourth node under the control of the data writing control signal provided by the data writing control terminal. The light-emitting control circuit is electrically connected to the light-emitting control line, the second voltage terminal, the fourth node, the first node, and the light-emitting element, respectively. It is used to control the connection between the fourth node and the second voltage terminal and the connection between the first node and the light-emitting element under the control of the light-emitting control signal provided by the light-emitting control line. The first terminal of the energy storage circuit is electrically connected to the drive control node, and the second terminal of the energy storage circuit is electrically connected to the second voltage terminal. The energy storage circuit is used to store electrical energy. The driving circuit is electrically connected to the driving control node, the fourth node, and the first node, respectively, and is used to generate a driving current flowing from the fourth node to the first node under the control of the potential of the driving control node.

14. The pixel circuit as claimed in claim 13, wherein, The driving circuit includes a driving transistor, the light-emitting control circuit includes a fifth transistor and a sixth transistor, the data writing circuit includes a seventh transistor, and the energy storage circuit includes a storage capacitor. The control electrode of the driving transistor is electrically connected to the driving control node, the first electrode of the driving transistor is electrically connected to the fourth node, and the second electrode of the driving transistor is electrically connected to the first node. The control electrode of the fifth transistor is electrically connected to the light-emitting control line, the first electrode of the fifth transistor is electrically connected to the second voltage terminal, and the second electrode of the fifth transistor is electrically connected to the fourth node. The control electrode of the sixth transistor is electrically connected to the light-emitting control line, the first electrode of the sixth transistor is electrically connected to the first node, and the second electrode of the sixth transistor is electrically connected to the light-emitting element. The control electrode of the seventh transistor is electrically connected to the data write control terminal, the first electrode of the seventh transistor is electrically connected to the data line, and the second electrode of the seventh transistor is electrically connected to the fourth node. The first end of the storage capacitor is electrically connected to the drive control node, and the second end of the storage capacitor is electrically connected to the second voltage terminal.

15. The pixel circuit as claimed in claim 1, wherein, The second initialization circuit includes an eighth transistor; The control electrode of the eighth transistor is electrically connected to the data writing control terminal, the first electrode of the eighth transistor is electrically connected to the second initial voltage terminal, and the second electrode of the eighth transistor is electrically connected to the first electrode of the light-emitting element. The eighth transistor is a low-temperature polycrystalline silicon thin-film transistor.

16. A pixel driving method, applied to a pixel circuit as described in any one of claims 1 to 15, wherein the display cycle includes an initialization phase and a data writing phase set sequentially; The pixel driving method includes: During the initialization phase, the first initialization circuit, under the control of the first initial control signal provided by the first initial control terminal, controls the first initial voltage terminal to provide the first initial voltage to the drive control node; During the data writing phase, the compensation circuit controls the connection between the compensation node and the first node under the control of the compensation control signal provided by the compensation control terminal. In high-brightness display mode, the voltage value of the third voltage signal provided by the control third voltage terminal is reduced, the voltage value of the first initial voltage is set to be greater than the voltage value of the second initial voltage, and the number of transistors in the first leakage path from the drive control node to the first initial voltage terminal is less than the number of transistors in the second leakage path from the drive control node to the second initial voltage terminal, so that the voltage difference between the drive control node and the first initial voltage terminal is small. In low brightness display mode, the voltage value of the third voltage signal is increased, and the voltage value of the second initial voltage is set to be greater than that of the first initial voltage, so that the leakage current from the drive control node to the second initial voltage terminal is reduced accordingly.

17. The pixel driving method as described in claim 16, wherein, The drive control node and the compensation node are the same node; or... The drive control node and the compensation node are different nodes. The first initialization circuit is also electrically connected to the first voltage terminal. The first initialization circuit includes a control sub-circuit and an initialization sub-circuit. The first initialization circuit, under the control of the first initial control signal provided by the first initial control terminal, controls the first initial voltage terminal to provide a first initial voltage to the drive control node. The steps include: the control sub-circuit, under the control of the first voltage signal provided by the first voltage terminal, controls the connection between the drive control node and the compensation node; the initialization sub-circuit, under the control of the first initial control signal, controls the writing of the first initial voltage to the compensation node.

18. The pixel driving method as described in claim 16, wherein, The drive control node and the compensation node are the same node; the first initialization circuit is also electrically connected to the first voltage terminal; the first initialization circuit includes a control sub-circuit and an initialization sub-circuit, and the first initialization circuit, under the control of the first initial control signal provided by the first initial control terminal, controls the first initial voltage terminal to provide a first initial voltage to the drive control node, including the following steps: Under the control of the first voltage signal provided by the first voltage terminal, the control sub-circuit controls the writing of the first initial voltage to the second node; under the control of the first initial control signal, the initialization sub-circuit controls the connection between the second node and the drive control node.

19. The pixel driving method as described in claim 16, wherein, The drive control node and the compensation node are the same node; the first initialization circuit is also electrically connected to the first voltage terminal; the first initialization circuit includes a control sub-circuit and an initialization sub-circuit, and the first initialization circuit, under the control of the first initial control signal provided by the first initial control terminal, controls the first initial voltage terminal to provide a first initial voltage to the drive control node, including the following steps: The control sub-circuit, under the control of the first voltage signal provided by the first voltage terminal, controls the connection between the drive control node and the second node; the initialization sub-circuit, under the control of the first initial control signal, controls the writing of the first initial voltage into the second node.

20. The pixel driving method as described in claim 16 or 17, wherein, The compensation circuit is also electrically connected to the first voltage terminal, and the compensation circuit includes a first compensation sub-circuit and a second compensation sub-circuit; the step of controlling the connection between the compensation node and the first node under the control of the compensation control signal provided by the compensation control terminal includes: The first compensation sub-circuit, under the control of the first voltage signal provided at the first voltage terminal, controls the connection between the compensation node and the third node; the second compensation sub-circuit, under the control of the compensation control signal, controls the connection between the third node and the first node.

21. The pixel driving method as described in claim 16 or 17, wherein, The compensation circuit is also electrically connected to the first voltage terminal, and the compensation circuit includes a first compensation sub-circuit and a second compensation sub-circuit; the step of controlling the connection between the compensation node and the first node under the control of the compensation control signal provided by the compensation control terminal includes: The first compensation sub-circuit controls the connection between the third node and the first node under the control of the first voltage signal provided by the first voltage terminal; the second compensation sub-circuit controls the connection between the third node and the compensation node under the control of the compensation control signal.

22. A display device comprising a pixel circuit as described in any one of claims 1 to 15.

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