Multiplexer and electronic device

Abstract

The invention provides a multiplexer and an electronic device. The multiplexer comprises a substrate and at least one oxide thin film transistor arranged on the substrate, the oxide thin film transistor comprises a first grid electrode, a second grid electrode, an active layer, a source electrode and a drain electrode which are arranged on a substrate. The active layer is arranged on the side, away from the substrate, of the first grid electrode, and a first interlayer insulating layer is arranged between the active layer and the first grid electrode; the second grid electrode is arranged on one side, deviating from the first grid electrode, of the active layer, and a second interlayer insulating layer is arranged between the active layer and the second grid electrode; the source electrode is connected with the source electrode contact region of the active layer, and the drain electrode is connected with the drain electrode contact region of the active layer; wherein the orthographic projection, on the substrate, of the second grid electrode of the oxide thin film transistor is located in the orthographic projection, on the substrate, of the first grid electrode, and the orthographic projection, on the substrate, of the first grid electrode is located in the orthographic projection, on the substrate, of the active layer.

Description

Technical Field

[0001] This disclosure belongs to the field of display technology, specifically relating to a multiplexer and electronic device. Background Technology

[0002] In the field of semiconductor displays, achieving high mobility is a constant pursuit. Higher mobility means that electrons can travel faster in semiconductor materials. With the same device size, high mobility can achieve higher quality display images and a longer lifespan.

[0003] Currently, commonly used active semiconductor materials in the semiconductor display field include amorphous silicon (a-Si), metal oxide IGZO (Indium Gallium Zinc Oxide), and low-temperature polycrystalline silicon (LTPS). The mobility of these three materials is approximately 1 cm⁻¹. 2 / V*s、10cm 2 / V*s and 80cm 2 / V*s, where LTPS exhibits a significant mobility advantage. For metal oxide IGZO, related technologies have improved its mobility to 20–50 cm⁻¹ by increasing the In element ratio and adding Sn element. 2 / V*s, but this is still somewhat different from LTPS.

[0004] To improve the channel carrier migration capability of metal oxide IGZO, metal oxide TFTs (Thin Film Transistors) have been fabricated into dual-gate devices with a top gate and a bottom gate, which has been verified to achieve the Mob50 effect. However, the power consumption of such dual-gate devices is much higher than that of LTPS devices. Summary of the Invention

[0005] The present invention aims to solve at least one of the technical problems existing in the prior art, and to provide a multiplexer and electronic device.

[0006] This disclosure provides a multiplexer including a substrate and at least one oxide thin-film transistor disposed on the substrate. The oxide thin-film transistor includes a first gate, a second gate, an active layer, a source, and a drain disposed on the substrate. The active layer is disposed on a side of the first gate opposite to the substrate, and a first interlayer insulating layer is disposed between the active layer and the first gate. The second gate is disposed on a side of the active layer opposite to the first gate, and a second interlayer insulating layer is disposed between the active layer and the second gate. The source is connected to a source contact region of the active layer, and the drain is connected to a drain contact region of the active layer.

[0007] The orthographic projection of the second gate of the oxide thin-film transistor on the substrate is located within the orthographic projection of the first gate on the substrate, and the orthographic projection of the first gate on the substrate is located within the orthographic projection of the active layer on the substrate.

[0008] In the oxide thin-film transistor, the first gate has a first side portion near the source and opposite to the source, and a second side portion near the drain and opposite to the drain; the second gate has a third side portion near the source and opposite to the source, and a fourth side portion near the drain and opposite to the drain; the distance between the orthographic projections of the first side portion and the third side portion on the substrate is a first distance, and the distance between the orthographic projections of the second side portion and the fourth side portion on the substrate is a second distance; at least one of the first distance and the second distance is not less than 2 μm.

[0009] In the oxide thin-film transistor, the first gate has a first side portion near the source and opposite to the source, and a second side portion near the drain and opposite to the drain; the second gate has a third side portion near the source and opposite to the source, and a fourth side portion near the drain and opposite to the drain; the distance between the orthographic projections of the first side portion and the third side portion on the substrate is a first distance, and the distance between the orthographic projections of the second side portion and the fourth side portion on the substrate is a second distance; the first distance and the second distance are equal.

[0010] The oxide thin-film transistor further includes a third interlayer insulating layer located on the side of the second gate and the active layer opposite to the first gate. A first connection via and a second connection via are formed on the third interlayer insulating layer. The first connection via exposes the source contact region of the active layer, and the second connection via exposes the drain contact region of the active layer.

[0011] The orthographic projection of the first gate on the substrate is located between the orthographic projections of the first connection via and the second connection via on the substrate.

[0012] In the oxide thin-film transistor, there is a third spacing between the first gate and the source as projected onto the substrate, and a fourth spacing between the first gate and the drain as projected onto the substrate; at least one of the third spacing and the fourth spacing is not less than 1 μm.

[0013] Specifically, for the oxide thin-film transistor, there is a third spacing between the first gate and the source as projected onto the substrate, and a fourth spacing between the first gate and the drain as projected onto the substrate; both the third spacing and the fourth spacing are not less than 2 μm.

[0014] The number of oxide thin-film transistors is two, namely a first thin-film transistor and a second thin-film transistor, and the first thin-film transistor and the second thin-film transistor share the same source.

[0015] The active layer is made of metal oxide.

[0016] The second gate and the second interlayer insulating layer are completely overlapped in their orthogonal projections on the substrate.

[0017] The oxide thin-film transistor further includes a third interlayer insulating layer located on the side of the second gate and the active layer opposite to the first gate. The source is connected to the source contact region of the active layer through a first connection via penetrating the third interlayer insulating layer, and the drain is connected to the drain contact region of the active layer through a second connection via penetrating the third interlayer insulating layer.

[0018] There are multiple first connection vias, which are spaced apart; there are also multiple second connection vias, which are spaced apart.

[0019] This disclosure provides an electronic device that includes any of the multiplexers described above. Attached Figure Description

[0020] Figure 1 This is a cross-sectional schematic diagram of an oxide thin-film transistor in a related technology;

[0021] Figure 2 This is a top view schematic diagram of an oxide thin-film transistor in related technologies;

[0022] Figure 3 This is a cross-sectional schematic diagram of a multiplexer in related technologies;

[0023] Figure 4 This is a top view of a multiplexer in related technologies;

[0024] Figure 5 This is a cross-sectional schematic diagram of an oxide thin-film transistor according to the first embodiment of this disclosure;

[0025] Figure 6 This is a top view schematic diagram of an oxide thin-film transistor according to the first embodiment of this disclosure;

[0026] Figure 7 This is a cross-sectional schematic diagram of the multiplexer according to the first embodiment of this disclosure;

[0027] Figure 8 This is a top view schematic diagram of the multiplexer according to the first embodiment of this disclosure;

[0028] Figure 9 This is a cross-sectional schematic diagram of an oxide thin-film transistor according to a second embodiment of the present disclosure;

[0029] Figure 10 This is a top view schematic diagram of an oxide thin-film transistor according to a second embodiment of the present disclosure;

[0030] Figure 11 This is a cross-sectional schematic diagram of the multiplexer according to the second embodiment of this disclosure;

[0031] Figure 12 This is a top view schematic diagram of a multiplexer according to the second embodiment of this disclosure;

[0032] Figure 13 This is a cross-sectional schematic diagram of the multiplexer according to the third embodiment of this disclosure;

[0033] Figure 14 This is a top view of a multiplexer according to a third embodiment of the present disclosure. Detailed Implementation

[0034] To enable those skilled in the art to better understand the technical solution of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0035] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0036] like Figure 1 and Figure 2 The image shown is a schematic diagram of an oxide thin-film transistor in the related technology. Figure 1 for Figure 2 A schematic diagram of section AA. (See diagram below.) Figure 3 and Figure 4 The diagram shown is a schematic of a multiplexer in related technologies. Figure 3 for Figure 4 A schematic diagram of the BB section. (See attached diagram.) Figure 3 and Figure 4 As shown, a multiplexer includes a substrate 10 and at least one oxide thin-film transistor disposed on the substrate 10.

[0037] like Figure 1 and Figure 2 As shown, the oxide thin-film transistor includes a first gate 20, a second gate 30, an active layer 40, a source 50, and a drain 60 disposed on a substrate 10; the active layer 40 is disposed on the side of the first gate 20 away from the substrate 10, and a first interlayer insulating layer 70 is disposed between the active layer 40 and the first gate 20; the second gate 30 is disposed on the side of the active layer 40 away from the first gate 20, and a second interlayer insulating layer 80 is disposed between the active layer 40 and the second gate 30; the source 50 is connected to the source contact region of the active layer 40, and the drain 60 is connected to the drain contact region of the active layer 40.

[0038] In related technologies, the orthographic projection of the second gate 30 of the oxide thin film transistor onto the substrate 10 is located within the orthographic projection of the first gate 20 onto the substrate 10, and the orthographic projection of the active layer 40 onto the substrate 10 is located within the orthographic projection of the first gate 20 onto the substrate 10.

[0039] like Figure 1 As shown, the oxide thin-film transistor also includes a third interlayer insulating layer 90 located on the side of the second gate 30 and the active layer 40 opposite to the first gate 20. The source 50 is connected to the source contact region of the active layer 40 through a first connection via H1 penetrating the third interlayer insulating layer 90, and the drain 60 is connected to the drain contact region of the active layer 40 through a second connection via H2 penetrating the third interlayer insulating layer 90. Figure 2 As shown, there are multiple first connecting vias H1, which are spaced apart; and there are multiple second connecting vias H2, which are also spaced apart. Figure 2 In the middle, multiple first connection vias H1 are arranged side by side along the extension direction of the source electrode 50, and multiple second connection vias H2 are arranged side by side along the extension direction of the drain electrode 60.

[0040] like Figure 2As shown, the first gate 20 and the second gate 30 can be connected via a gate connection via H penetrating the first interlayer insulating layer 70 and the second interlayer insulating layer 80. The orthographic projection of the gate connection via H onto the substrate 10 does not overlap with the orthographic projection of the active layer 40 onto the substrate 10. Thus, when a potential is applied to either the first gate 20 or the second gate 30, both gates can have the same potential; even when the first gate 20 and the second gate 30 are not connected, the same potential can still be applied to both gates. During thin-film transistor operation, the first gate 20 and the second gate 30 jointly apply an electric field to the active layer 40, improving the carrier mobility in the thin-film transistor channel region. When this dual-gate oxide thin-film transistor is applied to a display device, it can result in higher quality display images and a longer lifespan.

[0041] like Figure 3 and Figure 4 The diagram shown is a schematic of a multiplexer in related technologies. Figure 3 for Figure 4 A schematic diagram of the BB cross section. The multiplexer includes two such as... Figure 1 and Figure 2 The oxide thin-film transistors shown are a first thin-film transistor T1 and a second thin-film transistor T2. The first gate and the second gate of the first thin-film transistor T1 are connected to a first control signal line C1, and the first gate and the second gate of the second thin-film transistor T2 are connected to a second control signal line C2. The sources of both the first thin-film transistor T1 and the second thin-film transistor T2 are connected to a data signal input line M. The drain of the first thin-film transistor T1 is connected to a first data signal lead N1, and the drain of the second thin-film transistor T2 is connected to a second data signal lead N2. The first control signal line C1 provides a first control signal to control the on / off state of the first thin-film transistor T1, and the second control signal line C2 provides a second control signal to control the on / off state of the second thin-film transistor T2, thereby realizing the selection switch function of the multiplexer.

[0042] In related technologies, oxide thin-film transistors (OTCs) include a first gate 20 as the bottom gate and a second gate 30 as the top gate. The orthographic projection of the active layer 40 onto the substrate 10 lies within the orthographic projection of the first gate 20 onto the substrate 10. This means there is a large facing area between the first gate 20 and the active layer 40. Consequently, after the source 50 and drain 60 are turned on, the capacitance between the first gate 20 and the active layer 40 is large, resulting in a much higher power consumption than LTPS devices. Especially when this oxide thin-film transistor is applied to a multiplexer, its power consumption is approximately six times that of an LTPS device, and the power consumption of a multiplexer using an oxide thin-film transistor is more than twice that of a multiplexer using an LTPS device. Therefore, it is necessary to reduce the power consumption of the oxide thin-film transistor while maintaining its performance.

[0043] like Figure 5 and Figure 6 The diagram shown is a schematic representation of an oxide thin-film transistor according to a first embodiment of this disclosure. Figure 5 for Figure 6 A schematic diagram of section A1-A1. (See attached diagram.) Figure 7 and Figure 8 The diagram shown is a schematic of a multiplexer according to the first embodiment of this disclosure. Figure 7 for Figure 8 A schematic diagram of section B1-B1. (See diagram below.) Figure 7 and Figure 8 As shown, the first embodiment of this disclosure provides a multiplexer, which includes a substrate 110, and at least one such multiplexer disposed on the substrate 110. Figure 5 and Figure 6 The oxide thin-film transistor shown.

[0044] like Figure 5 and Figure 6 As shown, the oxide thin-film transistor includes a first gate 120, a second gate 130, an active layer 140, a source 150, and a drain 160 disposed on a substrate 110. The active layer 140 is disposed on the side of the first gate 120 away from the substrate 110, and a first interlayer insulating layer 170 is disposed between the active layer 140 and the first gate 120. The second gate 130 is disposed on the side of the active layer 140 away from the first gate 120, and a first interlayer insulating layer 170 is disposed between the active layer 140 and the first gate 120. A second interlayer insulating layer 180 is disposed between 130; the source 150 is connected to the source contact region of the active layer 140, and the drain 160 is connected to the drain contact region of the active layer 140; wherein, the orthogonal projection of the second gate 130 of the oxide thin film transistor on the substrate 110 is located within the orthogonal projection of the first gate 120 on the substrate 110, and the orthogonal projection of the first gate 120 on the substrate 110 is located within the orthogonal projection of the active layer 140 on the substrate 110.

[0045] The first gate 120 and the second gate 130 can be connected by a gate connection via H3 that penetrates the first interlayer insulating layer 170 and the second interlayer insulating layer 180, wherein the orthographic projection of the gate connection via H3 on the substrate 110 does not overlap with the orthographic projection of the active layer 140 on the substrate 110.

[0046] The oxide thin-film transistor of this disclosure includes a first gate 120 as the bottom gate and a second gate 130 as the top gate. The orthographic projection of the first gate 120 onto the substrate 110 lies within the orthographic projection of the active layer 140 onto the substrate 110. Compared to oxide thin-film transistors with dual-gate structures in related technologies, the thin-film transistor of this disclosure also has a dual-gate structure. The difference is that the first gate 120 and the active layer 140 have a smaller facing area, resulting in a smaller capacitance between the first gate 120 and the active layer 140 after the source 150 and drain 160 are turned on. This allows the oxide thin-film transistor to have lower power consumption while maintaining the superior performance of the dual-gate structure, with an estimated power consumption reduction of 25%.

[0047] In one embodiment, such as Figure 5 As shown, for an oxide thin-film transistor, the first gate 120 has a first side portion near and opposite to the source 150, and a second side portion near and opposite to the drain 160; the second gate 130 has a third side portion near and opposite to the source 150, and a fourth side portion near and opposite to the drain 160; the distance between the orthographic projections of the first side portion and the third side portion on the substrate is a first distance W1, and the distance between the orthographic projections of the second side portion and the fourth side portion on the substrate is a second distance W2; at least one of the first distance W1 and the second distance W2 is not less than 2 μm.

[0048] In this embodiment, the region of the active layer 140 covered by the orthogonal projection of the second gate 130 onto the active layer 140 forms a channel region. By setting a first spacing W1 of not less than 2μm, the first gate 120 sufficiently shields the channel region from light on the side near the source 150. By setting a second spacing W2 of not less than 2μm, the first gate 120 sufficiently shields the channel region from light on the side near the drain 160. By sufficiently shielding the channel region from light, it is possible to prevent the generation of photogenerated carriers in the channel region, which would lead to a decrease in the turn-on current and affect device performance.

[0049] In one embodiment, such as Figure 5As shown, for an oxide thin-film transistor, the first gate 120 has a first side portion near and opposite to the source 150, and a second side portion near and opposite to the drain 160; the second gate 130 has a third side portion near and opposite to the source 150, and a fourth side portion near and opposite to the drain 160; the distance between the orthographic projections of the first side portion and the third side portion on the substrate is a first distance W1, and the distance between the orthographic projections of the second side portion and the fourth side portion on the substrate is a second distance W2; the first distance W1 and the second distance W2 are equal.

[0050] In this embodiment, the region of the active layer 140 covered by the orthogonal projection of the second gate 130 onto the active layer 140 forms a channel region. By setting the first spacing W1 and the second spacing W2 to be equal, the first gate 120 has the same light-shielding effect on the channel region on both the side near the source 150 and the side near the drain 160, making the turn-on current of the channel region more uniform and the device have better electrical performance.

[0051] In one embodiment, such as Figure 5 As shown, the oxide thin film transistor also includes a third interlayer insulating layer 190 located on the side of the second gate 130 and the active layer 140 away from the first gate 120. The source 150 is connected to the source contact region of the active layer 140 through a first connection via H1 penetrating the third interlayer insulating layer 190, and the drain 160 is connected to the drain contact region of the active layer 140 through a second connection via H2 penetrating the third interlayer insulating layer 190.

[0052] In one embodiment, such as Figure 6 As shown, there are multiple first connecting vias H1, which are spaced apart; there are also multiple second connecting vias H2, which are spaced apart. Figure 6 In one embodiment, multiple first connection vias H1 are arranged side-by-side along the source 150 extension direction, and multiple second connection vias H2 are arranged side-by-side along the drain 160 extension direction. In another embodiment, the multiple first connection vias H1 may also be arranged in an array along the source 150 extension direction and perpendicular to the source 150 extension direction, and / or, the multiple second connection vias H2 may also be arranged in an array along the drain 160 extension direction and perpendicular to the drain 160 extension direction. In yet another embodiment, the multiple first connection vias H1 may be randomly arranged, and / or, the multiple second connection vias H2 may be randomly arranged. Regardless of the arrangement, the spacing between the multiple first connection vias H1 can be set as needed; the spacing between the multiple first connection vias H1 may be equal or unequal, and the spacing between the multiple second connection vias H2 can also be set as needed; the spacing between the multiple second connection vias H2 may be equal or unequal, and no specific limitation is made here.

[0053] By setting multiple first connection vias H1 to connect the source 150 to the active layer 140, and by setting multiple second connection vias H2 to connect the drain 160 to the active layer 140, the current distribution can be controlled, the current flow path can be increased, and the resistance can be reduced to improve the conductivity of the device, reduce local hot spots and thermal stress concentration, improve the heat dissipation performance of the device, keep the operating temperature of the device stable, and make the device have high reliability and stability, while extending the service life of the device.

[0054] In one embodiment, such as Figure 5 As shown, the orthographic projections of the second gate 130 and the second interlayer insulating layer 180 on the substrate 110 completely overlap. Therefore, when using the second gate 130 as a mask to conduct the active layer 140, ion implantation of the active layer 140 can be performed directly using relatively low energy. However, if the orthographic projection of the second gate 130 on the substrate 110 lies within the orthographic projection of the second interlayer insulating layer 180 on the substrate 110, then when using the second gate 130 as a mask to conduct the active layer 140, higher energy is required to achieve ion implantation of the active layer.

[0055] like Figure 7 and Figure 8 As shown, the multiplexer includes two such as 5 and Figure 6 The oxide thin-film transistors shown are a first thin-film transistor T1 and a second thin-film transistor T2. The first gate and the second gate of the first thin-film transistor T1 are connected to a first control signal line C1, and the first gate and the second gate of the second thin-film transistor T2 are connected to a second control signal line C2. The sources of both the first thin-film transistor T1 and the second thin-film transistor T2 are connected to a data signal input line M. The drain of the first thin-film transistor T1 is connected to a first data signal lead N1, and the drain of the second thin-film transistor T2 is connected to a second data signal lead N2. The first control signal line C1 provides a first control signal to control the on / off state of the first thin-film transistor T1, and the second control signal line C2 provides a second control signal to control the on / off state of the second thin-film transistor T2, thereby realizing the selection switch function of the multiplexer.

[0056] like Figure 9 and Figure 10 The diagram shown is a schematic representation of an oxide thin-film transistor according to a second embodiment of this disclosure. Figure 9 for Figure 10 A schematic diagram of section A2-A2. (See attached diagram.) Figure 11 and Figure 12 The diagram shown is a schematic of a multiplexer according to a second embodiment of this disclosure. Figure 11 for Figure 12A schematic diagram of section B2-B2. (See diagram below.) Figure 11 and Figure 12 As shown, the multiplexer of the second embodiment of this disclosure includes a substrate 210, and at least one such multiplexer disposed on the substrate 210 is described above. Figure 9 and Figure 10 The oxide thin-film transistor shown.

[0057] like Figure 9 and Figure 10 As shown, the oxide thin-film transistor includes a first gate 220, a second gate 230, an active layer 240, a source 250, and a drain 260 disposed on a substrate 210. The active layer 240 is disposed on the side of the first gate 220 away from the substrate 210, and a first interlayer insulating layer 270 is disposed between the active layer 240 and the first gate 220. The second gate 230 is disposed on the side of the active layer 240 away from the first gate 220, and a first interlayer insulating layer 270 is disposed between the active layer 240 and the first gate 220. A second interlayer insulating layer 280 is disposed between 230; the source 250 is connected to the source contact region of the active layer 240, and the drain 260 is connected to the drain contact region of the active layer 240; wherein, the orthographic projection of the second gate 230 of the oxide thin film transistor on the substrate 210 is located within the orthographic projection of the first gate 220 on the substrate 210, and the orthographic projection of the first gate 220 on the substrate 210 is located within the orthographic projection of the active layer 240 on the substrate 210.

[0058] In one embodiment, such as Figure 9 As shown, the oxide thin-film transistor also includes a third interlayer insulating layer 290 located on the side of the second gate 230 and the active layer 240 opposite to the first gate 220. A first connection via H1 and a second connection via H2 are formed on the third interlayer insulating layer 290. The first connection via H1 exposes the source contact region of the active layer 240, and the second connection via H2 exposes the drain contact region of the active layer 240. The orthographic projection of the first gate 220 on the substrate 210 is located between the orthographic projections of the first connection via H1 and the second connection via H2 on the substrate 210.

[0059] In one embodiment, the area of ​​the active layer 240 can be increased to make the spacing between the first connection via H1 and the second connection via H2 larger, so that the orthographic projection of the first gate 220 on the substrate 210 is located between the orthographic projections of the first connection via H1 and the second connection via H2 on the substrate 210 of the third interlayer insulating layer 290.

[0060] In this embodiment, the orthographic projection of the first gate 220 on the substrate 210 is located between the orthographic projections of the first connection via H1 and the second connection via H2 of the third interlayer insulating layer 290 on the substrate 210. That is, there is no direct area between the first gate 220 and the first connection via H1 and the second connection via H2. When the thin film transistor is working, electrostatic discharge between the first side of the first gate 220 near the source 250 and the source 260, as well as between the second side of the first gate 220 near the drain 260 and the drain 260, can be avoided, thereby improving product yield.

[0061] In one embodiment, such as Figure 9 As shown, the source 250 is connected to the source contact area of ​​the active layer 240 through the first connection via H1, and the drain 260 is connected to the drain contact area of ​​the active layer 240 through the second connection via H2. Figure 10 As shown, there are multiple first connecting vias H1, which are spaced apart; and there are multiple second connecting vias H2, which are also spaced apart. The arrangement and beneficial effects of the multiple first connecting vias H1 and the multiple second connecting vias H2 are the same as in the first embodiment, and will not be repeated here.

[0062] In one embodiment, such as Figure 9 As shown, for an oxide thin-film transistor, there is a third spacing W3 between the first gate 220 and the source 250 as projected onto the substrate 210, and a fourth spacing W4 between the first gate 220 and the drain 260 as projected onto the substrate 210; at least one of the third spacing W3 and the fourth spacing W4 is not less than 1 μm.

[0063] In this embodiment, the third distance W3 between the orthographic projections of the first gate 210 and the source 250 on the substrate 210 is not less than 1 μm, which can prevent electrostatic discharge between the first side of the first gate 220 near the source 250 and the source 250. The fourth distance W4 between the orthographic projections of the first gate 220 and the drain 260 on the substrate 210 is not less than 1 μm, which can prevent electrostatic discharge between the second side of the first gate 220 near the drain 260 and the drain 260, thereby preventing device damage.

[0064] In one embodiment, such as Figure 9 As shown, for an oxide thin-film transistor, there is a third spacing W3 between the first gate 220 and the source 250 projected onto the substrate 210, and a fourth spacing W4 between the first gate 220 and the drain 260 projected onto the substrate 210; both the third spacing W3 and the fourth spacing W4 are not less than 2μm.

[0065] In this embodiment, the third distance W3 between the orthogonal projections of the first gate 220 and the source 250 on the substrate 210 is not less than 2μm, which can effectively prevent electrostatic discharge between the first side of the first gate 220 near the source 250 and the source 250. The fourth distance W4 between the orthogonal projections of the first gate 220 and the drain 260 on the substrate 210 is not less than 2μm, which can effectively prevent electrostatic discharge between the second side of the first gate 220 near the drain 260 and the drain 260, thereby preventing device damage.

[0066] like Figure 11 and Figure 12 As shown, the multiplexer includes two such as Figure 9 and Figure 10 The oxide thin-film transistors shown are a first thin-film transistor T1 and a second thin-film transistor T2. The first gate and the second gate of the first thin-film transistor T1 are connected to a first control signal line C1, and the first gate and the second gate of the second thin-film transistor T2 are connected to a second control signal line C2. The sources of both the first thin-film transistor T1 and the second thin-film transistor T2 are connected to a data signal input line M. The drain of the first thin-film transistor T1 is connected to a first data signal lead N1, and the drain of the second thin-film transistor T2 is connected to a second data signal lead N2. The first control signal line C1 provides a first control signal to control the on / off state of the first thin-film transistor T1, and the second control signal line C2 provides a second control signal to control the on / off state of the second thin-film transistor T2, thereby realizing the selection switch function of the multiplexer.

[0067] The substrate 110 can be formed of a rigid material or a flexible material. For example, rigid materials include one of rigid glass, silicon substrate, germanium substrate, and silicon-coated insulating substrate; flexible materials include one of polyethylene naphthalate, polyethylene terephthalate, polyimide, and flexible glass.

[0068] The materials of the first gate 120 and the second gate 130 can each include one or more of the following metals: molybdenum (Mo), chromium (Cr), titanium (Ti), aluminum (Al), aluminum alloys, and copper (Cu). The materials of the first gate 120 and the second gate 130 can also include one or more of the following transparent conductive materials: indium tin oxide, aluminum-doped zinc oxide, and boron-doped zinc oxide. The materials of the first gate 120 and the second gate 130 can be the same or different. The first gate 120 and the second gate 130 can be a single-layer structure or a composite structure with two or more layers.

[0069] The active layer 140 can be made of metal oxides, such as zinc oxide (ZnO), indium oxide (In2O3), indium zinc oxide (IZO), aluminum-doped zinc oxide (AZO), boron-doped zinc oxide (BZO), magnesium-doped zinc oxide (MZO), zinc tin oxide (ZTO), indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), gallium zinc oxide (GZO), indium tin oxide (ITO), hafnium indium zinc oxide (HIZO), and tin oxide (SnO2), as well as p-type semiconductor materials such as tin suboxide (SnO) and cuprous suboxide (Cu2O).

[0070] The source electrode 150 and the drain electrode 160 may be made of one or more of the following metals: molybdenum (Mo), chromium (Cr), titanium (Ti), aluminum (Al), aluminum alloys, and copper (Cu). The source electrode 150 and the drain electrode 160 may be made of the same or different materials.

[0071] The materials of the first interlayer insulating layer 170 and the second interlayer insulating layer 180 include one or more of silicon oxide, silicon nitride, aluminum oxide, hafnium oxide, tantalum oxide, and zirconium oxide. The materials of the first interlayer insulating layer 170 and the second interlayer insulating layer 180 may be the same or different.

[0072] The material of the third interlayer insulating layer 190 includes one or more of silicon oxide, silicon nitride, aluminum oxide, hafnium oxide, tantalum oxide and zirconium oxide.

[0073] In one embodiment, the multiplexer may include a plurality of oxide thin-film transistors, each oxide thin-film transistor may have the structure of any of the above embodiments. For example, the multiplexer may include two oxide thin-film transistors that share the same source.

[0074] like Figure 13 and Figure 14 The diagram shown is a schematic of a multiplexer according to a third embodiment of this disclosure. Figure 13 for Figure 14A schematic diagram of section B3-B3. The multiplexer of the third embodiment of this disclosure includes a substrate 310 and two oxide thin-film transistors disposed on the substrate 310, namely a first thin-film transistor T1 and a second thin-film transistor T2; the oxide thin-film transistors T1 / T2 include a first gate 321 / 322, a second gate 331 / 332, an active layer 340, a source 350, and a drain 361 / 362 disposed on the substrate 310; the active layer 340 is disposed on the side of the first gate 321 / 322 facing away from the substrate 310, and a first interlayer insulating layer 370 is disposed between the active layer 340 and the first gate 321 / 322; the second gate 331 / 332 is... A second interlayer insulating layer 381 / 382 is disposed between the active layer 340 and the second gate 331 / 332, and is located on the side of the active layer 340 opposite to the first gate 321 / 322. The source 350 is connected to the source contact region of the active layer 340, and the drain 361 / 362 is connected to the drain contact region of the active layer 340. The orthogonal projection of the second gate 331 / 332 of the oxide thin-film transistor onto the substrate 310 lies within the orthogonal projection of the first gate 321 / 322 onto the substrate 310, and the orthogonal projection of the first gate 321 / 322 onto the substrate 310 lies within the orthogonal projection of the active layer 340 onto the substrate 310. The first thin-film transistor T1 and the second thin-film transistor T2 share the same source 350.

[0075] like Figure 14 As shown, the oxide thin-film transistors T1 / T2 further include a third interlayer insulating layer 390 located on the side of the second gate 331 / 332 and the active layer 340 opposite to the first gate 321 / 322. The source 350 is connected to the source contact region of the active layer 350 through a first connection via H1 penetrating the third interlayer insulating layer 390, and the drain 361 / 362 is connected to the drain contact region of the active layer 340 through a second connection via H2 penetrating the third interlayer insulating layer 390. In one embodiment, there are multiple first connection vias H1, which are spaced apart, and there are multiple second connection vias H2, which are spaced apart. The arrangement and beneficial effects of the multiple first connection vias H1 and the arrangement and beneficial effects of the multiple second connection vias H2 are the same as in the first embodiment, and will not be repeated here.

[0076] like Figure 14As shown, the first gate and second gate of the first thin-film transistor T1 are connected to the first control signal line C1, and the first gate and second gate of the second thin-film transistor T2 are connected to the second control signal line C2. The sources of both the first and second thin-film transistors T1 and T2 are connected to the data signal input line M. The drain of the first thin-film transistor T1 is connected to the first data signal lead N1, and the drain of the second thin-film transistor T2 is connected to the second data signal lead N2. The first control signal line C1 provides a first control signal to control the on / off state of the first thin-film transistor T1, and the second control signal line C2 provides a second control signal to control the on / off state of the second thin-film transistor T2, thereby realizing the selection switch function of the multiplexer.

[0077] In this embodiment, the first thin-film transistor T1 and the second thin-film transistor T2 share the same source 350, which can reduce the space occupied by the multiplexer; when the multiplexer is applied to the display device, the bezel size can be effectively reduced, which is beneficial to improving the pixel density of the display area.

[0078] This disclosure provides a method for fabricating a multiplexer, comprising: providing a substrate; forming at least one oxide thin-film transistor on the substrate; forming the oxide thin-film transistor on the substrate comprises: forming a first gate on the substrate; sequentially forming a first interlayer insulating layer and an active layer on the side of the first gate away from the substrate; sequentially forming a second interlayer insulating layer and a second gate on the side of the active layer away from the first gate; forming a source and a drain; the source is connected to a source contact region of the active layer; and the drain is connected to a drain contact region of the active layer; wherein the orthographic projection of the second gate of the oxide thin-film transistor on the substrate is located within the orthographic projection of the first gate on the substrate, and the orthographic projection of the first gate on the substrate is located within the orthographic projection of the active layer on the substrate.

[0079] In this embodiment, the processes for forming the first gate and the second gate may include magnetron sputtering, electron beam evaporation, thermal evaporation, etc., or optical coating, etc. The processes for forming the first gate and the second gate may be the same or different. The processes for forming the active layer may include magnetron sputtering, reactive sputtering, anodizing, spin coating, etc. The processes for forming the first interlayer insulating layer and the second interlayer insulating layer may include chemical vapor deposition (CVD), physical vapor deposition (PVD), vacuum evaporation, etc., or spin coating, etc.

[0080] In one embodiment, the method further includes: before forming the source and drain, forming a third interlayer insulating layer on the side of the second gate and the active layer away from the first gate, and forming a first connection via and a second connection via on the third interlayer insulating layer, wherein the first connection via exposes the source contact region of the active layer, and the second connection via exposes the drain contact region of the active layer; the orthographic projection of the first gate on the substrate is located between the orthographic projections of the first connection via and the second connection via on the substrate.

[0081] In this embodiment, the process for forming the third interlayer insulating layer may include chemical vapor deposition, physical vapor deposition, vacuum evaporation, etc. The process for forming the first and second connection vias on the third interlayer insulating layer may include dry etching, wet etching, etc.

[0082] In one embodiment, the method further includes: forming a source electrode in a first connection via, the source electrode being connected to a source contact region of an active layer; and forming a drain electrode in a second connection via, the drain electrode being connected to a drain contact region of an active layer.

[0083] In this embodiment, the source electrode can be formed in the first interconnect via and the drain electrode can be formed in the second interconnect via using a patterning process. The source and drain electrodes can be disposed on the same layer, thereby simplifying the fabrication process.

[0084] In one embodiment, the method further includes forming two oxide thin-film transistors on a substrate, namely a first thin-film transistor and a second thin-film transistor, wherein the first thin-film transistor and the second thin-film transistor share the same source.

[0085] In this embodiment, the active layer of the first thin-film transistor and the active layer of the second thin-film transistor can be disposed in the same layer. Furthermore, the active layers of the first thin-film transistor and the active layers of the second thin-film transistor can be connected into an integral structure, thereby forming in a single deposition process.

[0086] In one embodiment, the first control signal line can be disposed on the same layer as the first gate or the second gate of the first thin-film transistor, and the second control signal line can be disposed on the same layer as the first gate or the second gate of the second thin-film transistor; the first data signal lead can be disposed on the same layer as the drain of the first thin-film transistor, and the second data signal lead can be disposed on the same layer as the drain of the second thin-film transistor; the data signal input line can be disposed on the same layer as the source of the first or second thin-film transistor. In other embodiments, the connection between different thin-film layers can be achieved through vias.

[0087] This disclosure provides an electronic device that includes any of the multiplexers described above.

[0088] In one embodiment, the electronic device may be an array substrate, which further includes: a data signal input line and first and second control signal lines. The data signal input line is connected to the source of two thin-film transistors, the first control signal line is connected to the first and second gates of one thin-film transistor, and the second control signal line is connected to the first and second gates of another thin-film transistor.

[0089] In one embodiment, the electronic device may be a display device, which may include the array substrate described above.

[0090] In one embodiment, the display device can be any product or component with display function, such as a liquid crystal panel, electronic paper, OLED panel, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0091] It is understood that the above embodiments are merely exemplary implementations used to illustrate the principles of the present invention, and the present invention is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. A multiplexer comprising a substrate and at least one oxide thin-film transistor disposed on the substrate; the oxide thin-film transistor comprising a first gate, a second gate, an active layer, a source, and a drain disposed on the substrate; the active layer being disposed on a side of the first gate opposite to the substrate, and a first interlayer insulating layer being disposed between the active layer and the first gate; The second gate is disposed on the side of the active layer away from the first gate, and a second interlayer insulating layer is disposed between the active layer and the second gate; The source electrode is connected to the source contact region of the active layer, and the drain electrode is connected to the drain contact region of the active layer; wherein... The orthographic projection of the second gate of the oxide thin-film transistor on the substrate is located within the orthographic projection of the first gate on the substrate, and the orthographic projection of the first gate on the substrate is located within the orthographic projection of the active layer on the substrate.

2. The multiplexer according to claim 1, wherein, For the oxide thin-film transistor, the first gate has a first side portion near the source and opposite to the source, and a second side portion near the drain and opposite to the drain; the second gate has a third side portion near the source and opposite to the source, and a fourth side portion near the drain and opposite to the drain; the distance between the orthographic projections of the first side portion and the third side portion on the substrate is a first distance, and the distance between the orthographic projections of the second side portion and the fourth side portion on the substrate is a second distance; at least one of the first distance and the second distance is not less than 2 μm.

3. The multiplexer according to claim 1, wherein, For the oxide thin-film transistor, the first gate has a first side portion near the source and opposite to the source, and a second side portion near the drain and opposite to the drain; the second gate has a third side portion near the source and opposite to the source, and a fourth side portion near the drain and opposite to the drain; the distance between the orthographic projections of the first side portion and the third side portion on the substrate is a first distance, and the distance between the orthographic projections of the second side portion and the fourth side portion on the substrate is a second distance; The first spacing is equal to the second spacing.

4. The multiplexer according to claim 1, wherein, The oxide thin-film transistor further includes a third interlayer insulating layer located on the side of the second gate and the active layer opposite to the first gate. A first connection via and a second connection via are formed on the third interlayer insulating layer. The first connection via exposes the source contact region of the active layer, and the second connection via exposes the drain contact region of the active layer. The orthographic projection of the first gate on the substrate is located between the orthographic projections of the first connection via and the second connection via on the substrate.

5. The multiplexer according to claim 1, wherein, For the oxide thin-film transistor, there is a third spacing between the first gate and the source as orthogonal projections on the substrate, and a fourth spacing between the first gate and the drain as orthogonal projections on the substrate; at least one of the third spacing and the fourth spacing is not less than 1 μm.

6. The multiplexer according to claim 1, wherein, For the oxide thin-film transistor, there is a third spacing between the first gate and the source as projected onto the substrate, and a fourth spacing between the first gate and the drain as projected onto the substrate; both the third spacing and the fourth spacing are not less than 2 μm.

7. The multiplexer according to claim 1, wherein, The number of oxide thin-film transistors is two, namely a first thin-film transistor and a second thin-film transistor, and the first thin-film transistor and the second thin-film transistor share the same source.

8. The multiplexer according to claim 1, wherein, The active layer is made of metal oxide.

9. The multiplexer according to claim 1, wherein, The second gate and the second interlayer insulating layer are completely overlapped in their orthogonal projections on the substrate.

10. The multiplexer according to claim 1, wherein, The oxide thin-film transistor further includes a third interlayer insulating layer located on the side of the second gate and the active layer opposite to the first gate. The source is connected to the source contact region of the active layer through a first connection via penetrating the third interlayer insulating layer, and the drain is connected to the drain contact region of the active layer through a second connection via penetrating the third interlayer insulating layer.

11. The multiplexer according to claim 10, wherein, There are multiple first connection vias, and the multiple first connection vias are spaced apart; there are multiple second connection vias, and the multiple second connection vias are spaced apart.

12. An electronic device comprising a multiplexer as claimed in any one of claims 1 to 11.

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