A high-precision current sampling and equalization circuit suitable for two-phase BUCK converter

Abstract

The application discloses a high-precision current sampling and equalization circuit suitable for two-phase BUCK converters and belongs to the field of analog integrated circuits, comprising two identical current sampling units and a current equalization unit. The two current sampling units detect the currents of two-phase inductors respectively, sample the currents of the inductors in proportion through special sampling resistors and current sampling resistors to obtain sampling currents, and input equalization input currents proportional to the sampling currents to the current equalization unit; the current equalization unit equalizes the received two-phase equalization input currents to obtain average currents to realize equalization. The application can realize sampling of two-phase inductor currents and average distribution of inter-phase currents, has a simple circuit structure, high precision of current sampling and equalization, and can improve the stability and reliability of a system.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of analog integrated circuit technology, in particular to a high-precision current sampling and equalization circuit suitable for two-phase BUCK converter. BACKGROUND

[0002] With the rapid development of semiconductor technology and the continuous expansion of application fields, various types of consumer-grade portable electronic products have been widely used in people's daily life, and their functions are becoming more and more powerful, meeting people's various needs.

[0003] Small volume and large capacity battery is the main factor affecting the light and thin, high efficiency of portable electronic products, which requires power management chips that can output large current and high conversion efficiency; and multi-phase BUCK converter power chip with large current, high efficiency and small size has gradually become the first choice. In the working of multi-phase BUCK converter power chip, in order to ensure the stability and reliability of the whole system, it is very important to keep the current balance between phases. Therefore, the current sampling and equalization circuit is an indispensable module in the multi-phase converter power chip.

[0004] The traditional current sampling and equalization technology has high requirements for the size and precision of the sampling resistor, and the precision and matching of the amplifier used for current equalization, and the design difficulty of the system is large. SUMMARY

[0005] The purpose of the present application is to provide a high-precision current sampling and equalization circuit for two-phase BUCK converter to solve the problems in the background art.

[0006] To solve the above technical problems, the present application provides a high-precision current sampling and equalization circuit for two-phase BUCK converter, which comprises two identical current sampling units and a current equalization unit.

[0007] The two current sampling units are a first-phase current sampling unit and a second-phase current sampling unit, the first-phase current sampling unit detects the current of the first-phase inductor L1, and the current of the first-phase inductor L1 is sampled in proportion by using the first-phase dedicated sampling resistor R SENSE1 and the first-phase current sampling resistor R ISENSE1 to obtain the first-phase sampling current I SEN1 ; the second-phase current sampling unit detects the current of the second-phase inductor L2, and the current of the second-phase inductor L2 is sampled in proportion by using the second-phase dedicated sampling resistor R SENSE2 and the second-phase current sampling resistor R ISENSE2 to obtain the second-phase sampling current I SEN2 .

[0008] The first phase current sampling unit will sample the first phase sampling current I SEN1 The first phase equalization input current proportional to the first phase sampling current I SEN2 The second phase equalization input current proportional to the second phase sampling current I

[0009] The current equalization unit averages the received first phase equalization input current and second phase equalization input current to achieve equalization function.

[0010] In an embodiment, one end of the first phase dedicated sampling resistor R SENSE1 is connected to the first phase inductor L1, and the other end is connected to the output capacitor C OUT The connection end of the first phase dedicated sampling resistor R SENSE1 and the output capacitor C OUT is the output voltage V OUT of the two-phase BUCK converter;

[0011] One end of the first phase current sampling resistor R ISENSE1 is connected to the output voltage V OUT , and the other end is grounded through the first capacitor C1;

[0012] The signal ISEN1_P at the connection end of the first phase dedicated sampling resistor R SENSE1 and the first phase inductor L1, and the signal ISEN1_N at the connection end of the first phase current sampling resistor R ISENSE1 and the first capacitor C1 are input signals obtained by sampling the current of the first phase inductor L1 by the first phase current sampling unit.

[0013] In an embodiment, one end of the second phase dedicated sampling resistor R SENSE2 is connected to the second phase inductor L2, and the other end is connected to the output voltage V OUT ;

[0014] One end of the second phase current sampling resistor R ISENSE2 is connected to the output voltage V OUT , and the other end is grounded through the second capacitor C2;

[0015] The signal ISEN2_P at the connection end of the second phase dedicated sampling resistor R SENSE2 and the second phase inductor L2, and the signal ISEN2_N at the connection end of the second phase current sampling resistor R ISENSE2 and the second capacitor C2 are input signals obtained by sampling the current of the second phase inductor L2 by the second phase current sampling unit.

[0016] In one embodiment, the current sampling unit comprises a first operational amplifier A1, PMOS transistors MP1-MP2, NMOS transistors MN1-MN3, and resistors R1-R2;

[0017] The output terminal of the first operational amplifier A1 is connected to the gate of the NMOS transistor MN1, the non-inverting terminal is connected to the signal ISENi_P, and the inverting terminal is connected to the signal ISENi_N;

[0018] The NMOS transistor MN2 and the NMOS transistor MN3 constitute a M:1 ratio mirror, the drain of the NMOS transistor MN2 is connected to the gate of itself, the sampling current I SENi SENi is connected to the inverting terminal of the first operational amplifier A1 and the source of the NMOS transistor MN1, and the source of the NMOS transistor MN2 is connected to the ground through the resistor R1; the gate of the NMOS transistor MN3 is connected to the gate of the NMOS transistor MN2, the source of the NMOS transistor MN3 is connected to the ground through the resistor R2, and the drain of the NMOS transistor MN3 and the drain of the PMOS transistor MP2 are both connected to the balanced input current I SENi *1 / M, i=1, 2;

[0019] The PMOS transistor MP1 and the PMOS transistor MP2 constitute a M:1 ratio mirror, the sources of both are connected to the internal power supply, the gates are connected to each other and to the drain of the NMOS transistor MN1.

[0020] In one embodiment, the current balancing unit comprises a second operational amplifier A2, current sources I REF , N*I REF , PMOS transistors MP3-MP4, and NMOS transistors MN4-MN8.

[0021] The output terminal of the second operational amplifier A2 is connected to the gate of the NMOS transistor MN4, the inverting terminal is connected to the source of the NMOS transistor MN4 and the drain of the NMOS transistor MN6, and the non-inverting terminal is connected to the bias voltage signal VR, the output terminal of the current source I REF , the first-phase balanced input current I SEN1 *1 / M, the second-phase balanced input current I SEN2 *1 / M, the drain and the gate of the NMOS transistor MN5; and the input terminal of the current source I REF is connected to the internal power supply.

[0022] The NMOS transistor MN6 and the NMOS transistor MN5 constitute an N:1 ratio mirror, the gates of both are connected to each other, and the sources are both connected to the ground; the PMOS transistor MP3 and the PMOS transistor MP4 constitute a 1:1 ratio mirror, the sources of both are connected to the internal power supply, the gates are connected to each other and to the drain of the NMOS transistor MN4; and the drain of the PMOS transistor MP4 is connected to the average current I AVGand the drain of the NMOS transistor MN7 is connected with the drain of the NMOS transistor MN8; the gate of the NMOS transistor MN7 is connected with the gate of the NMOS transistor MN8, and the sources of the two are grounded; the gate and the drain of the NMOS transistor MN8 are connected with the output end of the current source N*I REF , and the input end of the current source N*I REF is connected with the internal power supply.

[0023] The application provides a high-precision current sampling and equalization circuit suitable for a two-phase BUCK converter, which can sample the inductance currents of two phases and average the inter-phase currents, has a simple circuit structure, high precision of current sampling and equalization, and can improve the stability and reliability of a system. BRIEF DESCRIPTION OF DRAWINGS

[0024] Figure 1 Fig. 1 is a system block diagram of the high-precision current sampling and equalization circuit provided by the application applied to a two-phase BUCK converter.

[0025] Figure 2 Fig. 2 is a structure diagram of a current sampling unit in the high-precision current sampling and equalization circuit.

[0026] Figure 3 Fig. 3 is a structure diagram of a current equalization unit in the high-precision current sampling and equalization circuit. DETAILED DESCRIPTION

[0027] The application provides a high-precision current sampling and equalization circuit suitable for a two-phase BUCK converter, which comprises two same current sampling units (i.e., a first-phase current sampling unit and a second-phase current sampling unit) and a current equalization unit.

[0028] The application provides a high-precision current sampling and equalization circuit suitable for a two-phase BUCK converter, which comprises two same current sampling units (i.e., a first-phase current sampling unit and a second-phase current sampling unit) and a current equalization unit.

[0029] The first-phase special sampling resistor R SENSE1 is connected in series between the first-phase inductance L1 and the output capacitor C OUT ; the connection end of the first-phase special sampling resistor R SENSE1 and the output capacitor C OUT is the output voltage V OUT of the two-phase BUCK converter; one end of the first-phase current sampling resistor R ISENSE1 is connected with the output voltage V OUT , and the other end is connected to the ground through the first capacitor C1; the first-phase special sampling resistor RSENSE1 signal ISEN1_P connected to one end of the first phase inductor L1, the first phase current sampling resistor R ISENSE1 signal ISEN1_N connected to the other end of the first phase inductor L1, as the input signal obtained by the first phase current sampling unit sampling the current of the first phase inductor L1.

[0030] second phase dedicated sampling resistor R SENSE2 connected to one end of the second phase inductor L2, and the other end connected to the output voltage V OUT of the two-phase BUCK converter, the second phase current sampling resistor R ISENSE2 connected to one end of the output voltage V OUT , and the other end grounded through the second capacitor C2; the second phase dedicated sampling resistor R SENSE2 signal ISEN2_P connected to one end of the second phase inductor L2, the second phase current sampling resistor R ISENSE2 signal ISEN2_N connected to the other end of the second capacitor C2, as the input signal obtained by the second phase current sampling unit sampling the current of the second phase inductor L2.

[0031] The dedicated sampling resistor R SENSEi (i = 1, 2) and the current sampling resistor R ISENSEi (i = 1, 2) proportionally sample the current of the inductor L i (i = 1, 2) to obtain the sampling current I SENi (i = 1, 2), taking the first phase as an example, the input signals ISEN1_P and ISEN1_N obtained by sampling are connected to the non-inverting and inverting terminals of the first operational amplifier A1 inside the current sampling unit, respectively. According to the virtual short characteristic of the operational amplifier, the first phase sampling current I SEN1 is obtained. L1 has the relationship shown in formula (1):

[0032]

[0033] As Figure 1 indicated in the first phase sampling current I SEN1 direction, according to the size of the first phase inductor current I L1 , the first phase current sampling unit will draw a proportional first phase sampling current I SEN1 through the first phase current sampling resistor R ISENSE1 , while the current balancing is the first phase balancing input current I SEN1 proportional to the first phase sampling current I SEN1 *1 / M. The first phase balancing input current I SEN1 *1 / M and the second phase balancing input current I SEN2*1 / M input to the current equalization unit for averaging, realizing the equalization function.

[0034] Referring to Figure 2 , the current sampling unit comprises a first operational amplifier A1, PMOS tubes MP1-MP2, NMOS tubes MN1-MN3, resistors R1-R2; the output end of the first operational amplifier A1 is connected to the gate of NMOS tube MN1, its non-inverting terminal is connected to input signal ISENi_P (i=1, 2), and its inverting terminal is simultaneously connected to input signal ISENi_N (i=1, 2), the source of NMOS tube MN1, sampling current I SENi (i=1, 2), the drain of NMOS tube MN2 and the gate of NMOS tube MN2.

[0035] NMOS tube MN2 and NMOS tube MN3 constitute a M:1 proportional mirror, the source of NMOS tube MN2 is connected to ground through the first resistor R1; the gate of NMOS tube MN3 is connected to the gate of NMOS tube MN2, and the source is connected to ground through the second resistor R2; the drain of NMOS tube MN3 is simultaneously connected to the drain of PMOS tube MP2 and equalization input current I SENi *1 / M (i=1, 2). PMOS tube MP1 and PMOS tube MP2 constitute a M:1 proportional mirror, the sources of both are connected to internal power supply, and the gates are connected and connected to the drain of NMOS tube MN1.

[0036] The first operational amplifier A1, NMOS tube MN1 and current sampling resistor R ISENSEi (i=1, 2) constitute a feedback loop, and when inductance current I Li (i=1, 2) changes, the corresponding sampling current I SENi (i=1, 2) can be accurately extracted; at the same time, through the proportional mirror composed of PMOS tube MP1 and PMOS tube MP2, and the proportional mirror composed of NMOS tube MN2 and NMOS tube MN3, the equalization input current I i *1 / M (i=1, 2) with inductance L SENi (i=1, 2) current information can be accurately mirrored.

[0037] As shown in Figure 3 , the current equalization unit comprises a second operational amplifier A2, current source I REF , current source N*I REF , PMOS tubes MP3-MP4, NMOS tubes MN4-MN8. The output end of the second operational amplifier A2 is connected to the gate of NMOS tube MN4, its non-inverting terminal is simultaneously connected to the source of NMOS tube MN4 and the drain of NMOS tube MN6, and its inverting terminal is simultaneously connected to bias voltage signal VR, current source I REFthe output end of the first phase equalization input current I SEN1 *1 / M, the second phase equalization input current I SEN2 *1 / M, the drain and the gate of the NMOS tube MN5 are connected; the current source I REF the input end is connected with the internal power supply.

[0038] The NMOS tube MN6 and the NMOS tube MN5 constitute N:1 proportional mirroring, the gates of the two are connected, and the sources are both connected with the ground. The PMOS tube MP3 and the PMOS tube MP4 constitute 1:1 proportional mirroring, the sources of the two are both connected with the internal power supply, the gates are connected and connected with the drain of the NMOS tube MN4; the drain of the PMOS tube MP4 is connected with the average current I AVG , and the drain of the NMOS tube MN7 is connected. The NMOS tube MN7 and the NMOS tube MN8 constitute 1:1 proportional mirroring, the gate of the NMOS tube MN7 is connected with the gate and the drain of the NMOS tube MN8, the sources of the two are both connected with the ground, and the gate and the drain of the NMOS tube MN8 are both connected with the current source N*I REF the output end, and the current source N*I REF the input end is connected with the internal power supply.

[0039] The second operational amplifier A2, the drains of the NMOS tube MN4 and the NMOS tube MN5 and the drain of the NMOS tube MN6 constitute negative feedback, which can ensure that the drain of the NMOS tube MN5 and the drain of the NMOS tube MN6 are strictly equal, and the current flowing through the NMOS tube MN5 can be accurately mirrored to the NMOS tube MN6. Through the 1:1 mirror constituted by the PMOS tube MP3 and the PMOS tube MP4 and the 1:1 mirror constituted by the NMOS tube MN7 and the NMOS tube MN8, the average current I AVG can be accurately mirrored. The current relationship in the circuit is shown in formula (2):

[0040]

[0041] By setting the ratio of N / M as 1:2, the average value of the two-phase sampling currents can be obtained, the equalization function of the two-phase inductance currents is realized, and the average current I AVG is fed back to the dual-phase BUCK converter, the average distribution of the currents between the two phases is realized by adjusting the duty cycles of the modulation signals of the phase converters; the average current I AVG can also be used to realize the monitoring function and the current limiting protection function of the output current.

[0042] Through the example analysis, the current sampling and equalization circuit of the application realizes the current sampling and equalization functions required by the multi-phase BUCK converter system in the electronic field with a simple and practical structure. The circuit design of the application is simple, the precision is high, and the stability and reliability of the system are improved.

[0043] The above description is only the description of the preferred embodiments of the present application, and is not any limitation on the scope of the present application. Any change and modification made by the person of ordinary skill in the art according to the above disclosure is within the protection scope of the claims.

Claims

1. A high precision current sampling and equalization circuit suitable for two-phase BUCK converter, characterized in that, The current sampling unit comprises two identical current sampling units and a current balancing unit; The two current sampling units are a first-phase current sampling unit and a second-phase current sampling unit. The first-phase current sampling unit detects the current of the first-phase inductor L1 by using a first-phase dedicated sampling resistor R SENSE1 and a first-phase current sampling resistor R ISENSE1 to proportionally sample the current of the first-phase inductor L1 to obtain a first-phase sampling current I SEN1 ; the second-phase current sampling unit detects the current of the second-phase inductor L2 by using a second-phase dedicated sampling resistor R SENSE2 and a second-phase current sampling resistor R ISENSE2 to proportionally sample the current of the second-phase inductor L2 to obtain a second-phase sampling current I SEN2 ; The first phase current sampling unit will input a first phase sampling current I SEN1 proportional to the first phase balanced input current into the current balancing unit, the second phase current sampling unit will input a second phase sampling current I SEN2 proportional to the second phase balanced input current into the current balancing unit; The current balancing unit averages the received first-phase balanced input current and second-phase balanced input current to realize the balancing function; The current equalization unit comprises a second operational amplifier A2, a current source I REF , a current source N*I REF , PMOS tubes MP3~MP4, NMOS tubes MN4~MN8; The output terminal of the second operational amplifier A2 is connected to the gate of the NMOS transistor MN4, the inverting terminal is connected to the source of the NMOS transistor MN4 and the drain of the NMOS transistor MN6, and the non-inverting terminal is connected to the bias voltage signal VR and the current source I REF The output terminal, the first phase balanced input current I SEN1 *1 / M, second phase balanced input current I SEN2 *1 / M, the drain and gate of NMOS tube MN5 are connected; the current source I REF The input terminal is connected to the internal power supply; NMOS MN6 and NMOS MN5 constitute N:1 scale mirror, both of whose gates are connected, and both of whose sources are grounded; PMOS MP3 and PMOS MP4 constitute 1:1 scale mirror, both of whose sources are connected to internal power supply, both of whose gates are connected and connected to the drain of NMOS MN4; the drain of PMOS MP4 is connected to the drain of NMOS MN7; NMOS MN7 and NMOS MN8 constitute 1:1 scale mirror, the gate of NMOS MN7 is connected to the gate of NMOS MN8, both of whose sources are grounded, the gate and the drain of NMOS MN8 are connected to the output of current source N*I AVG , and the input of current source N*I REF is connected to internal power supply. REF ​ 2. The high precision current sensing and equalization circuit for two-phase BUCK converter of claim 1, wherein, The first phase dedicated sampling resistor R SENSE1 One end is connected to the first phase inductor L1, and the other end is connected to the output capacitor C OUT , the first phase dedicated sampling resistor R SENSE1 and the output capacitor C OUT The connection end is the output voltage V of the two-phase BUCK converter OUT ; One end of the first phase current sampling resistor R ISENSE1 is connected to the output voltage V OUT , and the other end is grounded through the first capacitor C1; The first phase dedicated sampling resistor R SENSE1 The signal ISEN1_P connected with the first phase inductor L1 end, the first phase current sampling resistor R ISENSE1 The signal ISEN1_N connected with the first capacitor C1 end is the input signal obtained by sampling the current of the first phase inductor L1 by the first phase current sampling unit.

3. The high precision current sensing and equalization circuit for two-phase BUCK converter of claim 2, wherein, One end of the second phase dedicated sampling resistor R SENSE2 is connected to the second phase inductor L2, and the other end is connected to the output voltage V OUT . One end of the second phase current sampling resistor R ISENSE2 is connected to the output voltage V OUT , and the other end is grounded through the second capacitor C2; The second phase dedicated sampling resistor R SENSE2 The signal ISEN2_P connected with the second phase inductor L2 end, the second phase current sampling resistor R ISENSE2 The signal ISEN2_N connected with the second capacitor C2 end is an input signal obtained by sampling the current of the second phase inductor L2 by the second phase current sampling unit.

4. The high precision current sensing and equalization circuit for two-phase BUCK converter of claim 3, wherein, The current sampling unit comprises a first operational amplifier A1, PMOS tubes MP1-MP2, NMOS tubes MN1-MN3 and resistors R1-R2; The output end of the first operational amplifier A1 is connected to the gate of the NMOS tube MN1, the non-inverting terminal thereof is connected to the signal ISENi_P, and the inverting terminal thereof is connected to the signal ISENi_N. NMOS transistor MN2 and NMOS transistor MN3 constitute M:1 ratio mirror, the drain of the NMOS transistor MN2 is connected with the gate of itself, sampling current I SENi , the inverting terminal of the first operational amplifier A1 and the source of NMOS transistor MN1, the source of NMOS transistor MN2 is connected with the ground through resistance R1; the gate of NMOS transistor MN3 is connected with the gate of NMOS transistor MN2, the source of NMOS transistor MN3 is connected with the ground through resistance R2, the drain of NMOS transistor MN3 and the drain of PMOS transistor MP2 are connected with the balanced input current I SENi *1 / M, i=1, 2; The PMOS tube MP1 and the PMOS tube MP2 constitute an M:1 proportional mirror image, the sources of the two are connected to the internal power supply, the gates are connected and connected to the drain of the NMOS tube MN1.

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